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JP2006086161A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2006086161A
JP2006086161A JP2004266496A JP2004266496A JP2006086161A JP 2006086161 A JP2006086161 A JP 2006086161A JP 2004266496 A JP2004266496 A JP 2004266496A JP 2004266496 A JP2004266496 A JP 2004266496A JP 2006086161 A JP2006086161 A JP 2006086161A
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JP
Japan
Prior art keywords
wiring board
printed wiring
semiconductor device
semiconductor
insulating
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Withdrawn
Application number
JP2004266496A
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Japanese (ja)
Inventor
Shinpei Tamura
新平 多村
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Canon Inc
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Canon Inc
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Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2004266496A priority Critical patent/JP2006086161A/en
Publication of JP2006086161A publication Critical patent/JP2006086161A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve the fatigue resistance strength of a solder joint between a semiconductor package and a printed wiring board, and to improve the service life of the semiconductor package and a semiconductor device wherein the semiconductor package is mounted to the printed wiring board. <P>SOLUTION: An opening 13 in the solder joint of a semiconductor device is formed like an inverse taper, and the joint angle of a solder bump 9 is made at an obtuse angle, and the solder bump 9 is formed like a nearly drum-like shape. The semiconductor device has a structure where stress or strain generating at the solder bump 9 is dispersed during its operation, so that the fatigue resistance strength at the solder joint can be improved, resulting in prolonged service life against fatigue or improved reliability in the semiconductor device. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体パッケージ、並びに、該半導体パッケージをプリント配線基板に実装した半導体装置に係り、特に、外部接続端子として、はんだバンプを具備する半導体パッケージをプリント配線基板に電気的、且つ、機械的に接続した半導体装置に関するものである。   The present invention relates to a semiconductor package and a semiconductor device in which the semiconductor package is mounted on a printed wiring board. In particular, the semiconductor package having solder bumps as external connection terminals is electrically and mechanically attached to the printed wiring board. The present invention relates to a semiconductor device connected to.

従来において、外部接続端子にはんだバンプを用いた半導体パッケージとしてBGA（Ball Grid Array）やCSP（Chip Size Package 又は Chip Scale Package）が知られている。これらの半導体パッケージは電子機器の小型化、軽量化、高機能化に対応して開発されたもので、はんだバンプをエリアアレイ状に配置することによって、実装面積の縮小化及び高密度化を狙い、半導体パッケージの軽薄短小化を実現している。   Conventionally, BGA (Ball Grid Array) and CSP (Chip Size Package or Chip Scale Package) are known as semiconductor packages using solder bumps for external connection terminals. These semiconductor packages were developed in response to miniaturization, weight reduction, and high functionality of electronic devices. By arranging solder bumps in an area array, the mounting area is reduced and the density is increased. Realizes lighter, thinner and smaller semiconductor packages.

図３は当該半導体パッケージをプリント配線基板に実装したもの、いわゆる半導体装置の概略的な構造を示している。簡単に説明すると、半導体素子１は絶縁性部材２の一方表面の中央部にダイボンド材４によって搭載され、その絶縁性部材２の表面には半導体素子１と電気的に接続するための配線パターン３が形成されている。ボンディングワイヤー７により半導体素子１の一方表面の周辺に沿って設けられたボンディングパッド６と配線パターン３とが電気的に接続され、半導体素子１周辺は封止樹脂材８により封止される。   FIG. 3 shows a schematic structure of a so-called semiconductor device in which the semiconductor package is mounted on a printed wiring board. Briefly, the semiconductor element 1 is mounted on the central portion of one surface of the insulating member 2 by a die bond material 4, and the wiring pattern 3 for electrically connecting to the semiconductor element 1 is formed on the surface of the insulating member 2. Is formed. The bonding pad 6 provided along the periphery of one surface of the semiconductor element 1 and the wiring pattern 3 are electrically connected by the bonding wire 7, and the periphery of the semiconductor element 1 is sealed with the sealing resin material 8.

そして、絶縁性部材２の他方表面には、はんだバンプ９が半導体素子側開口部１３を介して配線パターン３と接続された状態で配置される。このはんだバンプ９の配置に対応してプリント配線基板６０を構成する絶縁性基板１０に設けられたプリント配線基板側開口部１５の位置に配線電極１１がエリアアレイ状に配置され、その配線電極１１上にリフロー工程を経て、はんだバンプ９の、少なくとも、その一部を溶融し配線電極１１とはんだバンプ９とを接合させて完成する。   The solder bump 9 is disposed on the other surface of the insulating member 2 in a state of being connected to the wiring pattern 3 through the semiconductor element side opening 13. Corresponding to the arrangement of the solder bumps 9, the wiring electrodes 11 are arranged in an area array at the position of the printed wiring board side opening 15 provided on the insulating substrate 10 constituting the printed wiring board 60. Through a reflow process, at least a part of the solder bump 9 is melted and the wiring electrode 11 and the solder bump 9 are joined to complete.

この半導体装置の構造上、電子機器の稼動中における大きな温度変化や電源の発停時において、半導体パッケージ及びプリント配線基板の構成部材の線膨張係数の相違に起因して発生する応力やひずみがはんだバンプ全体に繰り返し集中すると、はんだバンプにクラックが発生して破断に至り、半導体装置としての機能が停止してしまうことが従来から懸念されている。従って、はんだ接合部における耐疲労強度の向上対策を講じることにより、半導体パッケージ並びにそれをプリント配線基板に実装した半導体装置の疲労寿命の向上を図る必要がある。   Due to the structure of this semiconductor device, the stress and strain generated due to the difference in coefficient of linear expansion of the components of the semiconductor package and the printed wiring board when the electronic device is in operation and the power supply is turned on and off. When concentrated repeatedly on the entire bump, there has been a concern that the solder bump will crack and break, and the function of the semiconductor device will stop. Therefore, it is necessary to improve the fatigue life of the semiconductor package and the semiconductor device in which the semiconductor package is mounted on the printed wiring board by taking measures to improve the fatigue strength at the solder joint.

そのための対策の１つに、はんだバンプとその接合対象との接合角度が鈍角となるように形成せしめることではんだ接合部の対疲労強度を向上させることが知られている。図６に示すように従来の太鼓型形状のはんだバンプの場合、半導体パッケージの配線パターン３やプリント配線基板の配線電極１１とはんだバンプとの接合角が鋭角となり、はんだ接合部に応力やひずみが集中し易いために、はんだバンプが破壊し易いという問題があった。   As one of countermeasures for this, it is known that the anti-fatigue strength of the solder joint portion is improved by forming the solder bump and the bonding target so that the joint angle becomes an obtuse angle. As shown in FIG. 6, in the case of a conventional drum-shaped solder bump, the bonding angle between the wiring pattern 3 of the semiconductor package or the wiring electrode 11 of the printed wiring board and the solder bump becomes an acute angle, and stress or strain is applied to the solder joint. There is a problem that solder bumps are easily broken because they are easy to concentrate.

そこで、半導体パッケージの配線パターンやプリント配線基板の配線電極と、はんだバンプとの接合角が鈍角になるような形状、即ち、鼓型形状に形成せしめることにより、はんだ接合部に掛かる応力やひずみを分散させ破壊しにくくすることが可能となる。   Therefore, the stress and strain applied to the solder joints can be reduced by forming the wire pattern of the semiconductor package or the wiring electrode of the printed circuit board and the solder bump into an obtuse angle, that is, a drum shape. It can be dispersed and made difficult to break.

例えば、（特許文献１において、図４及び図５に示すように、半導体パッケージとプリント配線基板との間に弾性体を介在させて、前記弾性体の圧縮変形を利用してはんだバンプを鼓型形状に形成する方法が開示されている。即ち、図４に示すように、半導体パッケージ５０をプリント配線基板６０に実装する際に、半導体パッケージ５０とプリント配線基板６０との間にはんだバンプ９とは他に弾性体１５を介在させ、配線パターン３の位置がプリント配線基板６０の配線電極１１上に対応するように、吸着器具１６で保持して半導体パッケージ５０を位置決めしてプリント配線基板６０に搭載した後に、吸着器具１６によって半導体パッケージ５０を加圧し、弾性体１５を圧縮変形させる第１工程と、図５に示すように、この状態ではんだバンプ９を加熱溶融している最中に、吸着器具１６を解除させて弾性体１５の圧縮変形を解除させることにより、はんだバンプ９の形状を鼓型形状に形成する第２工程で構成されている。
特開平１１−２７４６８２号公報 For example (in Patent Document 1, as shown in FIG. 4 and FIG. 5, an elastic body is interposed between a semiconductor package and a printed wiring board, and solder bumps are drum-shaped using the compression deformation of the elastic body. 4, a method for forming a semiconductor package 50 is mounted between the semiconductor package 50 and the printed wiring board 60, as shown in FIG. In addition, the elastic body 15 is interposed, and the semiconductor package 50 is positioned by holding the suction package 16 so that the position of the wiring pattern 3 corresponds to the wiring electrode 11 of the printed wiring board 60, and the printed wiring board 60 is positioned. After mounting, the semiconductor package 50 is pressurized by the suction device 16 and the elastic body 15 is compressed and deformed. In this state, as shown in FIG. While the bump 9 is being heated and melted, the suction device 16 is released to release the compression deformation of the elastic body 15, thereby forming the solder bump 9 into a drum shape. Yes.
JP 11-274682 A

しかしながら、上記従来の方法は、半導体パッケージとプリント配線基板との間にはんだバンプとは他に弾性体を介在させた状態で、半導体パッケージをプリント配線基板に実装しているため、半導体パッケージとプリント配線基板との電気的接続に直接関与しない弾性体を設置するためのスペースが必要となり、そのスペース分だけ半導体パッケージが大型化し、電子機器の小型化を妨げることになる。弾性体を設置しない場合と同一の半導体パッケージ面積で実現させるにしても、同じ数だけのはんだバンプを配列させるには、例えば、バンプピッチを更に密にしなければならず、電気的接続の面から信頼性が高いとはいえない。   However, since the conventional method mounts the semiconductor package on the printed wiring board with an elastic body in addition to the solder bump between the semiconductor package and the printed wiring board, the semiconductor package and the printed wiring board A space for installing an elastic body that is not directly involved in the electrical connection with the wiring board is required, and the semiconductor package is enlarged by that amount, thereby preventing the electronic device from being downsized. Even if it is realized with the same semiconductor package area as when no elastic body is installed, in order to arrange the same number of solder bumps, for example, the bump pitch must be made denser, from the viewpoint of electrical connection It is not reliable.

又、半導体パッケージを加圧・保持・解除することにより弾性体の変形をコントロールして、はんだバンプを鼓型形状に形成せしめるための大規模で複雑な吸着器具が必要となり、コストも増加する。   Further, a large-scale and complicated suction device for controlling the deformation of the elastic body by pressurizing, holding, and releasing the semiconductor package to form the solder bumps in a drum shape is required, and the cost also increases.

本発明は、上記の問題に鑑みてなされたもので、半導体パッケージ及びそれをプリント配線基板に実装した半導体装置にこれらの構成部材以外の部材を付与することなく、且つ、簡単な方法で半導体パッケージの配線パターンやプリント配線基板の配線電極とはんだバンプとの接合角を鋭角にし、概ね、鼓型形状に形成せしめることで、はんだ接合部の耐疲労強度を向上させ、半導体パッケージ、並びに、それをプリント配線基板に実装した半導体装置の寿命を改善することを目的としている。   The present invention has been made in view of the above problems, and a semiconductor package and a semiconductor device in which the semiconductor package is mounted on a printed wiring board are provided with a member other than these constituent members and in a simple method. By making the joint angle between the wiring pattern of the printed circuit board and the wiring electrode of the printed wiring board and the solder bump an acute angle, and forming it in a generally drum shape, the fatigue resistance of the solder joint is improved. The object is to improve the life of a semiconductor device mounted on a printed wiring board.

上記本発明の目的を達成する本発明の構成は、絶縁性部材と、前記絶縁性部材の一方表面に搭載された半導体素子と、前記絶縁性部材の一方表面に搭載され、且つ、前記半導体素子とを電気的に接続する配線パターンと、前記絶縁性部材に設けられた半導体素子側開口部を通じて前記配線パターンに接合された外部接続端子と、前記半導体素子周辺をコーディングするモールド樹脂材とを有する半導体パッケージを、絶縁性基板と、前記絶縁性基板の一方表面に搭載され、且つ、前記半導体パッケージに装着された前記外部接続端子を電気的に接続する配線電極と、前記絶縁性基板の一方表面をコーディングする絶縁性保護層と、前記配線電極の位置に対応して前記絶縁保護層に設けられたプリント配線基板側開口部とを有するプリント配線基板に実装した半導体装置において、前記半導体素子側開口部と前記プリント配線基板側開口部はその断面が前記はんだバンプ中心部に近い方の辺の長さをもう一方側の辺の長さ以下に短くした四辺形であることを特徴とする。   The configuration of the present invention for achieving the object of the present invention includes an insulating member, a semiconductor element mounted on one surface of the insulating member, and mounted on one surface of the insulating member, and the semiconductor element A wiring pattern that electrically connects to the wiring pattern, an external connection terminal joined to the wiring pattern through a semiconductor element side opening provided in the insulating member, and a mold resin material that codes the periphery of the semiconductor element. A semiconductor package is mounted on an insulating substrate, one surface of the insulating substrate, and a wiring electrode for electrically connecting the external connection terminal mounted on the semiconductor package, and one surface of the insulating substrate And a printed wiring board side opening provided in the insulating protective layer corresponding to the position of the wiring electrode. In a semiconductor device mounted on a board, the side of the semiconductor element side opening and the printed wiring board side opening are closer to the length of the side closer to the center of the solder bump than the length of the other side. It is a short quadrilateral.

本発明によれば、半導体パッケージとプリント配線基板とを接続するはんだバンプが、半導体素子側開口部やプリント配線基板側開口部の形状に追従して、半導体パッケージの配線パターンやプリント配線基板の配線電極とはんだバンプとの接合角が鈍角になり、はんだバンプは概ね鼓型形状を形成する。上記構成の半導体装置は、半導体パッケージ及びプリント配線基板の構成部材の線膨張係数の相違に起因して発生する応力やひずみが分散される構造となり、クラックの発生を阻害することができ、はんだ接合部における信頼性および耐疲労強度が向上し、半導体装置の寿命が改善される。又、新たに別の材料を付与したり、吸着器具のようなコストの掛かる大規模で複雑な装置を用いることなく、既存の構成部材の形状を変化させるだけで、信頼性の高い半導体装置を提供することが可能である。   According to the present invention, the solder bumps connecting the semiconductor package and the printed wiring board follow the shape of the opening on the semiconductor element side or the opening on the printed wiring board, and the wiring pattern of the semiconductor package or the wiring of the printed wiring board The joint angle between the electrode and the solder bump becomes an obtuse angle, and the solder bump forms a generally drum shape. The semiconductor device having the above structure has a structure in which stress and strain generated due to the difference in linear expansion coefficients of the constituent members of the semiconductor package and the printed wiring board are dispersed, and can inhibit the occurrence of cracks, and solder bonding The reliability and fatigue resistance strength of the part are improved, and the life of the semiconductor device is improved. In addition, a highly reliable semiconductor device can be obtained simply by changing the shape of the existing components without adding a new material or using a large-scale and complicated device such as an adsorption device. It is possible to provide.

又、図７に示すように、絶縁性部材と絶縁性保護層離との距離Ａとはんだバンプの高さＢとの比Ａ／Ｂを０〜０．８としたことを特徴とする。   Further, as shown in FIG. 7, the ratio A / B between the distance A between the insulating member and the insulating protective layer and the height B of the solder bump is set to 0 to 0.8.

本発明によれば、絶縁性部材と絶縁性保護層との距離とはんだバンプの高さとの比を０〜０．８の適切な値に設定することにより、はんだバンプ高さやはんだバンプの形状などを最適な状態に形成することが可能となる。   According to the present invention, by setting the ratio between the distance between the insulating member and the insulating protective layer and the height of the solder bump to an appropriate value of 0 to 0.8, the solder bump height, the shape of the solder bump, etc. Can be formed in an optimum state.

以上から、本発明によれば、はんだ接合部の耐疲労強度を高めることができ、結果として半導体パッケージ、並びに、それをプリント配線基板に実装した半導体装置の寿命を飛躍的に延長することができる。   As described above, according to the present invention, the fatigue strength of the solder joint can be increased, and as a result, the life of the semiconductor package and the semiconductor device in which the semiconductor package is mounted on the printed wiring board can be dramatically extended. .

本発明によれば、半導体パッケージとプリント配線基板とを接続するはんだバンプが、半導体素子側開口部やプリント配線基板側開口部の形状に追従して、半導体パッケージの配線パターンやプリント配線基板の配線電極とはんだバンプとの接合角が鈍角になり、はんだバンプは概ね鼓型形状を形成するため、半導体パッケージ及びプリント配線基板の構成部材の線膨張係数の相違に起因して発生する応力やひずみが分散される構造となり、クラックの発生を阻害することができ、はんだ接合部における信頼性及び耐疲労強度が向上し半導体装置の寿命が改善される。 According to the present invention, the solder bumps connecting the semiconductor package and the printed wiring board follow the shape of the opening on the semiconductor element side or the opening on the printed wiring board, and the wiring pattern of the semiconductor package or the wiring of the printed wiring board The bonding angle between the electrodes and the solder bumps becomes obtuse, and the solder bumps generally form a drum shape, so that stress and strain generated due to differences in the linear expansion coefficients of the components of the semiconductor package and the printed wiring board It becomes a dispersed structure, can inhibit the generation of cracks, improves the reliability and fatigue resistance at the solder joints, and improves the life of the semiconductor device.

又、絶縁性部材と絶縁性保護層との距離とはんだバンプの高さとの比を０〜０．８の適切な値に設定することにより、はんだバンプ高さやはんだバンプの形状などを最適な状態に形成することが可能となる。   In addition, by setting the ratio between the distance between the insulating member and the insulating protective layer and the height of the solder bump to an appropriate value between 0 and 0.8, the solder bump height, the shape of the solder bump, etc. are in an optimal state. Can be formed.

又、新たに別の材料を付与したり吸着器具のようなコストの掛かる大規模で複雑な装置を用いることなく、既存の構成部材の形状を変化させるだけで、信頼性の高い半導体装置を提供することが可能である。   In addition, a highly reliable semiconductor device can be provided simply by changing the shape of existing components without adding new materials or using a large-scale and complicated device such as an adsorption device. Is possible.

以上から、本発明によれば、はんだ接合部の耐疲労強度を高めることができ、結果として半導体パッケージ、並びに、それをプリント配線基板に実装した半導体装置の寿命を飛躍的に延長することができる。   As described above, according to the present invention, the fatigue strength of the solder joint can be increased, and as a result, the life of the semiconductor package and the semiconductor device in which the semiconductor package is mounted on the printed wiring board can be dramatically extended. .

以下、本発明の実施の形態を図面に基づいて詳細に説明する。以下の図面の記載において、同一又は類似の部分には同一の記号を付与している。
＜実施の形態１＞ Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description of the drawings, the same symbols are assigned to the same or similar parts.
<Embodiment 1>

図１は本発明の実施の形態１に係る半導体装置の模式的な断面図である。又、図８は本発明の実施の形態１に係る半導体装置における、はんだ接合部の拡大図である。図１及び図８に示すように、本発明の実施の形態１に係る半導体パッケージは、絶縁性部材２の一方表面の中央部にダイボンド材４により半導体素子１を搭載し、この半導体素子１周辺を封止樹脂材８により封止した構造をしている。半導体素子１の一方表面にはその周辺に沿って複数のボンディングパッド６が設けられ、これらのボンディングパッド６と絶縁性部材２の一方表面に設けられた複数の配線パターン３が、それぞれボンディングワイヤー７で電気的に接続される。そして、絶縁性部材２に設けられた半導体素子側開口部１３を通じて配線パターン３とはんだバンプ９が電気的に接合される。   FIG. 1 is a schematic cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention. FIG. 8 is an enlarged view of a solder joint in the semiconductor device according to the first embodiment of the present invention. As shown in FIGS. 1 and 8, in the semiconductor package according to the first embodiment of the present invention, the semiconductor element 1 is mounted on the central portion of one surface of the insulating member 2 by the die bond material 4, and the periphery of the semiconductor element 1 Is sealed with a sealing resin material 8. A plurality of bonding pads 6 are provided on one surface of the semiconductor element 1 along the periphery thereof, and the bonding pads 6 and a plurality of wiring patterns 3 provided on one surface of the insulating member 2 are respectively bonded to bonding wires 7. Is electrically connected. Then, the wiring pattern 3 and the solder bump 9 are electrically joined through the semiconductor element side opening 13 provided in the insulating member 2.

絶縁性部材２は、具体的には絶縁性のエラストマーであるポリイミド樹脂である。ポリイミド樹脂以外でも電気的絶縁性を有する材料であれば何でも良い。例えば、エポキシ樹脂、ガラスエポキシ樹脂、ＢＴ（ビスマレイド・トリアジン）樹脂、アラミド樹脂等がある。はんだバンプ９の一部はアニール時の融解によって半導体素子側開口部１３内に進入し、配線パターン３の一部である電極部と電気的に接合し凝固して埋設される。   The insulating member 2 is specifically a polyimide resin that is an insulating elastomer. Any material other than polyimide resin may be used as long as it is an electrically insulating material. For example, there are epoxy resin, glass epoxy resin, BT (bismaleide triazine) resin, aramid resin, and the like. A part of the solder bump 9 enters the semiconductor element side opening 13 by melting at the time of annealing, and is electrically bonded to the electrode part which is a part of the wiring pattern 3 and solidified and buried.

配線パターン３は低抵抗導電材料である銅から成っている。又、ボンディングワイヤー７も低抵抗導電材料である金或はアルミニウムから成っている。このように、配線パターン３、或は、ボンディングワイヤー７の材料としては、ハンダと濡れが良く電気的に低抵抗な導電体が好ましく用いられる。   The wiring pattern 3 is made of copper which is a low resistance conductive material. The bonding wire 7 is also made of gold or aluminum which is a low resistance conductive material. Thus, as the material of the wiring pattern 3 or the bonding wire 7, a conductor that has good wettability with solder and low electrical resistance is preferably used.

封止樹脂材８は具体的にはエポキシ樹脂である。エポキシ樹脂以外でも電気的絶縁性を有する材料であれば何でも良い。例えば、ポリイミド樹脂、フェノール樹脂等があり、前記絶縁性部材２と同一材料であっても良い。   Specifically, the sealing resin material 8 is an epoxy resin. Any material other than an epoxy resin may be used as long as it is an electrically insulating material. For example, there are polyimide resin, phenol resin, and the like, and the same material as the insulating member 2 may be used.

以下、本発明の実施の形態１における半導体素子側開口部について説明する。   Hereinafter, the semiconductor element side opening in the first embodiment of the present invention will be described.

半導体素子１が搭載されている絶縁性部材２には、配線パターン３とはんだバンプ９とを電気的接合させるために、半導体素子側開口部１３が設けられている。前記半導体素子側開口部１３は逆テーパ形状を形成している。即ち、半導体素子側開口部１３の断面は、はんだバンプ中心部に近い方の辺の長さをもう一方側の辺の長さ以下に短くした四辺形としている。本発明の絶縁性部材２の半導体素子側開口部１３の開け方は、幾つかの方法があり、例えば、絶縁性部材２上にレジスト材を塗布、露光、現像した後、エッチング液によるウエットエッチング或は
Ｏ２ プラズマ によるドライエッチングにより半導体素子側開口部を形成した後、レジストを剥離する方法や、レーザー光を照射して、絶縁性部材を溶融、分解させ半導体素子側開口部をあける方法等がある。 The insulating member 2 on which the semiconductor element 1 is mounted is provided with a semiconductor element side opening 13 in order to electrically connect the wiring pattern 3 and the solder bump 9. The semiconductor element side opening 13 has a reverse taper shape. That is, the cross section of the semiconductor element side opening 13 is a quadrilateral in which the length of the side closer to the center of the solder bump is shorter than the length of the other side. There are several methods for opening the semiconductor element side opening 13 of the insulating member 2 of the present invention. For example, after applying a resist material on the insulating member 2, exposing and developing, wet etching with an etching solution is performed. Alternatively, after forming the opening on the semiconductor element side by dry etching using O2 plasma, a method of peeling the resist, or a method of irradiating a laser beam to melt and decompose the insulating member to open the opening on the semiconductor element side, etc. is there.

以上の方法により、半導体素子側開口部１３をその断面が長方形か或は台形になるように形成することが可能である。但し、半導体素子側開口部１３の断面が台形になる場合は、半導体素子側の辺の長さが、プリント配線基板側の辺の長さ以上に長くなるように絶縁性部材を設置して、半導体パッケージを形成すれば良い。   By the above method, it is possible to form the semiconductor element side opening 13 so that its cross section is rectangular or trapezoidal. However, if the cross section of the semiconductor element side opening 13 is trapezoidal, install an insulating member so that the length of the side on the semiconductor element side is longer than the length of the side on the printed wiring board side, A semiconductor package may be formed.

以下、本発明の実施の形態１におけるプリント配線基板について説明する。   Hereinafter, the printed wiring board in Embodiment 1 of this invention is demonstrated.

本発明の実施の形態１におけるプリント配線基板は、絶縁性基板１０の一方表面に半導体パッケージのはんだバンプ９の配置に対応したプリント配線基板側開口部１４が設けられ、その位置に配線電極１１が配置され、絶縁性基板１０の一方表面は絶縁性保護層１２でコーディングされている。   In the printed wiring board according to Embodiment 1 of the present invention, a printed wiring board side opening 14 corresponding to the arrangement of the solder bumps 9 of the semiconductor package is provided on one surface of the insulating substrate 10, and the wiring electrode 11 is provided at that position. The one surface of the insulating substrate 10 is coded with an insulating protective layer 12.

絶縁性基板１０は、具体的には、絶縁性材料であるガラスエポキシ樹脂である。又、配線電極１１は低抵抗導電材料である銅から成っている。絶縁性基板１０の材料は、電気的絶縁性を有する材料であれば何でも良く、例えば、紙フェノール樹脂、ガラスエポキシ樹脂、ポリイミド樹脂、ＢＴ（ビスマレイド・トリアジン）樹脂などがある。配線電極１１の材料としては、はんだと濡れが良く、電気的に低抵抗な導電体が好ましく用いられる。絶縁性保護層１２の材料は、電気的絶縁性を有する材料であれば何でも良く、半導体パッケージを構成する絶縁性部材２と同一材料であっても良い。   Specifically, the insulating substrate 10 is a glass epoxy resin which is an insulating material. The wiring electrode 11 is made of copper which is a low resistance conductive material. The material of the insulating substrate 10 may be anything as long as it is an electrically insulating material. Examples thereof include paper phenol resin, glass epoxy resin, polyimide resin, and BT (bismaleide triazine) resin. As a material for the wiring electrode 11, a conductor that has good wettability with solder and is electrically low in resistance is preferably used. The insulating protective layer 12 may be made of any material having electrical insulation properties, and may be the same material as the insulating member 2 constituting the semiconductor package.

以下、本発明の実施の形態１におけるプリント配線基板側開口部について説明する。   Hereinafter, the printed wiring board side opening in the first embodiment of the present invention will be described.

絶縁性基板１０の一方表面にコーディングする絶縁性保護層１２には、リフロー工程における実装において配線電極１１と半導体パッケージのはんだバンプ９とを電気的接合させるために、プリント配線基板側開口部１４が設けられている。前記プリント配線基板側側開口部１４は逆テーパ形状を形成している。即ち、プリント配線基板側開口部１４は、その断面が絶縁性基板側の辺の長さをもう一方側の辺の長さ以上に長くした四辺形としている。本発明の絶縁性保護層１２のプリント配線基板側開口部１４の開け方は、幾つかの方法があり、例えば、絶縁性保護層１２上にレジスト材を塗布、露光、現像した後、エッチング液によるウエットエッチング或はＯ２ プラズマによるドライエッチングによりプリント配線基板側開口部１４を形成した後、レジストを剥離する方法や、レーザー光を照射して、絶縁性保護層を溶融、分解させ、プリント配線基板側開口部を開ける方法等がある。   The insulating protective layer 12 coded on one surface of the insulating substrate 10 has an opening 14 on the printed wiring board side in order to electrically connect the wiring electrode 11 and the solder bump 9 of the semiconductor package in the mounting in the reflow process. Is provided. The printed wiring board side opening 14 has a reverse taper shape. That is, the printed wiring board side opening 14 has a quadrilateral shape whose cross section is longer than the length of the other side on the side of the insulating board. There are several methods for opening the printed wiring board side opening 14 of the insulating protective layer 12 of the present invention. For example, after applying, exposing and developing a resist material on the insulating protective layer 12, an etching solution After the printed wiring board side opening 14 is formed by wet etching with O2 or dry etching with O2 plasma, the resist is peeled off, or the insulating protective layer is melted and decomposed by irradiating a laser beam. There is a method of opening the side opening.

以上の方法により、プリント配線基板側開口部１４をその断面が長方形か、或は、台形になるように形成することが可能である。但し、プリント配線基板側開口部１４の断面が台形になる場合は、半導体素子側の辺の長さがプリント配線基板側の辺の長さ以下に短くなるように絶縁性保護層１２を設置してプリント配線基板を形成すれば良い。   By the above method, it is possible to form the printed wiring board side opening 14 so that its cross section is rectangular or trapezoidal. However, when the cross section of the printed wiring board side opening 14 is trapezoidal, the insulating protective layer 12 is installed so that the length of the side on the semiconductor element side is shorter than the length of the side on the printed wiring board side. A printed wiring board may be formed.

本発明の実施の形態１によれば、半導体パッケージとプリント配線基板とを接続するはんだバンプが、半導体素子側開口部１３やプリント配線基板側開口部１４の形状に追従して、半導体パッケージの配線パターン３やプリント配線基板１１の配線電極とはんだバンプとの接合角が鈍角になり、図８に示すようにはんだバンプは概ね鼓型形状を形成する。半導体素子側開口部１３の断面が長方形の場合でも、絶縁性部材２ははんだバンプ９に濡れないため、ハンダバンプ９の一部はアニール時の融解によって半導体素子側開口部１３内に進入し、電極パターン３と電気的に接合し凝固して埋設されるときに、配線パターン３とはんだバンプ９との接合角は鈍角となる。   According to the first embodiment of the present invention, the solder bumps connecting the semiconductor package and the printed wiring board follow the shapes of the semiconductor element side opening 13 and the printed wiring board side opening 14 to wire the semiconductor package. The joint angle between the wiring electrode of the pattern 3 or the printed wiring board 11 and the solder bump becomes an obtuse angle, and the solder bump forms a generally drum shape as shown in FIG. Even when the cross section of the semiconductor element side opening 13 is rectangular, the insulating member 2 does not get wet with the solder bump 9, so that a part of the solder bump 9 enters the semiconductor element side opening 13 by melting during annealing, and the electrode When the wiring pattern 3 and the solder bump 9 are buried by being electrically bonded to the pattern 3 and solidified, the bonding angle becomes an obtuse angle.

一方、プリント配線基板側開口部１４の断面が長方形の場合でも同様の理由により、リフロー工程において配線電極１１とプリント配線基板側開口部１４との接合角が鈍角となった状態で半導体装置が形成される。上記構成の半導体装置は、半導体パッケージ及びプリント配線基板の構成部材の線膨張係数の相違に起因して発生する応力やひずみが分散される構造となり、クラックの発生を阻害することができ、はんだ接合部における信頼性及び耐疲労強度が向上し半導体装置の寿命が改善される。又、新たに別の材料を付与したり、吸着器具のような、コストの掛かる大規模で複雑な装置を用いることなく、既存の構成部材の形状を変化させるだけで、信頼性の高い半導体装置を提供することが可能である。
＜実施の形態２＞ On the other hand, even when the cross section of the printed wiring board side opening 14 is rectangular, for the same reason, the semiconductor device is formed in a state where the junction angle between the wiring electrode 11 and the printed wiring board side opening 14 becomes an obtuse angle in the reflow process. Is done. The semiconductor device having the above structure has a structure in which stress and strain generated due to the difference in linear expansion coefficients of the constituent members of the semiconductor package and the printed wiring board are dispersed, and can inhibit the occurrence of cracks, and solder bonding This improves the reliability and fatigue resistance at the portion, thereby improving the life of the semiconductor device. In addition, a highly reliable semiconductor device can be obtained simply by changing the shape of existing components without adding new materials or using costly large-scale and complicated devices such as adsorption devices. Can be provided.
<Embodiment 2>

図２は本発明の実施の形態２に係る半導体装置の模式的な断面図である。又、図９は本発明の実施の形態２に係る半導体装置におけるはんだ接合部の拡大図である。図２及び図９は絶縁性部材と絶縁性保護層との距離Ａと、前記はんだバンプの高さＢとの比Ａ／Ｂを０.１としたことを特徴とする半導体装置である。   FIG. 2 is a schematic cross-sectional view of a semiconductor device according to Embodiment 2 of the present invention. FIG. 9 is an enlarged view of a solder joint in the semiconductor device according to the second embodiment of the present invention. 2 and 9 show a semiconductor device characterized in that the ratio A / B between the distance A between the insulating member and the insulating protective layer and the height B of the solder bump is set to 0.1.

その他の構成については、実施の形態１と同じである。又、半導体素子側開口部１３やプリント配線基板側開口部１４についても実施の形態１と同じである。   Other configurations are the same as those in the first embodiment. The semiconductor element side opening 13 and the printed wiring board side opening 14 are also the same as in the first embodiment.

本発明の実施の形態によれば、半導体パッケージとプリント配線基板とを接続するはんだバンプが、半導体素子側開口部１３やプリント配線基板側開口部１４の形状に追従して、半導体パッケージの配線パターン３やプリント配線基板の配線電極１１とはんだバンプ９との接合角が鈍角になり、図９に示すようにはんだバンプは、鼓型形状を形成する。上記構成の半導体装置は、半導体パッケージ及びプリント配線基板の構成部材の線膨張係数の相違に起因して発生する応力やひずみが分散される構造となり、クラックの発生を阻害することができ、はんだ接合部における信頼性及び耐疲労強度が向上し、半導体装置の寿命が改善される。又、絶縁性部材２と絶縁性保護層１２との距離と、はんだバンプの高さとの比を０．１に設定することで、図９に示すように、はんだバンプ高さを最適にするとともに、はんだバンプを中央部がくびれた鼓型形状に形成できる等、はんだバンプを最適な状態に形成することが可能となる。又、新たに別の材料を付与したり、吸着器具のようなコストの掛かる大規模で複雑な装置を用いることなく、既存の構成部材の形状を変化させるだけで信頼性の高い半導体装置を提供することが可能である。   According to the embodiment of the present invention, the solder bumps connecting the semiconductor package and the printed wiring board follow the shapes of the semiconductor element side opening 13 and the printed wiring board side opening 14 so that the wiring pattern of the semiconductor package is obtained. 3 and the bonding angle between the wiring electrode 11 of the printed wiring board and the solder bump 9 become an obtuse angle, and the solder bump forms a drum shape as shown in FIG. The semiconductor device having the above structure has a structure in which stress and strain generated due to the difference in linear expansion coefficients of the constituent members of the semiconductor package and the printed wiring board are dispersed, and can inhibit the occurrence of cracks, and solder bonding This improves the reliability and fatigue resistance strength of the part and improves the life of the semiconductor device. Further, by setting the ratio of the distance between the insulating member 2 and the insulating protective layer 12 and the height of the solder bump to 0.1, the solder bump height is optimized as shown in FIG. The solder bumps can be formed in an optimal state, for example, the solder bumps can be formed in a drum shape with a constricted central portion. In addition, a highly reliable semiconductor device can be provided by simply changing the shape of the existing components without adding new materials or using a large-scale and complicated device such as an adsorption device. Is possible.

本発明者の検討により、図１０に示すように、絶縁性部材２と絶縁性保護層１２との距離Ａと前記はんだバンプの高さＢとの比Ａ／Ｂを０〜０．８としたときに、半導体パッケージの配線パターン３やプリント配線基板の配線電極１１とはんだバンプとの接合角が鈍角になり、はんだバンプが、概ね、鼓型形状を形成し疲労寿命の改善に大きく寄与することが判明した。   According to the study of the present inventor, as shown in FIG. 10, the ratio A / B between the distance A between the insulating member 2 and the insulating protective layer 12 and the height B of the solder bump is set to 0 to 0.8. Sometimes, the bonding angle between the wiring pattern 3 of the semiconductor package or the wiring electrode 11 of the printed wiring board and the solder bump becomes an obtuse angle, and the solder bump generally forms a drum shape and greatly contributes to the improvement of the fatigue life. There was found.

以上から、本発明によれば、はんだ接合部の耐疲労強度を高めることができ、結果として半導体パッケージ、並びに、それをプリント配線基板に実装した半導体装置の寿命を飛躍的に延長することができる。   As described above, according to the present invention, the fatigue strength of the solder joint can be increased, and as a result, the life of the semiconductor package and the semiconductor device in which the semiconductor package is mounted on the printed wiring board can be dramatically extended. .

尚、上述の実施の形態は、本発明の好適な実施の一例である。但し、これに限定されるものではなく、本発明の要旨を逸脱しない範囲内において、種々変形実施が可能である。   The above-described embodiment is an example of a preferred embodiment of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention.

本発明の実施の形態１に係る半導体装置を示す模式的断面図である。1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態２に係る半導体装置を示す模式的断面図である。It is typical sectional drawing which shows the semiconductor device which concerns on Embodiment 2 of this invention. 従来の半導体装置を示す模式的断面図である。It is typical sectional drawing which shows the conventional semiconductor device. 従来の半導体装置を示す模式的断面図である。It is typical sectional drawing which shows the conventional semiconductor device. 従来の半導体装置を示す模式的断面図である。It is typical sectional drawing which shows the conventional semiconductor device. 従来の半導体装置におけるはんだ接合部の拡大図である。It is an enlarged view of the solder joint part in the conventional semiconductor device. 本発明の半導体装置におけるはんだ接合部の拡大図である。It is an enlarged view of the solder joint part in the semiconductor device of this invention. 本発明の実施の形態１に係る半導体装置におけるはんだ接合部の拡大図である。It is an enlarged view of the solder joint part in the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態２に係る半導体装置におけるはんだ接合部の拡大図である。It is an enlarged view of the solder joint part in the semiconductor device which concerns on Embodiment 2 of this invention. 絶縁性部材と絶縁性保護層との距離と、はんだバンプの高さとの比と、疲労寿命に影響を及ぼす非弾性ひずみ振幅との関係を示すグラフである。It is a graph which shows the relationship between the ratio of the distance of an insulating member and an insulating protective layer, the height of a solder bump, and the inelastic strain amplitude which affects a fatigue life.

符号の説明Explanation of symbols

１ 半導体素子
２ 絶縁性部材
３ 配線パターン
４ ダイボンド材
５ 絶縁性保護膜
６ ボンディングパッド
７ ボンディングワイヤー
８ 封止樹脂材
９ 外部接続端子（はんだバンプ）
１０ 絶縁性基板
１１ 配線電極
１２ 絶縁性保護層
１３ 半導体素子側開口部
１４ プリント配線基板側開口部
１５ 弾性体
１６ 吸着器具
５０ 半導体パッケージ
６０ プリント配線基板 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Insulating member 3 Wiring pattern 4 Die-bonding material 5 Insulating protective film 6 Bonding pad 7 Bonding wire 8 Sealing resin material 9 External connection terminal (solder bump)
DESCRIPTION OF SYMBOLS 10 Insulating board | substrate 11 Wiring electrode 12 Insulating protective layer 13 Semiconductor element side opening part 14 Printed wiring board side opening part 15 Elastic body 16 Adsorption instrument 50 Semiconductor package 60 Printed wiring board

Claims (2)

絶縁性部材と、前記絶縁性部材の一方表面に搭載された半導体素子と、前記絶縁性部材の一方表面に搭載され、且つ、前記半導体素子とを電気的に接続する配線パターンと、前記絶縁性部材に設けられた半導体素子側開口部を通じて前記配線パターンに接合された外部接続端子と、前記半導体素子周辺をコーディングするモールド樹脂材とを有する半導体パッケージを、絶縁性基板と、前記絶縁性基板の一方表面に搭載され、且つ、前記半導体パッケージに装着された前記外部接続端子を電気的に接続する配線電極と、前記絶縁性基板の一方表面をコーディングする絶縁性保護層と、前記配線電極の位置に対応して前記絶縁保護層に設けられたプリント配線基板側開口部とを有するプリント配線基板に実装した半導体装置において、
前記半導体素子側開口部と前記プリント配線基板側開口部はその断面が前記はんだバンプ中心部に近い方の辺の長さをもう一方側の辺の長さ以下に短くした四辺形であることを特徴とする半導体装置。 An insulating member; a semiconductor element mounted on one surface of the insulating member; a wiring pattern mounted on one surface of the insulating member and electrically connecting the semiconductor element; and the insulating material A semiconductor package having an external connection terminal joined to the wiring pattern through a semiconductor element side opening provided in a member and a mold resin material coding around the semiconductor element, an insulating substrate, and an insulating substrate A wiring electrode mounted on one surface and electrically connecting the external connection terminal mounted on the semiconductor package, an insulating protective layer coding one surface of the insulating substrate, and a position of the wiring electrode In a semiconductor device mounted on a printed wiring board having a printed wiring board side opening provided in the insulating protective layer correspondingly,
The semiconductor element side opening and the printed wiring board side opening have a quadrilateral shape whose cross section is shorter than the length of the other side on the side closer to the center of the solder bump. A featured semiconductor device. 前記絶縁性部材と前記絶縁性保護層との距離Ａと前記はんだバンプの高さＢとの比Ａ／Ｂを０〜０．８としたことを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a ratio A / B between a distance A between the insulating member and the insulating protective layer and a height B of the solder bump is set to 0 to 0.8.
JP2004266496A 2004-09-14 2004-09-14 Semiconductor device Withdrawn JP2006086161A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011146625A (en) * 2010-01-18 2011-07-28 Mitsubishi Electric Corp High-frequency circuit board device
JP2013247344A (en) * 2012-05-29 2013-12-09 Canon Inc Stacked-type semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011146625A (en) * 2010-01-18 2011-07-28 Mitsubishi Electric Corp High-frequency circuit board device
JP2013247344A (en) * 2012-05-29 2013-12-09 Canon Inc Stacked-type semiconductor device

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