JP2006080975A - Multiple signal separating method and device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiple signal separating method and a device, which are capable of separating low-order group signals of each channel from time division multiple signals which are multiplexed through synchronization of one or more asynchronous low-order group signals with each other and capable of outputting them in a desired channel arrangement. <P>SOLUTION: The time division multiple signals, which are time-division multiplexed through synchronization of one or more asynchronous low-order group signals that contain information on channel numbers with each other, are separated into the two or more low-order group signals of each channel, the arrangement of the low-order group signals is changed through n×n switches and outputted as channel data, if necessary. Information on the channel numbers contained in the channel data is extracted from the channel data, it is judged whether the channel data arrangement outputted through the n×n switches is a desired one or not, and when it is found that the channel data arrangement is not a desired one, the channel data arrangement outputted through the n×n switches is switched to a desired one. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a multiplexed signal separation method and apparatus for separating each low-order group signal from a time-division multiplexed signal obtained by synchronously multiplexing a plurality of low-order group signals.

  In a long-distance optical communication system using an optical submarine cable or the like, a plurality of land-side line signals (low-order group signals) are accommodated in a submarine terminal device that connects submarine sections. In general, a communication system having a transmission speed of 2.4 Gb / s (for example, SDH: Synchronous Digital Hierarchy) is often used for land-side lines, and therefore, 10 Gb / s for increasing the line capacity between submarine terminal stations. In many cases, the signal (line signal) is transmitted at a transmission speed of. In that case, the submarine terminal equipment accommodates four 2.4 Gb / s land-side lines.

  Also, the submarine terminal device encodes data to be transmitted in accordance with FEC (Forward Error Correction) defined by ITU-T G.709 in order to ensure transmission quality in the submarine section.

  The FEC temporarily stores data to be transmitted in a memory using a clock synchronized with the FEC, converts the transmission speed by reading data from the memory in synchronization with a faster clock, and converts data on the receiving side. This is a method of generating and adding a redundant code for error correction for restoring the error (see Non-Patent Document 1). For example, when encoding data to be transmitted by the (255,239) Reed-Solomon (RS) method, the frame generated by the encoding is redundant at a rate of 16 × 16 = 256 bytes with respect to 16 × 239 = 3824 bytes of data. It is the structure to which the code | symbol was added. At this time, the transmission rate of the frame is 255/239 times the transmission rate of the data to be transmitted. Note that in ITU-T G.709, there is an error correction frame (hereinafter referred to as an FEC frame) in which overhead including a frame configuration, information indicating the head of a frame, or various control information is added to data to be transmitted and a redundant code. It is prescribed.

  As described above, the submarine terminal device accommodates a plurality of signals having a transmission speed of 2.4 Gb / s (four signals when the transmission speed of the seabed section is 10 Gb / s). Requires a signal multiplexing device for time-division multiplexing, and a receiving side requires a multiple signal demultiplexing device for separating the time-division multiplexed signals.

  It is conceivable to use an SDH demultiplexer that multiplexes and demultiplexes each signal in accordance with the above SDH regulations for the signal multiplexer and the multiple signal demultiplexer. However, when the SDH multiplexer / demultiplexer is used, a signal on the land side line (SDH frame) is terminated at the submarine terminal device and the overhead is rewritten, so that there is a problem that transparency cannot be secured.

  Opposite communication devices that send and receive data using land-side lines and submarine sections usually monitor transmission lines using information in overhead, so rewrite data sent and received on land-side lines in submarine sections. It is essential not to do this, that is, to ensure transparency. If the SDH demultiplexer is used for the submarine terminal device, there is a disadvantage in this respect. Further, since the synchronization of the signals on the plurality of landside lines accommodated by the submarine terminal equipment is not guaranteed, the use of the SDH demultiplexing apparatus also causes inconvenience.

  For this reason, the stuff synchronous multiplexing system is generally used for the signal multiplexing apparatus used in the conventional submarine terminal equipment. The stuff synchronization multiplexing method is a method of temporarily storing received data in a memory, reading out data from the memory using a common clock, synchronizing a plurality of asynchronous signals, and multiplexing each signal after synchronization ( For example, refer nonpatent literature 2). At this time, the difference between writing and reading data to the memory is compensated by using an area (stuff byte) in which dummy data and received data can be written in common.

  However, if the stuff synchronous multiplexing described above is used to synchronously multiplex a plurality of asynchronous signals, overhead and stuff bytes are inserted at the time of stuff multiplexing. Therefore, time division multiplexing for transmitting these information in the submarine section. The signal transmission rate increases and becomes faster than the transmission rate specified by ITU-T G.709. For this reason, various devices (such as LSI) compatible with ITU-T G.709 cannot be used in the signal multiplexing device or the multiplexed signal demultiplexing device, and a dedicated circuit must be manufactured, so the cost of the submarine terminal equipment There was a problem of rising.

In view of such problems, a technique for generating a time-division multiplexed signal having a transmission rate specified in ITU-T G.709 while simultaneously multiplexing a plurality of asynchronous low-order group signals in synchronization is studied. Has been.
ITU-T G.975, "Forward error correction for submarine systems", 10/2000 Edited by Satoshi Yamashita, “Easy Digital Transmission”, Telecommunications Association, Ohmsha, p. 75-79

  As described above, in a signal multiplexing device used in a submarine terminal station device, etc., time division having a transmission rate specified by ITU-T G.709 while simultaneously multiplexing a plurality of asynchronous low-order group signals. Techniques for generating multiple signals are being studied. Therefore, assuming a case where a time division multiplex signal generated by such a technique is received, a multiplex signal demultiplexer for separating a low-order group signal for each channel from the time division multiplex signal is required. .

  In addition, when each low-order group signal which comprises a time division multiplex signal contains each channel information, it is desirable for a multiple signal demultiplexer to output each separated low-order group signal in a desired channel arrangement. Furthermore, since recent communication devices such as submarine terminal devices are strictly required to reduce costs, it is desirable that the multiplex signal demultiplexer can be configured as simply as possible.

  The present invention has been made in order to solve the above-described problems of the prior art. From the time-division multiplexed signal obtained by synchronizing and multiplexing a plurality of asynchronous low-order group signals, the low-order for each channel is provided. An object of the present invention is to provide a multiple signal separation method and apparatus capable of separating group signals and outputting them in a desired channel arrangement.

In order to achieve the above object, a multiple signal separation method according to the present invention separates a plurality of low-order group signals from a time-division multiplexed signal obtained by synchronously multiplexing a plurality of low-order group signals including channel number information. A multiple signal separation method comprising:
Separating the time division multiplexed signal into the plurality of low-order group signals for each channel;
Outputting the low-order group signal through an n × n switch for switching the arrangement of the low-order group signal;
The arrangement of the low-order group signals is rearranged by an n × n switch as necessary, and output.
Extracting the channel number information included in the low-order group signal output from the n × n switch,
It is determined from the arrangement of the channel number whether the arrangement of the low-order group signals output from the n × n switch is a desired arrangement, and when the arrangement of the low-order group signals is not a desired arrangement, Generate a control signal to match the desired sequence,
According to this control signal, the arrangement of channel data output from the n × n switch is switched.

  In the method as described above, channel number information included in each low-order group signal output from the n × n switch is extracted, and the low-order group signal output from the n × n switch is extracted from the channel number array. It is determined whether or not the arrangement is a desired arrangement. When the arrangement of the low-order group signals is not the desired arrangement, the arrangement of the low-order group signals output from the n × n switch by the control signal is the desired arrangement. Therefore, the arrangement of the low-order group signals can be switched by the n × n switch and output in a desired channel arrangement.

On the other hand, the multiplex signal demultiplexing device of the present invention is a multiplex signal demultiplexing device for demultiplexing the plurality of low-order group signals from a time division multiplex signal obtained by synchronously multiplexing a plurality of low-order group signals including channel number information. Because
A signal separator for separating the time division multiplexed signal into the plurality of low-order group signals for each channel;
An n × n switch that receives a plurality of low-order group signals output from the signal separator and switches the arrangement according to a predetermined control signal; and
A plurality of channel extraction units that respectively extract information of the channel numbers included in the low-order group signal output from the n × n switch;
It is determined from the arrangement of the channel numbers extracted by the channel extraction unit whether or not the arrangement of the low-order group signals output from the n × n switch is a desired arrangement, and the arrangement of the low-order group signals is desired A channel identification unit that outputs a control signal for matching with the desired arrangement to the n × n switch,
It is the structure which has.

  In the configuration as described above, channel number information included in each of the low-order group signals output from the n × n switch is extracted by the channel extraction unit, and the channel identification unit extracts the n × n switch from the channel number array. It is determined whether or not the arrangement of the low-order group signals output from is a desired arrangement, and when the arrangement of the low-order group signals is not the desired arrangement, the low-order group signal output from the n × n switch by the control signal In order to make the arrangement of the next group signal coincide with the desired arrangement, the arrangement of the low order group signals can be switched by the n × n switch and output in the desired channel arrangement.

  In the multiplex signal demultiplexing method and apparatus of the present invention, if information indicating the channel number is included in each multiplexed low-order group signal, the low-order group signal for each channel is separated from the time division multiplex signal. In addition, the desired channel arrangement can be output.

  Next, the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a first embodiment of a multiple signal demultiplexer according to the present invention.

  The time division multiplexed signal input to the multiplexed signal demultiplexer shown in FIG. 1 is a signal that is time-division-multiplexed by synchronizing a plurality of asynchronous low-order group signals that include information about their own channel numbers.

As shown in FIG. 1, the multiple signal demultiplexer according to the first embodiment performs, for example, serial-parallel conversion on the above-described time division multiplexed signal and outputs in parallel as separated data (low-order group signal) for each channel. The signal separation unit 10 and a plurality (n: n is a positive integer) of separation data output from the signal separation unit 10 are input, and the arrangement is switched according to the control signal supplied from the channel identification unit 40 Output n × n switch 20 and a plurality of channel extraction units 30 ₁ that extract channel numbers included in each of n separated data (hereinafter referred to as channel data) output from n × n switch 20. ˜30 _n and whether the channel number sequence extracted by the channel extraction units 30 ₁ -30 _n matches the desired sequence (hereinafter referred to as the target sequence), and the n × n switch 20 And a channel identification unit 40 for outputting a control signal for matching the arrangement of the channel data output from the target arrangement.

The n channel data output from the n × n switch 20 is output from the n output ports 2 ₁ to 2 _n via the corresponding channel extraction units 30 ₁ to 30 _n . Note that the sequence of time the target sequence, an array of channel data to be output from the output port 2 ₁ to 2 _n, for example, the channel number of each channel data matches all the numbers of the output ports 2 ₁ to 2 _n To do.

  Next, the operation of the multiple signal demultiplexer according to the first embodiment will be described with reference to the drawings.

  FIG. 2 is a flowchart showing a processing procedure of the multiple signal demultiplexer shown in FIG.

  As shown in FIG. 2, when receiving the time division multiplexed signal from the outside, the multiplexed signal demultiplexing apparatus of this embodiment first converts the time division multiplexed signal into a low-order group signal (separated data) for each channel by the signal demultiplexing unit 10. (Step S1).

The arrangement of the separated data output from the signal separation unit 10 is rearranged by the n × n switch 20 as necessary, and is output as channel data (step S2). Further, channel numbers included in the channel data output from the n × n switch 20 are extracted by the channel extraction units 30 ₁ to 30 _n (step S3).

The channel identification unit 40 determines whether or not the channel number extracted by the channel extraction units 30 ₁ to 30 _n matches the target sequence (step S4). If the channel number array matches the target array, the array of channel data output from the n × n switch 20 is maintained (step S5). In that case, channel data is output from the output ports 2 ₁ to 2 _n in a desired arrangement.

On the other hand, if the channel number array does not match the target array, a control signal for matching the channel number array to the target array is supplied from the channel identification unit 40 to the n × n switch 20 and output by the n × n switch 20. The arrangement of channel data to be supplied to the ports 2 _{1 to} 2 _n is switched (step S6).

  For example, when the time division multiplexed signal is composed of ch1, ch2, ch3,..., Chn data, the separated data output from the signal separation unit 10 is not necessarily arranged in order from the ch1 data. One of the n arrangement patterns shown.

  Here, the pattern 1 is the target array, and the separation data is output from the signal separation unit 10 in the order of ch2, ch3,..., That is, the pattern 2, and is the same as the separation data to which the n × n switch 20 in the initial state is input. Assuming that the array of channel data is output, the array of channel data output from the n × n switch 20 is ch2, ch3,..., Chn, ch1 (pattern 2).

At this time, the channel identification unit 40 that has received the channel numbers from the channel extraction units 30 ₁ to 30 _n determines that the arrangement of the channel numbers is the pattern 2 and sets a control signal for switching the pattern 2 to the pattern 1 to n Xn is supplied to the switch 20.

The n × n switch 20 switches the output destination of the channel data according to the control signal received from the channel identification unit 40, and outputs ch1 data, ch2 data, ch3 data,... to the output ports 2 ₁ to 2 _n . , Chn-1 data and chn data are output in the order (pattern 1).

  Next, the configuration and operation of the channel identification unit 40 shown in FIG. 1 will be described in detail with reference to FIG.

  FIG. 3 is a block diagram showing the configuration of the channel identification unit shown in FIG.

In general, in a communication system, there is an error in a received signal due to noise or signal distortion generated in a transmission / reception device or a relay device, or signal degradation in a transmission line. Therefore, the channel extraction units 30 ₁ to 30 _n illustrated in FIG. 1 may not be able to correctly extract the channel number of each channel data. The channel identification unit 40 of the present embodiment outputs a control signal for matching the arrangement of channel data output from the n × n switch 20 with the target arrangement, and there is an error in a part of the extracted channel number. In some cases, even if some channel numbers cannot be extracted, a function for estimating the correct channel number arrangement is provided.

As shown in FIG. 3, the channel identification unit 40 of this embodiment can be assumed to be determined by the channel number detection register 401 in which each channel number extracted by the channel extraction units 30 ₁ to 30 _n is stored and the number of channels. A channel number pattern table 402 in which array patterns of a plurality of channel numbers are registered in advance, a switching pattern register 404 to which bits are assigned corresponding to each array pattern registered in the channel number pattern table 402, and n × n A switching pattern table 405 in which a plurality of control signals for switching the array of channel data output from the switch 20 to the target array is registered in advance, and a control signal registered in the switching pattern table 405 in accordance with the output of the switching pattern register 404 Switch to output to nxn switch 20 The configuration includes a turn selector 406 and an arithmetic processing unit 407 that writes data to the switching pattern register 404 based on the array of channel numbers stored in the channel number detection register 401 and the array pattern registered in the channel number pattern table 402. . The arithmetic processing unit 407 can be realized by, for example, a DSP or a logic circuit, and stores a comparison result between the channel number array stored in the channel number detection register 401 and the array pattern registered in the channel number pattern table 402. A number match detection register 403 is provided.

  The arithmetic processing unit 407 uses an array of channel numbers stored in the channel number detection register 401 (hereinafter referred to as a detection pattern) and an array pattern registered in the channel number pattern table 402 (hereinafter referred to as a registered pattern). Compare each. Then, the number of channel numbers whose arrangement positions coincide with the detection pattern is counted for each registered pattern, and the count result is stored in the channel number coincidence detection register 403.

  The arithmetic processing unit 407 selects the registered pattern having the largest count number based on the count result stored in the channel number match detection register 403, sets the corresponding bit of the switching pattern register 404 to “1”, and others Bit “0”. That is, the registration pattern (pattern 2 in FIG. 3) corresponding to the bit set to “1” in the switching pattern register 404 is the detection pattern.

In this way, when there is an error in a part of the channel numbers extracted by the channel extraction units 30 ₁ to 30 _n by selecting the registered pattern having the largest number of channel numbers whose array positions match the detected pattern. Even when some of the channel numbers cannot be extracted, the correct arrangement of the channel data (low-order group signal) output from the n × n switch 20 can be estimated.

  The switching pattern selector 406 is a control signal corresponding to the bit set to “1” in the switching pattern register 404 among the plurality of control signals registered in the switching pattern table 405 (in FIG. 3, “pattern 2 to pattern 1”). ”) Is selected and output to the n × n switch 20.

  The n × n switch 20 that has received the control signal from the channel identification unit 40 rearranges the array of the separated data into the target array (in this case, pattern 1) according to the control signal, and outputs it as channel data.

  According to the multiplex signal demultiplexing apparatus of this embodiment, channel number information included in each low-order group signal output from the n × n switch 20 is extracted and output from the n × n switch 20 from the array of the channel numbers. It is determined whether or not the arrangement of the low-order group signals is a desired arrangement. When the arrangement of the low-order group signals is not the desired arrangement, the low-order output from the n × n switch 20 by the control signal In order to make the arrangement of the group signals coincide with the desired arrangement, the arrangement of the low-order group signals can be switched by the n × n switch 20 and output in the desired channel arrangement.

  Therefore, if information indicating the channel number is included in each multiplexed low-order group signal, the low-order group signal for each channel is separated from the time division multiplexed signal and further output in a desired channel arrangement. be able to.

  The signal separation unit 10 that separates the time-division multiplexed signal can be realized by, for example, a serial / parallel converter, and is configured to rearrange the arrangement of the low-order group signals using the n × n switch 20. The separation device can be realized relatively easily. Therefore, an increase in device cost is suppressed.

  Further, the number of channel numbers whose arrangement positions match the detection pattern is counted for each registration pattern, and the registration pattern having the largest number of counts is determined as a correct arrangement of the detection patterns, thereby performing a low-order group Even when some of the channel numbers extracted from the signal are erroneous or when some of the channel numbers cannot be extracted, the correct arrangement of the low-order group signals output from the n × n switch 20 can be estimated.

(Second Embodiment)
As described above, since there is an error in the received signal in the communication system, there is a possibility that the channel number cannot be correctly extracted by the channel extraction unit. The second embodiment proposes another method for estimating the correct arrangement of channel data when some of the extracted channel numbers are erroneous or when some of the channel numbers cannot be extracted. In the first embodiment, the channel number coincidence detection register 403 compares the detection pattern with the registered pattern only once. In the second embodiment, the detection pattern and the registered pattern are compared multiple times. .

  FIG. 4 is a block diagram showing the configuration of the second embodiment of the multiple signal demultiplexer according to the present invention.

As shown in FIG. 4, the multiple signal demultiplexer according to the second embodiment has a plurality of channel number coincidence detections for storing the comparison result of the detection pattern and the registered pattern in the arithmetic processing unit 707 of the channel identification unit 70. The registers 703 _{1 to} 703 _m (m is a positive integer) are provided, and the processing procedure of the arithmetic processing unit 707 is different from that of the first embodiment. Since other configurations and operations are the same as those in the first embodiment, the description thereof is omitted.

The arithmetic processing unit 707 included in the channel identification unit 70 of the present embodiment first compares the detection pattern stored in the channel number detection register 701 with the registered pattern registered in the channel number pattern table 702, and matches the detection pattern. It is determined whether there is a registered pattern. When there is a registered pattern that matches the detection pattern (pattern 2 in FIG. 4), the arithmetic processing unit 707 sets information indicating the arrangement pattern (for example, sets the corresponding bit to “1”) as the channel number match detection register 703. Store in ₁ . If there is no array pattern that matches the detection pattern, information indicating that there is no match pattern (for example, all bits are set to “0”) is stored in the channel number match detection register 703 ₁ .

If there is no registered pattern that matches the detected pattern, the arithmetic processing unit 707 determines that the detected pattern is unconfirmed, then compares the detected pattern stored in the channel number detection register 701 with the registered pattern, and matches the detected pattern. It is determined again whether there is a registered pattern to be used. The determination result is stored in the channel number match detection register 703 ₂ .

Thereafter, the same processing is repeated, and the registered pattern having the largest number of matches with the detection pattern is determined as the correct arrangement of the detection pattern from the determination results stored in the channel number match detection registers 703 _{1 to} 703 _m .

  When the arrangement of the detection pattern is determined, the arithmetic processing unit 707 sets the bit of the switching pattern register 704 corresponding to the arrangement pattern to “1” and the other bit “0”, as in the first embodiment. Set to. The switching pattern selector 706 selects a control signal corresponding to the bit set to “1” in the switching pattern register 704 from among a plurality of control signals registered in the switching pattern table 705, and outputs the control signal to the n × n switch. .

  Next, the process of the multiple signal demultiplexer according to this embodiment will be specifically described.

  In the following, the arrangement of the separated data output from the signal separation unit is pattern 2 (ch2, ch3,..., Chn-1, chn, ch1), and the target arrangement is pattern 1 (ch1, ch2, ch3, ..., chn-1, chn) will be described as an example.

  In the multiplex signal demultiplexing apparatus of this embodiment, when a time division multiplex signal is received, as in the first embodiment, first, the signal demultiplexer separates the data for each channel, and the channel extractor decouples from the n × n switch. A channel number included in the output channel data is extracted.

  The channel identification unit 70 first determines the arrangement of channel numbers extracted from the time division multiplexed signal received for the first time by the arithmetic processing unit 707. Here, the arrangement of ch2, ch *, ch4,..., Chn-1, chn, ch1 is detected, and ch * is the channel number extracted in error.

In this case, the channel identifying unit 70, the arrangement pattern is determined to be undetermined, and stores the determination result to the channel number match detection register 703 _1. Then, the arrangement of channel numbers extracted from the next received time division multiplexed signal is determined again.

  Here, there is no error in the channel number extracted from the time-division multiplexed signal received at the second time, and the arrangement of ch2, ch3, ch4,..., Chn-1, chn, ch1 is detected, and it is determined as pattern 2 To do.

Channel identifying unit 70 further determines the sequence of the determination result and stores the channel number match detection register 703 _2, then channel number extracted from time-division multiplexed signal received.

  Here, there is no error in the channel number extracted from the time-division multiplexed signal received at the third time, and the arrangement of ch2, ch3, ch4,..., Chn-1, chn, ch1 is detected, and the pattern 2 is determined. To do.

Channel identification unit 70 stores the judgment result to the channel number match detection register 703 _3, the number of matches between the detected pattern from the first round, second third determination results to determine the largest registered pattern as a correct sequence. Here, since it is determined that the pattern 2 matches the pattern 2 in the determination process twice, the correct arrangement of the detection patterns is determined to be the pattern 2.

  When the channel number extracted from the time-division multiplexed signal received at the second time or the third time has an error or when another arrangement pattern is detected, the channel identification unit 70, for example, uses the same pattern (here, the pattern The same process may be repeated until 2) is detected at least twice.

  Also in the second embodiment, if each low-order group signal multiplexed in the same way as in the first embodiment includes information indicating each channel number, the time-division multiplexed signal can be used for each channel. Low-order group signals can be separated and further output in a desired channel arrangement.

  Further, the signal separation unit can be realized by, for example, a serial / parallel converter, and has a configuration in which the arrangement of the low-order group signals is rearranged using an n × n switch, so that the multiple signal separation device can be realized relatively easily. . Therefore, an increase in device cost is suppressed.

  Further, as in the present embodiment, the time division multiplexed signal is received a plurality of times, and the channel number arrangement is repeatedly determined, so that one of the channel numbers extracted from the low-order group signal as in the first embodiment. Even when there is an error in the part, or even when some channel numbers cannot be extracted, the correct arrangement of the low-order group signals output from the n × n switch can be estimated. Moreover, if the determination process shown in this embodiment is combined with the process of the channel identification unit 40 of the first embodiment, the channel identification unit 40 of the first embodiment or the channel identification of the second embodiment. Detection patterns that cannot be determined only by the processing of the unit 70 can be estimated more reliably.

(Third embodiment)
FIG. 5 is a block diagram showing the configuration of the third embodiment of the multiple signal demultiplexer according to the present invention.

As illustrated in FIG. 5, the multiple signal demultiplexer according to the third embodiment includes a plurality of gate units 50 ₁ to 50 _n for outputting or not outputting channel data output from the channel extraction unit to an output port. It is the structure which has further.

The channel identification unit 80 included in the multiplex signal demultiplexer according to the present embodiment uses the control signal to transmit the channel data from the gate units 50 ₁ to 50 _n when the target array channel data is not output to the output port. Stop output. Then, after the channel data array is switched to the target array by the n × n switch, each channel data is output from the gate sections 50 ₁ to 50 _n . In addition, what is necessary is just to perform these processes by the arithmetic processing part with which the channel identification part 80 is provided, for example.

  According to the configuration of the third embodiment, it is possible to prevent channel data different from the target array from being output from the output port.

(Fourth embodiment)
FIG. 6 is a block diagram showing the configuration of the fourth embodiment of the multiple signal demultiplexer according to the present invention.

As shown in FIG. 6, the multiplexed signal demultiplexer according to the fourth embodiment includes error correction decoding units 60 _{1 to} 60 _n and decodes each channel data output from the n × n switch. In this configuration, the original signal (low-order group signal) is restored.

  The time division multiplexed signal input to the multiplexed signal demultiplexer according to the present embodiment has a configuration in which a plurality of FEC frames including channel number information are multiplexed.

  For example, according to the ITU-T G.709 standard, an FEC frame is defined as shown in FIG. 7, and an unused byte RES (Reserved), a control byte JC (Justification Control), and a phase difference absorption byte NJO ( The overhead OH including Negative Justification Opportunity, information bytes (payload) in which low-order group signal data is stored, and redundant bytes in which a redundant code for error correction is stored. The channel number is stored in the unused byte RES of the FEC frame, for example.

  In this embodiment, even when each low-order group signal has an error, the low-order group signal can be correctly restored because error correction is performed using a redundant code included in the FEC frame. Accordingly, errors in channel numbers extracted by the channel extraction unit are also reduced.

  In the first to fourth embodiments, a signal separation unit, an n × n switch, a channel extraction unit, a channel identification unit, a gate unit, and an error correction decoding unit are used as the multiplexed signal separation device. Although the multiple signal demultiplexing device of the present invention has been shown, the processing of each component shown in the first to fourth embodiments, for example, a CPU that performs processing according to a program, You may implement | achieve with information processing apparatuses provided with memory, such as RAM and ROM, the recording medium with which the program was recorded, and other LSI (For example, a bus controller, an I / O controller, a shift register, etc.).

(Fifth embodiment)
FIG. 8 is a block diagram showing a configuration example of the communication system of the present invention.

  As shown in FIG. 8, the communication system of the present invention includes a signal multiplexer 110 that generates a time division multiplexed signal by synchronizing a plurality of low-order group signals including channel number information and time division multiplexing them. For example, the first communication device 100 that transmits the time division multiplexed signal as a line signal via a transmission line 300 provided in, for example, the seabed section, and the time division multiplexed signal received via the transmission line 300 for each channel. And the second communication device 200 including the multiple signal demultiplexing device 210 shown in the first to fourth embodiments for separating the signals into low-order group signals and outputting them in a desired sequence. is there.

  According to the communication system of the present invention, since the multiple signal demultiplexing device 210 included in the second communication device 200 can be realized relatively easily, an increase in device cost is suppressed, and the second communication device 200 and the communication including the same are suppressed. Increase in cost of the entire system can be suppressed.

It is a block diagram which shows the structure of 1st Embodiment of the multiple signal demultiplexer of this invention. 2 is a flowchart showing a processing procedure of the multiple signal demultiplexer shown in FIG. 1. It is a block diagram which shows the structure of the channel identification part shown in FIG. It is a block diagram which shows the structure of 2nd Embodiment of the multiplex signal separation apparatus of this invention. It is a block diagram which shows the structure of 3rd Embodiment of the multiple signal separator of this invention. It is a block diagram which shows the structure of 4th Embodiment of the multiple signal demultiplexer of this invention. It is a schematic diagram showing a format of an error correction frame defined by ITU-T G.709. It is a block diagram which shows the example of 1 structure of the communication system of this invention.

Explanation of symbols

2 _{1 to} 2 _n output port 10 signal separation unit 20 n × n switch 30 ₁ to 30 _n channel extraction unit 40, 70, 80 channel identification unit 50 ₁ to 50 _n gate unit 60 _{1 to} 60 _n error correction decoding unit 100 1 communication apparatus 110 signal multiplexing apparatus 200 second communication apparatus 210 multiplexed signal demultiplexing apparatus 300 transmission line 401, 701 channel number detection register 402, 702 channel number pattern table 403, 703 _{1 to} 703 _m channel number coincidence detection register 404, 704 switching pattern register 405, 705 switching pattern table 406, 706 switching pattern selector 407, 707 arithmetic processing unit

Claims (19)

A multiple signal separation method for separating each of the plurality of low-order group signals from a time-division multiplexed signal obtained by synchronously multiplexing a plurality of low-order group signals including channel number information,
Separating the time division multiplexed signal into the plurality of low-order group signals for each channel;
Outputting the low-order group signal through an n × n switch for switching the arrangement of the low-order group signal;
Extracting the channel number information included in the low-order group signal output from the n × n switch,
It is determined from the arrangement of the channel number whether the arrangement of the low-order group signals output from the n × n switch is a desired arrangement, and when the arrangement of the low-order group signals is not a desired arrangement, Generate a control signal to match the desired sequence,
A multiple signal separation method for switching an array of channel data output from the n × n switch according to the control signal. A detection pattern that is an array of low-order group signals output from the n × n switch is compared with a registration pattern that is an array of a plurality of possible channel numbers registered in advance.
Counting the number of channel numbers whose arrangement positions match the detection pattern for each of the registration patterns, and confirming the registration pattern having the largest count as the correct arrangement of the detection patterns,
The multiple signal demultiplexing method according to claim 1, wherein among the plurality of control signals registered in advance for switching the registered pattern to a desired arrangement, a control signal corresponding to a determined registered pattern is supplied to the n × n switch. . For each time-division multiplexed signal received a plurality of times, a detection pattern that is an array of low-order group signals output from the n × n switch and a registration pattern that is an array of a plurality of possible channel numbers registered in advance Are compared with each other,
Determine whether there is a registered pattern that matches the detected pattern,
From the determination result for each time-division multiplexed signal received a plurality of times, the registered pattern that has the largest number of matches with the detection pattern is determined as the correct arrangement of the detection pattern,
3. The multiplexed signal according to claim 1, wherein among the plurality of control signals registered in advance for switching the registered pattern to a desired arrangement, a control signal corresponding to the determined registered pattern is supplied to the n × n switch. Separation method.   When the low-order group signal output from the n × n switch is not in the desired arrangement, the output of the low-order group signal is stopped using a gate circuit with a predetermined control signal, and the n × n switch The multiplexed signal separation according to any one of claims 1 to 3, wherein after switching the arrangement of the low-order group signals to a desired arrangement, the low-order group signals after switching are output using the gate circuit by the control signal. Method.   When the time division multiplexed signal has a configuration in which a plurality of error correction frames including a redundant code generated from the low-order group signal and the low-order group signal are time-division multiplexed, the output from the n × n switch 5. The multiple signal separation method according to claim 1, wherein the low-order group signal is restored by performing error correction using the redundant code included in the error correction frame. A multiplex signal demultiplexer for respectively demultiplexing the plurality of low-order group signals from a time-division multiplex signal obtained by synchronously multiplexing a plurality of low-order group signals including channel number information,
A signal separator for separating the time division multiplexed signal into the plurality of low-order group signals for each channel;
An n × n switch that receives a plurality of low-order group signals output from the signal separator and switches the arrangement according to a predetermined control signal; and
A plurality of channel extraction units that respectively extract information of the channel numbers included in the low-order group signal output from the n × n switch;
It is determined from the arrangement of the channel numbers extracted by the channel extraction unit whether or not the arrangement of the low-order group signals output from the n × n switch is a desired arrangement, and the arrangement of the low-order group signals is desired A channel identification unit that outputs a control signal for matching with the desired arrangement to the n × n switch,
A multiple signal demultiplexer. The channel identification unit
A detection pattern that is an array of low-order group signals output from the n × n switch is compared with a registration pattern that is an array of a plurality of possible channel numbers registered in advance,
Counting the number of channel numbers whose arrangement positions match the detection pattern for each of the registration patterns, and confirming the registration pattern having the largest count as the correct arrangement of the detection patterns,
7. The multiple signal separation according to claim 6, wherein among the plurality of control signals registered in advance for switching the registered pattern to a desired arrangement, a control signal corresponding to the determined registered pattern is supplied to the n × n switch. apparatus. The channel identification unit
For each of the time-division multiplexed signals received a plurality of times, a detection pattern that is an array of low-order group signals output from the n × n switch and a registration that is an array of a plurality of possible channel numbers registered in advance. Compare with each pattern,
Determine whether there is a registered pattern that matches the detected pattern,
From the determination result for each time-division multiplexed signal received a plurality of times, the registered pattern that has the largest number of matches with the detection pattern is determined as the correct arrangement of the detection pattern,
The multiplexing according to claim 6 or 7, wherein a control signal corresponding to the determined registration pattern is supplied to the n × n switch among a plurality of control signals registered in advance for switching the registration pattern to a desired arrangement. Signal separation device. A plurality of gate units for outputting or not outputting the low-order group signal output through the channel extraction unit;
The channel identification unit
When the low-order group signal output from the n × n switch is not in the desired arrangement, the low-order group signal is stopped at the gate by a predetermined control signal, and the low-order group signal is stopped by the n × n switch. 9. The multiple signal demultiplexing apparatus according to claim 6, wherein after the group signal array is switched to a desired array, a low-order group signal after switching is output to the gate unit by the control signal. The time division multiplexed signal is:
A plurality of error correction frames including redundant codes generated from the low-order group signal and the low-order group signal are time-division multiplexed,
10. A plurality of error correction decoding units that restore a low-order group signal by performing error correction using the redundant code included in the error correction frame output from the n × n switch. The multiple signal demultiplexer according to any one of the above. A signal multiplexing device for generating a time division multiplexed signal in which a plurality of asynchronous low-order group signals including channel number information are synchronized and time division multiplexed, and transmitting the time division multiplexed signal via a transmission line; A communication device;
The multiplex signal demultiplexing device according to claim 6, wherein the multiplex signal demultiplexing device according to claim 6, which demultiplexes the low-order group signals for each channel from the time division multiplex signal received via the transmission line and outputs the signals in a desired arrangement. A second communication device;
A communication system. A channel identification method for identifying an array of a plurality of low-order group signals separated from a time division multiplexed signal,
Determining whether or not the arrangement of the low-order group signals is a desired arrangement based on the arrangement of channel numbers respectively extracted from the low-order group signals;
A channel identification method for switching using a control signal for making the arrangement of the low-order group signal coincide with the desired arrangement when the arrangement of the low-order group signal is not a desired arrangement. Each of the detection pattern that is an array of the low-order group signals and a registration pattern that is an array of a plurality of possible channel numbers registered in advance are respectively compared.
Counting the number of channel numbers whose arrangement positions match the detection pattern for each of the registration patterns, and confirming the registration pattern having the largest count as the correct arrangement of the detection patterns,
13. The channel identification method according to claim 12, wherein a control signal corresponding to the determined registered pattern is output from a plurality of control signals registered in advance for switching the registered pattern to a desired arrangement. For each of the time-division multiplexed signals received a plurality of times, the detection pattern that is an array of the low-order group signals is compared with a registered pattern that is an array of a plurality of possible channel numbers registered in advance, and the detection is performed. Determine whether there is a registered pattern that matches the pattern,
From the determination result for each time-division multiplexed signal received a plurality of times, the registered pattern that has the largest number of matches with the detection pattern is determined as the correct arrangement of the detection pattern,
The channel identification method according to claim 12 or 13, wherein a control signal corresponding to the determined registered pattern is output from among a plurality of control signals registered in advance for switching the registered pattern to a desired arrangement.   The output of the low-order group signal is stopped when the low-order group signal is not in the desired arrangement, and the low-order group signal is output after switching the arrangement of the low-order group signal to a desired arrangement. 15. The channel identification method according to any one of 12 to 14. A channel identification device for identifying an array of a plurality of low-order group signals separated from a time division multiplexed signal,
A switching pattern table in which a plurality of control signals for switching the arrangement of the low-order group signals to a desired arrangement are registered in advance;
When determining whether or not the arrangement of the low-order group signals is a desired arrangement based on the arrangement of channel numbers extracted from the low-order group signals, respectively, and when the arrangement of the low-order group signals is not a desired arrangement An arithmetic processing unit that generates a signal for outputting the control signal registered in the switching pattern table required for switching from the low-order group signal array to the desired array;
A channel identification device. The arithmetic processing unit includes:
The detection pattern, which is the array of channel numbers extracted from the low-order group signal, is compared with a plurality of registration patterns, which are arrays of possible channel numbers determined by the number of channels, and the detection pattern and array position match. The number of channel numbers to be counted is counted for each of the registered patterns, the registered pattern having the largest count number is determined as a correct array of the detection patterns, and the switching required for switching from the determined array to the desired array 17. The channel identification device according to claim 16, wherein a signal for outputting a control signal registered in the pattern table is generated. The arithmetic processing unit includes:
For each of the time division multiplexed signals received a plurality of times, a detection pattern that is an array of the channel numbers extracted from the low-order group signal, and a plurality of registration patterns that are an array of possible channel numbers determined by the number of channels; And determining whether there is a registered pattern that matches the detected pattern, and from the determination result for each time-division multiplexed signal received a plurality of times, the registered pattern having the highest number of times matched with the detected pattern is determined. 18. A signal for outputting a control signal registered in the switching pattern table required for switching from the determined array to the desired array is determined as a correct array of the detection patterns. Channel identification device. The arithmetic processing unit includes:
The output of the low-order group signal is stopped when the low-order group signal is not in the desired arrangement, and the low-order group signal is output after switching the arrangement of the low-order group signal to a desired arrangement. The channel identification device according to any one of 16 to 18.

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