JP2006060523A - Method for dynamic balancing of clock tree - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for dynamic balancing of a clock tree, which generates more current for compensating for the time delay of slow clock by a sink. <P>SOLUTION: A controllable buffer is inserted in a specific level of a clock tree, and a controller is provided for adjusting two clocks having different phases, and PMOS/NMOS arrangements in the controllable buffer are controlled by the output bus C[x:0] of the controller. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a method for balancing clock phase differences in the design of a synchronous logic circuit, and more particularly to a circuit for adjusting a clock phase difference in the design of a synchronous logic circuit by balancing clock tree circuits.

When designing a synchronous circuit, it is common to assume that all memory devices use the same clock, and the clocks of each memory device change state at the same time (from high level to low level, Alternatively, since all the remaining logic blocks use the same clock period, the preparation time and the holding time for the clock state conversion are the memory element, flip-flop, and latch. It can be estimated by such as. However, since the clock is connected to the electric wires having different lengths of the elements and the input capacitors having different specific elements, the above temporary setting cannot be actually realized.

The clock shown in FIG. 1 has a faster conduction time from clock source 0 to sink 1 than a conduction time to sink n, because the length of the wire to sink n is greater than the length of the wire to sink 1 Because it is too long. Longer wires have higher resistance and capacitance, so the clock is delayed.

Currently, the circuit designer uses a clock tree synthesis tool to generate a "balanced clock tree", which divides the output of clock source 0 into multiple groups, each group being a branch of clock source 0, When such a division process is used for each branch, a clock tree is formed as shown in FIG. The clock tree synthesis tool adjusts the length of the wire in consideration of the resistance and capacitance of the wire and the input capacitance of the element, so that the length of the wire from the clock source 0 to each sink is the same. The sinking clock has a similar time delay. Such an idea has already been applied to the early H-tree method and the recent Steiner-tree method. When the clock tree circuit is generated, the delays from clock 0 (clock tree root) to each sink (clock tree leaf) are all the same.

If the “balanced clock tree” cannot compensate for the time delay, the circuit designer inserts the buffer 20 into the appropriate branch (hot branch), so that a “buffer tree” is generated as shown in FIG. The One buffer includes two inverters.

The above method presumes that the temperature and voltage of the entire circuit are similar, that is, the above method seems to make the clock tree circuit static, but in practice the IC chip at work is not.

IC chips at work have different surface temperatures in different areas because certain circuit blocks have more switching operations. The difference in temperature affects the hole / electron fluidity of the semiconductor element, and the resistance of the wire is also changed. These phenomena disturb the timing from clock 0 to each sink. On the other hand, circuits that generate more operation (generate more heat) create a larger voltage drop, and this larger voltage drop makes the local Vdd (power supply) lower than other parts of the chip, so The response of the circuit (eg, plugged in buffer) is slower than other normal Vdd devices. Voltage drops and temperature rises make the “balanced” clock tree circuit unbalanced.

To compensate for circuits with different temperatures and voltage drops at each location, the CAE design has too many buffers inserted into the clock tree circuit, resulting in poor clock balance, which can be attributed to active devices (eg, buffer ) Are more sensitive to voltage and temperature than passive elements (eg, wires).

The object of the present invention is to plug a controllable buffer into a specific level of the clock tree circuit and control the PMOS / NMOS combination in the buffer controllable by the controller to adjust two clocks with different phase differences This provides a dynamic balancing method of the clock tree that can generate more current and compensate for the time delay of some sinking that makes the clock slower.

In order to achieve the above object, the present invention provides a controller for inserting a controllable buffer into a specific level of the clock tree circuit and receiving a clock having two different phases in the clock tree circuit. Providing and controlling the PMOS / NMOS arrangement in the controllable buffer by the output bus C [x: 0] of the controller, so that more current is generated at the output of the controllable buffer and the clock The gist of the present invention is a dynamic balancing method of a clock tree characterized by compensating for the time delay of a slower clock of the tree circuit sinking.

In the invention of the present application, the controller includes a phase detector, a charging circuit, a voltage detector, an increment / decrement counter, and an output bus C [x: 0]. The gist is the clock tree dynamic balancing method described in 1.

In the present invention, the controllable buffer is composed of a plurality of rows of PMOS and NMOS, each row has two PMOSs and two NMOSs connected in series, and a clock input signal is passed through an inverter through the top and bottom PMOSs and bottoms. The control signals C (0), C (1), C (2), ..C (x) on the output bus C [x: 0] are input to the gate of the NMOS and the NMOS in the middle of each row. It is input separately to the gate of the NMOS, the inverter is inserted separately between the central PMOS and NMOS of each row, and a clock output signal is generated at the point where the central PMOS and NMOS are connected The gist of the present invention is the clock tree dynamic balancing method according to claim 1.

According to the dynamic balancing method of the clock tree according to the present invention, the controllable buffer is inserted into a specific level of the clock tree circuit, and the composition of the PMOS / NMOS in the buffer controllable by the controller is controlled to be different. By adjusting two clocks with a phase difference, more current can be generated to compensate for the time delay of some sinking that makes the clock slower.

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

Shown in FIG. 3 is a clock tree circuit that has a controllable buffer 31 plugged into a particular level of the clock tree circuit and having a controller 50 for controlling the buffer 31.

FIG. 4 shows an example of a controllable buffer 31, which is a combination of multiple rows of PMOS and NMOS. In each row, two PMOSs and two NMOSs are connected in series. The clock input signal Clk_in is separately input to the gates of the topmost PMOS 42 and the bottommost NMOS 45 of each row through the inverter 41. The control signals C (0), C (1), C (2),... C (x) of the output bus C [x: 0] are separately input to the gates of the PMOS 43 and NMOS 44 in the center of each row. The inverter 46 is separately inserted between the central PMOS 43 and NMOS 44 of each row.

When each control signal C (0), C (1), C (2),... C (x) is “1” (high level), the copied clock input signal Clk_in is the clock output signal Clk_out. Occurs at the output end 47 of each row. When each control signal C (0), C (1), C (2),... C (x) is “0” (low level), the output terminal 47 of each row has a high resistance value.

Therefore, the control signals C (0), C (1), C (2),... C (x) can control which row is connected in series to generate the clock output signal Clk_out. The larger the number of rows that generate the clock output signal Clk_out and are connected in series, the more current is output. The clock output signal Clk_out is output to the next level of the clock tree.

Reference is now made to FIG. One controller 50 is designed in a phase latch circuit (PLL), and two clocks having different sinks are input to the controller 50. The controller 50 compares the phase difference between the two input clocks by the phase detector 51, generates an appropriate voltage by the one charging circuit 52, and performs "increase", "hold", etc. by the voltage detector 53. An instruction such as “decrease” is input to the increment / decrement counter 54 to control the output bus C [x: 0]. The output bus C [x: 0] includes control signals C (0), C (1), C (2), ..C (x), and C (0), C (1), C (2) ,... C (x) are separately output to the gates of the PMOS 43 and NMOS 44 in the center of each row.

Reference is now made to FIG. The controller 50 receives any two sinking clocks and compares the phase difference between them to generate an output bus C [x: 0]. The output bus C [x: 0] is specified as a clock tree. By transmitting to the correct level, the number of rows connected in series is adjusted to provide the clock output signal Clk_out so that the appropriate output current drives the associated sink x and the phase difference between the two clocks is compensated. The

Reference is now made to FIG. Since the controller 50 can be used for any two clocks, a control circuit is formed.

The spirit and scope of the present invention are limited to the claims, and are not limited to the above embodiments.

FIG. 3 is a schematic diagram of an unbalanced clock tree circuit. FIG. 2 is a schematic diagram of a balanced clock tree circuit. 1 is a schematic diagram of a dynamically balanced clock tree circuit according to the present invention. FIG. FIG. 3 is a schematic diagram of a controllable buffer according to the present invention. It is a block diagram of the controller concerning the present invention. FIG. 2 is a schematic diagram of a dynamically balanced clock tree circuit having a control circuit according to the present invention.

Explanation of symbols

20 buffer 31 buffer 41 inverter 42 PMOS
43 PMOS 44 NMOS
45 NMOS 46 Inverter 47 Output 50 Controller 51 Phase detector 52 Charging circuit 53 Voltage detector 54 Increment / decrement counter

Claims (3)

In the clock tree circuit, a controller is provided which inserts a controllable buffer into a specific level of the clock tree circuit and receives any two clocks having different phases, and outputs an output bus C [x: 0 of the controller. ] To control the PMOS / NMOS arrangement in the controllable buffer, so that more current is generated at the output of the controllable buffer to compensate for the slower time delay of the clock tree circuit sink. It is characterized by
Clock tree dynamic balancing method. The controller of claim 1, wherein the controller includes a phase detector, a charging circuit, a voltage detector, an increment / decrement counter, and an output bus C [x: 0]. Clock tree dynamic balancing method. The controllable buffer is composed of a plurality of rows of PMOS and NMOS. Each row has two PMOSs and two NMOSs connected in series, and a clock input signal passes through an inverter to gate the top and bottom NMOSs of each row. The control signals C (0), C (1), C (2), ..C (x) of the output bus C [x: 0] are input to the gates of the PMOS and NMOS in the center of each row. The clock output signal is generated at a point where the central PMOS and NMOS are connected to each other, and the inverter is separately inserted between the central PMOS and NMOS of each row. 2. The clock tree dynamic balancing method according to 1.

Images