JP2006060294A - Solid-state imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging element widening an aperture through which a photodiode receives light while reducing decrease in potential of an FD at reset of the solid-state imaging element. <P>SOLUTION: A first pixel 20<SB>i, j</SB>of an imaging face of the imaging element includes: a first PD 21<SB>i</SB>; a first FD 22<SB>i</SB>; a first transfer transistor 23<SB>i</SB>; a first reset transistor 24<SB>i</SB>; and a first amplification transistor 25<SB>i</SB>. The first transfer transistor 23<SB>i</SB>is connected between the first PD 21<SB>i</SB>and the first FD 22<SB>i</SB>. The first reset transistor 24<SB>i</SB>is connected between the first FD 22<SB>i</SB>and the first amplification transistor 25<SB>i</SB>. An amplifier power supply V<SB>DA</SB>capable of switching ON/OFF of a voltage applied to the first amplification transistor 25<SB>i</SB>is connected to the first amplification transistor 25<SB>i</SB>. The first reset transistor 24<SB>i</SB>resets potential of the first FD 22<SB>i</SB>and thereafter voltage application to the first amplification transister 25<SB>i</SB>by the amplifier power supply V<SB>DA</SB>is started. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device capable of enlarging an opening area of a photoelectric conversion means and capable of reducing a voltage.

  2. Description of the Related Art As a conventionally known XY address type solid-state image pickup device, a CMOS solid-state image pickup device using a CMOS / LSI manufacturing process is known. As shown in FIG. 4, the CMOS solid-state imaging device resets the charge accumulated in the FD 122 and the transfer transistor 123 that transfers the signal charge accumulated in the photodiode (PD) 121 to the floating diffusion (FD) 122, as shown in FIG. 4. A reset transistor 124, a selection transistor 129 for controlling the timing at which a signal is output from the pixel 120, and an amplification transistor 125 for amplifying the signal are provided.

  In such a solid-state imaging device, an image signal for each pixel is acquired by taking a difference between the potential of the FD 122 in a reset state for each pixel and the potential of the FD 122 in a state where signal charges are accumulated.

  As shown in FIG. 5, in the operation of a conventionally known solid-state imaging device, the potential of the FD 122 is lowered by turning off the reset transistor 124 after resetting the potential of the FD 122 to a predetermined high potential (reference D reference).

  Therefore, the difference between the potential lowered from the high potential and the ground potential corresponds to the width (sign W) of the image signal that can be detected. Accordingly, the high potential needs to be set to be equal to or higher than the potential obtained by adding the potential decrease due to the reset of the FD 122 to the width of the image signal necessary for practical use, and it has been difficult to reduce the drive voltage of the entire image sensor. To solve this problem, it has been proposed to reduce the potential drop of the FD 122 by changing the arrangement of the amplification transistor and the selection transistor (Patent Document 1).

  On the other hand, the ratio of the area of the opening for the PD 121 that performs photoelectric conversion in each pixel 120 to receive light is larger than the area of the entire pixel, thereby reducing noise, wide dynamic range, and miniaturization of the pixel 120. Therefore, a configuration in which the selection transistor 129 is not used is disclosed (Patent Document 2 and Patent Document 3).

However, when the selection transistor 129 is not used, the potential drop of the FD 122 cannot be reduced. Therefore, it is difficult to reduce the potential of the FD 122 while increasing the area of the opening.
Japanese Patent Laid-Open No. 2003-87662 JP 2002-51263 A JP 2002-335455 A

  Therefore, in the present invention, an image sensor having a new configuration capable of reducing the number of electronic components provided in each pixel, an image sensor having a new configuration capable of reducing the potential drop of the FD, or the area of the opening An object of the present invention is to provide an imaging device capable of increasing the FD and reducing the potential drop of the FD.

  The solid-state imaging device according to the present invention includes a photoelectric conversion unit that generates and accumulates charges according to the amount of received light, a floating diffusion that changes in potential according to charges received and received by the photoelectric conversion unit, and photoelectric conversion. A transfer transistor that transfers the charge accumulated by the means to the floating diffusion, a reset transistor that resets the received charge that is received by the floating diffusion and resets the potential of the floating diffusion, and outputs a pixel signal corresponding to the received charge Amplification transistor, amplifier power supply connected to the main electrode of the amplification transistor and capable of switching on / off of voltage application to the main electrode, and amplifier power supply after the reset of the floating diffusion potential by the reset transistor Applying a voltage to the main electrode of the al amplifying transistor is turned on, the photoelectric conversion unit, a floating diffusion, a transfer transistor, a reset transistor, and an amplification transistor are characterized in that it is provided for each of a plurality of pixels constituting the imaging plane. With such a configuration, it is possible to reduce a decrease in potential of the floating diffusion.

  In addition, the solid-state imaging device of the present invention includes a photoelectric conversion unit that generates and accumulates charges according to the amount of received light, a floating diffusion that receives charges accumulated in the photoelectric conversion unit, and a floating diffusion that accumulates charges accumulated by the photoelectric conversion unit. A transfer transistor for transferring to the semiconductor device, a reset transistor for resetting the received charge received by the floating diffusion, and an amplifying transistor for outputting a pixel signal corresponding to the received charge, a photoelectric conversion means, a floating diffusion, and a transfer transistor In the solid-state imaging device in which the reset transistor and the amplification transistor are provided for each of a plurality of pixels constituting the imaging surface, a single readout line for reading a pixel signal from the amplification transistor is provided in the first pixel constituting the plurality of pixels. The first amplification transistor connected to the second amplification transistor provided in the second pixel constituting the plurality of pixels is connected to the main electrode of the first reset transistor provided in the first pixel and connected to the ground potential and the ground. A first reset power supply that can be switched to a first potential higher than the potential; and a second reset potential that is connected to a main electrode of a second reset transistor provided in the second pixel and can be switched between a ground potential and a second potential higher than the ground potential. 2 reset power supply, and after resetting the potential of the first floating diffusion provided in the first pixel to the ground potential by the first reset transistor in a state where the first reset power supply is switched to the ground potential, The second floating diffusion provided in the second pixel in a state where the ground potential is switched to the second potential. Characterized by resetting the position to the second potential by a second reset transistor. With such a configuration, conventionally, it is possible to omit a selection transistor provided for each pixel.

  The first reset transistor and the second reset transistor preferably include a single reset signal line for transmitting a reset signal for resetting the received charge or the potential of the floating diffusion. Further, it is preferable that the reset signal is continuously supplied to the reset signal line after the first floating diffusion is reset to the ground potential until the second reset power source is switched from the ground potential to the second potential. This is because the first reset transistor and the second reset transistor obtain the reset signal and the non-reset signal from a single reset signal line, and thus continuing the reset signal simplifies control of the reset signal line.

  According to the present invention, it is possible to provide a solid-state imaging device capable of increasing the area of an opening in a pixel by reducing the potential drop of the FD without using a selection transistor.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a plan view schematically showing the overall configuration of a solid-state imaging device to which the first embodiment of the present invention is applied.

  The CMOS solid-state imaging device 10 includes an imaging unit 11, a vertical shift register 12, a correlated double sampling / sample hold (CDS / SH) circuit 13, a horizontal shift register 14, and a horizontal readout line 15. The imaging unit 11 and the vertical shift register 12 are directly connected, and the horizontal readout line 15 is connected to the imaging unit 11 via the CDS / SH circuit 13.

  A plurality of pixels 20 are arranged in a matrix on the imaging surface of the imaging unit 11. Signal charges are generated in the individual pixels 20. The image signal of the entire subject image is constituted by a set of pixel signals corresponding to the signal charges of the pixels 20 on the entire imaging surface. The generated pixel signal is read out for each pixel 20. The pixel 20 to be read is selected directly or indirectly by the vertical shift register 12 and the horizontal shift register 14.

  A row of pixels 20 is selected by the vertical shift register 12. The pixel signal output from the selected pixel 20 is correlated double sampled by the CDS / SH circuit 13. Further, the pixel signal held in the CDS / SH circuit 13 is selected by the horizontal shift register 14 and read out to the horizontal readout line 15. The pixel signal read to the horizontal readout line 15 is sent to, for example, a computer (not shown) that performs signal processing, and is subjected to predetermined processing to be processed into an image signal of the entire subject image.

FIG. 2 is a circuit diagram showing a pixel configuration of the image sensor to which the first embodiment of the present invention is applied. The first pixel 20 _i , _{j in the} i row and j column will be described, but the configuration of the other pixels 20 is the same. The first pixel 20 _i , _j includes a first photodiode (PD) 21 _i , a first floating diffusion (FD) 22 _i , a first transfer transistor 23 _i , a first reset transistor 24 _i , and a first amplification transistor 25 _i. Is provided.

In the first PD 21 _i , charges generated according to the amount of received light in the first pixels 20 _i , _j are accumulated. The source of the first transfer transistor 23 _i is connected to the first PD 21 _i , and the drain is connected to the first FD 22 _i . The gate of the first transfer transistor 23 _i is connected to the i-row transfer signal line 26 _i .

The i-row transfer signal line 26 _i is a signal line extending in the horizontal direction between the first pixels 20 _i , _j and the pixels (not shown) in the (i−1) -th row and j-th column, and a pulse-like ON / OFF signal is transmitted. Alternating flow. When flowing ON signal to the i line transfer signal line 26 _i, the charge accumulated in the first 1PD21 _i is transferred to the 1FD22 _i by the first transfer transistor 23 _i. The first FD 22 _i receives the charge, and the potential of the first FD 22 _i changes to a potential corresponding to the charge.

The source of the first reset transistor 24 _i is connected to the first FD 22 _i , and the drain is connected to the i-row reset power line 27 _i . The gate of the first reset transistor 24 _i is connected to a reset signal line [Phi _R. The i-row reset power supply line 27 _i is a power supply line extending in the horizontal direction between the first pixel 20 _i , _j and the pixel in the (i−1) th row and jth column, and is switched to the ground potential and a predetermined high potential higher than the ground potential Is possible.

The reset power supply line is different for each row, and the reset transistor 24 _{i + 1} in the pixel in the i + 1 row is connected to the i + 1 row reset power supply line 27 _{i + 1} . On the other hand, regarding the reset signal line Φ _R , a single reset signal line Φ _R is connected to the reset transistors in all the pixels 20.

When flowing ON signal to the reset signal line [Phi _R, charge received to the 1FD22 _i is reset swept out to the i row reset power supply line 27 _i by a first reset transistor 24 _i. Further, the potential of the first FD 22 _i is reset to the potential of the i-row reset power line 27 _i .

The gate of the first amplification transistor 25 _i is connected to the first FD 22 _i , and the source is connected to the j column vertical readout line 28 _j . The vertical read line 28 _j is connected to the CDS / SH circuit 13. The drain of the first amplification transistor 25 _i is connected to the amplifier power supply V _DA . Amplifier power supply V _DA is capable of switching between ON / OFF.

When the amplifier power supply V _DA is turned on, a voltage is applied between the drain and source of the first amplification transistor 25 _i . When the voltage is applied, the first amplification transistor 25 _i is turned on, and a signal voltage corresponding to the charge received in the first FD 22 _i can be output as a pixel signal to the j column vertical readout line 28 _j .

The i-row reset power supply line 27 _i , the i-row transfer signal line 26 _i , the reset signal line Φ _R , and the amplifier power supply V _DA are connected to the vertical shift register 12. the potential of the i-th row reset power supply line 27 _i, i line transfer signal line 26 _i and ON / OFF signals flowing through the reset signal line [Phi _R, and ON / OFF of the amplifier power supply V _DA is controlled by the vertical shift register 12.

The signal voltage output from the first amplification transistor 25 _i is sampled and held in the CDS / SH circuit 13. The CDS / SH circuit 13 includes a first sample hold (SH) signal line 161, a second sample hold (SH) signal line 162, and a third sample hold (SH) signal line 163 through which an ON / OFF switching signal flows. Connected.

When flowing ON signal to the 1SH signal line 161, first signal corresponding to the potential of the 1FD22 _i being reset is sampled and held. When flowing ON signal to the 2SH signal line 162, a second signal the 1FD22 _i is corresponding to the potential of the 1FD22 _i in the state received the charge from the 1PD21 _i is sampled and held. When an ON signal flows through the third SH signal line 163, a third signal obtained by subtracting the second signal from the first signal is sampled and held.

The output side of the CDS / SH circuit 13 is connected to the source of the j column selection transistor 17 _j . The drain of the j column selection transistor 17 _j is connected to the horizontal readout line 15, and the gate is connected to the horizontal shift register 14. A pulse-like ON / OFF signal is supplied from the horizontal shift register 14 to the gate of the j column selection transistor 17 _j . When the ON signal is supplied to the gate of the j column selection transistor 17 _j , the third signal sampled and held in the CDS / SH circuit 13 is output to the horizontal readout line 15.

Next, the operation of the image sensor 10 having the above-described configuration and the potential of the FD 22 _i will be described with reference to the timing chart of FIG. An operation in the first pixel 20 _i , _j in the i row and j column shown in FIG. 2 and the potential of the first FD 22 _i will be described as an example.

First, at the timing t1, the potential of the i-row reset power supply line 27 _i is the ground potential, and the ON signal flows through the reset signal line Φ _R and the first reset transistor 24 _i is in the ON state, so that the first FD 22 _i The potential has been reset to ground potential. The potential remains i row reset power supply line 27 _i is ON signal flows to the reset signal line [Phi _R at the timing t2 is switched to the high potential, the potential of the 1FD22 _i is reset to high potential.

Next, at the timing of t3, an OFF signal flows through the reset signal line Φ _R and the first reset transistor 24 _i is turned OFF, so that the first FD 22 is capacitively coupled between the gate of the first reset transistor 24 _i and the first FD 22 _i . The potential of _i decreases (see symbol D).

The amplifier power supply V _DA at timing t4, when it comes to ON, the node and the potential of the 1FD22 _i by capacitive coupling between the first 1FD22 _i between the amplifier power supply V _DA and first amplifying transistor 25 _i rises (code U reference). Therefore, since the potential drop of the first FD 22 _i due to turning off the reset transistor is reduced, the high potential of the reset power supply line can be set low.

At time t5, an ON signal is sent to the first SH signal line 161, and the first signal is sampled and held in accordance with the _i potential of the first FD 22 when reset. The first transfer transistor 23 _i is turned ON at the timing t6, the charge accumulated in the 1PD21 _i is accumulated in the 1FD22 _i.

Next, at a timing t7 after the first transfer transistor 23 _i is turned OFF, an ON signal is supplied to the second SH signal line 162, and the second signal corresponding to the potential of the first FD 22 _i when the charge is accumulated is CDS. The sample is held in the / SH circuit 13. The amplifier power source V _DA is switched off after the end of the sample signal hold of the second signal. Note that the third signal, which is the difference between the second signal and the first signal, is sampled and held after the amplifier power supply V _DA is switched off, and is output to the horizontal readout line 15.

Next, at timing t8, an ON signal is sent to the reset signal line Φ _R and the i-row transfer signal line 26 _i , and the first FD 22 _i is reset by turning on the first reset transistor 24 _i and the first transfer transistor 23 _i. The Next, at the timing of t9, the potential of the _i- th row reset power supply line 27 _i is switched to the ground potential while the first reset transistor 24 _i remains ON, so that the potential of the first FD 22 _i is reset to the ground potential.

By resetting the potential of the first FD 22 _i to the ground potential, the output of the first amplification transistor 25 _i remains the ground potential even if the amplifier power supply V _DA is subsequently turned ON. The selection of the pixel from which the pixel signal is read can be performed by switching the potential of the reset power supply line, and the selection transistor that has been conventionally required in the pixel becomes unnecessary.

Next, at the timing of t10, the potential of the i + 1 row reset power supply line 27 _{i + 1} is switched from the ground potential to the high potential while the ON signal is flowing in the reset signal line Φ _R as in the timing of t2, and the j column vertical reading is performed. The potential of the second FD 22 _{i + 1} in the second pixel 20 _{i +} 1, _j in the i + 1 row and j column having the second amplification transistor 25 _{i + 1} connected to the line 28 _j is reset to the high potential. Thereafter, the same operation as that from t3 to t9 is performed in the second pixel 20 _{i +} 1, _j . Exactly the same operation is performed in all the pixels 20, and pixel signals from all the pixels 20 are obtained.

As described above, according to the image sensor of this embodiment, the drive voltage of the image sensor can be reduced. Further, the number of transistors can be reduced as compared with the conventional imaging device (see FIG. 4), and the area occupied by one transistor in the pixel can be used as an opening for the PD 21 _i to receive light. Can be expanded. As a result, noise can be reduced and a wide dynamic range can be achieved.

  Alternatively, when the area of the opening is not changed, the area of the transistor occupied in the pixel is reduced, so that the area of the pixel can be reduced. That is, each pixel 20 can be miniaturized, and the entire image sensor 10 can be downsized or the number of pixels in the entire image sensor 10 can be increased.

In the present embodiment, the transistors 23 _i , 24 _i , 25 _i and the j column selection transistor 17 _j provided in each pixel are n-channel type, but may be p-channel type. However, in the case of the p-channel type, it is necessary to change the voltage level in the connection of the transistors 23 _i , 24 _i , 25 _i , and 17 _j . Therefore, in any transistor, the main electrode, that is, the drain or the source of the reset transistor 24 _i or the amplification transistor 25 _i is connected to the amplifier power source V _DA .

  In this embodiment, the amplification transistors of all the pixels are connected to a single amplifier power supply. However, even if the amplifier transistor is connected to a different amplifier power supply for each row and can be switched ON / OFF for each amplifier power supply. Good. If the amplifier power supply for applying a voltage to a plurality of amplification transistors connected to the same vertical signal line is different, the reset transistors provided in all the pixels can be connected to a single reset power supply line as in this embodiment. The effect is obtained.

  When a single reset power supply line is used, the reset transistor potentials of all the pixels are simultaneously switched, and the FD potentials of the pixels other than the pixel that reads the pixel signal change from the ground potential. Cannot read out pixel signals. However, if only the amplifier power source connected to the amplification transistor provided in the pixel to be read is turned on, an accurate pixel signal can be read.

  In this embodiment, the reset signal line is a single signal line for all the reset transistors, but the same effect as that obtained by this embodiment can be obtained even if the reset signal line is different for each pixel.

  In the present embodiment, the arrangement of the pixels 20 on the imaging surface is a matrix, but may be any two-dimensional arrangement. In addition, the image pickup device in the present embodiment is a CMOS solid-state image pickup device, but can be applied to any solid-state image pickup device using an XY address system.

1 is a plan view schematically showing an overall configuration of a solid-state imaging device to which an embodiment of the present invention is applied. It is a circuit diagram which shows the structure of the pixel of the solid-state image sensor to which one Embodiment of this invention is applied. It is a timing chart which shows the operation | movement in a pixel, and the figure which shows transition of the electric potential of FD in the timing of each operation | movement. It is a circuit diagram which shows the structure of the pixel of a solid-state image sensor for description of background art. It is a timing chart showing the operation in the pixel for explaining the background art, and a diagram showing the transition of the potential of the FD at the timing of each operation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 CMOS solid-state image sensor 11 Image pick-up part 20 Pixel 21 _i 1st photodiode (PD)
22 _i 1st floating diffusion (FD)
23 _i first transfer transistor 24 _i first reset transistor 25 _i first amplification transistor 26 _i i row transfer signal line 27 _i i row reset power supply line 27 _{i + 1} i + 1 row reset power supply line Φ _R reset signal line V _DA amplifier power supply

Claims (5)

Photoelectric conversion means for generating and storing charges according to the amount of received light; and
Floating diffusion for receiving the charge accumulated in the photoelectric conversion means;
A transfer transistor for transferring the charge accumulated in the photoelectric conversion means to the floating diffusion;
A reset transistor that resets a received charge that is a charge received by the floating diffusion and a potential of the floating diffusion;
An amplification transistor that outputs a pixel signal according to the received charge;
An amplifier power supply connected to the main electrode of the amplification transistor and capable of switching on or off the voltage application to the main electrode;
After the reset of the potential of the floating diffusion by the reset transistor, the voltage application from the amplifier power supply to the main electrode of the amplification transistor is turned on,
The solid-state imaging device, wherein the photoelectric conversion means, the floating diffusion, the transfer transistor, the reset transistor, and the amplification transistor are provided for each of a plurality of pixels constituting an imaging surface. Photoelectric conversion means for generating and accumulating charges according to the amount of received light; a floating diffusion for receiving the charges accumulated in the photoelectric conversion means; and a transfer transistor for transferring the charges accumulated in the photoelectric conversion means to the floating diffusion A reset transistor that resets a received charge that is a charge received by the floating diffusion, and an amplification transistor that outputs a pixel signal corresponding to the received charge,
In the solid-state imaging device in which the photoelectric conversion means, the floating diffusion, the transfer transistor, the reset transistor, and the amplification transistor are provided for each of a plurality of pixels constituting the imaging surface.
A single readout line for reading out the pixel signal from the amplification transistor, a first amplification transistor provided in a first pixel constituting the plurality of pixels, and a second provided in a second pixel constituting the plurality of pixels. Connected to the amplification transistor,
A first reset power source connected to a main electrode of a first reset transistor provided in the first pixel and capable of switching between a ground potential and a first potential higher than the ground potential;
A second reset power source connected to a main electrode of a second reset transistor provided in the second pixel and switchable between a ground potential and a second potential higher than the ground potential;
In a state where the first reset power source is switched to the ground potential, the potential of the first floating diffusion provided in the first pixel is reset to the ground potential by the first reset transistor, and then the second reset power source is changed from the ground potential. A solid-state imaging device, wherein a potential of a second floating diffusion provided in the second pixel is reset to the second potential by the second reset transistor in a state of switching to the second potential. An amplifier power supply connected to the main electrodes of the first amplification transistor and the second amplification transistor and capable of switching on or off the voltage application to the main electrode;
After the reset of the received charge by the first reset transistor is completed, voltage application from the amplifier power supply to the main electrode of the first amplification transistor or from the amplifier power supply after the reset of the received charge by the second reset transistor is completed. The solid-state imaging device according to claim 2, wherein voltage application to the main electrode of the second amplification transistor is turned on.   3. A single reset signal line for transmitting a reset signal for resetting the received charge or the potential of the floating diffusion to the first reset transistor and the second reset transistor, respectively. Item 6. The solid-state imaging device according to Item 3. 5. The reset signal is continuously supplied to the reset signal line after the first floating diffusion is reset to the ground potential until the second reset power source is switched from the ground potential to the second potential. The solid-state image sensor described in 1.

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