JP2006060255A - Leadless package semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a leadless package semiconductor device which is miniaturized, is made thin, which can decrease the electric resistance between a semiconductor chip and a lead, and reduce the number of manufacturing man-hour. <P>SOLUTION: The device is provided with a common external electrode TD directly connected to electrodes D1 and D2 provided on one surfaces of a plurality of semiconductor chips MC1 and MC2 arranged in a plane; individual external electrodes TG1 and TG2 directly connected respectively to electrodes G1 and G2 provide on the other surfaces of the semiconductor chips MC1 and MC2; and a seal resin R filled in a region surrounded by these external electrodes TD, TG1, and TG2, to seal the plurality of semiconductor chips MC1 and MC2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a leadless package type semiconductor device.

A leadless package type semiconductor device (hereinafter referred to as a leadless package) has a package whose outer dimensions are sealed because the lead as an electrode for external connection does not protrude from the sealing resin sealing the semiconductor chip. Since it can be configured to have the same external dimensions as the resin, it is advantageous for reducing the size and thickness of the semiconductor device. As such a leadless package, there is a technique described in Patent Document 1. In the technique of Patent Document 1, as shown in FIG. 16A, a semiconductor chip 301 is sealed with a resin package 302, and the surface of a resin protrusion 303 provided on the bottom surface of the resin package 302 is externally connected. A metal film 304 is formed as a lead, and the metal film 304 and the electrode 305 of the semiconductor chip 301 are electrically connected by a bonding wire 306.
Japanese Patent No. 3074264

  Although the technique of this patent document 1 does not appear in the figure, the bonding wire 306 is connected to the metal film 304 and the resin package 302 is formed while the semiconductor chip 301 is supported using the lead frame, and then the resin package 302 is formed. However, a leadless package having a structure in which a semiconductor chip is mounted on the lead frame and the lead frame is left has been proposed. FIG. 16B shows an example in which a semiconductor chip 401 is mounted on a lead frame 402, and the semiconductor chip 401 and the external connection lead 403 are electrically connected by a bonding wire 404. Bonding wires 404 and the like are collectively sealed with a sealing resin 405, and then the lead frame 404 is cut and separated to form individual packages. As described above, in the leadless package of Patent Document 1 shown in FIG. 16A or the leadless package shown in FIG. 16B, the lead for external connection is formed to have the same dimension as the external dimension of the package. Therefore, it is advantageous for making the package smaller and thinner.

  In the conventional leadless package configuration, since the semiconductor chip and the external connection lead are connected by a bonding wire, a high loop shape is required to prevent the bonding ear from short-circuiting to the edge portion of the semiconductor chip. The height of the package is required by the length, which becomes an obstacle to further downsizing of the package, particularly reduction in thickness. Further, since the semiconductor chip and the lead are connected by a thin bonding wire, a wire bonding process is required for each of the plurality of semiconductor chips, which increases the number of manufacturing steps. Furthermore, there is a problem that the electric resistance of the bonding wire is large, which is not preferable in terms of high-speed operation of the leadless package.

  Among these problems, conventionally, with respect to the problem of electrical resistance, the semiconductor chip 401 is replaced with a metal plate piece 406 instead of a bonding wire as shown in FIG. There have been proposed a package form in which the lead 403 is connected and a package form in which a part of the lead frame 402 is extended as a metal piece terminal 407 and connected to the semiconductor chip 401 as shown in FIG. In these techniques, the resistance of the metal plate piece and the metal piece terminal can be made lower than that of the bonding wire, which is advantageous in reducing the electrical resistance in the package and realizing high-speed operation. However, even with these improved techniques, it is difficult to reduce the thickness of the package by using metal plate pieces or metal piece terminals, and the metal plate pieces or metal piece terminals are connected to individual semiconductor chips. Therefore, it is difficult to reduce the number of manufacturing steps.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a leadless package type semiconductor device capable of reducing the electrical resistance between a semiconductor chip and leads while reducing the package size and thickness, and reducing the number of manufacturing steps. .

  The present invention provides a common semiconductor device in which one electrode is provided on one surface and a plurality of semiconductor chips provided with a plurality of electrodes on the other surface and all electrodes provided on one surface are directly connected. A plurality of semiconductors filled in a region sandwiched between an external electrode, a plurality of individual external electrodes directly and independently connected to each of all the electrodes provided on the other surface, and the common external electrode and the individual external electrodes And a sealing resin for sealing the chip.

  The individual external electrode is integrally connected to an electrode wiring portion having an area larger than the area of the individual external electrode, and is connected to an electrode provided on the other surface via the electrode wiring portion. This electrode wiring portion is covered with a sealing resin.

  According to the semiconductor device of the present invention, one electrode on one surface of a plurality of semiconductor chips is directly connected to a common external electrode, and each electrode on the other surface of each semiconductor chip is directly connected to an individual external electrode. In addition, since the semiconductor chip is sealed by filling a sealing resin between these external electrodes, a bonding wire or the like for electrically connecting the semiconductor chip electrode and each external electrode becomes unnecessary, and the lead The height of the less package can be reduced, and the size and thickness can be reduced. Further, since a bonding wire or the like is not required, it is advantageous in reducing electrical resistance between the semiconductor chip and the lead frame and realizing high-speed operation. Further, it is not necessary to connect bonding wires to individual semiconductor chips, and the number of manufacturing steps can be reduced.

  Furthermore, the individual external electrode is integrally connected to an electrode wiring portion having an area larger than the area of the individual external electrode, and the electrodes of the semiconductor chip are connected via this electrode wiring portion. The bonding of the electrodes of the semiconductor chip is facilitated, and the area of each of the plurality of individual external electrodes can be reduced to the minimum necessary area. When the leadless package is mounted on a circuit board, the adjacent individual external electrodes There is no short circuit caused by mounting solder or the like.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic perspective view of a first embodiment of a leadless package type semiconductor device (hereinafter referred to as leadless package LLP) in which the present invention is integrally packaged with a semiconductor chip (hereinafter referred to as MOS chip) comprising MOSFET elements. FIG. 4A is a diagram viewed from the upper surface side, and FIG. 4B is a diagram viewed from the lower surface side. FIG. 2 is a partially exploded perspective view excluding the sealing resin, and FIG. 3 is a longitudinal sectional view taken along the line AA in FIG. The leadless package LLP of the first embodiment is a configuration example in which two MOS chips are packaged, and the first and second MOS chips MC1 and MC2 having the same configuration on the first lead frame L1 are arranged in a plane. The drain electrodes on the back surfaces of the MOS chips MC1 and MC2 are fixed on the first lead frame L1 as the common external drain electrode TD. Further, on the surfaces of the two MOS chips MC1 and MC2, first and second external gate electrodes TG1 and TG2, and second leads constituting the first and second external source electrodes TS1 and TS2 are formed. A frame L2 is placed and connected to a plurality of electrodes formed on the surfaces of the MOS chips MC1 and MC2. The first and second lead frames L1 and L2 are formed to have a minimum area size required to sandwich the two MOS chips MC1 and MC2, and the first and second lead frames L1 and L2 A resin R is filled in between, and the two MOS chips MC1 and MC2 are sealed with resin to form a leadless package LLP.

The first and second MOS chips MC1 and MC2 are each formed as a power MOSFET as shown in a sectional structure in FIG. Here, an n ⁻ -type epitaxial layer 102 is formed on an n ⁺ -type substrate 101, a p-type base layer 103 is formed on the main surface of the n ⁻ -type epitaxial layer 102, and an n ^- type epitaxial layer 102 is formed on the p-type base layer 103. ^{A +} type source layer 104 is formed. A gate insulating film 105 is formed on the surface of the n ⁻ type epitaxial layer 102, and a polysilicon gate 106 is formed in a region sandwiched by the n ⁺ type source layer 104. A source contact hole 108 is opened in a region including the p-type base layer 103 to the n ⁺ -type source region 104 in the interlayer insulating film 107 covering the polysilicon gate 106, and the source contact hole 108 is made of a metal film. A source electrode 109 (S1, S2 in FIG. 2) is formed. Further, a gate electrode 110 (G1, G2 in FIG. 2) made of a metal film is formed on the polysilicon gate 106, and the gate electrode 110 and the source electrode 109 are made of gold as shown in FIG. Bumps (or solder balls) B are formed. A drain electrode 111 (D1, D2 in FIG. 2) made of a metal film is formed on the back surface of the n ⁺ type substrate 101.

  As shown in an equivalent circuit in FIG. 5, the two MOS chips MC1 and MC2 are configured as a common external drain electrode TD as a leadless package by electrically connecting the drain electrodes D1 and D2 to each other. The gate electrodes G1 and G2 and the source electrodes S1 and S2 of the first and second MOS chips MC1 and MC2 are respectively independent of the first external gate electrode TG1, the second external gate electrode TG2, and the package. The first external source electrode TS1 and the second external source electrode TS2 are configured. The first lead frame L1 forms the common external drain electrode TD, and the second lead frame L2 forms the first and second external gate electrodes TG1 and TG2 and the external source electrodes TS1 and TS2. It is configured.

  The first lead frame L1 is formed of a flat metal plate, and as described above, the drain electrodes D1 and D2 of the two MOS chips MC1 and MC2 are connected in common and configured as a common external drain electrode TD. ing. The second lead frame L2 is formed by etching a flat metal plate into a required pattern to form gate electrode wiring portions HG1, HG2 and source electrode wiring portions HS1, HS2. The gate electrodes G1, G2 and the source electrodes S1, S2 of the MOS chips MC1, MC2 are connected to the gate electrode wiring portions HG1, HG2 and the source electrode wiring portions HS1, HS2 by the gold bumps B, respectively. In addition, partial regions of the gate electrode wiring portions HG1 and HG2 and the source electrode wiring portions HS1 and HS2 protrude from the outer surface of the second lead frame L2, and the protruding regions are the external gate electrodes TG1 and TG2. , And external source electrodes TS1, TS2. The sealing resin R is filled between the first and second lead frames L1 and L2 to seal the MOS chips MC1 and MC2. A part of the sealing resin R is part of the external resin. In the region excluding the gate electrodes TG1 and TG2 and the external source electrodes TS1 and TS2, it is formed so as to cover the outer surface of the second lead frame L2.

  Here, the common drain electrode TD in the leadless package LLP in the first embodiment is not necessarily required to be electrically connected to the outside, but in the first embodiment, the first lead frame L1 is Since it is exposed on the outer surface of the sealing resin R, as shown in FIG. 5, it is configured as a common external drain electrode TD that can be electrically connected to the outside. If external connection to the common drain electrode is unnecessary, the first lead frame may be covered with a sealing resin. Alternatively, the first lead frame may have a configuration in which a conductive film capable of short-circuiting the drain electrode is formed on the inner surface of the insulating substrate.

  In the leadless package LLP of the first embodiment, the drain electrodes D1, D2 of the MOS chips MC1, MC2 are directly connected to the first lead frame L1, and the gate electrodes G1, G2 and the source electrodes S1, S2 are connected to the second lead frame. Since it is configured to be directly connected to L2, bonding wires, metal plate pieces, metal piece terminals and the like for electrically connecting the gate electrodes and source electrodes of the MOS chips MC1 and MC2 become unnecessary, and the top surfaces of the MOS chips MC1 and MC2 The height dimension between the first lead frame L2 and the second lead frame L2 can be reduced, and the leadless package can be made smaller and thinner. In addition, by eliminating the need for bonding wires, metal plate pieces, metal piece terminals, etc., it is advantageous in reducing the electrical resistance between the MOS chips MC1, MC2 and the second lead frame L2 and realizing high-speed operation. become. In addition, a connection process such as a bonding wire for each MOS chip is not required, and the number of manufacturing steps can be reduced.

  In the leadless package LLP, the individual external electrodes TG and TS have electrode wiring portions HG and HS having an area larger than the area exposed on the outer surface of the sealing resin R. Since the electrodes G and S of the semiconductor chip MC are connected to the HG and HS, the bonding of the electrodes G and S of the semiconductor chip MC to the individual external electrodes TG and TS is facilitated and exposed to the outer surface of the sealing resin R. The area of each of the plurality of individual external electrodes TG, TS can be reduced to a necessary minimum area. When the leadless package LLP is mounted on a circuit board or the like, the adjacent individual external electrodes TG, TS are mounted with solder for mounting, etc. No short circuit

  FIG. 6 is a process cross-sectional view for explaining a first manufacturing method of the leadless package LLP of the first embodiment. As shown in FIG. 6A, the plurality of MOS chips formed on the semiconductor wafer are cut and separated into individual pieces by dicing, and then the first MOS chip MC1 and the second MOS chip among the individual MOS chips. MC2 is sequentially arranged in a predetermined position on the first lead frame L1 made of a flat metal material with the drain electrodes D1 and D2 on the back surface facing downward, and silver paste is applied to the drain electrodes D1 and D2. Chip mounting is performed by such as. If the MOS chips MC1 and MC2 are of the same type, the individual MOS chips are mounted on the first lead frame L1 without distinction. Next, as shown in FIG. 6B, the second lead frame L2 is placed on the first lead frame L1, and the gate electrodes G1, G2 and source electrodes (in FIG. 6) of the individual MOS chips MC1, MC2. Connection to the second lead frame L2 is performed by gold bumps (or solder balls) B provided on the second lead frame L2. In this connection, the second lead frame L2 is heated and pressed against the MOS chips MC1 and MC2, and thermocompression bonding with the gold bumps B is performed.

  Here, as shown in FIG. 2, the second lead frame L2 is connected to the gate electrodes G1 and G2 and the source electrodes S1 and S2 of the MOS chips MC1 and MC2. , HG2 and the source electrode wiring portions HS1 and HS2, leaving the pattern regions corresponding to the half-etching removal from the inner surface side by half the thickness, while the gate electrode wiring portions HG1 and HG2 and the source electrode wiring portions HS1 and HS2 are removed. In a partial region of HS2, that is, a region other than the region configured as the external gate electrodes TG1 and TG2 and the external source electrodes TS1 and TS2, the metal plate is formed by half etching removal from the outer surface side by half etching. As a result, in the regions configured as the external gate electrodes TG1, TG2 and the external source electrodes TS1, TS2, the metal plate is left over the entire thickness, and the regions of the gate electrode wiring portions HG1, HG2 and the source electrode wiring portions HS1, HS2 are left. Then, the metal plate is left in half thickness, and the metal plate is removed over the entire thickness in other regions.

  Thereafter, as shown in FIG. 6C, the sealing resin R is filled between the first lead frame L1 and the second lead frame L2 by a molding resin molding method or the like, and the MOS chips MC1 and MC2 are sealed with resin. Stop. At this time, the first and second lead frames L1 and L2 perform resin sealing with their surfaces exposed, respectively, but as shown in FIG. 2 is filled in the region removed over the entire thickness of the lead frame L2, and the outer surface is covered with the sealing resin R in the regions of the gate electrode wiring portions HG1 and HG2 and the source electrode wiring portions HS1 and HS2, and the external gate electrode TG1. , TG2 and the external source electrodes TS1, TS2 are exposed. Thereafter, as shown in FIG. 6D, the first and second lead frames L1 and L2 and the sealing resin R are cut over the entire thickness and cut and separated into individual packages. Thereby, the leadless package LLP shown in FIG. 1 is completed.

  In the first manufacturing method, in the step of chip mounting the MOS chips MC1 and MC2 of FIG. 6A on the first lead frame L1, the gate electrodes G1 and G2 and the source electrodes S1 and S1 of the MOS chips MC1 and MC2 are performed. In S2, that is, the gold bumps B of the respective electrodes are exposed on the upper surface, the MOS chips MC1 and MC2 can be positioned with high accuracy with reference to these electrodes. 6B, the second lead frame L2 can be easily positioned with respect to the gate electrodes G1, G2 and the source electrodes S1, S2 exposed on the upper surface, so that the MOS chip MC1, The positioning of the second lead frame L2 with respect to MC2 can be performed with high accuracy. This makes it possible to increase the reliability of the electrical connection of the gate electrode wiring portions HG1, HG2 and the source electrode wiring portions HS1, HS2 of the second lead frame L2 particularly with respect to the gate electrodes G1, G2 and the source electrodes S1, S2. Become.

  FIG. 7 is a process cross-sectional view for explaining a second manufacturing method of the leadless package of the first embodiment. As shown in FIG. 7A, after the plurality of MOS chips MC1 and MC2 formed on the semiconductor wafer are cut and separated into individual pieces by dicing, the individual MOS chips MC1 and MC2 face the surface downward. The gate electrodes G1 and G2 and the source electrodes S1 and S2 are placed on the second lead frame L2 while being positioned and pressed from the upper back side of the MOS chip. Flip chip mounted. In the second lead frame L2, the external gate electrodes TG1 and TG2 and the external source electrodes TS1 and TS2 are left in full thickness, and the gate electrode wiring portions HG1 and HG2 and the source electrode wiring portions HS1 and HS2 are left in half thickness. The second lead frame in the first manufacturing method is the same as the second lead frame in that the other regions are etched and removed over the entire thickness. Next, as shown in FIG. 7B, the first lead frame L1 made of a flat metal plate is put on the MOS chips MC1 and MC2, and the drain electrodes D1 and D2 on the back surface of the MOS chips MC1 and MC2 are formed. Mounting is performed on the first lead frame L1 as the common external drain electrode TD by silver paste or the like. Next, as shown in FIG. 7C, the sealing resin R is filled between the first lead frame L1 and the second lead frame L2 by a molding resin molding method or the like, and the MOS chips MC1 and MC2 are resin-sealed. To do. At this time, the first and second lead frames L1 and L2 are sealed with resin so that the surfaces are exposed. A part of the sealing resin R is formed so as to cover the surfaces of the gate electrode wiring portions HG1 and HG2 and the source electrode wiring portions HS1 and HS2. Thereafter, as shown in FIG. 7D, the first and second lead frames L1 and L2 and the sealing resin R are cut over the entire thickness and cut and separated into individual packages.

  The leadless package LLP of the first embodiment can be manufactured by the second manufacturing method as in the first manufacturing method. In the second manufacturing method, since the MOS chips MC1 and MC2 are chip-mounted on the second lead frame L2 with the surfaces facing downward, the gate electrodes G1 and G2 and the source electrodes S1 and S1 of the MOS chips MC1 and MC2 are mounted. Since it is difficult to confirm S2 from above, the first manufacturing method is more advantageous for increasing the positioning accuracy of each electrode of the MOS chips MC1 and MC2 with respect to the second lead frame L2. On the other hand, in the second manufacturing method, the individual MOS chips MC1 and MC2 can be handled while being pressed against the second lead frame L2 and heated for chip mounting. Since it is only necessary to mount the drain electrodes D1 and D2 on the first lead frame L1, the second lead frame is connected to the plurality of MOS chips by gold bumps as in the first manufacturing method. Compared with the case of performing the above, the mounting operation for each electrode on each surface of the MOS chip is easier than the first manufacturing method.

  8 is a schematic perspective view of a leadless package LLP according to a second embodiment of the present invention, FIG. 9 is a partially exploded perspective view excluding the sealing resin, and FIG. 10 is a longitudinal sectional view thereof. In addition, in Example 2, the same code | symbol is attached | subjected to the part equivalent to Example 1. FIG. In the second embodiment, the configuration in which the two semiconductor chips are mounted between the first lead frame L1 and the second lead frame L2 is the same as that of the first embodiment, but one semiconductor chip is mounted. Is a MOS chip MC, and the other semiconductor chip is a diode chip DC. Each of the first and second lead frames L1 and L2 includes each electrode wiring portion having a required pattern. Here, the drain electrode wiring portion HD and the anode electrode wiring portion HA are integrally formed on the first lead frame L1. The second lead frame L2 is formed with a gate electrode wiring portion HG, a source electrode wiring portion HS, and a cathode electrode wiring portion HK. In the same manner as the second lead frame L2 of the first embodiment, each of these wiring portions is manufactured by half-etching each electrode wiring portion with a predetermined pattern from the front side and the back side of each lead frame L1, L2. HD, HA, HG, HS, and HK have a half-thickness configuration, the gate, source, drain, and cathode external electrodes TG, TS, TD, and TK have a full-thickness configuration, and other regions are removed over the entire thickness. It is configured.

  The MOS chip MC connects the drain electrode to the drain electrode wiring portion HD of the first lead frame L1, and connects the gate electrode wiring portion HG and the source electrode wiring portion HS of the second lead frame L2. The gate electrode G and the source electrode S are connected. On the other hand, the diode chip DC connects the anode electrode A to the anode electrode wiring portion HA of the first lead frame L1, and connects the cathode electrode K to the cathode electrode wiring portion HK of the second lead frame L2. is doing. Further, the sealing resin R is filled between the first lead frame L1 and the second lead frame L2 to seal the MOS chip MC and the diode chip DC, and a part of the sealing resin R Is formed so as to cover the electrode wiring portions HG, HS, HK, HD, HA of the lead frames L1, L2, and only the external electrodes TG, TS, TK, TD are exposed in the first embodiment. Same as leadless package. Also, each leadless package is formed by being cut and separated into individual pieces as in the first embodiment.

  The equivalent circuit of the leadless package LLP of the second embodiment is as shown in FIG. 11, and the drain electrode wiring in which the drain electrode D of the MOS chip MC and the anode electrode A of the diode chip DC are provided in the first lead frame L1. The gate electrode G and source electrode S of the MOS chip MC and the cathode electrode K of the diode chip DC are provided on the second lead frame L2 and connected to the external drain electrode TD via the part HD and the anode electrode wiring part HA. The external gate electrode TG, the external source electrode TS, and the external cathode electrode TK are connected, and each external electrode is configured as an external electrode of the leadless package.

  In the leadless package LLP of the second embodiment, the gate, source, drain G, S, and D electrodes of the MOS chip MC are directly connected to the first and second lead frames L1 and L2, and the diode chip. Since the DC anode electrode A and cathode electrode K are directly connected to the first and second lead frames L1 and L2, bonding for connecting each electrode of the MOS chip MC or diode chip DC and each external electrode is performed. Wires, clips, beam leads and the like are no longer required, the height dimension between the first and second lead frames L1 and L2 is reduced, and the leadless package can be made smaller and thinner. At the same time, the electrical resistance between the MOS chip MC and the diode chip DC and the first and second lead frames L1 and L2 is reduced, which is advantageous in realizing high-speed operation. In addition, it is not necessary to connect bonding wires to individual chips, and the number of manufacturing steps can be reduced.

  In the manufacturing method of the leadless package LLP of the second embodiment, that is, the third manufacturing method of the present invention, as shown in FIG. 12A, the first and second lead frames L1 and L2 are respectively connected to the front side and the back side. In the first lead frame L1, the drain electrode wiring portion HD and the anode electrode wiring portion HA are formed, and in the second lead frame L2, the gate electrode wiring portion HG, the source electrode wiring portion HS, and the cathode electrode wiring are formed. Part HK is formed. Thereafter, the drain electrode D is chip-mounted on the drain electrode wiring portion HD of the first lead frame L1 on the MOS chip MC. Further, as shown in FIG. 12B, the diode electrode DC is chip-mounted on the cathode electrode wiring part HK of the second lead frame L2. Next, as shown in FIG. 12C, the first lead frame L1 is placed upside down on the second lead frame L2, and the gate electrode of the MOS chip MC mounted on the first lead frame L1. G and source electrode S (not shown in FIG. 12) are positioned with respect to the gate electrode wiring portion HG of the second lead frame L2, and at the same time, the anode of the diode chip DC mounted on the second lead frame L2. The anode electrode wiring portion HA of the first lead frame L1 is positioned with respect to the electrode A. Then, the gate electrode G and the source electrode S of the MOS chip MC are mounted on the second lead frame L2, and the anode electrode A of the diode chip DC is mounted on the first lead frame L1 at the same time. Thereafter, the sealing resin R is filled between the first and second lead frames L1 and L2 in the same manner as in the first and second manufacturing methods, and the MOS chip MC and the diode chip DC are sealed with resin. Further, as shown in FIG. 12D, individual leadless packages are formed by cutting and separating the first and second lead frames L1, L2 and the sealing resin R over the entire thickness.

  A mode of mounting the leadless package LLP of the first and second embodiments configured as described above will be described. Here, an example of mounting the leadless package LLP of the first embodiment will be described. FIG. 13 is a cross-sectional view illustrating a first mounting structure example of the leadless package of the first embodiment. In the first mounting structure example, the mounting substrate 201 is formed with circuit wiring 203 in which a metal film such as copper is formed in a required pattern on the surface of the insulating substrate 202. 2, the external gate electrodes TG 1 and TG 2 and the external source electrodes TS 1 and TS 2 (not shown in FIG. 13) configured by the second lead frame are respectively arranged on the mounting substrate 201. The pad portion 203 is connected by face-down bonding using a brazing material such as silver paste or solder. In addition, for the first lead frame L1 of the leadless package LLP disposed on the upper side, when electrical connection to the common external drain electrode TD is necessary, a metal plate is stripped as shown in FIG. The mounting substrate 201 and the common external drain electrode TD are electrically connected to each other by the metal piece terminal 204 processed into the shape.

  This first mounting structure example is a structural example suitable for mounting the leadless package of the present invention on a generally provided mounting board, and includes a conventional leadless package mounting technique based on the face-down method. The mounting can be easily performed using a connection technique using a metal piece terminal.

  FIG. 14 is a cross-sectional view illustrating a second mounting structure example of the leadless package LLP according to the first embodiment. In the second mounting structure example, the first and second mounting boards 211 and 221 are used, and these mounting boards 211 and 221 are respectively the insulating board 212 and the mounting board 212 in the same manner as the mounting board in the first mounting structure example. Circuit wirings 213 and 223 are formed on 222. Then, the first lead frame L1 of the leadless package LLP is opposed to the first mounting substrate 212, and the common external drain electrode TD is made of silver paste, solder, or the like on the pad portion of the circuit wiring 213 of the first mounting substrate 211. Electrical connection using brazing material. Similarly, the second lead frame L2 faces the second mounting substrate 221, and the external gate electrodes TG1 and TG2 and the external source electrodes TS1 and TS2 (not shown in FIG. 14) are respectively mounted in the second mounting. It connects to the pad part of the circuit wiring 223 of the board | substrate 221 with brazing materials, such as a silver paste and solder. Although not shown, the first and second mounting boards 211 and 221 may be electrically connected to each other by a flexible wiring board at the edges of both mounting boards. Alternatively, the first and second mounting substrates 211 and 221 may be configured by bending a single flexible substrate.

  This second mounting structure example does not require a connection technique using a metal piece terminal or the like as in the first mounting structure example, and the height dimension of the entire mounting structure is substantially equal to the thickness dimension of the leadless package. This is effective in realizing a thin mounting structure.

  FIG. 15 is a diagram illustrating a third mounting structure example of the leadless package LLP according to the first embodiment. In the third mounting structure example, the first lead frame L1 is mounted on the first mounting board 231 so as to face the second mounting board 241, and the second lead frame L2 is mounted on the second mounting board 241 so as to face. Here, the first and second mounting substrates 231 and 241 are formed as insulating substrates 232 and 242 having recesses in which the leadless package can be embedded on the surfaces facing each other. When the less package LLP is mounted, the mounting boards 231 and 241 constitute a case for housing the leadless package LLP. In mounting on the first mounting substrate 231, the first lead frame L1, that is, the common external drain electrode TD is soldered to the circuit wiring 233 provided in the recess of the first mounting substrate 231, such as silver paste or solder. Electrical connection by material. In mounting on the second mounting substrate 241, the external gate electrodes TG1 and TG2 and the external source electrodes TS1 and TS2 (not shown in FIG. 15) formed on the second lead frame L2 are respectively mounted in the second mounting. The circuit wiring 243 formed on the substrate 241 is connected to each pad portion by a brazing material such as silver paste or solder. Then, the circuit boards 233 and 243 of the mounting boards 231 and 241 are electrically connected to each other at the same time at the peripheral edges of the recesses so that the required circuit including the leadless package LLP is obtained. A structure is constructed.

  Since the third mounting structure example is configured as a circuit structure including a leadless package by a pair of mounting substrates, it is possible to realize a small and thin circuit structure. In addition, the leadless package can be sealed with the mounting substrate, and a circuit structure having stable characteristics against environmental changes can be obtained.

  In the above description, the leadless package of the present invention has been described with respect to the embodiment in which two semiconductor chips are mounted and connected between the first and second lead frames and resin-sealed. However, three or more semiconductor chips are mounted. It is also possible to connect and seal with resin. In each of the above embodiments, the configuration example in which the same type of semiconductor chip is packaged as the same MOS chip and the configuration example in which different types of semiconductor chips such as the MOS chip and the diode chip are packaged have been described. It is also possible to package different types of semiconductor chips together. However, in the present invention, the plurality of semiconductor chips to be mounted must be directly mounted and connected to the first and second lead frames on the front surface side and the back surface side, respectively. Are preferably equal.

  In addition, the leadless package of the present invention is not limited to the case where the equivalent circuit as shown in each of the above embodiments is configured, and is configured as an arbitrary equivalent circuit and a package in which external electrodes are arbitrarily arranged. It goes without saying that it can be configured. In particular, by arbitrarily designing the pattern of the electrode wiring portions of the first and second lead frames, the package can be configured as a leadless package having an arbitrary equivalent circuit.

It is each external appearance perspective view of the upper surface side of the leadless package of Example 1 of this invention, and a lower surface side. FIG. 3 is a partially exploded perspective view excluding the sealing resin of Example 1. It is a longitudinal cross-sectional view which follows the AA line of Fig.1 (a). It is sectional drawing of a MOS chip. 1 is an equivalent circuit diagram of Embodiment 1. FIG. FIG. 6 is a process cross-sectional view illustrating a first manufacturing method of the leadless package of Example 1. It is process sectional drawing explaining the 2nd manufacturing method of the leadless package of Example 1. FIG. It is an external appearance perspective view of the leadless package of Example 2 of this invention. It is a partial exploded perspective view except sealing resin of Example 2. FIG. 6 is a longitudinal sectional view of Example 2. FIG. 6 is an equivalent circuit diagram of Embodiment 2. FIG. 10 is a process cross-sectional view illustrating the manufacturing method of the leadless package of Example 2. FIG. 6 is a cross-sectional view illustrating a first mounting structure of the leadless package of Example 1. FIG. 6 is a cross-sectional view showing a second mounting structure of the leadless package of Example 1. FIG. 7 is a cross-sectional view illustrating a third mounting structure of the leadless package of Example 1. FIG. It is sectional drawing of two examples of the conventional leadless package. 2 is a cross-sectional view of two examples of a conventional improved leadless package. FIG.

Explanation of symbols

LLP leadless package MC (MC1, MC2) MOS chip (semiconductor chip)
DC diode chip (semiconductor chip)
L1 1st lead frame L2 2nd lead frame TG, TS, TD, TK External electrode HG, HS, HD, HK, HA Electrode wiring part R Sealing resin 201, 2111, 221, 231, 241 Mounting substrate

Claims (3)

  A plurality of semiconductor chips provided with one electrode on one surface and a plurality of electrodes on the other surface; one common external electrode directly connected to all the electrodes provided on the one surface; A plurality of individual external electrodes that are directly and independently connected to all of the electrodes provided on the other surface, and a region sandwiched between the common external electrode and the individual external electrodes, A leadless package type semiconductor device comprising: a sealing resin for sealing the semiconductor chip.   The individual external electrode is integrally connected to an electrode wiring portion having an area larger than the area of the individual external electrode, and is connected to an electrode provided on the other surface via the electrode wiring portion. The leadless package semiconductor device according to claim 1, wherein the leadless package semiconductor device is a semiconductor device. The leadless package semiconductor device according to claim 3, wherein the electrode wiring portion is covered with the sealing resin.

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