JP2006054369A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device where a laminated structure originally possessed by a non-volatile memory is utilized as the capacitor of a peripheral circuit and to provide its manufacturing method. <P>SOLUTION: The semiconductor device is equipped with a laminated gate structure Gs which is composed of a first insulating film 13 formed on a semiconductor substrate 11, a first conductive film 14 which is formed on the first insulating film 13 to serve as a floating gate, a second insulating film 15 provided on the first conductive film 14, and a second conductive film 16 which is formed on the second insulating film 15 to serve as a control gate, a first contact plug 21 connected to the first conductive film 14, a second contact plug 20 connected to the second conductive film 16, and third contact plugs 27 and 28 connected to the semiconductor substrate 11. The first and second insulating film, 13 and 15, are used as the dielectric films of a capacitor. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a stacked gate structure in a nonvolatile memory cell as a capacitor.

  In a semiconductor device, a capacitor using a gate oxide film in a transistor (hereinafter referred to as a gate capacitor) is used when a capacitor is required for the purpose of stabilizing a power supply, signal delay, and the like.

  Among them, some circuits require large capacity. Especially, charge pump booster circuit that generates high voltage in the device has a very large capacitor area, and the proportion of the chip size The situation cannot be ignored.

  Although it is well known to form a charge pump booster circuit using a transistor and a capacitor, in order to obtain a large current as an output, it is necessary to increase the capacity of the capacitor. However, since it is necessary to use a thick gate insulating film that can withstand a high voltage, the capacitance per unit area decreases, and as a result, the capacitor area increases.

  Furthermore, in order to create a high voltage, it is necessary to increase the number of stages of the capacitor section, and the same circuit is required for the type of high voltage used in the device. Will occupy a large area. As a result, the shrink of the peripheral circuit does not progress with respect to the cell area where the shrink progresses.

In the charge pump booster circuit, in order to prevent dielectric breakdown of a capacitor to which a high voltage is applied, the capacitor C is constituted by a two-stage stacked capacitor in which two capacitors C1 and C2 are connected in series, and one capacitor C1 Patent Document 1 describes that the voltage applied to C2 is relaxed.
JP 2002-261239 A

  Therefore, an object of the present invention is to provide a semiconductor device that eliminates the above-mentioned conventional drawbacks and uses a stacked structure originally possessed by a nonvolatile memory as a capacitor of a peripheral circuit.

  According to an aspect of the present invention, a semiconductor device includes a first insulating film provided on a semiconductor substrate, a first conductive film provided on the first insulating film and serving as a floating gate, and the first A stacked gate structure including a second insulating film provided on the conductive film; a second conductive film provided on the second insulating film and serving as a control gate; and the first conductive film. A first contact plug connected to the second conductive film; a second contact plug connected to the second conductive film; and a third contact plug connected to the semiconductor substrate. This insulating film is used as a dielectric film of a capacitor.

  By using the stacked gate structure originally possessed by the nonvolatile memory as the gate capacitor of the peripheral circuit, the area of the peripheral region can be reduced without increasing the process flow steps. In other words, since the gate sandwiched between the two insulating films is used as a capacitor, a capacitor having a capacity approximately twice the normal per unit area can be obtained, and the withstand voltage can be obtained simply by changing the contact plug connection. Application of a voltage to an insulating film having a low thickness and dielectric breakdown thereof can be prevented.

[Example]
FIG. 1 is a plan view of a gate capacitor using a stacked gate structure in a nonvolatile memory cell as a capacitor, FIGS. 2 and 3 are II-II sectional views of FIG. 1, and FIG. 4 is a III-III sectional view of FIG. Shown respectively.

  That is, as shown in FIG. 1, N + or P + diffusion layers 22 and 23 are formed on both sides of a later-described laminated gate structure Gs formed on the N-well 11 of the silicon substrate, and these diffusion layers are not shown in FIG. Contact plugs 25 and 26 are respectively provided through openings formed in the insulating film.

  In the III-III cross-sectional direction of the stacked gate structure Gs, an N + diffusion layer 24 formed in the N-well 11 is provided, and similarly, contact plugs 27 and 28 are provided, respectively. Further, in the II-II cross-sectional direction of the stacked gate structure Gs, the contact plug 20 connected to the second polysilicon film 16 serving as the control gate and the first polysilicon film 14 serving as the floating gate are connected. A contact plug 21 is formed.

  As shown in FIG. 2, an element isolation insulating film 12 is selectively provided in the N-well 11, and a first insulating film 13 having a thickness of, for example, 10 nm is provided between the element isolation insulating films 12. Is formed.

  A first polysilicon film 14 serving as a floating gate is formed on the first insulating film 13 so as to straddle the element isolation insulating film 12, and on the first polysilicon film 14, for example, A second insulating film 15 having a thickness of 15 nm as in the ONO structure is formed. A second polysilicon film 16 serving as a control gate is provided on the second insulating film 15. Further, in order to form a contact plug serving as a terminal in the first polysilicon film 14, a part of the second polysilicon film 16 is removed to form a stacked gate structure Gs.

  Sidewall insulating films 17 are provided on the exposed end surfaces of the first polysilicon film 14 and the second polysilicon film 16, and a protection is provided on the side wall insulating film 17 and the second polysilicon film 16. An insulating film 18 is formed. Further, such a stacked gate structure Gs is covered with the first interlayer insulating film 19.

  In order to use the laminated gate structure Gs as a capacitor, contact plugs 20 and 21 are provided in the first and second polysilicon films 14 and 16, respectively.

  Depending on the process flow, the first polysilicon film 14 may be formed so as not to overlap the element isolation insulating film 12. In such a structure, the partially removed portion of the second polysilicon film 16 and the contact plug 21 are provided not on the element isolation insulating film 12 but on the first insulating film 13 as shown in FIG. Will be. A cross section of the structure is shown in FIG.

  As shown in FIG. 4, N + or P + diffusion layers 22 and 23 are formed in the N-well 11 adjacent to the element isolation insulating film 12 on both sides of the stacked gate structure Gs, and the element isolation insulating film. An N + diffusion layer 24 is formed between 12.

  Contact plugs 25-28 are respectively provided for the diffusion layers 22 and 23 and the N + diffusion layer 24, and these contact plugs 25-28 are electrically connected to each other by a conductor layer 29. The conductor layer 29 is covered with a second interlayer insulating film 30.

  Next, a case where the stacked gate structure Gs is used in a charge pump booster circuit will be described. In FIG. 2, the first polysilicon film 14 to be a floating gate is sandwiched between insulating films 13 and 15.

  Therefore, by fixing the contact plug 20 and the N-well 11 (substrate) at the same potential, the first polysilicon film 14 has a capacity approximately twice that of a normal gate capacitor per unit area. become.

  That is, as shown in FIG. 5, it is used as the capacitor 41 in a normal charge pump booster circuit 43 made by repeating a part A composed of a capacitor 41 and a transistor 42, and CLK is applied to the contact plug 20 and the N-well 11. By applying a signal and connecting the contact plug 21 to the transfer transistor 42, a charge pump booster circuit can be provided in an area smaller than the conventional one.

  As shown in FIG. 4, a voltage is applied to the N− well 11 from the contact plug 27-28 through the N + diffusion layer 24. When the diffusion layers 22 and 23 are formed as N + diffusion layers, a voltage is applied through the contact plugs 25 and 26. In actual wiring, the conductor layer 29 and the contact plug 20 are connected and used.

  As described above, when a gate capacitor is used for the charge pump booster circuit 43, it is necessary to consider the dielectric breakdown voltage. In FIG. 5, since a higher voltage is applied to the capacitor 41 closer to OUT that outputs a high voltage, a capacitor having an insulating film that can withstand it must be used. That is, the output voltage is limited by one of the insulating films 13 and 15 having the lower withstand voltage.

  Such inconvenience can be avoided by changing the contact plug connection without changing the structure of FIG. That is, in the case of a stacked gate generally used in a nonvolatile memory cell, the insulating film 13 is designed to be thinner than the insulating film 15, and thus the breakdown voltage is lowered. Therefore, it is necessary to change the connection of the conductor layer 29 to the contact plug 21. Instead, the contact plug 20 is connected to the transfer transistor 42 side to prevent voltage application to the insulating film 13 and its destruction. it can. However, in this case, only the insulating film 15 is used as a capacitor, and only a conventional capacitance can be obtained.

  However, in order to compensate for the disadvantages as described above, the following method is possible. That is, a high voltage is applied to the side close to OUT of the charge pump booster circuit 43, but only about VDD or VDD + several V is applied to the side close to the first stage. Therefore, on the low voltage side, as described above, the contact plug 20 and the N − well 11 (the conductor layer 29) are connected to apply the CLK signal, and the contact plug 21 is connected to the transfer transistor 42. A gate capacitor to be connected is used, and on the high voltage side, the connection of the conductor layer 29 is changed to the contact plug 21 and used as a gate capacitor. As a result, the structure can be used even during high voltage output while reducing the area.

  Further, in FIG. 5, if the required number of gate capacitors of the present invention are provided, a desired plurality of gate capacitors can be obtained by performing connection switching later using a wiring layer or the like.

  For example, when an internal voltage of 10 V is to be obtained with a device of VDD = 1.5 V, a charge pump booster circuit of about 8 stages is required. When laying out this circuit, 12 units using the gate capacitor of the present invention are prepared, the first stage side four stages use the connection method of connecting the contact plug 20 and the conductor layer 29, and the output side four stages are A connection method is used in which the connection of the conductor layer 29 is changed to the contact plug 21 and the contact plug 20 is connected to the transfer transistor 42 side. In this case, since the output-side four-stage capacitor can obtain only half the capacity per unit, it is necessary to use double 8 units.

  Furthermore, such a layout can also be used for a charge pump circuit of a device with VDD = 3 V. By changing the connection of the wiring, the contact plug 20 and the conductor layer 29 are connected as described above for the first two stages. Using the connected connection method, the two stages on the output side may use a connection method in which the connection of the conductor layer 29 is changed to the contact plug 21 and the contact plug 20 is connected to the transfer transistor 42 side.

  The device usually has several types of charge pump circuits depending on the required voltage (level) and current. However, the charge pump circuit that outputs the highest level has 12 stages of capacitors and 1 stage. The charge pump circuit that outputs about 100 pF per unit and outputs the largest current has five stages of capacitors and is laid out at about 200 pF per stage. These are examples of the charge pump circuit, and these numerical values vary greatly depending on the device configuration, chip size, and the like.

  6 to 11 show a method of manufacturing a semiconductor device including a gate capacitor (a) using the above-described stacked gate structure as a capacitor and a transistor (b) in the peripheral region.

  As shown in FIG. 6, after forming an element isolation insulating film 12 in an N-well 11 formed on a semiconductor substrate, a first insulating film 13 serving as a gate oxide film, and a first polysilicon serving as a floating gate. A film 14, a second insulating film 15, and a second polysilicon film 16 serving as a control gate are sequentially deposited. Also, a formation flow in which the element isolation insulating film 12 is partially selectively formed after the first insulating film 13 to be uniformly formed as a gate oxide film is deposited on the N-well 11 is often used.

  As shown in FIG. 7, the gate capacitor region (a) is covered with a resist film 51, and the transistor region (b) is formed by RIE (Reactive Ion Etching) with the second polysilicon film 16 and the second insulating film. 15 are sequentially etched and removed.

  As shown in FIG. 8, TEOS or the like serving as a mask material 52 is formed on the second polysilicon film 16 in the gate capacitor region (a) and the first polysilicon film 14 in the transistor region (b). Then, the gate-shaped pattern etching is performed, and the second polysilicon film 16 and the first polysilicon film 14 are etched in the same process to form a gate structure of the transistor region.

  As shown in FIG. 9, in order to form the gate structure of the gate capacitor and the contact plug 21, the entire transistor region is covered with a resist film 53, and a part of the gate structure of the gate capacitor is covered with the resist film 53. The second insulating film 15 and the first polysilicon film 14 that are covered and exposed are sequentially removed.

  As shown in FIG. 10, the resist film 53 and the mask material 52 are removed. Thereafter, impurities for forming the diffusion regions 22 and 23 shown in FIG. 4 are introduced (although not shown, P-type source / drain regions 54 and 55 are formed in the transistor region), and exposed end faces of the respective gate structures. A sidewall insulating film 17 is formed on the substrate, and the entire surface thereof is covered with a protective insulating film 18.

  As shown in FIG. 11, the substrate surface is covered with an interlayer insulating film 19. Then, as usual, openings for reaching the first and second polysilicon films 14 and 16 are formed in the interlayer insulating film 19 to form contact plugs 20 and 21. Thereby, the gate capacitor shown in FIG. 2 is obtained.

  In FIG. 10, the mask material 52 used at the time of gate processing is removed, but it may be left as it is. Further, WSi or the like can be formed on the second polysilicon film 16 or silicided.

  As described above, the structure of the gate capacitor is formed in the flow of forming the conventional stacked gate structure. That is, the gate capacitor according to the present invention can be realized without adding any new process.

  In addition to the process flow as described above, a similar stacked gate structure can be formed, and in this case, the same effect can be obtained. For example, in FIG. 3 shown as an example, first, after depositing a first insulating film 13 which becomes a gate oxide film uniformly on the N-well 11, and subsequently a first polysilicon film 14, an element is formed. The isolation insulating film 12 is partially selectively formed. By such a flow, a structure in which the element isolation insulating film 12 and the first polysilicon film 14 do not overlap can be formed.

  Next, an embodiment will be described as follows. (1) The gate capacitor is used as a capacitor in a charge pump booster circuit.

  (2) A semiconductor device including a gate capacitor (a) using a stacked gate structure as a capacitor and a transistor (b) in a peripheral region is formed by the following process.

(A) After forming an element isolation insulating film in the N-well 11 formed on the semiconductor substrate, a first insulating film to be a gate oxide film, a first polysilicon film to be a floating gate, and a second insulating film A second polysilicon film 16 to be a film and a control gate are sequentially deposited;
(B) The gate capacitor region is covered with a resist film, and the transistor region is removed by sequentially etching the second polysilicon film and the second insulating film by RIE.
(C) forming masks on the second polysilicon film in the gate capacitor region and the first polysilicon film in the transistor region, respectively, and performing gate-shaped pattern etching;
(D) The entire surface of the transistor region is covered with a resist film, and a part of the gate structure of the gate capacitor is covered with a resist film, and the exposed second insulating film and the first polysilicon film are sequentially formed. Remove,
(E) After removing the resist film, a sidewall insulating film is formed on the exposed end face of each gate structure, and the entire surface is covered with a protective insulating film;
(F) Covering the substrate surface with an interlayer insulating film,
(G) An opening reaching each of the first and second polysilicon films is formed to form a contact plug.

1 is a plan view of a gate capacitor using a stacked gate structure in a nonvolatile memory cell according to an embodiment of the present invention as a capacitor; It is II-II sectional drawing of FIG. It is II-II sectional drawing of FIG. FIG. 3 is a sectional view taken along line III-III in FIG. 1. This is a normal charge pump booster circuit. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor device containing the gate capacitor (a) which uses the laminated gate structure by the Example of this invention as a capacitor, and the transistor (b) of a peripheral region. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor device containing the gate capacitor (a) which uses the laminated gate structure by the Example of this invention as a capacitor, and the transistor (b) of a peripheral region. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor device containing the gate capacitor (a) which uses the laminated gate structure by the Example of this invention as a capacitor, and the transistor (b) of a peripheral region. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor device containing the gate capacitor (a) which uses the laminated gate structure by the Example of this invention as a capacitor, and the transistor (b) of a peripheral region. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor device containing the gate capacitor (a) which uses the laminated gate structure by the Example of this invention as a capacitor, and the transistor (b) of a peripheral region. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor device containing the gate capacitor (a) which uses the laminated gate structure by the Example of this invention as a capacitor, and the transistor (b) of a peripheral region.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... N-well, 12 ... Element isolation insulating film, 13 ... 1st insulating film, 14 ... 1st polysilicon film, 15 ... 2nd insulating film, 16 ... 2nd polysilicon film, 17 ... Side wall Insulating film, 18 ... protective insulating film, Gs ... laminated gate structure, 19 ... interlayer insulating film, 20, 21 ... contact plug, 22, 23 ... N + or P + diffusion region, 24 ... N + diffusion layer, 25-28 ... contact plug , 29 ... conductor layer, 30 ... interlayer insulating film, 41 ... capacitor, 42 ... transistor, 43 ... charge pump booster circuit, 51, 53 ... resist film, 52 ... mask material, 54, 55 ... source / drain regions

Claims (5)

A first insulating film provided on a semiconductor substrate; a first conductive film provided on the first insulating film and serving as a floating gate; and a second conductive film provided on the first conductive film. A laminated gate structure including an insulating film and a second conductive film provided on the second insulating film and serving as a control gate;
A first contact plug connected to the first conductive film;
A second contact plug connected to the second conductive film;
A third contact plug connected to the semiconductor substrate;
A semiconductor device, wherein the first and second insulating films are used as a dielectric film of a capacitor. 2. The semiconductor device according to claim 1, wherein the stacked gate structure is a gate structure constituting a nonvolatile memory cell. 2. The semiconductor device according to claim 1, wherein the second contact plug and the third contact plug are connected, and a capacitance between the second contact plug and the first contact plug is a capacitor. 2. The semiconductor device according to claim 1, wherein the connection between the first to third contact plugs is changed. A semiconductor device characterized in that a plurality of capacitors having different connection methods are mixed inside the device by changing the connection between the first to third contact plugs.

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