JP2006049759A - Semiconductor apparatus and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor apparatus capable of coping with the reduction of pitches in a multilayer interconnection and a manufacturing method of the same. <P>SOLUTION: There are provided a process of forming a plurality of first wiring layers on a substrate, a process of forming a first interlayer dielectric 9 so as to cover the first wiring layer, a process of forming a plurality of first plugs 14 which penetrate the first interlayer dielectric from the surface to the thickness direction and connected to the first wiring layers, a process of forming a second wiring layer 40 on the first interlayer dielectric and just above a part of the first plugs out of the first plugs, a process of forming a second interlayer dielectric 19 so as to cover the second wiring layer on the first interlayer dielectric, a process of simultaneously forming a second plug 24' which penetrates the second interlayer dielectric from the surface to the thickness direction and is connected to the second wiring layer and a third plug 24 which penetrates the second interlayer dielectric from the surface to the thickness direction and is directly connected to the first plugs, and a process of forming a third wiring layer 50 on the second interlayer dielectric and just above the second plug and the third plug. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a multilayer wiring and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device and a method for manufacturing the semiconductor device that can cope with a narrow pitch of the multilayer wiring.

  In recent years, with the miniaturization and high performance of semiconductor integrated circuits, higher integration of semiconductor devices has progressed. Multilayer wiring is widely used in order to promote high integration of semiconductor devices. Many technologies have been studied as a semiconductor device using such a multilayer wiring. For example, a semiconductor device having a substrate, at least one layer of metal wiring, and a ceramic thin film capacitance, the ceramic thin film capacitance is: A semiconductor device capable of easily forming a multilayer metal wiring is proposed in which a lower electrode, a ceramic thin film, and an upper electrode are laminated in this order, and the lower electrode, the ceramic thin film, and the upper electrode are formed above the metal wiring. (For example, refer to Patent Document 1).

JP 11-317500 A

  By the way, as the integration of such semiconductor devices increases, it is essential to reduce the pitch of metal wiring. In the conventional semiconductor device, for example, in the case of a semiconductor device having three layers of metal wiring, that is, the semiconductor substrate, the first layer metal wiring on the semiconductor substrate side, and the second layer immediately above the semiconductor substrate. In the case of being configured to include a metal wiring and a third-layer metal wiring immediately above the metal wiring, first, the semiconductor substrate or the first-layer metal wiring and the second-layer metal wiring are connected by a plug, and then the second layer The layer metal wiring and the third layer metal wiring must be connected by a plug.

  For this reason, when the pitch of the metal wiring is reduced, the layout of the entire metal wiring may be rate-controlled by the minimum design rule of the second layer metal wiring. In order to make the design rule of the second layer metal wiring compatible with a finer pattern, it is necessary to use an expensive manufacturing apparatus or process, which raises a problem that the manufacturing cost increases. Moreover, when these cannot be used, there exists a problem that a layout area will expand and the chip size of a semiconductor chip will become large.

  However, in the conventional technique according to Patent Document 1 as described above, a reduction in the pitch of the metal wiring is not studied.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a semiconductor device that can cope with a narrow pitch of a multilayer wiring and a manufacturing method thereof.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to the present invention is a semiconductor device having a wiring layer formed over multiple layers on a semiconductor substrate, and is not adjacent in the thickness direction. A semiconductor substrate and a wiring layer that is not adjacent to the semiconductor substrate in the thickness direction are directly electrically connected to each other by a plug.

  According to the present invention, wiring layers that are not adjacent to each other in the thickness direction, or a semiconductor substrate and a wiring layer that is not adjacent to the semiconductor substrate in the thickness direction are directly electrically connected without passing through another wiring layer. Has been. Thereby, the wiring layers that are not adjacent to each other in the thickness direction regardless of the layout of the wiring layers, or the semiconductor substrate and the wiring layer that is not adjacent to the semiconductor substrate in the thickness direction are connected.

  According to the present invention, even when the pitch of the multilayer wiring is reduced, the wiring layers that are not adjacent to each other in the thickness direction, or the thickness of the semiconductor substrate and the semiconductor substrate, regardless of the design rule of the wiring layer. It is possible to electrically connect wiring layers that are not adjacent to each other in the direction. That is, according to this semiconductor device, the layout of the entire wiring layer is not limited by the design rule of the specific wiring layer, and the layout of the entire wiring layer is further improved even when the pitch of the multilayer wiring is reduced. It is possible to cope with a fine pattern, and the wiring layout can be reduced. Therefore, according to the present invention, there is an effect that it is possible to provide a semiconductor device that can cope with a narrow pitch of multilayer wiring.

  Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below in detail with reference to the drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably.

Embodiment.
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. First, the structure of the semiconductor device will be described. A gate structure 30 is formed on the silicon substrate 1 which is a semiconductor substrate. A first metal wiring 40 is provided on the gate structure 30 with the interlayer insulating film 9 interposed therebetween. The first metal wiring 40 is formed by laminating barrier metal films 15 and 17 made of titanium nitride (TiN) or the like and a conductive film 16 made of aluminum copper (AlCu) or the like.

  Further, an oxide film 100 having an etching selectivity higher than that of the interlayer insulating film 19 formed around the first metal wiring 40 is laminated on the first metal wiring 40, that is, on the barrier metal film 17. Yes. In this oxide film 100, the content ratio of silicon (Si) to oxygen (O) is such that silicon (Si) is 1 and oxygen (O) is less than 2. The first metal wiring 40 and the impurity diffusion region 8 functioning as the source / drain of the gate structure 30 are electrically connected through the contact plug 14 and the barrier metal film 12.

  The upper surface and the periphery of the first metal wiring 40 are covered with the interlayer insulating film 19, and the second metal wiring 50 is formed on the interlayer insulating film 19. The second metal wiring 50 is formed by laminating barrier metal films 25 and 27 made of titanium nitride (TiN) or the like and a conductive film 26 made of aluminum copper (AlCu) or the like. The second metal wiring 50 and the first metal wiring 40 are electrically connected via the via plug 24 ′ and the barrier metal film 22. Further, the second metal wiring 50 and the impurity diffusion region 8 are electrically connected through the via plug 24, the barrier metal film 22, the contact plug 14 and the barrier metal film 12. That is, the second metal wiring 50 and the impurity diffusion region 8 are electrically connected without passing through the first metal wiring 40.

  As described above, in the semiconductor device according to the present embodiment, the via plug 24 and the contact plug 14 pass through the first metal wiring 40 in the connection between the impurity diffusion region 8 and the second metal wiring 50. There is no direct connection. In other words, in this semiconductor device, the via plug 24 and the contact plug 14 are directly electrically connected without passing through the first metal wiring 40.

  In this way, the via plug 24 and the contact plug 14 are directly connected without passing through the first metal wiring 40, thereby causing the second metal wiring 50 and the impurity diffusion due to the design rule of the first metal wiring 40. The situation that the region 8 cannot be connected does not occur, and the second metal wiring 50 and the impurity diffusion region 8 can be reliably connected regardless of the design rule of the first metal wiring 40.

  That is, according to this semiconductor device, even when the pitch of the multilayer wiring is reduced, the second metal wiring 50 and the impurity diffusion region 8 are reliably connected regardless of the design rule of the first metal wiring 40. Is possible. Therefore, according to this semiconductor device, the layout of the entire metal wiring is not limited by the minimum design rule of the first layer metal wiring, and the layout of the entire metal wiring can be achieved even when the pitch of the multilayer wiring is reduced. Can be made to correspond to a finer pattern, and the wiring layout can be reduced.

  Therefore, according to the semiconductor device according to the present embodiment, it is possible to provide a semiconductor device that can cope with the narrow pitch of the multilayer wiring.

  Further, according to this semiconductor device, it is not necessary to use an expensive manufacturing apparatus or process for connecting the second metal wiring 50 and the impurity diffusion region 8, and a complicated layout design is also unnecessary. For this reason, it can be manufactured at low cost without increasing the manufacturing cost. Even when the pitch of multilayer wiring is reduced, the layout of the entire metal wiring can be made to correspond to a finer pattern, so that a miniaturized semiconductor device can be manufactured without increasing the layout area. Can be manufactured.

  Next, a method for manufacturing the semiconductor device according to the present embodiment configured as described above will be described with reference to the drawings. First, as shown in FIG. 2, an element isolation oxide film 2 and a gate structure 30 are formed on a silicon substrate 1 by a known technique. That is, a gate electrode 4 made of polysilicon, a gate electrode 5 made of tungsten silicide (WSi), and a hard mask 6 made of silicon nitride film (SiN) are formed on the silicon substrate 1 via the gate oxide film 3, and silicon Impurity diffusion regions 8 are formed in the substrate 1. Further, sidewalls 7 made of silicon nitride (SiN) are formed on the sidewalls of the gate electrodes 4 and 5 and the hard mask 6.

  Next, as shown in FIG. 3, an interlayer insulating film 9 made of a silicon oxide film or the like is formed on the silicon substrate 1 so as to cover the gate structure 30 by a plasma CVD (Chemical Vapor Deposition) method or the like. A photoresist 10 is formed on the film 9 by photolithography. Here, the photoresist 10 is formed in a pattern having an opening in a portion corresponding to a contact hole formation region in the next step.

  Next, the interlayer insulating film 9 is dry-etched using the photoresist 10 as an etching mask to remove the interlayer insulating film 9 in the contact hole formation region. Then, after the dry etching, the photoresist 10 is removed. Thereby, a contact hole 11 is formed as shown in FIG.

  Next, as shown in FIG. 5, titanium nitride (TiN) or the like is formed on the upper surface of the interlayer insulating film 9 and the inner wall, that is, the inner side surface and the bottom surface of the contact hole 11 to form the barrier metal film 12. Then, as shown in FIG. 6, a conductive film 13 such as tungsten (W) is formed on the upper surface of the barrier metal film 12 and the inner wall of the contact hole 11. The conductive film 13 is formed with a film thickness that is at least half of the upper diameter of the contact hole 11 so that the contact hole 11 is reliably filled.

  Next, as shown in FIG. 7, the conductive film 13 and the barrier metal formed on the upper surface of the interlayer insulating film 9 with the conductive film 13 in the contact hole 11 left by CMP (Chemical Mechanical Polishing) or etch back. The film 12 is removed to form a contact plug 14. Next, as shown in FIG. 8, a titanium nitride (TiN) film is formed on the upper surfaces of the interlayer insulating film 9, the barrier metal film 12 and the contact plug 14 to form a barrier metal film 15, and on the barrier metal film 15. A conductive film 16 such as aluminum copper (AlCu) is formed, and further a titanium nitride (TiN) film is formed thereon to form a barrier metal film 17.

Then, an oxide film 100 is formed on the barrier metal film 17 as shown in FIG. Here, the oxide film 100 has a silicon (Si) / oxygen (O) content ratio of silicon (Si) of 1 and oxygen (O) of less than 2, and silicon (Si) more than an interlayer insulating film 19 described later. This is a film having a high Si (Si) content and a higher selectivity than the interlayer insulating film 19 in dry etching. The oxide film 100 is a film having a higher selection ratio than the barrier metal film 17, the conductive film 16, and the barrier metal film 15. As such an oxide film 100, for example, an oxide film made by a plasma CVD method from a mixed gas of silane and oxygen (O ₂ ) can be formed.

  Next, as shown in FIG. 10, a photoresist 18 is formed on the oxide film 100 by photolithography. Here, the photoresist 18 is formed in a pattern that covers a portion corresponding to the formation region of the first metal wiring 40 and has an opening in the other portion.

  Next, as shown in FIG. 11, the oxide film 100 is dry-etched using the photoresist 18 as an etching mask, and the oxide film 100 other than the formation region of the first metal wiring 40 is removed. Then, after the dry etching, the photoresist 18 is removed. Thereby, as shown in FIG. 12, patterning is performed in which the oxide film 100 is left only in the formation region of the first metal wiring 40.

  Next, the barrier metal film 17, the conductive film 16, and the barrier metal film 15 are dry-etched using the oxide film 100 patterned as shown in FIG. 13 as an etching mask. Thereby, the first metal wiring 40 is formed as shown in FIG. Thereafter, as shown in FIG. 14, an interlayer insulating film 19 made of an oxide film or the like is formed so as to cover the first metal wiring 40, and a photoresist 20 is formed on the interlayer insulating film 19 by photolithography. Here, the photoresist 20 is formed in a pattern having an opening in a portion corresponding to a formation region of the via hole 21 reaching the contact plug 14 and the via hole 21 ′ reaching the first metal wiring 40.

  Next, as shown in FIG. 15, the interlayer insulating film 19 is dry-etched using the photoresist 20 as an etching mask to remove the interlayer insulating film 19 in the formation region of the via hole 21 and the via hole 21 ', thereby forming a via hole. . Here, in the conventional manufacturing method, since the depth of the via hole formed on the contact plug 14 and the first metal wiring 40 is different, the contact plug 14 and the first metal wiring 40 are simultaneously formed. It is difficult to form a via hole.

  Therefore, in the present invention, the oxide film 100 is formed on the first metal wiring 40. Here, the oxide film 100 has a higher silicon (Si) content than the interlayer insulating film 19, and a higher selectivity in the dry etching process when forming a via hole than the interlayer insulating film 19. Accordingly, when the via hole is formed by dry etching the interlayer insulating film 19 using the photoresist 20 as an etching mask, the etching rate is lowered on the first metal wiring 40. As a result, when the via hole is formed by etching the interlayer insulating film 19, the difference in depth of the via hole to be formed is absorbed, and the depth of the contact plug 14 and the first metal wiring 40 is simultaneously reduced. Different via holes can be formed.

  Then, after the dry etching, the photoresist 20 is removed. Thereby, as shown in FIG. 16, a via hole 21 reaching the contact plug 14 and a via hole 21 ′ reaching the first metal wiring 40 can be formed simultaneously.

  Next, as shown in FIG. 17, titanium nitride (TiN) or the like is formed on the upper surface of the interlayer insulating film 19 and the inner walls, that is, the inner side surface and the bottom surface of the via holes 21 and 21 ′ to form the barrier metal film 22. To do. Then, as shown in FIG. 18, a conductive film 23 such as tungsten (W) is formed on the upper surface of the barrier metal film 22 and the inner walls of the via holes 21 and 21 '. The conductive film 23 is formed with a film thickness of more than half of the upper diameter of the via hole 21 and the via hole 21 ′ so that the via hole 21 and the via hole 21 ′ are surely filled.

  Next, as shown in FIG. 19, the conductive film 23 and the barrier film formed on the upper surface of the interlayer insulating film 19 with the conductive film 23 in the via hole 21 and via hole 21 ′ left by CMP or etch back. The metal film 22 is removed. Thereby, the via plug 24 connected to the contact plug 14 through the barrier metal film 22 and the via plug 24 ′ connected to the first metal wiring 40 through the barrier metal film 22 can be formed.

  Next, as shown in FIG. 20, a barrier metal film 25 is formed by depositing titanium nitride (TiN) or the like on the upper surface of the interlayer insulating film 19, the barrier metal 22, the via plug 24, and the via plug 24 '. A conductive film 26 such as aluminum copper (AlCu) is formed on the metal film 25, and titanium nitride (TiN) or the like is further formed thereon to form a barrier metal film 27.

  Next, as shown in FIG. 21, a photoresist 28 is formed on the barrier metal film 27 by photolithography. Here, the photoresist 28 is formed in a pattern that covers a portion corresponding to the formation region of the second metal wiring 50 and has an opening in the other portion.

  Next, as shown in FIG. 22, dry etching is performed using the photoresist 28 as an etching mask to remove the barrier metal film 27, the conductive film 26, and the barrier metal film 25 other than the formation region of the second metal wiring 50. Then, after the dry etching, the photoresist 28 is removed. Thereby, a semiconductor device as shown in FIG. 1 can be manufactured.

  As described above, in the method of manufacturing the semiconductor device according to the present embodiment, when the impurity diffusion region 8 of the gate structure 30 and the second metal wiring 50 are connected, the first metal wiring 40 and the second metal wiring are used. The via plug 24 formed simultaneously with the via plug 24 ′ and the contact plug 14 connected to the impurity diffusion region 8 can be directly connected without passing through the first metal wiring 40. In other words, the via plug 24 and the contact plug 14 can be directly electrically connected without passing through the first metal wiring 40. Thereby, the second metal wiring 50 and the impurity diffusion region 8 can be easily and reliably connected. That is, it is possible to prevent the situation in which the second metal wiring 50 and the impurity diffusion region 8 cannot be connected due to the design rule of the first metal wiring 40, and regardless of the design rule of the first metal wiring 40. The second metal wiring 50 and the impurity diffusion region 8 can be reliably connected.

  That is, according to this method of manufacturing a semiconductor device, even when the pitch of the multilayer wiring is reduced, the second metal wiring 50 and the impurity diffusion region 8 can be reliably connected regardless of the design rule of the first metal wiring 40. It is possible to connect easily and reliably. Therefore, according to this method of manufacturing a semiconductor device, the layout of the entire metal wiring is not limited by the minimum design rule of the first layer metal wiring, and even when the pitch of the multilayer wiring is reduced, the metal wiring The entire layout can correspond to a finer pattern, and the wiring layout can be reduced.

  Therefore, according to the manufacturing method of the semiconductor device according to the present embodiment, it is possible to provide a semiconductor device that can cope with the narrow pitch of the multilayer wiring.

  In addition, according to this method for manufacturing a semiconductor device, it is not necessary to use an expensive manufacturing device or process, and a complicated layout design is not required. Therefore, a semiconductor device can be manufactured at low cost without increasing the manufacturing cost. Can do. Even when the pitch of multilayer wiring is reduced, the layout of the entire metal wiring can be made to correspond to a finer pattern, so that a miniaturized semiconductor device can be manufactured without increasing the layout area. Can be manufactured.

  In the above description, the case where the first metal wiring 40 and the second metal wiring 50 are provided as the multilayer wiring and the second metal wiring 50 and the impurity diffusion region 8 are electrically connected has been described as an example. The present invention is not limited to this, and can be widely applied to the case where the metal wiring and the impurity diffusion region 8 or the metal wirings are electrically connected to each other when there are many multilayer wirings.

  As described above, the semiconductor device according to the present invention is useful for a semiconductor device having a multilayer wiring, and is particularly suitable for a semiconductor device in which the multilayer wiring has a narrow pitch.

It is sectional drawing which shows the structure of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation oxide film 3 Gate oxide film 4 Gate electrode which consists of polysilicon 5 Gate electrode which consists of tungsten silicide (WSi) 6 Hard mask 7 Side wall 8 Impurity diffusion region 9 Interlayer insulating film 10 Photoresist 11 Contact hole 12 Barrier metal film 13 Conductive film 14 Contact plug 15 Barrier metal film 16 Conductive film 17 Barrier metal film 18 Photo resist 19 Interlayer insulating film 20 Photo resist 21 Via hole 21 'Via hole 22 Barrier metal film 23 Conductive film 24 Via plug 24' Via Plug 25 Barrier metal film 26 Conductive film 27 Barrier metal film 28 Photoresist 30 Gate structure 100 Oxide film

Claims (9)

A semiconductor device having a wiring layer formed over multiple layers on a semiconductor substrate,
Wiring layers that are not adjacent to each other in the thickness direction, or the semiconductor substrate and the wiring layer that is not adjacent to the semiconductor substrate in the thickness direction are directly electrically connected by a plug. . A wiring layer formed between the wiring layers not adjacent to each other has a layer having a higher etching selectivity than an interlayer insulating film layer covering the wiring layer, and the wiring layer is an upper layer of the wiring layer and the wiring layer. 2. The semiconductor according to claim 1, wherein the semiconductor layer is electrically connected to each other via a plug penetrating the interlayer insulating film layer and a layer having a higher etching selectivity than the interlayer insulating film layer in a thickness direction thereof. apparatus. The semiconductor device according to claim 2, wherein a layer having a higher etching selectivity than the interlayer insulating film layer has a higher etching selectivity than the wiring layer. A first wiring layer forming step of forming a plurality of first wiring layers on a semiconductor substrate;
A first interlayer insulating layer forming step of forming a first interlayer insulating film layer so as to cover the first wiring layer;
A first plug forming step of forming a plurality of first plugs that penetrate the first interlayer insulating film layer from the surface in the thickness direction and connect to the first wiring layer;
A second wiring layer forming step of forming a second wiring layer on the first interlayer insulating layer and immediately above a part of the first plugs of the first plugs;
A second interlayer insulating film layer forming step of forming a second interlayer insulating film layer on the first interlayer insulating film layer so as to cover the second wiring layer;
A second plug that penetrates the second interlayer insulating film layer from the surface in the thickness direction and connects to the second wiring layer; and a third plug that penetrates from the surface in the thickness direction and connects directly to the first plug; , And a second plug forming step for simultaneously forming,
Forming a third wiring layer on the second interlayer insulating film layer and immediately above the second plug and the third plug;
A method for manufacturing a semiconductor device, comprising: The second wiring layer forming step includes
Forming a layer having a higher etching selectivity than the second interlayer insulating film layer on the second wiring layer;
In the second and third plug forming steps,
5. The semiconductor device according to claim 4, wherein the third plug is formed simultaneously with the second plug by etching the second interlayer insulating film layer and the layer having a high etching selectivity. 6. Method. The second wiring layer forming step includes
Forming a second wiring layer film on the first interlayer insulating layer;
Forming a film having a higher etching selectivity than the second interlayer insulating film layer and the second wiring layer film on the second wiring layer film;
Patterning the film having a high etching selectivity by etching to form a layer having a higher etching selectivity than the second interlayer insulating film layer and the second wiring layer film;
Forming the second wiring layer by etching the second wiring layer film using the layer having a high etching selectivity as an etching mask;
Including
In the second and third plug forming steps,
5. The semiconductor device according to claim 4, wherein the third plug is formed simultaneously with the second plug by etching the second interlayer insulating film layer and the layer having a high etching selectivity. 6. Method. A semiconductor element step of forming a semiconductor element including an impurity diffusion layer on a semiconductor substrate;
A first interlayer insulating film layer forming step of forming a first interlayer insulating film layer so as to cover the semiconductor element;
A first plug forming step of forming a plurality of first plugs penetrating from the surface in the thickness direction to the impurity diffusion layer in the first interlayer insulating film layer;
Forming a first wiring layer on the first interlayer insulating layer and immediately above a part of the first plugs of the first plugs;
A second interlayer insulating film layer forming step of forming a second interlayer insulating film layer on the first interlayer insulating film layer so as to cover the first wiring layer;
A second plug that penetrates from the surface in the thickness direction to the second wiring layer and connects to the first wiring layer; and a third plug that penetrates from the surface in the thickness direction and connects directly to the first plug; , And a second plug forming step for simultaneously forming,
A second wiring layer forming step of forming a second wiring layer on the second interlayer insulating film layer and immediately above the second plug and the third plug;
A method for manufacturing a semiconductor device, comprising: The first wiring layer forming step includes
Forming a layer having a higher etching selectivity than the second interlayer insulating film layer on the first wiring layer;
In the second and third plug forming steps,
The semiconductor device according to claim 7, wherein the third plug is formed simultaneously with the second plug by etching the second interlayer insulating film layer and the layer having a high etching selectivity. Method. The first wiring layer forming step includes
Forming a first wiring layer film on the first interlayer insulating layer;
Forming a film having a higher etching selectivity than the second interlayer insulating film layer and the first wiring layer film on the first wiring layer film;
Patterning the film having a high etching selectivity by etching to form a layer having a higher etching selectivity than the second interlayer insulating film layer and the first wiring layer film;
Forming the second wiring layer by etching the second wiring layer film using the layer having a high etching selectivity as an etching mask;
Including
In the second and third plug forming steps,
The semiconductor device according to claim 7, wherein the third plug is formed simultaneously with the second plug by etching the second interlayer insulating film layer and the layer having a high etching selectivity. Method.

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