JP2005337824A - Probe card and electrical performance inspection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a probe card capable of comprehensive electrical performance inspection for a semiconductor device composed of stacked semiconductor chips and an electrical performance inspection method for improving productivity of an assembly process.
A probe card used for performing an electrical performance test on a semiconductor device formed by stacking another semiconductor chip on a semiconductor chip is stacked on a holder (2a, 2b, 2c). By providing a step corresponding to the thickness of the semiconductor chip, the probe pins (5a, 5b, 5c) can be correctly connected to the electrode pads of both semiconductor chips. Thus, it is possible to provide a probe card that enables comprehensive electrical performance inspection and an electrical performance inspection method that increases the productivity of the assembly process.
[Selection] Figure 1

Description

  The present invention relates to a probe card used for electrical performance inspection of a laminated semiconductor integrated circuit device and an electrical performance inspection method using the same.

Hereinafter, conventional probe inspection will be described.
FIG. 7 is a cross-sectional structure of a conventional probe card and a prober stage, and FIG. 8 is a cross-sectional structure diagram of a probe card and a prober stage during a conventional electrical performance test.

First, the configuration of a conventional probe card and prober stage will be described.
In FIG. 7, a plurality of connectors 3 and a ring 4 are attached to the base 1 on the inner periphery thereof, and the bases of the plurality of connectors 3 and the plurality of probe pins 5 are connected to each other. The tip of the probe pin 5 is bent so as to be in contact with the electrode pad of the semiconductor wafer 8. The ring 4 and the probe pin 5 are fixed with a fixing material 6 to correct the arrangement of the probe pin 5. The semiconductor wafer 8 is arranged on the stage 7 so that the circuit surface faces upward, and the tip of the probe pin 5 is arranged so as to be in contact with the plurality of electrode pads of the semiconductor chip formed on the circuit surface of the semiconductor wafer 8.

The operation of the conventional probe inspection configured as described above will be described with reference to FIG.
As shown in FIG. 8, when the stage 7 is raised, the tip of the probe pin 5 comes into contact with the plurality of electrode pads of the semiconductor wafer 8 disposed on the stage 7, and an electrical performance test is performed.

Even in the case of manufacturing a semiconductor device composed of stacked semiconductor chips, conventionally, each semiconductor chip is subjected to an electrical performance inspection in a wafer state before being stacked, and then divided into individual semiconductor chips as semiconductor devices. It is assembled (see, for example, Patent Document 1).
JP-A-9-102520

  However, when manufacturing a semiconductor device composed of stacked semiconductor chips, if the electrical performance inspection is performed in a wafer state before stacking, the consistency between the stacked semiconductor chips cannot be inspected. The performance inspection is after the assembly process.

  At this time, the electrical performance inspection result in each wafer state may be different from the overall electrical performance result in the state where the semiconductor chips are separated from the wafer and stacked. In other words, even if each semiconductor chip is a non-defective product for electrical performance inspection, the stacked semiconductor chip may not be a good product for electrical inspection, resulting in production loss and reduced assembly process productivity. There was a problem.

  An object of the present invention is to provide a probe card that enables a comprehensive electrical performance test for a semiconductor device composed of stacked semiconductor chips and an electrical performance test method that increases the productivity of the assembly process. .

  To achieve the above object, a probe card according to claim 1 of the present invention is a probe card used for electrical performance inspection of a semiconductor device formed by stacking a second semiconductor chip on a first semiconductor chip. A base as a whole skeleton, a plurality of holders installed on the base and independently movable, a plurality of connectors fixed to each holder and electrically connected to an external inspection device, And a plurality of probe pins electrically connected to corresponding electrode pads of the first semiconductor chip or the second semiconductor chip, and the semiconductor at the tip portion of the probe pin The height in the vertical direction with respect to the device is different according to the semiconductor chip to be connected.

  The probe card according to claim 2 is the probe card according to claim 1, wherein the thickness of the holder corresponding to the second semiconductor chip is set to be greater than the thickness of the holder corresponding to the first semiconductor chip. By reducing the thickness of the semiconductor chip 2 by the thickness, a difference is provided in the height in the vertical direction of the tip portion of the probe pin with respect to the semiconductor device.

  The probe card according to claim 3 is the probe card according to claim 1, wherein a height of a tip portion of the probe pin corresponding to the second semiconductor chip in a direction perpendicular to the semiconductor device is the first semiconductor chip. The length of the probe pin corresponding to the first semiconductor chip is lower than the height of the tip portion of the probe pin corresponding to the height of the second semiconductor chip than the height in the direction perpendicular to the semiconductor device. The length of the probe pin corresponding to the second semiconductor chip is shortened.

  The probe card according to claim 4 is the probe card according to claim 1 or claim 2 or claim 3, wherein the holder becomes movable by being installed on the base via a bearing. It is characterized by.

  The probe card according to claim 5 is the probe card according to claim 1 or claim 2 or claim 3, wherein the holder becomes movable when the holder is placed on the base via silicone rubber. It is characterized by that.

  6. The electrical performance inspection method according to claim 6, wherein electrical performance inspection is performed on a semiconductor device formed by stacking a second semiconductor chip on a first semiconductor chip. An electrical performance inspection method performed using the probe card according to any one of the above, wherein the first semiconductor chip and the second semiconductor chip are connected via the probe card, and the semiconductor chip The connection state between the electrode pad and the probe pin is optimized.

  The electrical performance inspection method according to claim 7 is an electrical performance inspection in a state where the semiconductor device is formed by stacking the second semiconductor chip on the first semiconductor chip and mounted on the lead frame. An electrical performance inspection method using the probe card according to claim 1 or claim 2, wherein the first semiconductor chip and the second semiconductor chip are connected via the probe card. The connection is performed and the connection state between the electrode pad of the semiconductor chip and the probe pin is optimized.

  As described above, it is possible to provide a probe card that enables comprehensive electrical performance inspection and an electrical performance inspection method that enhances the productivity of the assembly process for a semiconductor device composed of stacked semiconductor chips.

  The present invention relates to a semiconductor device at a tip portion connected to an electrode pad of a probe pin of a probe card used for performing an electrical performance test on a semiconductor device formed by stacking another semiconductor chip on a semiconductor chip. Proper connection of the probe pin to the electrode pads of both semiconductor chips by providing a difference corresponding to the thickness of the semiconductor chip to be stacked on the vertical height (hereinafter referred to as the height of the tip of the probe pin) Therefore, it is possible to provide a probe card that enables comprehensive electrical performance inspection and an inspection method that increases the productivity of the assembly process for a semiconductor device composed of stacked semiconductor chips. .

  In particular, by providing a step corresponding to the thickness of the semiconductor chip to be stacked on the holder, the probe pin can be correctly connected to the electrode pads of both semiconductor chips. It is possible to provide a probe card that enables comprehensive electrical performance inspection and an electrical performance inspection method that increases the productivity of the assembly process.

  Also, by providing a difference corresponding to the thickness of the semiconductor chip to be stacked on the length of the probe pin, the probe pin can be correctly connected to the electrode pads of both semiconductor chips, and therefore, it is composed of stacked semiconductor chips. Therefore, it is possible to provide a probe card that enables comprehensive electrical performance inspection and an inspection method that increases the productivity of the assembly process.

  The probe card of the present invention is used for electrical performance inspection of a semiconductor device formed by stacking semiconductor chips, and the height of the tip portion of the probe pin is made different according to the semiconductor chip to be connected.

  For example, when an electrical performance test is performed on a semiconductor device formed by stacking a second semiconductor chip on a first semiconductor chip, a probe pin connected to the second semiconductor chip is previously connected to the second semiconductor chip. The height of the tip of the probe pin connected to the first semiconductor chip is made higher by the thickness of the semiconductor chip.

As described above, since the height of the tip portion of the probe pin differs corresponding to the semiconductor chip to be connected, the probe pin can be correctly connected to the electrode pads of both semiconductor chips at the time of inspection. Thus, it is possible to provide a probe card that enables comprehensive electrical performance inspection and an inspection method that increases the productivity of the assembly process for a semiconductor device including the semiconductor chip.
(Embodiment 1)
Embodiment 1 of the present invention will be described below with reference to the drawings.
FIG. 1 shows a cross-sectional structure diagram of a probe card and a prober stage according to Embodiment 1 of the present invention.

  In FIG. 1, the base 1 is the entire skeleton. The holders 2a, 2b, and 2c are positioned parallel to or below the base 1. The connectors 3a, 3b, and 3c are positioned below the holders 2a, 2b, and 2c, and the fixing portions 6a, 6b, and 6c are also positioned below the holders 2a, 2b, and 2c. The connectors 3a, 3b and 3c are located on the outer circumferences of the holders 2a, 2b and 2c, and the rings 4a, 4b and 4c are located on the inner circumferences of the holders 2a, 2b and 2c. The probe pins 5a, 5b, and 5c are connected to the connectors 3a, 3b, and 3c at the base, and the fixing members 6a, 6b, and 6c are positioned below the rings 4a, 4b, and 4c near the middle of the probe pins 5a, 5b, and 5c, The probe pins 5a, 5b and 5c are fixed respectively. The stage 7 is located below the base 1, the semiconductor wafer 8 is located on the stage 7, and the semiconductor chip 10 is located on the semiconductor wafer 8 via the adhesive 9.

Next, the configuration of the probe card and prober stage of FIG. 1 will be described.
The base 1 is the entire skeleton, the holders 2a, 2b, and 2c are the parts that physically support each probe pin, the connectors 3a, 3b, and 3c are the parts that electrically connect each probe pin to the inspection equipment, and the ring 4a 4b and 4c are parts for assisting high-precision placement of each probe pin, probe pins 5a, 5b and 5c are parts which are in contact with and electrically connected to electrode pads of the semiconductor wafer, and fixing members 6a, 6b and 6c are probes. The part 7 for fixing the pin arrangement is a part for arranging and fixing the wafer.

  A plurality of holders 2 a, 2 b, 2 c that can be moved up and down via bearings (not shown) are incorporated in the base 1, and a plurality of connectors 3 a, 3 b, 3 c and rings 4 a, 4 b, 4 c on the inner periphery of each holder Are attached, and the bases of the connectors 3a, 3b, 3c and the probe pins 5a, 5b, 5c are connected to each other. The tips of the probe pins 5 a, 5 b, and 5 c are bent so as to be in contact with the stacked semiconductor chip 10 and the electrode pads of the semiconductor wafer 8. The fixing members 6a, 6b, and 6c are located between the bent portions of the probe pins 5a, 5b, and 5c and the connectors 3a, 3b, and 3c, and fix the rings 4a, 4b, and 4c and the probe pins 5a, 5b, and 5c, The arrangement of the probe pins 5a, 5b and 5c is corrected. The stage 7 is movable up and down. Here, the thicknesses of the holder 2a and the holders 2b and 2c differ by the thickness of the semiconductor chip 10 to be laminated.

The operation of the probe card and the prober stage configured as described above according to Embodiment 1 of the present invention will be described with reference to FIG.
FIG. 2 shows a cross-sectional structure diagram of the semiconductor chip laminated with the probe card at the time of electrical performance inspection in Embodiment 1 of the present invention.

  As the stage 7 moves up, the tips of the probe pins 5 a come into contact with the electrode pads of the semiconductor chip 10, and the tips of the probe pins 5 b and 5 c come into contact with the electrode pads of the semiconductor wafer 8. In the electrode pad of the semiconductor chip 10 laminated on the semiconductor wafer 8, a step corresponding to the thickness of the semiconductor chip 10 (100 to 300 μm) is generated, but the step between the holders 2a, 2b, and 2c is a step corresponding to the thickness. Offset. Further, since the holder is movable, the position of the holder can be adjusted and optimized so that the probe pins are in uniform contact with each electrode pad.

  As the prober stage is raised, the probe pin and the electrode pad of the semiconductor wafer are physically changed from the non-contact state to the contact state, but the prober stage movement amount exceeds the movement point when it is further raised from the movement point at the initial contact. Drive amount. A less than 100 μm is distinguished from a low overdrive, and a 100 μm or more is distinguished from a high overdrive.

For comparison, FIG. 9 shows a cross-sectional structure in the case where an electrical performance test is performed on stacked semiconductor chips with a low overdrive amount using a conventional probe card and a prober stage.
The probe pins 5a are in contact with the electrode pads of the upper semiconductor chip 10, but the probe pins 1b and 1c are not in contact with the electrode pads of the lower semiconductor wafer 8, so that electrical continuity cannot be obtained, and electrical performance inspection is performed. I can't.

  As another comparison, FIG. 10 shows a cross-sectional structure when a stacked semiconductor chip is inspected for electrical performance with a high overdrive amount using a conventional probe card and a prober stage.

  The probe pins 1b and 1c are in contact with the electrode pads of the lower semiconductor wafer 8, but the probe pins 5a are excessively in contact with the electrode pads of the upper semiconductor chip 10, causing damage and breakage of the electrode pads. The performance inspection is not possible.

  In the first embodiment of the present invention, the probe pin reliably contacts the electrode pad without causing the damage or breakage of the electrode pad as described above, and the electrical characteristics including the matching between the stacked semiconductor chip and the semiconductor wafer are included. Performance tests can be performed.

In the first embodiment of the present invention, it has been described that the holder 8 incorporated in the base 5 can be moved up and down via a bearing. However, there is a configuration in which the holder 8 is movable up and down by using elastic silicone rubber without using a bearing. is there.
(Embodiment 2)
Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a cross-sectional structure diagram of the probe card and the prober stage according to the second embodiment of the present invention.
Base 1 is the entire skeleton. The holders 2a, 2b, and 2c are located at the same level as or below the base 1. The connectors 3a, 3b, and 3c are positioned below the holders 2a, 2b, and 2c, and the fixing portions 6a, 6b, and 6c are positioned below the holders 2a, 2b, and 2c. The connectors 3a, 3b, and 3c are positioned on the outer periphery of the holders 2a, 2b, and 2c, and the rings 4a, 4b, and 4c are positioned on the inner periphery of the holders 2a, 2b, and 2c.

  The probe pins 5a, 5b, and 5c are connected to the connectors 3a, 3b, and 3c at their respective bases, and the fixing portions 6a, 6b, and 6c are positioned below the rings 4a, 4b, and 4c near the middle of the probe pins 5a, 5b, and 5c. To do.

The stage 7 is positioned below the base 5, the semiconductor wafer 8 is positioned on the stage 7, and the semiconductor chip 10 is positioned on the semiconductor wafer 8 via the adhesive 9.
Next, the configuration of the probe card and prober stage of FIG. 3 will be described.

  A plurality of holders 2 a, 2 b, 2 c that can be moved up and down via bearings (not shown) are incorporated in the base 1 that is a skeleton, and a plurality of connectors 3 a, 3 b, 3 c and the inside of each holder 2 a, 2 b, 2 c Rings 4a, 4b, and 4c are attached to the periphery, and the bases of the connectors 3a, 3b, and 3c and the plurality of probe pins 5a, 5b, and 5c are connected to each other. The tips of the probe pins 5a, 5b, and 5c are bent so as to be in contact with the semiconductor wafer 8 and the electrode pads of the semiconductor chip 10, and the fixing portions 6a, 6b, and 6c are bent at the probe pins 5a, 5b, and 5c and the connector 3a. Positioned between 3b and 3c, the rings 4a, 4b, and 4c and the probe pins 4a, 4b, and 4c are fixed, and the arrangement of the probe pins 4a, 4b, and 4c is corrected. The stage 7 is movable up and down. The length of the distal end side of the probe pin 5a is different from the length of the distal end side of the probe pins 5b and 5c, and the height of the distal end portion of the probe pin 5a is set to the thickness of the semiconductor chip 9 from the height of the distal end portion of the probe pins 5b and 5c. It is a configuration that becomes higher by a minute.

The operation of the probe card and the prober stage of the present invention configured as described above will be described with reference to FIG.
FIG. 4 is a cross-sectional structure diagram of a semiconductor chip laminated with a probe card at the time of electrical performance inspection in Embodiment 2 of the present invention.

  As the stage 7 moves up, the tips of the probe pins 5 a come into contact with the electrode pads of the semiconductor chip 10, and the tips of the probe pins 5 b and 5 c come into contact with the electrode pads of the wafer 8. In the electrode pad of the semiconductor chip 10 stacked on the wafer 8, a step corresponding to the thickness of the semiconductor chip 9 (100 to 300 μm) occurs, but the height of the tip of the probe pin 5a is higher than the height of the tip of the probe pins 5b and 5c. By increasing the thickness by the thickness of the semiconductor chip 9, the step of the semiconductor chip 10 is offset. Further, the probe pins uniformly contact each electrode pad by the movement of the holders 4a, 4b, and 4c. Further, by keeping the shape of the base side from the bent part of the probe pins 5a, 5b, and 5c to a fixed length, the stress on the electrode pad surface with the chip thickness step becomes uniform, and the probe trace is uniform and small. it can.

Therefore, in the probe card according to the second embodiment of the present invention, the probe pin surely contacts the electrode pad without causing damage / breakage of the electrode pad, and includes the consistency between the stacked semiconductor chip and the semiconductor wafer. Conduct electrical performance tests.
(Embodiment 3)
Next, an inspection method using the probe card according to Embodiment 3 of the present invention will be described with reference to FIG.

FIG. 5 is a cross-sectional structure diagram of a semiconductor chip laminated with a probe card at the time of electrical performance inspection in Embodiment 3 of the present invention.
In FIG. 5, first, the semiconductor chip 10 as an upper layer is divided individually through a back grinding process and a dicing process without performing an electrical performance inspection for each chip in the wafer state. Next, in the wafer state, the lower semiconductor wafer 8 is not subjected to electrical performance inspection for each chip, and the semiconductor chip 10 is placed on the circuit surface of the semiconductor wafer 8 with the adhesive 9 so that the circuit surface faces upward. And glue. At this point, there is a semiconductor wafer 8 in which the semiconductor chips 10 are stacked. A semiconductor wafer 8 on which a semiconductor chip 10 is laminated is placed on a prober stage 7, and a probe pin is connected to an external lead electrode pad of the semiconductor chip 10 using the probe card according to the first or second embodiment of the present invention. 1a is brought into contact, the probe pin 1b is brought into contact with the internal interface electrode pad of the semiconductor wafer 8, and the probe pin 1c is brought into contact with the external lead-out electrode pad of the semiconductor wafer 8 to be electrically connected. At this time, since there is a difference in the thickness of the tip of the probe pin by the thickness of the semiconductor chip 10, the probe pin can be connected to both semiconductor chips, and further, the holder that can be moved up and down is more reliable. It is possible to optimize the connection state by adjusting the height of the probe pin so as to be in the connection state. Also, the internal interface electrode pad of the semiconductor wafer 8 and the external interface electrode pad of the semiconductor chip 10 which is electrically connected to the internal interface electrode pad by a wire in a subsequent process are electrically connected through a circuit in the probe card. As a result, not only the electrical performance inspection of individual semiconductor chips, but also the electrical performance inspection including consistency can be performed as a semiconductor chip in which the semiconductor chip 10 laminated on the wafer 8 is formed as one unit.
(Embodiment 4)
Next, an inspection method using a probe card according to Embodiment 4 of the present invention will be described with reference to FIG.

FIG. 6 is a cross-sectional structure diagram of a semiconductor chip laminated with a probe card at the time of electrical performance inspection in Embodiment 4 of the present invention.
In FIG. 6, first, in the wafer state, the lower semiconductor chip 14 is divided into individual semiconductor chips through a back grinding process and a dicing process without performing an electrical performance inspection for each chip. Next, in the wafer state, the upper semiconductor chip 10 is divided into individual semiconductor chips through a back grinding process and a dicing process without performing electrical performance inspection for each chip. Thereafter, the semiconductor chip 14 is fixed on the lead frame 11 with an insulating adhesive 12 so that the circuit surface faces upward, and the semiconductor chip 10 is placed on the circuit surface of the semiconductor chip 14 so that the circuit surface faces upward. It is fixed through the adhesive film 13. A lead frame 11 laminated on a stage 15 provided with guide rails is arranged so that the lead frame can be conveyed, and the probe card according to the first or second embodiment of the present invention is used to lead out the semiconductor chip 10 to the outside. The probe pin 5a is brought into contact with the electrode pad for use, the probe pin 5b is brought into contact with the electrode pad for the internal interface of the semiconductor wafer 14, and the probe pin 5c is brought into contact with the electrode pad for leading out to be electrically connected. At this time, since there is a difference in the thickness of the tip of the probe pin by the thickness of the semiconductor chip 10, the probe pin can be connected to both semiconductor chips, and further, the holder that can be moved up and down is more reliable. It is possible to optimize the connection state by adjusting the height of the probe pin so as to be in the connection state. In addition, the internal interface electrode pad of the semiconductor wafer 14 and the external interface electrode pad of the semiconductor chip 10 which are electrically connected to the internal interface electrode pad by a wire in a subsequent process are electrically connected through a circuit in the probe card. As a result, not only the electrical performance inspection of individual semiconductor chips but also the electrical performance inspection including consistency as a semiconductor chip in which the semiconductor chip 10 and the semiconductor chip 14 stacked on the lead frame 11 are formed as one unit. Can be implemented.

  The probe card and electrical performance inspection of the present invention are a probe card that enables comprehensive electrical performance inspection for a semiconductor device composed of stacked semiconductor chips and an inspection method that increases the productivity of the assembly process. The probe card can be provided, and is useful as a probe card used for electrical performance inspection of a stacked semiconductor integrated circuit device, and an electrical performance inspection method using the same.

Sectional structure diagram of probe card and prober stage in Embodiment 1 of the present invention Sectional structure diagram of semiconductor chip laminated with probe card at the time of electrical performance inspection in Embodiment 1 of the present invention Sectional structure diagram of probe card and prober stage in embodiment 2 of the present invention Sectional structure diagram of semiconductor chip stacked with probe card at the time of electrical performance inspection in Embodiment 2 of the present invention Sectional structure diagram of semiconductor chip laminated with probe card at the time of electrical performance inspection in Embodiment 3 of the present invention Sectional structure diagram of semiconductor chip laminated with probe card at the time of electrical performance inspection in Embodiment 4 of the present invention Cross-sectional structure diagram of conventional probe card and prober stage Cross-sectional structure diagram of probe card and prober stage during conventional electrical performance inspection Cross-sectional structure diagram of electrical performance inspection of stacked semiconductor chips with a low overdrive amount using a conventional probe card and prober stage Cross-sectional structure diagram of electrical performance inspection of stacked semiconductor chips using a conventional probe card and prober stage with a high overdrive amount

Explanation of symbols

1 Base 2a Holder 2b Holder 2c Holder 3 Connector 3a Connector 3b Connector 3c Connector 4 Ring 4a Ring 4b Ring 4c Ring 5 Probe Pin 5a Probe Pin 5b Probe Pin 5c Probe Pin 6 Fixing Material 6a Fixing Material 6b Fixing Material 6c Fixing Material 6c Fixing Material 6c 8 Semiconductor wafer 9 Adhesive 10 Semiconductor chip 11 Lead frame 12 Insulating adhesive 13 Adhesive film 14 Semiconductor chip 15 Stage provided with guide rail

Claims (7)

A probe card used for electrical performance inspection of a semiconductor device formed by stacking a second semiconductor chip on a first semiconductor chip,
The base that is the whole skeleton,
A plurality of holders installed on the base and independently movable;
A plurality of connectors fixed for each holder and electrically connected to an external inspection device;
A plurality of probe pins electrically connected to the respective connectors and electrically connected to corresponding electrode pads of the first semiconductor chip or the second semiconductor chip; A probe card, wherein a height in a vertical direction with respect to the semiconductor device is different according to a semiconductor chip to be connected.   By making the thickness of the holder corresponding to the second semiconductor chip thinner than the thickness of the holder corresponding to the first semiconductor chip by the thickness of the second semiconductor chip, the tip of the probe pin 2. The probe card according to claim 1, wherein a difference is provided in a height in a vertical direction of the portion with respect to the semiconductor device.   The vertical height of the tip portion of the probe pin corresponding to the second semiconductor chip with respect to the semiconductor device is the vertical height of the tip portion of the probe pin corresponding to the first semiconductor chip with respect to the semiconductor device. The length of the probe pin corresponding to the second semiconductor chip is made shorter than the length of the probe pin corresponding to the first semiconductor chip so as to be lower than the thickness of the second semiconductor chip. The probe card according to claim 1.   The probe card according to claim 1, wherein the holder is movable when the holder is installed on the base via a bearing.   4. The probe card according to claim 1, wherein the holder is movable when the holder is placed on the base via silicone rubber. An electrical performance test is performed on the semiconductor device formed by stacking the second semiconductor chip on the first semiconductor chip using the probe card according to claim 1, claim 2, or claim 3. An electrical performance inspection method,
Electrical performance inspection characterized in that the first semiconductor chip and the second semiconductor chip are connected via the probe card, and the connection state between the electrode pads and the probe pins of the semiconductor chip is optimized. Method. 4. The electrical performance inspection of the semiconductor device formed by stacking the second semiconductor chip on the first semiconductor chip in a state of being mounted on the lead frame. An electrical performance inspection method performed using the probe card described in 1.
Electrical performance inspection characterized in that the first semiconductor chip and the second semiconductor chip are connected via the probe card, and the connection state between the electrode pads and the probe pins of the semiconductor chip is optimized. Method.

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