JP2005328684A - Abnormal cell detecting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect an abnormal cell, without providing a cell controller. <P>SOLUTION: An abnormality discriminating portion A1-An provided for each cell outputs an abnormality detection signal and turns on its corresponding one of MOS transistor B1-Bn, if abnormality of its corresponding cell is detected. This constitutes a CR circuit with a resistor R1 and one of capacitors C1-Cn being connected to the turned-on one of the MOS transistors B1-Bn. Thus, the output of rectangular wave pulse signals from a battery controller 10 gradually raises a voltage at K1 point with a time constant τ of the CR circuit so that the pulse width of the rectangular wave pulse signals outputted from an AND circuit 6 has a value different from that of outputted pulses. Thus, an abnormal cell is detected. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an apparatus for detecting an abnormality in a plurality of cells constituting an assembled battery.

  A technique is known in which a cell controller is provided for each module composed of a predetermined number of cells, a failure of a cell in the module is detected, and cell failure information is transmitted to the battery controller via serial communication (patent) Reference 1).

JP 2003-134683 A

  However, in the conventional technique, a cell controller is required to detect a cell failure, and communication between a plurality of cell controllers and a battery controller is required, which complicates the configuration of the apparatus. There was a problem.

  An abnormal cell detection device according to the present invention is provided with a pulse signal output means for outputting a rectangular wave pulse signal having a reference pulse width, and is provided for each of a plurality of cells to determine whether or not an abnormality has occurred in the corresponding cell. And a pulse for changing the pulse width of the pulse signal output from the pulse signal output means to be different for each cell in which an abnormality has occurred when it is determined that an abnormality has occurred in the corresponding cell. An abnormal cell detection unit that detects a cell in which an abnormality has occurred based on the width changing unit, the reference pulse width, and the pulse width changed by the pulse width changing unit.

  According to the abnormal cell detection device of the present invention, it is possible to detect a cell in which an abnormality has occurred without providing a cell controller, and to identify a cell in which an abnormality has occurred.

  FIG. 1 is a diagram showing a configuration of an embodiment of an abnormal cell detection device according to the present invention. An abnormal cell detection device according to an embodiment includes an abnormality determination unit A1 to An (n is a natural number of 2 or more), N channel MOS transistors B1 to Bn (hereinafter simply referred to as MOS transistors B1 to Bn), a capacitor C1-Cn, diode 5, AND circuit 6, P-channel MOS transistor 7 (hereinafter simply referred to as MOS transistor 7), power supply circuit 8, resistors R1, R2, R3, capacitor Ca, PNP A transistor 9 and a battery controller 10 are provided.

  The assembled battery 1 is configured by connecting a plurality of cells S1 to Sn in series. Abnormality determination units A1 to An, MOS transistors B1 to Bn, and capacitors C1 to Cn are provided corresponding to the cells S1 to Sn, respectively. The capacities of the n capacitors C1 to Cn are all different.

  Each of the abnormality determination units A1 to An detects a cell overcharge abnormality by comparing the voltage of the corresponding cell S1 to Sn with a predetermined upper limit voltage, and compares the cell voltage with a predetermined lower limit voltage. By doing so, an overdischarge abnormality of the cell is detected. The gates of the MOS transistors B1 to Bn are connected to the abnormality determination units A1 to An, respectively, and a signal (positive voltage) indicating a cell overcharge abnormality or overdischarge abnormality is supplied to the gate from the corresponding abnormality determination unit A1 to An. When input, the MOS transistors B1 to Bn are turned on.

  One input terminal of the AND circuit 6 is connected to the capacitors C <b> 1 to Cn, and the other input terminal is connected to the cathode of the diode 5. The output terminal of the AND circuit 6 is connected to the battery controller 10. The anode of the diode 5 is connected to each of the capacitors C <b> 1 to Cn, and the resistor R <b> 1 is connected in parallel with the diode 5. Further, a connection point K2 where the cathode of the diode 5 and the resistor R1 are connected is also connected to the battery controller 10.

  A series circuit including the resistor R2 and the capacitor Ca is connected in parallel with the assembled battery 1. The gate of the MOS transistor 7 is connected to a connection point K3 between the resistor R2 and the capacitor Ca, and the source is connected to the positive electrode of the assembled battery 1. The drain of the MOS transistor 7 is connected to the negative electrode of the assembled battery 1 through the power supply circuit 8. The power supply circuit 8 supplies power to the abnormality determination units A1 to An while the MOS transistor 7 is turned on.

  One end of the resistor R3 is connected to the connection point K3, and the other end is connected to the emitter of the PNP transistor 9. The base of the PNP transistor 9 is connected to the battery controller 10, and the collector is connected to the negative electrode of the assembled battery 1.

  A method for detecting an abnormal cell by the battery controller 10 will be described. Hereinafter, a case will be described in which all of the cells S2 to Sn are normal and an abnormality determination unit A1 detects an overcharge abnormality or an overdischarge abnormality of the cell S1. The battery controller 10 includes a transmission circuit 10a, and outputs an abnormality diagnosis clock signal CLK having a reference pulse width from the transmission circuit 10a when detecting a cell abnormality.

  FIG. 2A is a diagram illustrating a waveform of the clock signal CLK output from the transmission circuit 10 a of the battery controller 10. As shown in FIG. 2A, the clock signal CLK is a rectangular wave pulse having a predetermined period. When the abnormality determination unit A1 does not detect the abnormality of the cell S1, the MOS transistor B1 is turned off, so that the voltage waveform at the connection point K1 between the capacitor C1 and the input terminal of the AND circuit 6 is as shown in FIG. As shown in (b), the waveform of the clock signal CLK output from the transmission circuit 10a of the battery controller 10 is the same.

  FIG. 2C is a diagram showing signal waveforms input from the AND circuit 6 to the battery controller 10 when no abnormality of the cell S1 is detected. As described above, when no abnormality occurs in the cell S1 (when all the cells are normal), a signal (FIG. 2A) input to the AND circuit 6 through the connection point K2, The signal input to the AND circuit 6 via the connection point K1 (FIG. 2B) has the same signal waveform and phase. Accordingly, the waveform of the clock signal CLK output from the transmission circuit 10a of the battery controller 10 and the waveform of the signal input to the battery controller 10 are the same.

  3 (a) to 3 (c) are signal waveforms when the overcharge abnormality or overdischarge abnormality of the cell S1 is detected by the abnormality determination unit A1, and FIGS. This corresponds to c). 3A shows the waveform of the clock signal CLK output from the transmission circuit 10a of the battery controller 10, FIG. 3B shows the signal waveform of the connection point K1, and FIG. 3C shows the battery. The waveforms of signals input to the controller 10 are shown.

  When the abnormality determination unit A1 detects an overcharge abnormality or an overdischarge abnormality of the cell S1, the MOS transistor B1 is turned on based on a signal output from the abnormality determination unit A1. In this case, the capacitor C1 is grounded via the MOS transistor B1. Therefore, when the clock signal CLK is output from the transmission circuit 10a of the battery controller 10, the signal waveform at the connection point K1 has a delayed pulse rise as shown in FIG. That is, when the MOS transistor B1 is turned on, the resistor R1 and the capacitor C1 form a CR circuit. Therefore, the time until the signal level (voltage value) at the connection point K1 reaches the H level is It is delayed by a constant τ1 (= C1 × R1).

  As a result, the waveform of the signal output from the AND circuit 6 is cut by the time constant τ from the waveform of the clock signal CLK output from the transmission circuit 10a of the battery controller 10, as shown in FIG. It becomes a square wave. The battery controller 10 detects that an abnormal cell has occurred by detecting that the on / off duty of the signal input from the AND circuit 6 is different from the on / off duty of the output clock signal CLK. Detect.

  In addition, by providing the diode 5 in parallel with the resistor R1, the voltage value at the connection point K1 quickly decreases as the pulse of the clock signal CLK falls. As a result, the voltage value at the connection point K1 can be set to zero until the next pulse of the clock signal CLK rises.

  4 (a) to 4 (c) show signal waveforms when the abnormality determination unit An detects an overcharge abnormality or an overdischarge abnormality of the cell Sn, and FIGS. 2 (a) to 2 (c) respectively. This corresponds to (c). It is assumed that the cells S1 to Sn-1 are all in a normal state. Here, description will be made assuming that the capacitance of the capacitor Cn is larger than the capacitance of the capacitor C1. In this case, the MOS transistor Bn is turned on, and a CR circuit is configured by the resistor R1 and the capacitor Cn. Therefore, the time until the signal level at the connection point K1 becomes H level is delayed by the time constant τn (= Cn × R1) of the CR circuit (see FIG. 4B). As a result, the signal input from the AND circuit 6 to the battery controller 10 becomes a narrow rectangular wave as shown in FIG.

  As described above, since the capacities of the capacitors C1 to Cn are all different, when an abnormality occurs in any of the cells S1 to Sn, the width of the rectangular wave input from the AND circuit 6 to the battery controller 10, that is, the input The ON / OFF duty of the signal to be changed is different for each cell. Therefore, the battery controller 10 can detect an abnormal cell by detecting the on / off duty of the signal input from the AND circuit 6, and can identify the cell in which the abnormality has occurred.

  When the number of cells constituting the assembled battery 1 is small, there are few patterns of signals input from the AND circuit 6 to the battery controller 10 when an abnormality occurs in the cells S1 to Sn. It is possible to identify the cell in which the occurrence occurred. However, when the number of cells constituting the assembled battery 1 increases, the amount of change in the time constants τ1 to τn (see FIG. 3B and FIG. 4B) must be reduced. Therefore, it is necessary to improve the detection accuracy of the on / off duty of the signal input from the AND circuit 6.

  In the abnormal cell detection apparatus according to the embodiment, in the battery controller 10, in order to identify an abnormal cell without increasing the on / off duty detection accuracy of the signal input from the AND circuit 6, the transmission circuit of the battery controller 10 is used. The frequency (pulse width) of the clock signal CLK output from 10a is changed.

  FIG. 5 shows an abnormality when the time constant τ of the CR circuit formed when the frequency of the clock signal CLK output from the transmission circuit 10a of the battery controller 10 is increased and any of the MOS transistors B1 to Bn is turned on is small. It is a figure for demonstrating the cell detection method. FIG. 6 shows a case where the time constant τ of the CR circuit configured when one of the MOS transistors B1 to Bn is turned on by decreasing the frequency of the clock signal CLK output from the transmission circuit 10a of the battery controller 10 is large. It is a figure for demonstrating this abnormal cell detection method. FIGS. 5A to 5C and FIGS. 6A to 6C correspond to FIGS. 2A to 2C, respectively.

  When the time constant τ of the CR circuit is small, the clock signal CLK output from the transmitter circuit 10a of the battery controller 10 is increased by increasing the frequency of the clock signal CLK (decreasing the period) (see FIG. 5A). It becomes easy to detect the difference between the on / off duty and the on / off duty of the signal input from the AND circuit 6. For example, when the frequency of the clock signal CLK is small as shown in FIG. 6A (the period is large), the H level portion of the signal input from the AND circuit 6 to the battery controller 10 and the output from the transmission circuit 10a Since the difference from the H level portion of the clock signal CLK to be generated becomes small, it becomes difficult to detect the difference between the two signals.

  On the other hand, when the time constant τ of the CR circuit is large, by reducing the frequency of the clock signal CLK (see FIG. 6A), the on / off duty of the clock signal CLK output from the transmission circuit 10a, and AND It becomes easy to detect the difference between the on / off duty of the signal input from the circuit 6. For example, when the frequency of the clock signal CLK is large as shown in FIG. 5A, if the time constant τ is larger than the time of the H level portion of the clock signal CLK, the battery controller 10 receives a rectangular wave signal. Is no longer entered. Therefore, when there are a plurality of CR circuits having a time constant τ larger than the time of the H level portion of the clock signal CLK, it becomes impossible to specify which cell has an abnormality.

  As described above, the battery controller 10 outputs the clock signal CLK while changing the frequency (reference pulse width) of the clock signal CLK, thereby increasing the on / off duty detection accuracy of the signal input from the AND circuit 6. An abnormal cell can be identified without increasing it. That is, an abnormal cell can be reliably identified whether the CR circuit time constant τ is small or large. Thereby, it is not necessary to reduce the capacitance difference between the capacitors C1 to Cn, compared to the case where the frequency of the clock signal CLK is not changed.

  Here, the operation of the power supply circuit 8 when the clock signal CLK is not output from the transmission circuit 10a of the battery controller 10 and when the clock signal CLK is output will be described. FIG. 7A shows the clock signal CLK output from the transmission circuit 10a of the battery controller 10, and FIG. 7B shows that the output of the clock signal CLK is stopped while the clock signal CLK is being output. It is a figure which shows the voltage applied to the gate (control terminal) of the MOS transistor 7 after being done.

  When the clock signal CLK is output from the transmission circuit 10a, that is, when a positive voltage is applied to the base of the PNP transistor 9, the PNP transistor 9 is turned on. On the contrary, when the clock signal CLK is not output, that is, when the positive voltage is not applied to the base of the PNP transistor 9, the PNP transistor 9 is turned off. When the PNP transistor 9 is turned off, the gate voltage of the MOS transistor 7 rises at the time constant τa1 of the CR circuit constituted by the resistor R2 and the capacitor Ca. However, since the PNP transistor 9 is turned on based on the clock signal CLK before the gate voltage reaches the reference voltage at which the MOS transistor 9 is turned off, the gate voltage is lowered. That is, when the PNP transistor 9 is turned on, the gate voltage of the MOS transistor 7 decreases at the time constant τa2 of the CR circuit formed by the resistor R3 and the capacitor Ca.

  Thus, the MOS transistor 7 is on while the clock signal CLK is output from the transmission circuit 10a of the battery controller 10. Thereby, power is supplied from the power supply circuit 8 to the abnormality determination units A1 to An.

  On the other hand, when the clock signal CLK is not output from the transmission circuit 10a of the battery controller 10 (output stop), the gate voltage of the MOS transistor 7 continues to rise and exceeds the reference voltage at which the MOS transistor 7 is turned off. . Thereby, since the MOS transistor 7 is turned off, the power supply from the power supply circuit 8 to the abnormality determination units A1 to An is also stopped.

  That is, according to the abnormal cell detection apparatus in the embodiment, when detecting an abnormal cell, power is supplied from the power supply circuit 8 to the abnormality determination units A1 to An, and the abnormal cell is not detected. During the period, the power supply from the power supply circuit 8 to the abnormality determination units A1 to An is stopped, so that it is possible to suppress power consumption during a period in which abnormal cells are not detected.

  According to the abnormal cell detection device in one embodiment, when an abnormality occurs in the cells S1 to Sn constituting the assembled battery 1, the pulse width of the rectangular wave pulse signal output from the transmission circuit 10a is changed to the cell in which the abnormality has occurred. The abnormal cell is detected based on the pulse width of the output pulse (reference pulse width) and the pulse width of the input pulse. Accordingly, it is possible to detect a cell in which an abnormality has occurred without providing a cell controller, and to identify a cell in which an abnormality has occurred.

  In addition, when an abnormal cell occurs, a CR circuit is configured with capacitors and resistors provided corresponding to each cell, and the pulse width is changed according to the time constant of the configured CR circuit. With a simple configuration, a circuit having a different pulse width for each cell in which an abnormality has occurred can be configured.

  In addition, according to the abnormal cell detection device in one embodiment, since the reference pulse width of the rectangular wave pulse signal output from the transmission circuit 10a of the battery controller 10 is changed, it is configured when an abnormal cell occurs. In both cases where the time constant τ of the CR circuit is small and large, an abnormal cell can be identified reliably.

  Furthermore, according to the abnormal cell detection device in one embodiment, power is supplied to the abnormality determination units A1 to An that detect abnormal cells based on the rectangular wave pulse signal output from the transmission circuit 10a of the battery controller 10. Since the stop is performed, it is possible to automatically suppress the power consumption when the abnormal cell is not detected.

  The present invention is not limited to the embodiment described above. For example, as an example of changing the frequency of the clock signal CLK output from the transmission circuit 10a of the battery controller 10, the method of switching between two types of frequencies has been described using FIG. 5 and FIG. You may make it switch.

  The correspondence between the constituent elements of the claims and the constituent elements of the embodiment is as follows. That is, the battery controller 10 changes the pulse width of the pulse signal output means and the abnormal cell detection means, the abnormality determination units A1 to An change the abnormality determination means, the MOS transistors B1 to Bn, the capacitors C1 to Cn, the resistor R1 and the AND circuit 6 change the pulse width. The power supply circuit 8 constitutes the power supply means. In addition, as long as the characteristic function of this invention is not impaired, each component is not limited to the said structure.

The figure which shows the structure of one Embodiment of the abnormal cell detection apparatus by this invention. FIG. 2A shows the waveform of the clock signal CLK output from the battery controller, FIG. 2B shows the signal waveform at the connection point K1, and FIG. c) shows the waveforms of signals input to the battery controller. FIG. 3 (a) shows the waveform of the clock signal CLK output from the battery controller, and FIG. 3 (b) shows the signal waveform at the connection point K1. 3 (c) shows the waveforms of signals input to the battery controller. FIG. 4 (a) shows the waveform of the clock signal CLK output from the battery controller, and FIG. 4 (b) shows the signal waveform of the connection point K1. 4 (c) shows the waveforms of signals input to the battery controller. FIG. 5 shows a signal waveform when the frequency of the clock signal CLK is increased when the time constant τ of the CR circuit is small. FIG. 5A shows the waveform of the clock signal CLK output from the battery controller. 5 (b) shows the signal waveform at the connection point K1, and FIG. 5 (c) shows the waveform of the signal input to the battery controller. FIG. 6 shows a signal waveform when the frequency of the clock signal CLK is reduced when the time constant τ of the CR circuit is large. FIG. 6A shows the waveform of the clock signal CLK output from the battery controller. 6 (b) shows the signal waveform at the connection point K1, and FIG. 6 (c) shows the waveform of the signal input to the battery controller. 7A shows the clock signal CLK output from the battery controller, and FIG. 7B shows the MOS when the clock signal CLK is output and when the output of the clock signal CLK is stopped. The figure which shows the voltage applied to the gate of the transistor 7

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Assembly battery 5 ... Diode 6 ... AND circuit 7 ... P channel MOS transistor 8 ... Power supply circuit 9 ... PNP transistor 10 ... Battery controller S1-Sn ... Cell A1-An ... Abnormality determination part B1-Bn ... N channel MOS transistor C1 ~ Cn, Ca ... Capacitors R1-R3 ... Resistance

Claims (5)

In an abnormal cell detection device for detecting an abnormality in a plurality of cells constituting an assembled battery,
Pulse signal output means for outputting a rectangular wave pulse signal having a reference pulse width;
An abnormality determining means that is provided for each of the plurality of cells and determines whether an abnormality has occurred in the corresponding cell;
When it is determined by the abnormality determining means that an abnormality has occurred in the corresponding cell, the pulse width of the pulse signal output from the pulse signal output means is changed to be different for each cell in which an abnormality has occurred. Pulse width changing means;
An abnormal cell detection apparatus, comprising: an abnormal cell detection unit that detects a cell in which an abnormality has occurred based on the reference pulse width and the pulse width changed by the pulse width change unit. In the abnormal cell detection device according to claim 1,
The pulse width changing means includes at least a resistor and a plurality of capacitors having different capacities provided corresponding to each cell, and the abnormality determining means determines that an abnormality has occurred in the cell. And a capacitor provided corresponding to the cell determined to have the abnormality and a resistor constitute a CR circuit, and the reference pulse is determined according to the time constant of the constructed CR circuit. An abnormal cell detection device characterized by changing a width. In the abnormal cell detection device according to claim 1 or 2,
The abnormality determining means determines whether or not the cell is overcharged abnormally by comparing the voltage of the corresponding cell with a predetermined upper limit voltage, and calculates the voltage of the corresponding cell and the predetermined lower limit voltage. An abnormal cell detection device, characterized in that, by comparing, it is determined whether or not a cell is overdischarge abnormal. In the abnormal cell detection apparatus in any one of Claims 1-3,
The abnormal cell detection device, wherein the pulse signal output means outputs a plurality of pulse signals having different reference pulse widths. In the abnormal cell detection apparatus in any one of Claims 1-4,
A power supply means for supplying power to the abnormality determination means;
The abnormal cell detection device, wherein the power supply means supplies and stops power to the abnormality determination means based on a pulse signal output from the pulse signal output means.

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