JP2005310817A - Method of manufacturing semiconductor device, circuit board, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein the warping of a substrate can be suppressed or removed which comes from a difference in physical constant between the substrate and a functional layer formed on the substrate, and also to provide its manufacturing method, a circuit board, and an electronic apparatus. <P>SOLUTION: The method of manufacturing the semiconductor device having an electrode 34 extended through the substrate 10 comprises processes of forming a concave portion H4 in the active surface of the substrate; forming a first insulation layer on the active surface of the substrate including the inner surface of the concave portion; forming the electrode by filling the inside of the concave portion formed with the first insulation film 22 by a conductor; removing the rear face side of the active surface to expose the electrode and the first insulation film formed in the periphery of the electrode from the rear face of the active surface; and forming, on the rear face of the active surface, a second insulation layer 26 having the same direction for the internal stress as that of the first insulation layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device manufacturing method, a circuit board, and an electronic apparatus.

  In portable electronic devices such as mobile phones, notebook personal computers, and PDAs (Personal data assistance), various electronic components such as semiconductor chips provided therein are becoming smaller in response to demands for miniaturization and weight reduction. It is planned. For example, in a semiconductor chip, the packaging method has been devised, and at present, ultra-small packaging called CSP (Chip Scale Package) is provided. A semiconductor chip manufactured using this CSP technology has a mounting area comparable to the area of the semiconductor chip, and thus realizes high-density mounting.

Therefore, since the electronic devices tend to be required to be smaller and more multifunctional in the future, it is necessary to further increase the mounting density of semiconductor chips. Under such background, in recent years, a three-dimensional mounting technique has been proposed. This three-dimensional mounting technique is a technique for achieving high-density mounting of semiconductor chips by stacking semiconductor chips having similar functions or semiconductor chips having different functions and interconnecting the semiconductor chips. (For example, refer to Patent Document 1).
JP 2001-53218 A

By the way, a through hole is formed in the semiconductor chip, and an electrode is formed in the through hole. The semiconductor chip is electrically connected to each other by the electrode to realize the above-described three-dimensional mounting technology. Yes. An insulating layer is formed on the active surface and the through hole of the semiconductor chip, and this insulating layer functions as an insulating film inside the through hole and a protective film for the electrode terminal formed on the back surface of the semiconductor chip.
However, the substrate constituting the semiconductor chip and the insulating layer formed on the substrate have different physical constants, that is, thermal expansion coefficient and internal stress. Furthermore, the insulating layer is formed only on one of the active surfaces on which the integrated circuit is formed. Therefore, when a chip is formed, stress (stress) is generated in the substrate due to the difference in internal stress between the substrate and the insulating layer formed on the substrate, and the substrate is deformed by this stress, and warpage occurs. Due to such warpage of the substrate, it becomes difficult to mount the semiconductor chip on the substrate. Furthermore, as described above, when semiconductor chips are stacked on a semiconductor chip (three-dimensional mounting), each of the semiconductor chips is curved toward the active surface side or the back surface side where the integrated circuit of the semiconductor chip is formed. Therefore, it may be difficult to stack semiconductor chips and to electrically or mechanically connect the electrodes of both semiconductor chips.

  The present invention has been made in view of the above problems, and a semiconductor device and a semiconductor device capable of suppressing or removing warpage of the substrate caused by a difference in physical constant between the substrate and a functional layer formed on the substrate A manufacturing method, a circuit board, and an electronic device are provided.

  In order to solve the above-described problems, the present invention provides a method of manufacturing a semiconductor device having an electrode penetrating a substrate, the step of forming a recess in an active surface of the substrate, and the substrate including the inside of the recess Forming a first insulating layer on the active surface; filling a conductive material into the recess in which the insulating layer is formed; and forming the electrode; and removing the back side of the active surface. Exposing the electrode and the first insulating layer formed on the outer periphery of the electrode from the back surface of the active surface; and the direction of internal stress on the back surface of the active surface is the same as that of the first insulating layer Forming a second insulating layer in a direction.

  The internal stress differs between the substrate and the insulating layer formed on the active surface of the substrate. When a chip is formed, the difference in internal stress causes the substrate to bend and warp to the active surface side or back surface side of the first substrate. According to the present invention, since the second insulating layer whose internal stress is in the same direction as the first insulating layer is formed on the back side of the active surface, the internal stress of the second insulating layer causes the substrate and the substrate to The difference in internal stress with the first insulating layer formed on the active surface can be balanced or reduced. As a result, it is possible to remove or suppress the occurrence of warpage of the substrate caused by the difference between the internal stress and the first insulating layer formed on the substrate and the active surface of the substrate.

The second insulating layer is made of the same material as the first insulating layer.
According to such a configuration, since the internal stress of the first insulating layer and the second insulating layer are composed of the same kind of layers, the internal stress of both layers can be made the internal stress in the same direction, It is possible to balance or reduce the difference in internal stress between the substrate and the first insulating layer. As a result, it is possible to suppress the occurrence of warpage of the substrate caused by the difference between the internal stress and the first insulating layer formed on the substrate and the active surface of the substrate.

Alternatively, it is preferable that the second insulating layer is substantially equal to the thickness of the first insulating layer.
According to such a configuration, since the internal stress of the first insulating layer and the second insulating layer are formed of the same kind of layers, the internal stress of both layers can be set to the internal stress in the same direction. . Further, since the first insulating layer and the second insulating layer have substantially the same thickness, as described above, the internal stress of both insulating layers is set in the same direction, and the magnitude of the internal stress of both insulating layers is substantially the same. It can be made equal. As a result, the internal stresses of the first insulating layer and the second insulating layer cancel each other, the internal stress does not act on the substrate, and the first insulation formed on the active surface of the substrate and the substrate. It is possible to suppress the occurrence of warping of the substrate caused by the difference between the layer and internal stress.

The present invention is also a method of manufacturing a semiconductor device having an electrode penetrating the substrate, the step of forming a recess in the active surface of the substrate, and a first insulation on the active surface of the substrate including the inside of the recess. A step of forming a layer, a step of laminating a second insulating layer whose direction of internal stress is different from that of the first insulating layer on the first insulating layer, and the step of forming the insulating layer. A step of filling the inside of the recess with a conductor to form the electrode; and removing the back surface side of the active surface, and forming the first electrode formed on the electrode and the outer peripheral portion of the electrode from the back surface of the active surface. A step of exposing the insulating layer and the second insulating layer, and a step of exposing the electrode from the back surface of the active surface.

  The internal stress differs between the substrate and the insulating layer formed on the active surface of the substrate. When a chip is formed, the difference in internal stress causes the substrate to bend and warp to the active surface side or back surface side of the first substrate. According to the present invention, since the second insulating layer having a different internal stress direction is laminated on the first insulating layer formed on the active surface side of the substrate, the internal stress of the second insulating layer causes the substrate and The difference in internal stress with the first insulating layer formed on the active surface of the substrate can be balanced or reduced. As a result, it is possible to remove or suppress the occurrence of warpage of the substrate caused by the difference between the internal stress and the first insulating layer formed on the substrate and the active surface of the substrate.

  In addition, the present invention is a circuit board including the above semiconductor device. Thereby, the circuit board with the said effect can be provided. Furthermore, the present invention is an electronic device including the circuit board. As a result, it is possible to provide an electronic device with the above effects.

  Embodiments of the present invention will be described below with reference to the drawings. In each drawing used in the following description, the scale of each layer and each member is appropriately changed so that each layer and each member have a recognizable size.

[First Embodiment]
First, a semiconductor chip which is a first embodiment of a semiconductor device according to the present invention will be described with reference to FIG. FIG. 1 is a side sectional view of an electrode portion of a semiconductor chip according to the present embodiment. In the semiconductor chip 2 according to the present embodiment, the first insulating layer 22 is formed inside the substrate 10 on which the integrated circuit is formed and the through hole H4 formed from the active surface 10a of the substrate 10 to the back surface 10b of the substrate 10. And the second insulating layer 26 formed on the back surface 10 b of the substrate 10.

(Semiconductor device)
In the semiconductor chip 2 shown in FIG. 1, an integrated circuit (not shown) made of transistors, memory elements, and other electronic elements is formed on a surface 10a of a substrate 10 made of Si (silicon) or the like. An insulating film 12 made of SiO ₂ (silicon oxide) or the like is formed on the active surface 10 a of the substrate 10. Further, an interlayer insulating film 14 made of borophosphosilicate glass (hereinafter referred to as BPSG) or the like is formed on the surface of the insulating film 12.

    An electrode pad 16 is formed on a predetermined portion of the surface of the interlayer insulating film 14. The electrode pad 16 includes a first layer 16a made of Ti (titanium) or the like, a second layer 16b made of TiN (titanium nitride) or the like, a third layer 16c made of AlCu (aluminum / copper) or the like, and TiN or the like. The fourth layer (cap layer) 16d is formed by sequentially stacking. Note that the constituent material of the electrode pad 16 may be appropriately changed according to the electrical characteristics, physical characteristics, and chemical characteristics required for the electrode pad 16. That is, the electrode pad 16 may be formed using only Al generally used as an electrode of the integrated circuit, or the electrode pad 16 may be formed using only Cu having a low electric resistance.

    The electrode pads 16 are formed side by side in the periphery of the semiconductor chip 2 in plan view. The electrode pad 16 may be formed side by side in the periphery of the semiconductor chip 2 or may be formed side by side in the center. When formed in the peripheral portion, the semiconductor chip 2 is formed side by side along at least one side (in many cases, two or four sides). Each electrode pad 16 is electrically connected to the integrated circuit described above at a location not shown. It should be noted that no integrated circuit is formed below the electrode pad 16.

A passivation film 18 is formed on the surface of the interlayer insulating film 14 so as to cover the electrode pad 16. The passivation film 18 is made of SiO ₂ (silicon oxide), SiN (silicon nitride), polyimide resin, or the like, and has a thickness of, for example, about 1 μm.

An opening H1 of the passivation film 18 and an opening H2 of the electrode pad 16 are formed at the center of the electrode pad 16. The diameter of the opening H2 is smaller than the diameter of the opening H1, and is set to about 60 μm, for example. The fourth layer 16d in the electrode pad 16 is opened with the same diameter as the opening H1. On the other hand, an insulating film 20 made of SiO ₂ (silicon oxide) or the like is formed on the surface of the passivation film 18 and the inner surfaces of the opening H1 and the opening H2.

    A hole H3 penetrating the insulating film 20, the interlayer insulating film 14, the insulating film 12, and the substrate 10 is formed at the center of the electrode pad 16. The diameter of the hole H3 is smaller than the diameter of the opening H2, for example, about 30 μm. The hole H3 is not limited to a circular shape in plan view, and may be formed in a rectangular shape in plan view. A through hole H4 penetrating from the active surface of the substrate to the back surface is formed by the opening H1, the opening H2, and the hole H3.

  The insulating layer 22 is formed along the inner wall surface of the through hole H4, and further extends from the inner wall surface of the through hole H4 onto the insulating film 20 formed on the substrate 10. An electrode 34 which will be described later is formed in the inside of the through hole H4 and a region slightly larger than the diameter of the opening H1 of the through hole H4. Therefore, the insulating layer 22 is exposed except in the region where the other electrodes 34 are formed. Further, the insulating film 20 and the insulating layer 22 formed on the surface of the third layer 16c of the electrode pad 16 are partially removed along the periphery of the opening H2, and the electrode pad 16 and the electrode 34 are electrically connected. It has come to be. This insulating layer 22 prevents the occurrence of current leakage, erosion due to oxygen, moisture, and the like. Furthermore, the insulating layer 22 is formed so as to protrude from the inner wall surface of the through hole H4 to the back surface 10b of the substrate 10 and functions as a protective film when an electrode terminal is formed on the back surface of the substrate 10. The insulating layer 22 has, for example, an internal stress in the extension side direction, and is formed to a thickness of about 3 μm.

      An insulating layer 22 as a first insulating layer is formed on the inner surface of the through hole H4 and the surface of the insulating film 20. The insulating layer 22 prevents current leakage, erosion due to oxygen, moisture, and the like, and is formed to a thickness of about 3 μm, for example. The insulating layer 22 has an internal stress on the stretch side. Further, the insulating layer 22 is formed so as to protrude from the back surface 10 b of the substrate 10. On the other hand, the insulating film 20 and the insulating layer 22 formed on the surface of the third layer 16c of the electrode pad 16 are partially removed along the periphery of the opening H2.

      A base film 24 is formed on the exposed surface of the third layer 16c of the electrode pad 16 and the remaining surface of the insulating layer 22. The base film 24 includes a barrier layer (barrier metal) formed on the surface of the insulating layer 22 and the like, and a seed layer (seed electrode) formed on the surface of the barrier layer. The barrier layer prevents the constituent material of the electrode 34 described later from diffusing into the substrate 10 and is made of TiW (titanium tungsten), TiN (titanium nitride), TaN (tantalum nitride), or the like. On the other hand, the seed layer serves as an electrode when an electrode 34 described later is formed by plating, and is made of Cu, Au, Ag, or the like.

      An electrode 34 is formed inside the base film 24. The electrode 34 is made of a conductive material having a low electrical resistance such as Cu or W. Note that if the electrode 34 is formed of a conductive material in which poly-Si (polysilicon) is doped with impurities such as B and P, it is not necessary to prevent diffusion to the substrate 10, so that the barrier layer described above becomes unnecessary. . And the plug part 36 of the electrode 34 is formed by forming the electrode 34 in the through-hole H4. The plug portion 36 and the electrode pad 16 are electrically connected via the base film 24 at the P portion in FIG. Further, the lower end surface of the plug portion 36 is exposed to the outside. On the other hand, the post part 35 of the electrode 34 is formed by extending the electrode 34 above the passivation film 18 and also at the peripheral part of the opening H1. The post portion 35 is not limited to a circular shape in plan view, and may be formed in a rectangular shape in plan view.

On the other hand, a second insulating layer 26 is formed on the back surface 10 b of the substrate 10. The insulating layer 26 is made of an inorganic material or an organic material such as SiO ₂ (silicon oxide) or SiN (silicon nitride). The layer thickness of the second insulating layer 26 is, for example, 3 μm, which is the same layer thickness as the first insulating layer 22. The insulating layer 26 has an internal stress on the stretch side, and has the internal stress in the same direction as the first insulating layer 22 described above. The insulating layer 26 is formed on the entire back surface 10 b of the substrate 10 except for the lower end surface of the plug portion 36 of the electrode 34.

  In the first embodiment, the tip end surface of the plug portion 36 of the electrode 34 on the back side of the substrate 10 is formed so as to protrude from the surface of the insulating layer 26. The protruding height of the plug part 36 is, for example, about 10 μm to 20 μm. Thereby, when laminating a plurality of semiconductor chips, a space between the semiconductor chips can be ensured, so that the gaps between the semiconductor chips can be easily filled with underfill or the like. Note that by adjusting the protruding height of the plug portion 36, the interval between the stacked semiconductor chips can be adjusted. Further, instead of filling underfill or the like after the lamination, even when a thermosetting resin or the like is applied to the back surface 10b of the semiconductor chip 2 before the lamination, the thermosetting resin or the like is applied while avoiding the protruding plug portion 36. Therefore, the semiconductor chip wiring connection can be reliably performed.

  On the other hand, a solder layer 40 is formed on the upper surface of the post portion 35 of the electrode 34. The solder layer 40 may be formed of a general PbSn alloy or the like, but is preferably formed of a lead-free solder material such as an AgSn alloy from the viewpoint of the environment. Instead of the solder layer 40 which is a soft wax material, a hard wax material (molten metal) layer made of SnAg alloy or the like, or a metal paste layer made of Ag paste or the like may be formed. It is preferable from the viewpoint of the environment and the like that the hard wax material layer and the metal paste layer are also formed of a lead-free material. The semiconductor chip 2 according to the present embodiment is configured as described above.

  According to the present embodiment, since the second insulating layer 26 whose internal stress is in the same direction as the first insulating layer 22 is formed on the back surface side of the substrate 10, the internal stress of the second insulating layer 26 The difference in internal stress between the substrate 10 and the first insulating layer 22 formed on the active surface of the substrate 10 can be balanced or reduced. As a result, it is possible to remove or suppress the occurrence of warpage of the substrate caused by the difference between the internal stress and the first insulating layer 22 formed on the active surface of the substrate 10 and the substrate 10.

  In the first embodiment, the thickness of the insulating layer 22 formed on the active surface of the substrate 10 and the thickness of the insulating layer 26 formed on the back surface of the substrate 10 or the material constituting each of these layers is appropriately changed. Is also preferable. Specifically, the first insulating layer 22 and the second insulating layer 26 are made of SiO 2 and have the same layer type, and the first insulating layer 22 and the second insulating layer 26 have different layer thicknesses. It is also preferable to make them different. The layer thickness at this time is, for example, 3 μm for the first insulating layer 22 and 2 μm for the second insulating layer 26. Thus, since the first insulating layer 22 and the second insulating layer 28 have different layer thicknesses, internal stress acting on the substrate 10 cannot be removed, but both insulating layers are of the same type. Therefore, the direction of the internal stress is the same, the difference in internal stress between the substrate 10 and the first insulating layer 22 can be reduced, and the occurrence of warpage of the substrate can be suppressed.

  Further, the first insulating layer 22 is made of SiO2, and the second insulating layer 26 is made of SiN having the same internal stress direction although the material of the second insulating layer 26 is different from that of the first insulating layer 22 and the layer type is different. It is also preferable that the first insulating layer 22 and the second insulating layer 26 have different layer thicknesses. As the layer thickness at this time, the layer thickness of the first insulating layer 22 is 3 μm, and the layer thickness of the second insulating layer 26 is 2 μm. Thereby, although the layer type and layer thickness of the first insulating layer 22 and the second insulating layer 28 are different, the direction of the internal stress of both the insulating layers is the same, so that the substrate 10 and the first insulating layer 22 are the same. The difference in internal stress with the substrate can be reduced, and the occurrence of warpage of the substrate can be suppressed.

  Further, the first insulating layer 22 is made of SiO2, and the second insulating layer 26 is made of SiN having the same internal stress direction although the material of the second insulating layer 26 is different from that of the first insulating layer 22 and the layer type is different. Further, the first insulating layer 22 and the second insulating layer 26 are made to have different thicknesses, and the second insulating layer 26 is removed by etching or the like to such an extent that a warp that causes no problem at the time of chip formation occurs. It is also preferable to make it thin. The layer thickness at this time is 3 μm for the first insulating layer 22 and 0.5 μm for the second insulating layer 26. Thereby, although the layer type and layer thickness of the first insulating layer 22 and the second insulating layer 28 are different, the direction of the internal stress of both the insulating layers is the same, so that the substrate 10 and the first insulating layer 22 are the same. The difference in internal stress with the substrate can be reduced, and the occurrence of warpage of the substrate can be suppressed.

(Production method)
Next, the semiconductor chip manufacturing method according to the present embodiment will be described with reference to FIGS. 2-6 is explanatory drawing of the manufacturing method of the semiconductor chip based on this embodiment. In the following, a case where a plurality of semiconductor chip formation regions on a substrate are simultaneously processed will be described as an example, but the following processing may be performed on each semiconductor chip.

      First, as shown in FIG. 2A, the insulating film 12 and the interlayer insulating film 14 are formed on the surface of the substrate 10. Then, an electrode pad 16 is formed on the surface of the interlayer insulating film 14. Specifically, first, the first to fourth layers of the electrode pad 16 are sequentially formed on the entire surface of the interlayer insulating film 14. Each film is formed by sputtering or the like. Next, a resist or the like is applied to the surface. Further, the final shape of the electrode pad 16 is patterned on the resist by photolithography. Then, etching is performed using the patterned resist as a mask to form electrode pads in a predetermined shape (for example, a rectangular shape). Thereafter, a passivation film 18 is formed on the surface of the electrode pad 16.

      Next, an opening H <b> 1 is formed in the passivation film 18. Specifically, a resist or the like is first applied to the entire surface of the passivation film. The resist may be a photoresist, an electron beam resist, an X-ray resist, or the like, and may be either a positive type or a negative type. The resist is applied by spin coating, dipping, spray coating, or the like. Note that pre-baking is performed after the resist is applied. Then, the resist is exposed using a mask in which the pattern of the opening H1 is formed, and further developed to pattern the shape of the opening H1 in the resist. Note that post-baking is performed after resist patterning.

      Then, the passivation film 18 is etched using the patterned resist as a mask. In the present embodiment, the fourth layer of the electrode pad 16 is also etched together with the passivation film 18. As the etching, wet etching can be employed, but dry etching is preferably employed. The dry etching may be reactive ion etching (RIE). Note that after the opening H1 is formed in the passivation film 18, the resist on the passivation film 18 is stripped with a stripping solution. As a result, as shown in FIG. 2A, the opening H1 is formed in the passivation film 18, and the electrode pad 16 is exposed.

Next, as illustrated in FIG. 2B, an opening H <b> 2 is formed in the electrode pad 16. Specifically, a resist or the like is applied to the entire exposed electrode pad 16 and passivation film 18 to pattern the shape of the opening H2.
Next, the electrode pad 16 is dry-etched using the patterned resist as a mask. Note that RIE can be used for dry etching. Thereafter, when the resist is peeled off, an opening H2 is formed in the electrode pad 16 as shown in FIG.

Next, as shown in FIG. 2C, an insulating film 20 is formed on the entire upper surface of the substrate 10. The insulating film 20 functions as a mask when the hole H3 is drilled in the substrate 10 by dry etching. The film thickness of the insulating film 20 is set to about 2 μm, for example, depending on the depth of the hole H3 drilled in the substrate 10. In the present embodiment, SiO ₂ is used as the insulating film 20, but a photoresist may be used as long as the selection ratio with Si can be obtained. Further, the insulating film 20 is formed by using tetraethyl silicate (Si (OC ₂ H ₅ ) ₄ : hereinafter referred to as TEOS), that is, PE-TEOS, which is formed by using PECVD (Plasma Enhanced Chemical Vapor Deposition). O ₃ -TEOS which is thermal CVD using ozone, silicon oxide formed using CVD, or the like can be used.

      Next, the shape of the hole H3 is patterned in the insulating film 20. Specifically, a resist or the like is first applied to the entire surface of the insulating film 20, and the shape of the hole H3 is patterned. Next, the insulating film 20, the interlayer insulating film 14, and the insulating film 12 are dry-etched using the patterned resist as a mask. Thereafter, if the resist is peeled off, the shape of the hole H3 is patterned in the insulating film 20 and the like, and the substrate 10 is exposed.

Next, the hole H3 is drilled in the substrate 10 by high-speed dry etching. Note that RIE or ICP (Inductively Coupled Plasma) can be used as dry etching. At this time, as described above, the insulating film 20 (SiO ₂ ) is used as a mask, but a resist may be used as a mask instead of the insulating film 20. The depth of the hole H3 is appropriately set according to the thickness of the semiconductor chip to be finally formed. That is, the depth of the hole H3 is set so that the tip of the electrode formed inside the hole H3 can be exposed on the back surface of the substrate 10 after the semiconductor chip is etched to the final thickness. Thus, the hole H3 is formed in the substrate 10 as shown in FIG. A recess H0 is formed from the active surface of the substrate 10 to the inside by the opening H1, the opening H2, and the hole H3.

Next, as illustrated in FIG. 3A, an insulating layer 22 that is a first insulating layer is formed on the inner surface of the recess H <b> 0 and the surface of the insulating film 20. The insulating layer 22 is made of, for example, PE-TEOS or O ₃ -TEOS, and is formed to have a surface layer thickness of about 3 μm by, for example, plasma TEOS.

      Next, anisotropic etching is performed on the insulating layer 22 and the insulating film 20 to expose a part of the electrode pad 16. In the present embodiment, a part of the surface of the electrode pad 16 is exposed along the periphery of the opening H2. Specifically, a resist or the like is first applied to the entire surface of the insulating layer 22, and the exposed portion is patterned. Next, the insulating layer 22 and the insulating film 20 are anisotropically etched using the patterned resist as a mask. For this anisotropic etching, it is preferable to use dry etching such as RIE. As a result, the state shown in FIG.

      Next, as shown in FIG. 3B, a base film 24 is formed on the exposed surface of the electrode pad 16 and the remaining surface of the insulating layer 22. As the base film 24, a barrier layer is first formed, and a seed layer is formed thereon. The barrier layer and the seed layer are formed using, for example, a PVD (Phisical Vapor Deposition) method such as vacuum deposition, sputtering, or ion plating, a CVD method, an IMP (ion metal plasma) method, an electroless plating method, or the like.

      Next, as shown in FIG. 4A, an electrode 34 is formed. Specifically, a resist 32 is first applied on the entire upper surface of the substrate 10. As the resist 32, a liquid resist for plating or a dry film can be employed. In addition, although it is possible to use a resist used when etching an Al electrode generally provided in a semiconductor device or an insulating resin resist, it has resistance to a plating solution and an etching solution used in a process described later. That is the premise.

      The resist 32 is applied by a spin coating method, a dipping method, a spray coating method, or the like. Here, the thickness of the resist 32 is set to be approximately the same as the height of the post portion 35 of the electrode 34 to be formed plus the thickness of the solder layer 40. Note that pre-baking is performed after the resist 32 is applied.

      Next, the planar shape of the post portion 35 of the electrode 34 to be formed is patterned into a resist. Specifically, the resist 32 is patterned by performing exposure processing and development processing using a mask on which a predetermined pattern is formed. Here, if the post portion 35 has a rectangular planar shape, a rectangular opening is patterned in the resist 32. The size of the opening is set according to the pitch of the electrodes 34 in the semiconductor chip, and is formed to have a size of 120 μm square or 80 μm square, for example. Note that the size of the opening is set so that the resist 32 does not fall after patterning.

      The method for forming the resist 32 so as to surround the post portion 35 of the electrode 34 has been described above. However, the resist 32 is not necessarily formed so as to surround the entire circumference of the post portion 35. For example, when the electrodes 34 are formed adjacent to each other only in the left-right direction of the paper surface of FIG. 4A, the resist 32 need not be formed in the depth direction of the paper surface. As described above, the resist 32 is formed along at least a part of the outer shape of the post portion 35.

      The method for forming the resist 32 using the photolithography technique has been described above. However, when the resist 32 is formed by this method, when the resist is applied to the entire surface, a part of the resist may enter the hole H3 and remain as a residue in the hole H3 even if development processing is performed. Therefore, it is preferable to form the resist 32 in a patterned state by using, for example, a dry film or a printing method such as screen printing. Alternatively, the resist 32 may be formed in a patterned state by discharging a droplet of a resist only to a position where the resist 32 is formed using a droplet discharge device such as an inkjet device. Thereby, the resist 32 can be formed without entering the hole H3.

      Next, using this resist 32 as a mask, the electrode material is filled into the recess H0 to form the electrode. The electrode material is filled by a plating process, a CVD method, or the like. For the plating process, for example, an electrochemical plating (ECP) method is used. Note that a seed layer constituting the base film 24 is used as an electrode in the plating process. Moreover, a cup type plating apparatus is used as the plating apparatus. The cup-type plating apparatus is an apparatus that performs plating by ejecting a plating solution from a cup-shaped container. Thereby, the electrode material is filled in the recess H0, and the plug portion 36 is formed. Further, the opening formed in the resist 32 is also filled with the electrode material, and the post portion 35 is formed.

      Next, a solder layer 40 is formed on the upper surface of the electrode 34. The solder layer 40 is formed by a solder plating method or a printing method such as screen printing. A seed layer constituting the base film 24 can be used as an electrode for solder plating. Moreover, a cup type plating apparatus can be used as the plating apparatus. On the other hand, a hard wax material layer made of SnAg or the like may be formed instead of the solder layer 40. The hard wax material layer can also be formed by a plating method or a printing method. As a result, the state shown in FIG.

      Next, as shown in FIG. 4B, the resist 32 is stripped (removed) using a stripping solution or the like. Note that ozone water or the like can be used as the stripping solution. Subsequently, the base film 24 exposed above the substrate 10 is removed. Specifically, a resist or the like is first applied to the entire upper surface of the substrate 10 and the shape of the post portion 35 of the electrode 34 is patterned. Next, the base film 24 is dry-etched using the patterned resist as a mask. When a hard wax material layer is formed instead of the solder layer 40, the base film 24 can be etched using the hard wax material layer as a mask. In this case, since a photolithography process is not required, the manufacturing process can be simplified.

      Next, as illustrated in FIG. 5A, the reinforcing member 50 is mounted below the substrate 10 after the substrate 10 is turned upside down. Although a protective film or the like may be employed as the reinforcing member 50, it is preferable to employ a hard material such as glass. Thereby, when processing the back surface 10b of the board | substrate 10, it can prevent that a crack etc. generate | occur | produce in the board | substrate 10. FIG. The reinforcing member 50 is attached to the substrate 10 via an adhesive 52 or the like. As the adhesive 52, it is desirable to use a curable adhesive such as a thermosetting adhesive or a photocurable adhesive. Thereby, the reinforcing member 50 can be firmly attached while absorbing the irregularities on the active surface 10a of the substrate 10. Further, when a photocurable adhesive such as an ultraviolet curable adhesive is used as the adhesive 52, it is preferable to employ a light transmissive material such as glass as the reinforcing member 50. In this case, the adhesive 52 can be easily cured by irradiating light from the outside of the reinforcing member 50.

      Next, as shown in FIG. 5B, the entire back surface 10b of the substrate 10 is etched to expose the tip of the insulating layer 22, and the tip of the electrode 34 is disposed outside the back 10b of the substrate 10. To do. For this etching, either wet etching or dry etching may be used. Note that if the back surface 10b of the substrate 10 is roughly polished and then etched to expose the tip of the insulating layer 22, the manufacturing time can be shortened. Further, the insulating layer 22 and the base film 24 may be etched and removed simultaneously with the etching of the substrate 10.

Next, as shown in FIG. 6A, the second insulating layer 26 is formed on the entire back surface 10 b of the substrate 10. The layer thickness of the second insulating layer 26 is, for example, about 3 μm. Further, when a film such as SiO ₂ or SiN is formed as the insulating layer 26, it is preferably formed by a CVD method. Further, the insulating layer 26 may be formed using SOG. SOG (Spin On Glass) is a liquid that becomes SiO ₂ by baking at a temperature of about 400 ° C. after being applied, and is used for an interlayer insulating film of an LSI for the purpose of planarization. Specifically, it is a polymer having a siloxane bond as a basic structure, and alcohol or the like is used as a solvent. Also when applying this SOG, a spin coat method is used.

      Instead of forming the insulating layer 26 on the entire back surface 10b of the substrate 10, the insulating layer 26 may be selectively formed only around the electrodes 34 on the back surface 10b of the substrate 10. In this case, the insulating layer 26 may be formed by discharging the insulating film material liquid only to the periphery of the electrode 34 using a droplet discharge device such as an ink jet device, and drying and baking.

      Next, as shown in FIG. 6B, the tip of the electrode 34 is exposed. Specifically, the insulating layer 26, the insulating layer 22, and the base film 24 covering the tip of the electrode 34 are removed, and the tip of the electrode 34 is exposed. The insulating layer 26, the insulating layer 22, and the base film 24 are removed by CMP (Chemical and Mechanical Polishing) polishing or the like. In CMP, the substrate is polished by a balance between mechanical polishing of the substrate by a polishing cloth and chemical action by a polishing liquid supplied thereto. Note that the tip of the electrode 34 may be polished when the insulating layer 26, the insulating layer 22, and the base film 24 are removed by polishing. In this case, since the base film 24 is completely removed, it is possible to prevent poor conduction between the electrodes when the semiconductor chips are stacked.

Thereafter, the adhesive 52 is dissolved with a solvent or the like, and the reinforcing member 50 is removed from the substrate 10. Next, a dicing tape (not shown) is attached to the back surface 10b of the substrate 10, and then the substrate 10 is diced to be separated into individual semiconductor chips. Note that the substrate 10 may be cut by irradiation with CO ₂ laser or YAG laser.
Thus, the state shown in FIG. 1 is obtained, and the semiconductor chip 2 according to the present embodiment is completed.

(Laminated structure)
The semiconductor chips 2 formed as described above are stacked to form a three-dimensionally mounted semiconductor device. FIG. 7 is a side cross-sectional view showing a state in which the semiconductor chips according to the present embodiment are stacked, and is an enlarged view of a portion corresponding to part A in FIG. Each of the semiconductor chips 2a and 2b is arranged so that the lower end surface of the plug portion of the electrode 34 in the upper semiconductor chip 2a is positioned on the upper surface of the post portion of the electrode 34 in the lower semiconductor chip 2b. Then, the electrodes 34 in the respective semiconductor chips 2a and 2b are joined to each other through the solder layer 40. Specifically, the semiconductor chips 2a and 2b are pressed against each other while the solder layer 40 is dissolved by reflow. As a result, a solder alloy is formed at the joint between the solder layer 40 and the electrode 34, and both are mechanically and electrically joined. Thus, the semiconductor chips 2a and 2b are connected by wiring. If necessary, an underfill is filled in the gaps between the stacked semiconductor chips.

      By the way, the melted solder layer 40 is deformed upward along the outer periphery of the plug portion 36 of the electrode in the upper semiconductor chip 2a, and thus may be in contact with the back surface 10b of the upper semiconductor chip 2a. In addition, since a signal line is connected to the solder layer 40 and a ground is connected to the back surface 10b of the semiconductor chip 2a, it is necessary to prevent a short circuit between them. In this respect, in the present embodiment, since the insulating layer 26 is formed on the back surface 10b of the semiconductor chip 2a, a short circuit between the solder layer 40 and the back surface 10b of the semiconductor chip 2a is prevented when the semiconductor chips are stacked. Is possible. Therefore, three-dimensional mounting can be performed while preventing a short circuit between the signal line and the ground.

      In recent years, due to demands for miniaturization and weight reduction of semiconductor devices, the back surface of the substrate is greatly etched to form a semiconductor chip very thin. Therefore, if the substrate after the back surface etching is processed, the substrate may be broken or broken. Therefore, the substrate after the back surface etching can only be subjected to the minimum necessary processing. Therefore, the idea of forming an insulating film on the back surface of the substrate has not been reached. Recently, however, a technique has been developed for freely processing a substrate after etching the back surface by attaching a reinforcing member to the active surface of the substrate before etching the back surface of the substrate. This technique for mounting a reinforcing member is to mount the reinforcing member while absorbing irregularities on the active surface of the substrate, and to freely remove the reinforcing member after processing the substrate. As a result, the inventors have conceived the present invention of forming an insulating film on the back surface of a substrate for the first time.

(Relocation wiring)
In order to mount the semiconductor device stacked as described above on the circuit board, it is desirable to perform rewiring. First, rewiring will be briefly described. FIG. 8 is an explanatory diagram of the rewiring of the semiconductor chip. Since a plurality of electrodes 62 are formed along the opposite side of the surface of the semiconductor chip 61 shown in FIG. 8A, the pitch between adjacent electrodes is narrowed. When such a semiconductor chip 61 is mounted on a circuit board, adjacent electrodes may be short-circuited. Therefore, in order to widen the pitch between the electrodes, rewiring is performed to draw out the plurality of electrodes 62 formed along the opposite sides of the semiconductor chip 61 to the center.

      FIG. 8B is a plan view of the semiconductor chip after rewiring. A plurality of circular electrode pads 63 are arranged on the matrix at the center of the surface of the semiconductor chip 61. Each electrode pad 63 is connected to one or a plurality of electrodes 62 by rewiring 64. As a result, the narrow-pitch electrodes 62 are drawn out to the central portion, and the pitch is increased.

      FIG. 9 is a side cross-sectional view taken along line AA in FIG. A solder resist 65 is formed at the center of the bottom surface of the semiconductor chip 61 that is the lowermost layer by inverting the stacked semiconductor device as described above. A rewiring 64 is formed from the post portion of the electrode 62 to the surface of the solder resist 65. An electrode pad 63 is formed at the end of the rewiring 64 on the solder resist 65 side, and a bump 78 is formed on the surface of the electrode pad. The bump 78 is, for example, a solder bump, and is formed by a printing method or the like. A reinforcing resin 66 and the like are molded on the entire bottom surface of the semiconductor chip 61.

(Circuit board)
FIG. 10 is a perspective view of the circuit board. In FIG. 10, the semiconductor device 1 formed by stacking semiconductor chips is mounted on a circuit board 1000. Specifically, bumps formed on the lowermost semiconductor chip in the semiconductor device 1 are mounted by performing reflow, FCB (Flip Chip Bonding), or the like on the electrode pads formed on the surface of the circuit board 1000. Has been. The semiconductor device 1 may be mounted with an anisotropic conductive film or the like sandwiched between the circuit board.

[Second Embodiment]
FIG. 11 is a cross-sectional view of the semiconductor chip 2 in the present embodiment. In the first embodiment described above, the second insulating layer 28 is formed on the back surface of the substrate 10, whereas in the present embodiment, the second insulating layer 28 is formed on the first insulating layer 22. It is different in that the layer 28 is formed by stacking. Hereinafter, a configuration different from that of the first embodiment will be described with reference to FIG. Note that the description of the same configuration as that of the first embodiment is omitted.
As described above, the first insulating layer 22 is made of SiO 2 or the like, and is formed on the insulating film 20. The second insulating layer 28 is laminated on the first insulating layer 22 as shown in FIG. The second insulating layer 22 is formed of PI (polyimide) or the like having a different internal stress direction from the first insulating layer 22. That is, the first insulating layer 22 has an internal stress in the extension side direction, and the second insulating layer 28 has an internal stress in the compression side direction opposite to the internal stress of the first insulating layer 22. . The layer thickness of the first insulating layer 22 is, for example, about 3 μm, and the layer thickness of the second insulating layer 28 is, for example, about 10 μm. The configuration of the semiconductor chip 2 described in FIG. 1 of the first embodiment is the same as that of the first embodiment except that the second insulating layer 28 is stacked on the first insulating layer 22 described above.

A method for manufacturing a semiconductor chip according to the present embodiment will be described below with reference to FIG. In addition, description is abbreviate | omitted when using the process similar to 1st Embodiment mentioned above.
First, as shown in FIGS. 2A to 2C and FIG. 3A in the first embodiment, the recess H0 is formed in the substrate 10, and the first insulating layer 22 is formed. Next, the second insulating layer 28 is prepared by dissolving polyimide resin or the like in a solvent and applying polyimide resin or the like dissolved by various coating methods such as spin coating or dip coating on the first insulating layer 22. Form. Thereafter, the applied second insulating layer 28 is also preferably dried and fired. Then, as shown in FIG. 12, anisotropic etching is performed on the insulating film 20, the first insulating layer 22, and the second insulating layer 28 to expose a part of the electrode pad 16. In the present embodiment, a part of the surface of the electrode pad 16 is exposed along the periphery of the opening H2. In this way, the exposed electrode pad 16 and the electrode 34 are electrically connected.
Subsequently, as shown in FIGS. 3B to 6A and 6B, the same steps as those in the first embodiment are performed. The semiconductor chip 2 is formed through such steps.

  The substrate 10 and the first insulating layer 22 formed on the active surface of the substrate 10 have different internal stresses. When the chip is formed, the difference in internal stress causes the substrate 10 to bend and warp to the active surface side or the back surface side of the first substrate. According to the present embodiment, the second insulating layer 28 whose internal stress with respect to the substrate 10 is opposite to the first insulating layer is formed on the first insulating layer 22 on the back side of the substrate 10. Therefore, due to the internal stress of the second insulating layer 28, the internal stress difference between the substrate 10 and the first insulating layer 22 formed on the active surface of the substrate 10 is balanced by the internal stress of the second insulating layer 28. Or it becomes possible to reduce. As a result, it is possible to remove or suppress the occurrence of warpage of the substrate caused by the difference between the internal stress and the first insulating layer 22 formed on the active surface of the substrate 10 and the substrate 10.

In the second embodiment, the second insulating layer 28 is formed on the first insulating layer 22. However, the electrode 34 is formed in the concave portion H 0 of the substrate, and the solder layer is formed on the upper surface of the electrode 34. After forming 40, it is also preferable to form the second insulating layer 28 on the substrate 10 including the solder layer 40. In this case, a resist is applied to the entire surface of the first insulating layer including the solder layer 40, and the resist is patterned into a predetermined shape by exposure processing and development processing. Thereafter, etching is performed using the patterned resist as a mask, the second insulating layer 28 formed on the upper surface of the solder layer 40 is removed, and the second insulating layer 28 formed on the outer periphery of the electrode 34 is left. . It is also preferable to stack the second insulating layer 28 after forming the insulating film 12 on the substrate 10.
(Electronics)
Next, an example of an electronic device including the above-described semiconductor device is described with reference to FIGS. FIG. 12 is a perspective view of a mobile phone. The semiconductor device described above is arranged inside the housing of the mobile phone 300.

  Note that the semiconductor device described above can be applied to various electronic devices other than mobile phones. For example, LCD projectors, multimedia-compatible personal computers (PCs) and engineering workstations (EWS), pagers, word processors, TVs, viewfinder type or monitor direct view type video tape recorders, electronic notebooks, electronic desk calculators, car navigation systems The present invention can be applied to electronic devices such as a device, a POS terminal, and a device provided with a touch panel.

  It should be noted that an electronic component can be manufactured by replacing the “semiconductor chip” in the above-described embodiment with an “electronic element”. Examples of electronic components manufactured using such electronic elements include optical elements, resistors, capacitors, coils, oscillators, filters, temperature sensors, thermistors, varistors, volumes, and fuses.

  It should be noted that the technical scope of the present invention is not limited to the above-described embodiments, and includes those in which various modifications are made to the above-described embodiments without departing from the spirit of the present invention. In other words, the specific materials and layer configurations described in the embodiments are merely examples, and can be changed as appropriate.

It is side surface sectional drawing of the electrode part of the semiconductor chip which concerns on 1st Embodiment. It is explanatory drawing of the manufacturing method of the semiconductor chip which concerns on 1st Embodiment. It is explanatory drawing of the manufacturing method of the semiconductor chip which concerns on 1st Embodiment. It is explanatory drawing of the manufacturing method of the semiconductor chip which concerns on 1st Embodiment. It is explanatory drawing of the manufacturing method of the semiconductor chip which concerns on 1st Embodiment. It is explanatory drawing of the manufacturing method of the semiconductor chip which concerns on 1st Embodiment. It is explanatory drawing of the lamination | stacking state of the semiconductor device which concerns on 1st Embodiment. It is explanatory drawing of rewiring. It is the schematic diagram which demonstrated rewiring. It is explanatory drawing of a circuit board. It is side surface sectional drawing of the electrode part of the semiconductor chip which concerns on 2nd Embodiment. It is explanatory drawing of the manufacturing method of the semiconductor chip which concerns on 2nd Embodiment. It is a perspective view of the mobile phone which is an example of an electronic device.

Explanation of symbols

2 ... Semiconductor chip, 10 ... Substrate, 22 ... First insulating layer, 24 ... Underlayer,
26, 28 ... second insulating layer, 34 ... electrode

Claims (6)

A method of manufacturing a semiconductor device having an electrode penetrating a substrate,
Forming a recess in the active surface of the substrate;
Forming a first insulating layer on an active surface of the substrate including the interior of the recess;
Filling the inside of the recess with the first insulating layer formed thereon to form the electrode; and
Removing the back side of the active surface and exposing the electrode and the first insulating layer formed on the outer periphery of the electrode from the back surface of the active surface;
Forming a second insulating layer on the back surface of the active surface, the direction of internal stress being the same direction as the first insulating layer;
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating layer is made of the same material as the first insulating layer.   The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating layer is substantially equal to a thickness of the first insulating layer. A method of manufacturing a semiconductor device having an electrode penetrating a substrate,
Forming a recess in the active surface of the substrate;
Forming a first insulating layer on an active surface of the substrate including the interior of the recess;
Laminating a second insulating layer on the first insulating layer, the direction of internal stress being different from that of the first insulating layer;
Filling the inside of the recess with the insulating layer formed therein to form the electrode; and
Removing the back side of the active surface to expose the electrode, the first insulating layer and the second insulating layer formed on the outer periphery of the electrode from the back surface of the active surface, and the active surface And a step of exposing the electrode from the back surface of the semiconductor device.   A circuit board comprising the semiconductor device according to claim 4.   An electronic apparatus comprising the electro-optical device according to claim 5.

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