JP2005354558A - Differential amplification circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a variable gain differential amplification circuit exhibiting good linearity to a differential input voltage. <P>SOLUTION: The differential amplification circuit comprises a first differential MOS transistor M1 and a second differential MOS transistor M2, a first constant current source 11 connected with the source of the first differential MOS transistor M1 and a second constant current source 12 connected with the source of the second differential MOS transistor M2, and a variable resistor element 20 connected between the sources of the first differential MOS transistor M1 and the second differential MOS transistor M2. The variable resistor element 20 comprises twelve P channel type MOS transistors M3-M14 connected in series and having gates being applied with a DC control voltage VCNT commonly through an operational amplifier 16. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a differential amplifier circuit, and more particularly to a differential amplifier circuit configured using MOS transistors.

  Conventionally, a differential input type operational transconductance amplifier circuit (hereinafter referred to as an OTA circuit) is known as a type of differential amplifier circuit. FIG. 3 is a circuit diagram of a basic OTA circuit.

  The OTA circuit includes a first differential MOS transistor M1, a second differential MOS transistor M2, and a first constant current source 1 (constant current value I0) connected to the source of the first differential MOS transistor M1. The second constant current source 2 (constant current value I0) connected to the source of the second differential MOS transistor M2, and between the sources of the first differential MOS transistor M1 and the second differential MOS transistor M2 And a resistance element 3 having a resistance value Rs (also called a floating resistance).

  The first differential input voltage VINP is applied to the gate of the first differential MOS transistor M1, and the second differential input voltage VINN is applied to the gate of the second differential MOS transistor M2. The first differential input signal VINP and the second differential input voltage VINN are voltages having opposite phases with respect to the common potential VCM.

  Now, assuming that the first differential MOS transistor M1 and the second differential MOS transistor M2 operate in the saturation region, and the differential input voltage changes by ΔV, VINP = VCM + ΔV and VINN = VCM−ΔV. expressed.

  When the source potential of the first differential MOS transistor M1 is V1, and the source potential of the second differential MOS transistor M2 is V2, V1 = V0 + ΔV and V2 = V0−ΔV. The current IR flows through the resistance element 3 due to the potential difference 2ΔV between V1 and V2. Here, the current IR is represented by IR = 2ΔV / Rs. Accordingly, the first output current I0-IR is obtained from the first output terminal 4 which is the drain of the first differential MOS transistor M1, and the second output terminal which is the drain of the second differential MOS transistor M2. 5 gives a second output current I0 + IR.

  The resistance element 3 of the OTA circuit includes two MOS transistors M3 and M4 connected in parallel between the first differential MOS transistor M1 and the second differential MOS transistor M2, as shown in the OTA circuit of FIG. Can be configured. In the OTA circuit of FIG. 4, in order to maintain the linearity of the resistive element 3 with respect to the differential input voltage, the second differential input voltage VINN is applied to the gate of the MOS transistor M3, and the first differential voltage is applied to the gate of the MOS transistor M4. A differential input voltage VINP is applied.

The OTA circuit is described in Patent Documents 1 and 2, for example.
JP-A-5-259761 JP-A-11-214935

  Incidentally, in order to apply the OTA circuit of FIG. 4 to a variable gain amplifier circuit, it is necessary to configure the resistance element 3 with a variable resistance element. Therefore, as shown in the circuit of FIG. 5, the DC control voltage VCNT is applied to the gates of the MOS transistors M3 and M4 through the operational amplifier 6, and the AC of the first differential input signal VINP and the second differential input voltage VINN is applied. It is necessary to transfer the component to a certain DC component through high-pass filter circuits 7 and 8 composed of capacitors and resistors. This DC component is an element for maintaining the linearity of the MOS transistors M3 and M4.

  However, in such a circuit configuration, the high-pass filter circuits 7 and 8 are required, so that the circuit scale becomes large, and the first differential input signal VINP and the second differential input voltage VINN are low frequency signals. In this case, it is necessary to increase the constants (resistance value, capacitor value) of the high-pass filter circuits 7 and 8, and when this OTA circuit is incorporated in an LSI, the number of pins of the LSI may increase.

  On the other hand, as shown in FIG. 6, the variable resistance element may be composed of one MOS transistor M5 controlled by the DC control voltage VCNT. However, as shown in FIG. 7, the first differential input signal VINP is used. When V1 and V2 change according to the amplitude change of the second differential input voltage VINN, the source potential of the MOS transistor M5 changes accordingly, so that Vsg (gate-drain voltage) changes greatly. There is a problem that the linearity as the resistance element is deteriorated and the linear amplification characteristic of the differential amplification is deteriorated.

  Therefore, a differential amplifier circuit according to the present invention includes first and second differential transistors, a first constant current source connected to a current path of the first differential transistor, and the second differential transistor. A second constant current source connected to the current path of the transistor; and a variable resistance element connected between the first differential transistor and the second differential transistor, the variable resistance element comprising: A DC control voltage is commonly applied to the respective gates, and is composed of a plurality of MOS transistors connected in series.

  According to the differential amplifier circuit of the present invention, since the variable resistance element is configured by a plurality of MOS transistors connected in series with a DC control voltage commonly applied to each gate, the resistance value of the variable resistance element is different. It becomes less dependent on the amplitude of the dynamic input voltage, the linearity of the variable resistance element is maintained, and a differential amplification characteristic having good linearity is obtained. Further, since the resistance value of the variable resistance element is controlled only by the DC control voltage, there is an advantage that a high-pass filter circuit is unnecessary and the circuit scale can be reduced.

  Next, a differential amplifier circuit according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of the differential amplifier circuit (OTA circuit). The differential amplifier circuit is a variable gain amplifier circuit, and includes a first differential MOS transistor M1, a second differential MOS transistor M2, and a first differential MOS transistor M1 connected to a source of the first differential MOS transistor M1. Constant current source 11 (constant current value I0), a second constant current source 12 (constant current value I0) connected to the source of the second differential MOS transistor M2, and a first differential MOS transistor M1 And a variable resistance element 20 connected between the sources of the second differential MOS transistor M2. Both the first differential MOS transistor M1 and the second differential MOS transistor M2 are P-channel type.

  The variable resistance element 20 includes 12 P-channel MOS transistors M3 to M14 connected in series, with a DC control voltage VCNT applied in common to each gate through an operational amplifier 16.

  The first differential input voltage VINP is applied to the gate of the first differential MOS transistor M1, and the second differential input voltage VINN is applied to the gate of the second differential MOS transistor M2. The first differential input signal VINP and the second differential input voltage VINN are voltages having opposite phases with respect to the common potential VCM.

  Now, assuming that the first differential MOS transistor M1 and the second differential MOS transistor M2 operate in the saturation region, and the differential input voltage changes by ΔV, VINP = VCM + ΔV and VINN = VCM−ΔV. expressed.

  When the source potential of the first differential MOS transistor M1 is V1, and the source potential of the second differential MOS transistor M2 is V2, V1 = V0 + ΔV and V2 = V0−ΔV. A current IR flows through the variable resistance element 20 due to the potential difference 2ΔV between V1 and V2. Here, the current IR is represented by IR = 2ΔV / RX. RX is a resistance value of a series resistor composed of 12 MOS transistors M3 to M14.

  A first output current I0-IR is obtained from the first output terminal 14 which is the drain of the first differential MOS transistor M1, and from the second output terminal 15 which is the drain of the second differential MOS transistor M2. A second output current I0 + IR is obtained.

  Here, the source-drain voltage Vds of the twelve MOS transistors M3 to M14 becomes close to 0V by dividing the potential difference (V1-V2) by these MOS transistors M3 to M14, and these MOS transistors M3 -M14 will all operate in the linear region. If the resistance value of the MOS transistor in this linear region is RMOS, this is expressed by the following equation (1).

ここで、Ｗはチャネル幅、Ｌはチャネル長、μはキャリア移動度、Ｃｏｘはゲート酸化膜容量、Ｖｓｇはゲートソース間電圧、Ｖｔｐはしきい値電圧である。

Here, W is the channel width, L is the channel length, μ is the carrier mobility, Cox is the gate oxide film capacitance, Vsg is the gate-source voltage, and Vtp is the threshold voltage.

  Assuming that the potentials (source potentials) at the connection points of the 12 MOS transistors M3 to M14 are V3, V4, V5,... V13 as shown in FIG. As shown in FIG. That is, the source potentials of these MOS transistors M3 to M14 are different, and Vsg is also different for each transistor. That is, the resistance value of each MOS transistor is different from Equation 1.

  However, since the average of the source potentials of these MOS transistors M3 to M14 is kept substantially constant, the total resistance value of the series resistors formed by these MOS transistors M3 to M14 is the differential input voltage (first differential). The input voltage VINP and the second differential input voltage VINN) are substantially independent of changes in amplitude. That is, the linearity of the variable resistance element 20 with respect to the differential input voltage becomes good, and a differential amplification characteristic having good linearity can be obtained.

1 is a circuit diagram of a differential amplifier circuit (OTA circuit) according to an embodiment of the present invention. It is a figure explaining operation | movement of the differential amplifier circuit (OTA circuit) which concerns on embodiment of this invention. It is a circuit diagram of the OTA circuit which concerns on a prior art example. It is a circuit diagram of the OTA circuit which concerns on a prior art example. It is a circuit diagram of the OTA circuit which concerns on a prior art example. It is a circuit diagram of the OTA circuit which concerns on a prior art example. FIG. 7 is a diagram for explaining the operation of the OTA circuit of FIG. 6.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 1st constant current source 12 2nd constant current source 14 1st output terminal 15 2nd output terminal 16 Operational amplifier 20 Variable resistance element

Claims (2)

A first constant current source connected to the current path of the first differential transistor; a second constant current source connected to the current path of the second differential transistor; A constant current source; and a variable resistance element connected between the first differential transistor and the second differential transistor, wherein the variable resistance element has a DC control voltage common to each gate. A differential amplifier circuit comprising a plurality of MOS transistors applied and connected in series. 2. The differential amplifier circuit according to claim 1, wherein the first and second differential transistors are composed of MOS transistors.

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