JP2005353817A - Field effect transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve device characteristics of a field effect transistor by improving the mobility of the carrier (two-dimensional electronic gas) of a channel. <P>SOLUTION: By the below-mentioned condition setting, interface roughness is prevented and the mobility of the carrier is improved. (1) A semiconductor layer A is constituted of a non-doped GaN crystal having a thickness of about 2 μm, and (2) another semiconductor layer B is constituted of a non-doped Al<SB>0.25</SB>Ga<SB>0.75</SB>N crystal having a thickness of about 35 nm. (3) The crystal growing temperature T<SB>A</SB>of the semiconductor layer A is 1,100 [°C] and (4) the crystal growing air pressure P<SB>A</SB>of the layer A is 1,013 [hPa]. In addition, (5) the crystal growing temperature T<SB>B</SB>of the semiconductor layer B is 1,000 [°C] (T<SB>B</SB>≤T<SB>A</SB>), and (6) the crystal growing air pressure P<SB>B</SB>of the layer B is 1,013 [hPa] (P<SB>B</SB>≈P<SB>A</SB>). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a structure of a field effect transistor (various FETs, HEMTs, etc.) that can be manufactured by crystal growth of a group III nitride compound semiconductor and a manufacturing method thereof.

FIG. 3 illustrates a cross-sectional view of a conventional field effect transistor 10. This field effect transistor 10 is a semiconductor element formed by sequentially stacking group III nitride compound semiconductors by crystal growth, and is formed on a crystal growth substrate 1 made of silicon carbide (SiC) having a thickness of about 500 μm. A buffer layer 2 made of AlN having a thickness of about 0.3 μm is formed.
A semiconductor layer 3 made of non-doped GaN having a thickness of about 2 μm is formed on the buffer layer 2, and a semiconductor layer 4 made of non-doped Al _0.25 Ga _0.75 N having a thickness of about 35 nm is formed thereon. Are stacked. Reference numerals 5, 6 and 7 indicate a source electrode, a gate electrode and a drain electrode, respectively.

Since the semiconductor layer 3 and the semiconductor layer 4 have different semiconductor crystal compositions, the crystal growth conditions that give optimum crystal quality are naturally different. In particular, growth conditions such as crystal growth temperature and atmospheric pressure (that is, partial pressure and total pressure of each gas) are important. For example, when crystal growth of AlGaN is performed, the crystal growth temperature that gives optimum crystal quality usually increases as the aluminum composition ratio increases.
Therefore, for example, in the case of the semiconductor layer 3, the optimum crystal growth temperature is about 1050 ° C., and in the semiconductor layer 4, about 1150 ° C., which is about 100 ° C. higher than that, is the optimum crystal. The growth temperature.
In addition, the crystal growth pressure (total pressure) of the semiconductor layer 4 made of AlGaN is usually set to be lower than that for crystal growth of the semiconductor layer 3 made of GaN in order to make the Al composition ratio in the semiconductor layer 4 uniform. It was.

As other conventional field effect transistors, for example, the following Patent Documents 1 to 4 disclose specific configuration examples.
JP 2002-57158 A JP2003-45899 JP2002-16087 JP 2003-277196 A

However, when the crystal growth conditions that emphasize the individual crystal quality of the individual semiconductor layers (3, 4) as described above are adopted, the crystal quality in each semiconductor layer can surely be kept high. According to proper crystal growth condition setting, the laminated state in the vicinity of the interface between the two semiconductor layers (3, 4) may be disturbed. That is, interface roughness occurs between the two layers. This is considered to be because the atoms that once formed the upper surface of the semiconductor layer 3 sublimate with the change of the crystal growth conditions between the two layers.
Such deterioration of crystallinity is largely based on the etching action by a carrier gas or the like. These circumstances can be easily understood from, for example, the following documents.

(1) Published patent publication: JP-A-11-068159
(2) Published patent publication: JP-A-9-139543
(3) Published patent publication: JP-A-8-88432
Further, such interface roughness causes a decrease in the mobility of carriers constituting a so-called pseudo two-dimensional electron gas that is planarly constrained by the channel, leading to a decrease in on-current, thereby causing a device failure. Characteristics deteriorate.

  The present invention has been made to solve the above-described problems, and its object is to improve the mobility of carriers passing through a channel in a field-effect transistor, thereby improving device characteristics. is there.

In order to solve the above problems, the following means are effective.
That is, according to the first means of the present invention, in a manufacturing process of a field effect transistor formed by laminating a plurality of semiconductor layers made of a group III nitride compound semiconductor by crystal growth, it is formed at or near the upper interface. A first crystal growth step of stacking the first semiconductor layer A in which the channel layer is generated and extinguished; and a second crystal growth step of stacking the second semiconductor layer B directly on the first semiconductor layer A; The band gap energy E _B of the second semiconductor layer B is made larger than the band gap energy E _A of the first semiconductor layer A, and at least of the second semiconductor layer B in the second crystal growth step The crystal growth condition in the initial stage of growth is set to a crystal growth condition that suppresses the sublimation action of atoms forming the vicinity of the surface of the first semiconductor layer A.

  However, since the channel layer (the electron gas layer) is generated and extinguished corresponding to ON / OFF of the gate voltage applied to a predetermined gate electrode, the channel layer is, of course, the above-described channel layer. It is not intended to be handled directly during the manufacturing process. When the gate is turned on, this channel layer (which is an electron gas layer) is usually an electron gas layer having a thickness of about 100 mm in the vicinity of the interface between the first semiconductor layer A and the second semiconductor layer B. It appears in

  Further, as important parameters that influence the crystal growth conditions for suppressing the sublimation action of atoms forming the vicinity of the surface of the first semiconductor layer A, for example, the crystal growth temperature, the partial pressures of various material gases, the carrier gas The type, the partial pressure of the carrier gas, the V / III ratio, the crystal growth rate, etc. can be considered. Therefore, for example, when Ga atoms of the GaN crystal are particularly easily sublimated, for example, a measure such as setting the partial pressure of trimethylgallium (TMG) to be relatively high or absolute can be considered.

The second means of the present invention, in the first means described above, the crystal growth temperature T _B of the second semiconductor layer B above, than the crystal growth temperature T _A of the first semiconductor layer A of the It is also to lower.

According to a third means of the present invention, in the first or second means, the crystal growth pressure P _B of the second semiconductor layer B is changed to the crystal growth pressure P A of the first semiconductor layer _A. And approximately match.

According to a fourth means of the present invention, in any one of the first to third means, the first semiconductor layer A is made of binary or ternary non-doped Al _x Ga _1-x N (0 ≦ x <1), and the second semiconductor layer B is formed of ternary non-doped Al _y Ga _1-y N (x <y ≦ 1).

The fifth aspect of the present invention, in the fourth means described above, the aluminum composition ratio x is approximately 0, aluminum composition ratio y of 0.15 or more, and 0.30 or less, the crystal growth pressure P _A , P _B are set at substantially normal pressure, and the crystal growth temperatures T _A , T _B are set so that the conditional expression “950 ° C. ≦ T _B <T _A ” is satisfied.

The sixth means of the present invention, in the first to fifth any one means described above is that the crystal growth temperature T _A of the first semiconductor layer A in the above 1200 ° C. or less.

The seventh aspect of the present invention, in the first to any one of the sixth means mentioned above, the crystal growth temperature T _A of the first semiconductor layer A, the crystal growth temperature of the second semiconductor layer B The temperature is higher than T _B by 50 ° C. or more. An appropriate range that seems to be more desirable for this temperature difference is 50 ° C. or more and 150 ° C. or less.

In addition, according to an eighth means of the present invention, in any one of the fifth to seventh means, the crystal growth temperature T _B of the second semiconductor layer B is expressed by the conditional expression “950 ° C. ≦ T _B <1050 It should be set to satisfy “℃”.

According to a ninth means of the present invention, the crystal growth temperature T _A of the first semiconductor layer A is set so as to satisfy the conditional expression “1050 ° C. <T _A ≦ 1150 ° C.” in the eighth means. It is to be.

According to a tenth means of the present invention, in a field effect transistor having a plurality of semiconductor layers made of a group III nitride compound semiconductor, a first semiconductor layer in which a channel layer is generated and extinguished at or near the upper interface. a and, and a second semiconductor layer laminated directly on the first semiconductor layer a B, the band gap energy of the band gap energy E _B of the second semiconductor layer B first semiconductor layer a The upper surface of the first semiconductor layer A is made substantially flat by suppressing the sublimation action of atoms of the first semiconductor layer A that is larger than E _A and forming the vicinity of the upper surface of the first semiconductor layer A. Is to form.

According to an eleventh means of the present invention, in the tenth means, the first semiconductor layer A is formed of binary or ternary non-doped Al _x Ga _1-x N (0 ≦ x <1). The second semiconductor layer B is formed of ternary non-doped Al _y Ga _1-y N (x <y ≦ 1).

  The twelfth means of the present invention is that, in the above eleventh means, the aluminum composition ratio x is substantially 0, and the aluminum composition ratio y is 0.15 or more and 0.30 or less. is there.

The thirteenth means of the present invention is that, in any one of the tenth to twelfth means, the thickness of the second semiconductor layer B is 1 nm or more. A more desirable thickness of the second semiconductor layer B is 5 nm or more.
By the above means of the present invention, the above-mentioned problem can be effectively or rationally solved.

The effects obtained by the above-described means of the present invention are as follows.
That is, according to the first means of the present invention, the crystal growth condition of the second semiconductor layer B in the second crystal growth step is the sublimation action of atoms forming the vicinity of the surface of the first semiconductor layer A. Since the crystal growth conditions are set to suppress the above, roughening of the interface of the first semiconductor layer A due to sublimation of atoms forming the vicinity of the upper surface of the first semiconductor layer A is satisfactorily prevented. Therefore, the upper surface of the first semiconductor layer A (hence, the lower surface of the second semiconductor layer B) is a substantially flat surface at least microscopically, and thereby the mobility of carriers moving in the channel layer described above. Therefore, the device characteristics are improved by increasing the on-current.

According to the second means of the present invention, the crystal growth temperature T _B of the second semiconductor layer B is set lower than the crystal growth temperature T _A of the first semiconductor layer A. The sublimation action of the atoms forming the vicinity of the surface of the semiconductor layer A can be suppressed very simply and effectively.

According to the third means of the present invention, since the crystal growth pressure P _B of the second semiconductor layer B substantially matches the crystal growth pressure P _A of the first semiconductor layer A, the first The sublimation action of the atoms forming the vicinity of the surface of the semiconductor layer A can be suppressed very simply and effectively.

According to the fourth means of the present invention, the band gap energy E _B of the second semiconductor layer B can be made necessary and sufficiently larger than the band gap energy E _A of the first semiconductor layer A. A layered structure that is necessarily achieved and in which the crystal quality of both layers A and B or the interface state such as interface flatness is stable can be obtained.
Therefore, according to the fourth means of the present invention, a field effect transistor having good operating characteristics can be manufactured easily and reliably.

  More generally, the group III nitride compound semiconductor forming the semiconductor layer A may contain indium (In). Such a stacked structure is not necessarily disadvantageous in ensuring a large difference in band gap energy between the semiconductor layers A and B. However, as can be seen from the above-mentioned published patent publications (1) to (3), in order to easily and surely form a flat and stable interface, indium (In) is formed in both of the semiconductor layers A and B. Should not be included.

Further, according to the fifth means of the present invention, it becomes easy and reliable to ensure the difference (E _B −E _A ) of the band gap energy as necessary and sufficient, and at the same time, both layers It is possible to obtain a laminated structure in which the interface state such as the crystal quality of A and B or the interface flatness is stable. Therefore, according to such conditions, a field effect transistor with extremely good electrical characteristics can be obtained.

  It is more desirable to follow at least one of the sixth to ninth means of the present invention. These appropriate ranges have been empirically determined as a result of our trial and error, and according to these measures, the design of the band gap centered on the channel, the mobility of carriers moving in the channel, In addition, it is possible to manufacture a semiconductor device that is comprehensively superior from various viewpoints such as controllability related to channel generation / extinction and crystal quality of each semiconductor layer.

  According to the tenth means of the present invention, in the field effect transistor, a field effect transistor having good operating characteristics can be easily and reliably manufactured based on the first means of the present invention.

According to the eleventh means of the present invention, in the field effect transistor, a field effect transistor having good operating characteristics can be easily and reliably manufactured based on the fourth means of the present invention. More desirably, the aluminum composition ratio x of the first semiconductor layer A is preferably substantially 0, and the aluminum composition ratio y of the second semiconductor layer B is preferably set in the range of 0.15 to 0.30. desirable. Further, the thickness of the second semiconductor layer B is preferably 1 nm or more, and the more desirable thickness of the second semiconductor layer B is 5 nm or more.
According to these conditions, a field effect transistor with extremely good electrical characteristics can be obtained.

As a material for the crystal growth substrate constituting the field effect transistor of the present invention, silicon carbide (SiC) is most suitable in terms of heat resistance and heat dissipation, but sapphire, silicon (Si), or a GaN substrate is used. It may be used.
Further, any known form can be adopted as a form of forming the ohmic electrode or the Schottky electrode.

Hereinafter, the present invention will be described based on specific examples.
However, the embodiments of the present invention are not limited to the following examples.

  FIG. 1 is a cross-sectional view of the field effect transistor 100 of the first embodiment. The field effect transistor 100 is a semiconductor element formed by sequentially stacking group III nitride compound semiconductors by crystal growth, and the crystal growth substrate 101 is made of silicon carbide (SiC) having a thickness of about 500 μm. ing. A buffer layer 102 made of AlN having a thickness of about 0.3 μm is formed on the crystal growth substrate 101.

A semiconductor layer 103 made of non-doped GaN having a thickness of about 2 μm is formed on the buffer layer 102. The semiconductor layer 103 corresponds to the first semiconductor layer A of the present invention. Further, on this semiconductor layer 103 (first semiconductor layer A), a semiconductor layer 104 made of non-doped Al _0.25 Ga _0.75 N having a thickness of about 35 nm corresponding to the second semiconductor layer B of the present invention is laminated. Has been. The film thickness of the semiconductor layer 104 (second semiconductor layer B of the present invention) is such that the channel layer generated near the interface between the semiconductor layers A and B when the gate is turned on and the individual ohmic electrodes (105 and 107) described below. The tunnel effect of the carriers (electrons) between them is set to be surely and satisfactorily exhibited.

  Reference numerals 105, 106, and 107 denote a source electrode (ohmic electrode), a gate electrode (Schottky electrode), and a drain electrode (ohmic electrode), respectively. Each ohmic electrode (source electrode 105 and drain electrode 107) is formed by laminating a thin metal layer made of titanium (Ti) with a thickness of about 100 mm and depositing aluminum (Al) thereon with a thickness of about 3000 mm. A metal layer is further laminated by vapor deposition. These ohmic electrodes are well adhered and alloyed by heat treatment at about 700 ° C. to 900 ° C. by flash annealing for less than 1 second. On the other hand, the gate electrode 106 is a Schottky electrode formed by depositing a metal layer made of nickel (Ni) of about 100 Å by vapor deposition, and further depositing a metal layer made of gold (Au) on it about 3000 Å. .

Hereinafter, the manufacturing method of the above-described field effect transistor 100 will be described focusing on the characteristic portions (semiconductor layers 103 and 104) of the present invention.
Each of the semiconductor layers (semiconductor layers 102, 103, 104) of the field effect transistor 100 is a crystal grown by vapor phase growth using a metal organic compound vapor phase growth method (MOVPE). The gases used here are carrier gas (H ₂ or N ₂ ), ammonia gas (NH ₃ ), trimethyl gallium (Ga (CH ₃ ) ₃ ), trimethyl aluminum (Al (CH ₃ ) ₃ ), etc. It is.
However, as a method for crystal growth of these semiconductor layers, in addition to the above-mentioned organometallic compound vapor phase epitaxy (MOVPE), molecular beam vapor phase epitaxy (MBE), halide vapor phase epitaxy (HVPE), etc. Is effective.

FIG. 2 shows the crystal growth conditions of the semiconductor layers A and B of the field effect transistor 100 of the first embodiment. As can be seen from FIG. 2, the crystal growth of the semiconductor layer 103 (that is, the first semiconductor layer A of the present invention) made of non-doped GaN crystal having a thickness of about 2 μm constituting the field effect transistor 100 is as follows. It carried out according to crystal growth conditions.
(Crystal growth conditions for semiconductor layer A)
(1) Crystal growth temperature T _A : 1100 [° C.]
(2) Crystal growth pressure P _A : 1013 [hPa]

Next, the crystal growth of the semiconductor layer 104 (that is, the second semiconductor layer B of the present invention) made of a non-doped Al _0.25 Ga _0.75 N crystal having a thickness of about 35 nm was performed according to the following crystal growth conditions. .
(Crystal growth conditions for semiconductor layer B)
(1) Crystal growth temperature T _B : 1000 [° C.]
(2) Crystal growth pressure P _B : 1013 [hPa]

The most significant feature of the first embodiment is that the crystal growth temperatures T _A and T _{B of} the first and second semiconductor layers A and B (semiconductor layers 103 and 104) and the crystal growth pressures P _A and P _B However, each of them satisfies the following formula (2). The following formula (1) is added to a typical setting example of crystal growth conditions in the manufacturing process of the conventional transistor 10 for comparison and comparison with the first embodiment.

(Conventional crystal growth conditions)
T _B > T _A ,
P _B <P _A (1)
(Crystal growth conditions of Example 1)
1000 ° C. = T _B <T _A = 1100 ° C.
P _B = P _A = (Normal pressure) (2)

  According to such crystal growth conditions, after the semiconductor layer 103 (first semiconductor layer A) is stacked by 2 μm, the crystal growth temperature in the crystal growth furnace is lowered, and the crystal growth pressure is maintained at substantially normal pressure. Maintained. For this reason, sublimation of atoms forming the upper surface of the semiconductor layer 103 (first semiconductor layer A) can be effectively suppressed. Therefore, according to the above crystal growth conditions, it is possible to effectively prevent the roughness of the interface between the semiconductor layers 103 and 104.

As a result, in the field effect transistor 100 of Example 1, as described in the characteristic column of FIG. 2, the on-current I is from 0.7 [A / mm] to 1.0 [A / mm]. improved, the sheet resistance ρ can be reduced from 650 [Omega / □] to 450 [Omega / □], and the mobility μ of the channel what was 1000 [cm ² / Vsec] extent, 1500 [cm ² / Vsec].

These electrical characteristics are extremely high performance equivalent to about 1 × 10 ¹³ [cm ⁻² ] in terms of the sheet carrier concentration of the channel layer (two-dimensional electron gas). . That is, according to the configuration and manufacturing method of the field effect transistor 100 of the first embodiment, the electrical characteristics of the device can be greatly improved as compared with the conventional case.

[Other variations]
The embodiment of the present invention is not limited to the above-described embodiment, and other modifications as exemplified below may be made. Even with such modifications and applications, the effects of the present invention can be obtained based on the functions of the present invention.
(Modification 1)
For example, in Example 1 described above, the interface between the semiconductor layer A (semiconductor layer 103) and the semiconductor layer B (semiconductor layer 104) is a substantially flat and substantially flat surface. Although it is desirable to be flat, it is not always necessary to have a planar shape from a macro viewpoint. For example, a curved surface composed of a part of a substantially spherical surface having a relatively large radius of curvature may form the interface between the two layers, or a non-planar surface having an appropriate inclination angle, wall surface installation interval, or repetition cycle. For example, the interface between the two layers may be formed. These shape designs are arbitrary design matters in each field effect transistor, and in any case of selecting any shape, the surface of the upper surface of the semiconductor layer A is prevented according to the means of the present invention. The effect of the present invention can be obtained by the smoothing effect.

  Since the present invention relates to the mobility of a channel layer or a two-dimensional electron gas generated in a substantially planar shape near the interface between semiconductor layers stacked by crystal growth, the mobility is effectively improved. The present invention is very useful for the design and manufacture of field effect transistors (various FETs, HEMTs, etc.) that can be manufactured by crystal growth of group III nitride compound semiconductors.

Sectional drawing of the field effect transistor 100 of Example 1 Table showing crystal growth conditions of semiconductor layers A and B of field effect transistor 100 Sectional view of a conventional field effect transistor 10

Explanation of symbols

100: Field effect transistor (Example 1)
101: Crystal growth substrate (SiC)
102: Buffer layer (AlN)
103: a semiconductor layer made of GaN (first semiconductor layer A)
104: Semiconductor layer made of AlGaN (second semiconductor layer B)
105: Source electrode (ohmic electrode)
106: Gate electrode (Schottky electrode)
107: drain electrode (ohmic electrode)

Claims (13)

A method of manufacturing a field effect transistor formed by laminating a plurality of semiconductor layers made of a group III nitride compound semiconductor by crystal growth,
A first crystal growth step of laminating a first semiconductor layer A in which a channel layer is generated and extinguished at or near the upper interface;
A second crystal growth step of directly stacking the second semiconductor layer B on the first semiconductor layer A,
The band gap energy E _B of the second semiconductor layer _B is
Greater than the band gap energy E _A of the first semiconductor layer A;
The crystal growth conditions at least in the initial growth stage of the second semiconductor layer B in the second crystal growth step are:
A method for manufacturing a field effect transistor, characterized in that the crystal growth conditions are set to suppress the sublimation action of atoms forming the vicinity of the surface of the first semiconductor layer A. The crystal growth temperature TB of the second semiconductor layer _B is
Method of manufacturing a field effect transistor according to claim 1, characterized in that below the crystal growth temperature T _A of the first semiconductor layer A. The crystal growth pressure P _B of the second semiconductor layer _B is:
Method of manufacturing a field effect transistor according to claim 1 or claim 2, characterized in that crystal growth pressure P _A substantially matching the first semiconductor layer A. The first semiconductor layer A includes
Consisting of binary or ternary non-doped Al _x Ga _1-x N (0 ≦ x <1),
The second semiconductor layer B includes
4. The method of manufacturing a field effect transistor according to claim 1, comprising ternary non-doped Al _y Ga _1-y N (x <y ≦ 1). 5. The aluminum composition ratio x is:
Almost zero,
The aluminum composition ratio y is
0.15 or more and 0.30 or less,
Crystal growth pressure P _A of the first semiconductor layer A, and both the crystal growth pressure P _B of the second semiconductor layer B,
Almost normal pressure,
Crystal growth temperature T _A of the first semiconductor layer A, and both the crystal growth temperature T _B of the second semiconductor layer B,
5. The method of manufacturing a field effect transistor according to claim 4, wherein the conditional expression “950 ° C. ≦ T _B <T _A ” is satisfied. The crystal growth temperature TA of the first semiconductor layer _A is
6. The method of manufacturing a field effect transistor according to claim 1, wherein the field effect transistor has a temperature of 1200 [deg.] C. or lower. The crystal growth temperature TA of the first semiconductor layer _A is
Method of manufacturing a field effect transistor according to any one of claims 1 to 6, characterized in that high or higher 50 ° C. than the crystal growth temperature T _B of the second semiconductor layer B. The crystal growth temperature TB of the second semiconductor layer _B is
The method of manufacturing a field effect transistor according to claim 5, wherein the conditional expression “950 ° C. ≦ T _B <1050 ° C.” is satisfied. The crystal growth temperature TA of the first semiconductor layer _A is
The method of manufacturing a field effect transistor according to claim 8, wherein the conditional expression “1050 ° C. <T _A ≦ 1150 ° C.” is satisfied. In a field effect transistor having a plurality of semiconductor layers made of a group III nitride compound semiconductor,
A first semiconductor layer A in which a channel layer is generated and extinguished at or near the upper interface;
A second semiconductor layer B directly stacked on the first semiconductor layer A,
The band gap energy E _B of the second semiconductor layer _B is
Greater than the band gap energy E _A of the first semiconductor layer A;
The upper surface of the first semiconductor layer A is
A field effect transistor characterized by being formed substantially flat by suppressing the sublimation action of atoms of the first semiconductor layer A forming the vicinity of the upper surface. The first semiconductor layer A includes
Consisting of binary or ternary non-doped Al _x Ga _1-x N (0 ≦ x <1),
The second semiconductor layer B includes
11. The field effect transistor according to claim 10, comprising ternary non-doped Al _y Ga _1-y N (x <y ≦ 1). The aluminum composition ratio x is:
Almost zero,
The aluminum composition ratio y is
The field effect transistor according to claim 11, wherein the field effect transistor is 0.15 or more and 0.30 or less. The thickness of the second semiconductor layer B is:
13. The field effect transistor according to claim 10, wherein the field effect transistor is 1 nm or more.

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