JP2005348168A - Clock control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock control circuit capable of precisely controlling phase relations at high speed, when a multiphase external clock signal is inputted, and frequency dividers are operated with that multiphase input clock signal. <P>SOLUTION: By dealing divided signals formed by frequency division from a multiphase clock signal (CLK11-CLK14) inputted externally, as data and clocks for downstream D flip-flops, time delay of each D flip-flop is canceled, and only the set up time of each D flip-flop becomes an element to determine the frequency of each clock. Clock control of a higher frequency can be performed, by causing this set up time to have a margin further by the use of delay buffers (111-115). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a clock control circuit that determines the order in accordance with a difference in phase difference between clocks when there are multiphase clocks, and more particularly to a circuit that improves operation accuracy at a high frequency. .

  The operation clock of LSI has been increasing year by year. However, the operation at several hundreds of MHz has been the limit for control circuits such as D flip-flops for this increase in speed. For this reason, as shown in Patent Document 1, a multiphase clock is required in a control system circuit, and if the order of the multiphase clock is not correct for performing control with the multiphase clock, malfunction occurs. It can happen a lot.

As an example, FIG. 4 shows a clock control circuit that generates a four-phase clock from a two-phase clock.
The external clock CLK1 and the external clock CLK2 are clocks whose phases are shifted from each other by 180 degrees.

  First, the external clock CLK 61 is input to the D flip-flop 601. The D flip-flop 601 is a circuit that divides the input clock by two.

  Further, the output Q61 of the D flip-flop 601 is input as data of the D flip-flop 602, and the clock CLK62 is input to the clock input of the D flip-flop 602.

  Further, the output Q62 of the D flip-flop 602 is input as data of the D flip-flop 603, and the clock CLK61 is input to the clock input of the D flip-flop 603.

  Further, the output Q63 of the D flip-flop 603 is input as data of the D flip-flop 604, and the clock CLK62 is input to the clock input of the D flip-flop 604.

  By this circuit, the four-phase clocks Q61, Q62, Q63, and Q64 shown in FIG. 7 are controlled and output in the order of the small phase difference from the two-phase clocks that are out of phase.

In the circuit shown in FIG. 6, the divided output Q81 and the divided output Q83 are output by the D flip-flop 801 having the external clock CLK81 as a clock input, and the D flip-flop 802 having the external clock CLK82 as a clock input. A frequency-divided output Q82 and a frequency-divided output Q84 are output, and a four-phase clock shown in FIG. 7 is generated.
JP 2001-350539 A

  The conventional clock control apparatus is configured as described above and can generate a four-phase clock from a two-phase clock. However, in the conventional circuit configuration, the external clock CLK61 in FIG. The output Q61 of the operating D flip-flop 601 is handled as the data input of the D flip-flop 602 operating with the external clock CLK62. The D flip-flop 601 has an output delay T61 from the input of CLK61. The flip-flop 602 requires a setup time T62 in which data must be determined before the input of the external clock CLK62. For this reason, the phase difference time between the external clock CLK61 and the external clock CLK62 is not longer than the sum (T61 + T62) of the delay time T61 of the D flip-flop 601 shown in FIG. 5 and the setup time T62 of the D flip-flop 602 shown in FIG. This multi-phase clock generation circuit (clock control measure) does not operate, and there is a problem that it is impossible to supply a high-frequency clock to a circuit that operates at a high frequency.

  Further, since the circuit shown in FIG. 6 operates independently with the external clock CLK81 and the external clock CLK82, when the reset timing as shown in FIG. There was a problem that there was a possibility of malfunction.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a clock control device that can provide a multiphase clock having an accurate phase relationship even when the frequency is high.

  The clock control circuit according to claim 1 of the present invention inputs external clocks of the same frequency in different phases from each other and controls the timing between the clocks when outputting the multi-phase clocks synchronized with the external clocks. A plurality of frequency dividing circuits provided corresponding to the number of external clocks, and one normal rotation or inverted output of each of the frequency dividing circuits as its data input; A plurality of D flip-flops having one of the normal or inverted outputs of the frequency divider circuit as its clock input, and the respective outputs of the plurality of D flip-flops as control signals for controlling the outputs of the frequency divider circuits, And a clock selection circuit that selectively outputs the output of either the frequency divider or the D flip-flop.

  A clock control circuit according to a second aspect of the present invention is the clock control circuit according to the first aspect, wherein the external clock is an n (n is an integer) phase clock, and each of the n phase clocks is divided. Each of the frequency dividing circuits includes the D flip-flop and the selection circuit as a circuit that outputs a multiphase clock synchronized with the input clock.

  A clock control circuit according to a third aspect of the present invention is the clock control circuit according to the first aspect, wherein the clock corresponding to the input data of the D flip-flop is shifted in phase from the cycle of the multiphase clock that generates the data. Or a clock that can ensure the setup time of the D flip-flop.

  A clock control circuit according to a fourth aspect of the present invention is the clock control circuit according to the first aspect, wherein the D flip-flop causes a hold error with respect to a clock input to the D flip-flop, and is set up. A buffer for providing a delay for securing time is provided.

  A clock control circuit according to a fifth aspect of the present invention is the clock control circuit according to the first aspect, wherein each of the clock selection circuits selects a predetermined one of the input signals and outputs a signal delay amount until the output. Is the same regardless of which signal is selected.

  A clock control circuit according to a sixth aspect of the present invention is the clock control circuit according to the first aspect, wherein the clock selection circuit has a function of exchanging signals of two inputs, and the signal of the signal is output by an output signal of the D flip-flop. The replacement is controlled.

  A clock control circuit according to a seventh aspect of the present invention is the clock control circuit according to the first aspect, wherein the output system in which the selection circuit is not inserted on the output side of the frequency divider circuit generates a multiphase data. A delay circuit having a delay amount corresponding to the clock having the largest phase shift from the clock cycle or a delay amount corresponding to a time that can secure the setup time of the D flip-flop is inserted.

  According to the clock control circuit of the present invention, the frequency-divided signal generated by the externally input multiphase clock is handled as the data and clock of the downstream D flip-flop. It is canceled out, and only the setup time of the D flip-flop becomes an element that determines the frequency of the clock, and an effect that clock control at a higher frequency can be performed is obtained.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a clock control circuit according to the first exemplary embodiment of the present invention. In FIG. 1, a D flip-flop 101 is a frequency dividing circuit that divides by an external input clock CLK11. The D flip-flop 102 is a frequency divider that operates with the external clock CLK14 that is 270 degrees out of phase with the external clock CLK11. The D flip-flop 103 is a frequency divider that operates with an external clock CLK13 that is 180 degrees out of phase with the external clock CLK11. The D flip-flop 104 is a frequency divider that operates with an external clock CLK12 that is 90 degrees out of phase with the external clock CLK11. As described above, clocks whose phases are shifted by 90 degrees are input to each frequency dividing circuit.

  The D flip-flop 105 is connected to operate by inputting the output Q11 of the D flip-flop 101 as data and the inverted output NQ14 of the D flip-flop 102 as a clock.

  The D flip-flop 106 is connected to operate by inputting the output Q14 of the D flip-flop 102 as data and inputting the output Q13 of the D flip-flop 103 as a clock.

  The D flip-flop 107 is connected to operate by inputting the output Q13 of the D flip-flop 103 as data and inputting the inverted output NNQ12 of the data D flip-flop 104 as a clock.

  Reference numeral 108 denotes a selection circuit connected downstream of the D flip-flop 102. If the output Q15 of the D flip-flop 105 is “L”, the input signal Q13 to the selection circuit 108 is output as S13. On the other hand, if the output Q15 of the D flip-flop 105 is “H”, the input signal Q13 to the selection circuit 108 is output as the inverted output NS13, and the inverted input signal NQ13 is output as S13. The delay time from the signal input to the circuit to the output is the same regardless of which signal is input and output.

  The selection circuit 109 is a selection circuit connected to the subsequent stage of the D flip-flop 103. If the three outputs Q16 of the D flip-flop 106 are “L”, the input signal Q13 to the selection circuit 109 is output as S13. The inverted signal NQ13 is output as the inverted output NS13. On the other hand, if the output Q16 of the D flip-flop 106 is "H", the input signal Q13 to the selection circuit 109 is output as the inverted output NS13, and the inverted signal NQ13 is output as S13. The delay time from signal input to output is the same regardless of which signal is input and output.

  The selection circuit 110 is a selection circuit connected to the subsequent stage of the D flip-flop 104. If the output Q17 of the D flip-flop 107 is “L”, the input signal Q12 to the selection circuit 110 is output as S12. The inverted signal NQ12 is output as the inverted output NS11. On the other hand, if the output Q17 of the D flip-flop 107 is “H”, the input signal Q12 to the selection circuit 110 is output as the inverted output NS12, and the inverted signal NQ12 is output as S12. The delay time from signal input to output is the same regardless of which signal is input and output.

In addition, it is assumed that the signal delay amounts of the selection circuits 108, 109, and 110 are all adjusted to be the same.
Further, reference numerals 111 to 115 denote delay buffers adjusted so as to have different delay amounts.

Next, the relationship between each waveform shown in FIG. 2 and the operation of each circuit shown in FIG. 1 will be described.
The same external clocks CLK11, CLK12, CLK13, and CLK14 having different frequencies of 90 degrees in FIG. 2 are input to the D flip-flops 101, 104, 103, and 102 constituting the frequency dividing circuit. When the reset signal is at the timing shown in FIG. 2, the outputs Q11, Q12, Q13, and Q14 of the D flip-flops 101, 102, 103, and 104, and the inverted outputs NQ11, NQ12, NQ13, and NQ14 have the waveforms shown in FIG. is there. These signals are also correctly output in phase relationship.

  Since the signal Q11 is the output of the D flip-flop 101, the signal Q11 is output with a delay of the D flip-flop 101 with respect to the rising edge of the external clock CLK11.

  Further, since the inverted signal NQ14 is also an output of the D flip-flop 102, it is output with a delay of the D flip-flop 102 with respect to the rising edge of the external clock CLK14.

  The signal Y111 is a signal obtained by delaying the inverted signal NQ14 by the delay buffer 111 in the same manner as the phase difference of the external clock CLK14 from the external clock CLK11, or the inverted signal NQ14 with a smaller delay amount, and the D flip-flop 105 inputs the data. On the other hand, it is a signal that is delayed in a direction in which the setup time is extended while not causing a clock hold error.

  The operation range of the D flip-flop 105 is operable as long as the rise time of the signal Y111 from the changing point of the output Q11 is longer than the minimum setup time of the D flip-flop 105. The delay time of the output Q11 and the delay time of the inverted signal NQ14 of the D flip-flop 102 with respect to the external clock CLK14 are offset from each other, and the phase difference between the external clocks CLK14 and CLK11 is delayed by the delay buffer 111. Therefore, only the setup time of the D flip-flop 105 is an element that determines the operating frequency.

  When the signal Q11 as data and Y111 as the clock are input to the D flip-flop 105, the time from the change point of the signal Q11 to the rise of the signal Y111 is ensured more than the setup time of the D flip-flop 105. The output signal Q15 of 105 is always “L”.

  The output signal Q15 of the D flip-flop 105 is input to the clock selection circuit 108. When L is input, the clock selection circuit 108 selects the signal Q14 as the output S14, and selects and outputs the inverted signal NQ14 as the inverted output NS14.

The signal Q11 passes through the delay buffer 114 and becomes the output S11, and the inverted signal NQ11 passes through the delay buffer 115 and becomes the inverted output NS11.
Here, the delay buffers 114 and 115 are delay buffers having the same delay amount as the selection circuit 108.

  Next, since the signal NQ12 is the output of the D flip-flop 102, the signal NQ12 is output with a delay of the delay amount of the D flip-flop with respect to the rising edge of the external clock CLK12.

  The signal Y113 is a signal obtained by delaying the inverted signal NQ12 by the delay buffer 113 in the same manner as the phase difference between the external clock CLK12 and the external clock CLK13, or a delay amount smaller than this, with respect to the output S14 of the signal Q14 of the selection circuit 108. This is a signal obtained by adding the amount and delaying the signal Q13 in the direction in which the clock hold error does not occur with respect to the data input of the D flip-flop 105 and in the direction in which the setup time is widened.

  The operation range of the D flip-flop 106 is operable as long as the rise time of the signal Y112 from the changing point of the output S14 is longer than the minimum setup time of the D flip-flop 106. The delay time of the output Q14 and the delay time of the output Q13 of the D flip-flop 103 with respect to the external clock CLK13 cancel each other, and further, the delay amount of the selection circuit 108 with respect to the output Q14 and the external clock CLK13. And the phase difference between the external clock CLK14 are delayed by the delay buffer 111, and only the setup time of the D flip-flop 106 is an element for determining the operating frequency.

  When the output S14 is input to the D flip-flop 106 as the data and the signal Y112 is input as the clock, the time from the change point of the output S14 to the rise of the signal Y112 is secured for the setup time of the D flip-flop 106 or more. The output Q16 of the D flip-flop 106 is always “L”.

The output Q16 of the D flip-flop 106 is input to the clock selection circuit 109.
When L is input, the clock selection circuit 109 selects the signal Q13 as the output S13 and selects and outputs the inverted output NQ13 as the inverted signal NS13.

  Next, since the signal Q13 is an output of the D flip-flop 103, it is output with a delay amount of the D flip-flop with respect to the rising edge of the external clock CLK13.

  The signal Y112 is obtained by adding a delay amount for the output S13 of the signal Q13 of the selection circuit 109 to a signal obtained by delaying the signal Q13 by the delay buffer 112 in the same manner as the phase difference of the external clock CLK13 with respect to CLK14 or a delay amount smaller than this. Thus, the inverted signal NQ12 is a signal obtained by delaying the set-up time in a time in which a clock hold error with respect to the data input of the D flip-flop 107 does not occur.

  The operation range of the D flip-flop 107 is operable as long as the rise time of the signal Y113 from the changing point of the output S13 is longer than the minimum setup time of the D flip-flop 107, but the output of the D flip-flop 103 with respect to the external clock CLK13. The delay time of Q13 and the delay time of the inverted output NQ12 of the D flip-flop 102 with respect to the external clock CLK12 cancel each other, and further, the delay amount from the signal Q13 of the output S13 of the selection circuit 109 and the external clock Since the phase difference between CLK12 and the external clock CLK13 is delayed by the delay buffer 113, only the setup time of the D flip-flop 107 is an element that determines the operating frequency.

  When the output S13 is input to the D flip-flop 107 as the data and the signal Y113 is input as the clock, the time from the change point of the output S13 to the rise of the signal Y113 is secured more than the setup time of the D flip-flop 107. The output Q17 of the flip-flop 107 is always “L”.

  The output Q17 of the D flip-flop 107 is input to the clock selection circuit 110.

  When L is input, the clock selection circuit 110 selects the signal Q12 as the output S12 and selects and outputs the inverted signal NQ12 as the inverted output NS12.

Next, the relationship between each waveform shown in FIG. 3 and the operation of each circuit shown in FIG. 1 will be described.
The external clocks CLK11, CLK12, CLK13, and CLK14 having the same frequency in FIG. 3 are input to the D flip-flops 101, 104, 103, and 102 constituting the frequency dividing circuit. When the reset signal has the timing shown in FIG. 3, the output signals Q11, Q12, Q13, and Q14 of the D flip-flops 101, 102, 103, and 104, and the inverted output signals NQ11, NQ12, NQ13, and NQ14 are shown in FIG. It is a waveform. These signals are not correctly phase-related.

  In the figure, since the signal Q11 is the output of the D flip-flop 101, the signal Q11 is output with a delay of the D flip-flop 101 with respect to the rising edge of the external clock CLK11.

  Further, since the inverted signal NQ14 is also an output of the D flip-flop 102, it is output with a delay of the D flip-flop with respect to the rising edge of the external clock CLK14.

  The signal Y111 is a signal obtained by delaying the inverted signal NQ14 by the delay buffer 111 in the same manner as the phase difference of the external clock CLK14 from the external clock CLK11, or the inverted signal NQ14 with respect to the data input of the D flip-flop 105 with a smaller delay amount. This is a signal that is delayed in the direction in which the set-up time is widened in a time in which no clock hold error occurs.

  The operation range of the D flip-flop 105 is operable as long as the rise time of the signal Y111 from the changing point of the signal Q11 is longer than the minimum setup time of the D flip-flop 105, but the output signal of the D flip-flop 101 with respect to the external clock CLK11 The delay time of Q11 and the delay time of the inverted output signal NQ14 of the D flip-flop 102 with respect to the external clock CLK14 are offset from each other. Further, the delay buffer 111 delays the phase difference between the external clocks CLK14 and CLK11. Only the setup time of 105 is an element that determines the operating frequency.

  When the signal Q11 is input as data to the D flip-flop 105 and the signal Y111 is input as the clock, the time from the change point of the signal Q11 to the rise of the signal Y111 is secured for the setup time of the D flip-flop 105. The output signal Q15 of the group 105 becomes H at the first rising edge of the signal Y111 after reset.

  The output Q15 of the D flip-flop 105 is input to the clock selection circuit 108.

  When H is input, the clock selection circuit 108 selects the inverted signal NQ14 as the output S14, selects the signal Q14 as the inverted output NS14, and outputs these.

The signal Q11 passes through the delay buffer 114 and becomes the output S11, and the inverted signal NQ11 passes through the delay buffer 115 and becomes the inverted output NS11.
Here, the delay buffers 114 and 115 are delay buffers having the same delay amount as the selection circuit 108.

  Next, since the inverted signal NQ12 is the output of the D flip-flop 102, it is output with a delay of the D flip-flop with respect to the rising edge of the external clock CLK12.

  The signal Y113 is a signal obtained by delaying the inverted signal NQ12 by the delay buffer 113 in the same manner as the phase difference of the external clock CLK12 relative to the external clock CLK13, or a smaller delay amount than the output S14 of the inverted signal NQ14 of the selection circuit 108. This is a signal obtained by adding the delay amount and delaying the signal Q13 in a time in which the D flip-flop 105 does not cause a clock hold error with respect to the data input and in the direction in which the setup time is widened.

  The operation range of the D flip-flop 106 is operable as long as the rise time of the signal Y112 from the change point of the output S14 is longer than the minimum setup time of the D flip-flop 106, but the inverted output of the D flip-flop 102 with respect to the external clock CLK14 The delay time of NQ14 and the delay time of the output Q13 of the D flip-flop 103 with respect to the external clock CLK13 cancel each other, and the delay amount of the output S14 of the selection circuit 108 with respect to the inverted signal NQ14 and the external clock CLK13 Since the phase difference from the external clock CLK14 is delayed by the delay buffer 111, only the setup time of the D flip-flop 106 is an element that determines the operating frequency.

  When the output S14 is input to the D flip-flop 106 as the data and the signal Y112 is input as the clock, the time from the change point of the output S14 to the rise of the signal Y112 is ensured more than the setup time of the D flip-flop 106. The output Q16 of the group 106 becomes “H” at the first rising edge of the signal Y112 after reset.

  The output signal Q16 of the D flip-flop 106 is input to the clock selection circuit 109.

  When L is input, the clock selection circuit 109 selects the inverted signal NQ13 as the output S13, and selects and outputs the signal Q13 as the inverted output NS13.

  Next, since the inverted signal NQ12 is the output of the D flip-flop 103, it is output with a delay of the D flip-flop with respect to the rising edge of the external clock CLK13.

  The signal Y112 is obtained by adding the delay amount for the output S13 of the signal Q13 of the selection circuit 109 to a signal obtained by delaying the signal Q13 by the delay buffer 112 in the same manner as the phase difference with respect to the CLK14 of the external clock CLK13 or a smaller delay amount. The inverted signal NQ12 is a signal obtained by delaying the inverted signal NQ12 in the direction in which the D flip-flop 107 does not cause a clock hold error and the setup time is increased with respect to the data input.

  The operation range of the D flip-flop 107 is operable as long as the rise time of the signal Y113 from the changing point of the output S13 is longer than the minimum setup time of the D flip-flop 107, but the output signal of the D flip-flop 103 with respect to the external clock CLK13 The delay time of Q13 and the delay time of the inverted output signal NQ12 of the D flip-flop 102 with respect to the external clock CLK12 cancel each other, and further, the delay amount of the output S13 of the selection circuit 109 with respect to the signal Q13 and the external clock Since the phase difference between CLK12 and the external clock CLK13 is delayed by the delay buffer 113, only the setup time of the D flip-flop 107 is an element that determines the operating frequency.

  When the output S13 is input to the D flip-flop 107 as the data and the signal Y113 is input as the clock, the time from the change point of the output S13 to the rise of the signal Y113 is secured more than the setup time of the D flip-flop 107. The output signal Q17 of the flip-flop 107 is always “L”.

  The output signal Q17 of the D flip-flop 107 is input to the clock selection circuit 110. When L is input, the clock selection circuit 110 selects the signal Q12 as the output S12, and selects and outputs the inverted signal NQ12 as the inverted output NS12.

  As described above, according to the clock control circuit according to the first exemplary embodiment of the present invention, the divided signal generated by the externally input multiphase clock (CLK11 to CLK14) is used as the data of the downstream D flip-flop. Since the delay time of the D flip-flop is canceled out because it is handled as a lock, only the setup time of the D flip-flop becomes an element for determining the clock frequency, and this setup time is further margined by the delay buffer (111 to 115). By providing this, it becomes possible to perform clock control at a higher frequency.

  In the above embodiment, the case where the frequency dividing circuit is a frequency dividing circuit of 2 and the number of phases of the external clock is 4 phases has been described, but the frequency dividing circuit is divided by n (n is 2 or more). The same effect can be obtained even when the number of external clocks is 2 or more.

  Use of the clock control circuit according to the present invention in a circuit that requires high-speed operation makes it possible to supply a higher frequency clock, which is useful in terms of providing a higher performance circuit. It is.

It is a block diagram for demonstrating the structure of the clock control circuit of embodiment of this invention. These are an internal waveform of the clock control circuit and an output waveform to the outside. These are an internal waveform of the clock control circuit and an output waveform to the outside. It is a block diagram for demonstrating the structure of the conventional clock control circuit. 2 shows input / output waveforms of a conventional clock control circuit. It is a block diagram for demonstrating the structure of another conventional clock control circuit. It shows an input / output waveform of another conventional clock control circuit. In other conventional clock control circuits, the input / output waveforms when the timing of the reset signal is different are shown.

Explanation of symbols

101, 102, 103, 104 Frequency dividing circuits 105, 106, 107 D flip-flops 108, 109, 110 Clock selection circuits 111, 112, 113, 114, 115 Delay buffers

Claims (7)

In a clock control circuit for controlling the timing between clocks when inputting multiphase external clocks having different phases from each other and outputting multiphase clocks synchronized with the external clocks,
A plurality of frequency dividing circuits provided corresponding to the number of external clocks;
A plurality of D flip-flops having one normal rotation or inverted output of each frequency divider circuit as its data input and one normal or inverted output of another frequency divider not selected as its clock input;
A clock selection circuit that outputs each of the plurality of D flip-flops as a control signal for controlling the output of each frequency divider, and selectively outputs one of the frequency divider or the D flip-flop;
A clock control circuit comprising: The clock control circuit according to claim 1, wherein
The external clock is a clock of n (n is an integer) phase, and includes n frequency dividing circuits each for dividing the clock of the n phase.
Each frequency dividing circuit includes the D flip-flop and the selection circuit as a circuit for outputting a multiphase clock synchronized with the input clock.
A clock control circuit. The clock control circuit according to claim 1, wherein
The clock corresponding to the input data of the D flip-flop is a clock having the largest phase shift from the cycle of the multiphase clock that generates the data, or a clock that can ensure the setup time of the D flip-flop.
A clock control circuit. The clock control circuit according to claim 1, wherein
A buffer for providing a delay for the D flip-flop to cause a hold error and to secure a setup time with respect to a clock input to the D flip-flop;
A clock control circuit. The clock control circuit according to claim 1, wherein
Each of the clock selection circuits selects a predetermined one of the input signals and the delay amount of the signal until the output is equal regardless of which signal is selected.
A clock control circuit. The clock control circuit according to claim 1, wherein
The clock selection circuit has a function of switching signals of two inputs, and switching of the signals is controlled by an output signal of the D flip-flop.
A clock control circuit. The clock control circuit according to claim 1, wherein
In an output system in which a selection circuit is not inserted on the output side of the frequency divider, a delay amount corresponding to the clock having the largest phase shift from the cycle of the multiphase clock that generates the data, or setup of a D flip-flop Inserted a delay circuit with a delay equivalent to the time that can be secured,
A clock control circuit.

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