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JP2005340268A - Transistor package - Google Patents

Transistor package Download PDF

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Publication number
JP2005340268A
JP2005340268A JP2004153305A JP2004153305A JP2005340268A JP 2005340268 A JP2005340268 A JP 2005340268A JP 2004153305 A JP2004153305 A JP 2004153305A JP 2004153305 A JP2004153305 A JP 2004153305A JP 2005340268 A JP2005340268 A JP 2005340268A
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Japan
Prior art keywords
transistor package
chip
resin
metal member
transistor
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JP2004153305A
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Japanese (ja)
Inventor
Kazutoshi Ito
和利 伊藤
Ryoichi Kajiwara
良一 梶原
Hirotake Oka
浩偉 岡
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Renesas Technology Corp
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Renesas Technology Corp
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Priority to JP2004153305A priority Critical patent/JP2005340268A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a transistor package having a reliable bonding structure of an Si chip and a metal member with a Pb free solder material of a high melting point. <P>SOLUTION: The transistor package A where the structure of a bonding part is set to be (Ti or Ni)/SnSbAgCu alloy/(Ti or Ni) is molded by resin 10 whose coefficient of linear expansion is 5 ppm/°C to 9 ppm/°C. The Pb free solder material 4 is used as a bonding material, and the Si chip and metal lead are bonded. Thus, the transistor package A which is proof against reflow of 260°C and is superior in temperature cycle reliability can be provided. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体チップをSn-Sb系の接合材でリードフレーム等の金属部材に搭載したトランジスタパッケージに関し、特に耐熱性や温度サイクル信頼性に優れたトランジスタパッケージとそのトランジスタパッケージの組み立てに用いられる接合材、金属部材及び封止樹脂に適用して有効な技術である。   The present invention relates to a transistor package in which a semiconductor chip is mounted on a metal member such as a lead frame with an Sn-Sb-based bonding material, and is particularly used for assembling a transistor package with excellent heat resistance and temperature cycle reliability. This technique is effective when applied to a bonding material, a metal member, and a sealing resin.

従来、トランジスタパッケージのSiチップ接合には、Pbを90％以上含む高融点はんだ材が使われていた。近年、有害物質のPbによる環境汚染を防ぐため、電子装置の組立部材からPbを除くことが早急に求められている。しかし、現時点では従来のPb入り高温はんだ材にそのまま置き換えることができる高融点のPbを含まないはんだ材は公表されていない。高温はんだ材としては、Sn-Sb系合金が知られている。例えば、特許文献１には、Sn-Sb系合金をはんだ材として用いた発明が開示されている。
特開２００１−２３７２５２号公報 Conventionally, a high melting point solder material containing 90% or more of Pb has been used for Si chip bonding of transistor packages. In recent years, in order to prevent environmental pollution due to the harmful substance Pb, it is urgently required to remove Pb from the assembly member of the electronic device. However, at the present time, no solder material that does not contain high melting point Pb that can be directly replaced with a conventional high-temperature solder material containing Pb has been disclosed. As a high temperature solder material, an Sn—Sb alloy is known. For example, Patent Document 1 discloses an invention using a Sn—Sb alloy as a solder material.
JP 2001-237252 A

ところが、Sn-Sb系合金を高温はんだ材として用いるには、以下の課題があることを本発明者は見出した。   However, the present inventor has found that there are the following problems in using the Sn—Sb alloy as a high-temperature solder material.

Sn-Sb系合金で、高濃度のSbを含み固相温度が300℃以上のはんだ材は、ペレット付け後のトランジスタパッケージを260℃の温度で２次実装（以下260℃リフローと記す）しても、ペレット付け部のはんだの再溶融が無く良好である。しかし、このはんだ材は非常に硬く、かつ高温域まで脆くて伸びが非常に小さい性質を持っているため、ペレット付け時にSiチップに発生する熱応力が高く、チップが割れてしまうという問題がある。   For solder materials with Sn-Sb-based alloys that contain high concentrations of Sb and a solid phase temperature of 300 ° C or higher, the transistor package after pelletization is secondarily mounted at a temperature of 260 ° C (hereinafter referred to as 260 ° C reflow). Also, it is good because there is no remelting of the solder in the pelletized portion. However, since this solder material is very hard and brittle to high temperatures and has very little elongation, the thermal stress generated in the Si chip during pelletization is high, causing the chip to crack. .

一方、Sn-Sb系合金で、低濃度のSbを含むはんだ材は、高濃度のSb入りはんだ材よりも柔らかく、ペレット付け後にSiチップ割れは起こさないが、固相温度が240℃と低いため、トランジスタパッケージの信頼性試験（85℃/85RH%-168ｈ後260℃リフロー処理×3回）を行うと、はんだの再溶融に伴う体積膨張によってモールド樹脂が押し上げられ、はんだ材内部でのクラック発生や、はんだ材が接合部から周囲に流出して凝固時に体積不足を生じて接合部にボイド欠陥が発生するなど、半導体装置に不具合が生じるという問題がある。   On the other hand, a solder material containing low concentration of Sb with Sn-Sb alloy is softer than solder material containing high concentration of Sb and does not cause Si chip cracking after pelleting, but the solid phase temperature is as low as 240 ° C. When a transistor package reliability test is performed (85 ° C / 85RH% -168h followed by 260 ° C reflow treatment x 3 times), the mold resin is pushed up by volume expansion accompanying remelting of the solder, and cracks are generated inside the solder material. In addition, there is a problem in that the semiconductor device has a problem such that the solder material flows out from the joint portion to cause a volume shortage during solidification and a void defect occurs in the joint portion.

トランジスタパッケージのSiチップ接合に要求されるはんだ材の性質としては、以下の４点があり、これら全てが満たされないとトランジスタパッケージの組立てには適用できない。かかる性質とは、1)SiチップをCuリードまたはNiめっきCuリードに接合したときの熱膨張差に伴う熱歪をはんだ接合部が緩和して、熱応力によるSiペレットの破損を防ぐこと、2)パッケージを配線基板に２次実装するときの加熱や高温環境での使用に耐える耐熱性を有していること、3)半導体デバイスの発熱によって引き起こされる温度変動に対してはんだ接合部の熱疲労寿命が十分に長いこと、4）はんだ材がSiペレットの電極材や金属部材に対して濡れ性に優れることである。   The properties of the solder material required for the Si chip bonding of the transistor package include the following four points, which cannot be applied to the assembly of the transistor package unless all of these are satisfied. These properties are: 1) the solder joints relieve the thermal strain associated with the thermal expansion difference when the Si chip is bonded to the Cu lead or Ni-plated Cu lead, and prevent Si pellet breakage due to thermal stress; 2 ) Has heat resistance to withstand heating when used for secondary mounting of a package on a wiring board and use in a high temperature environment. 3) Thermal fatigue of solder joints against temperature fluctuations caused by heat generation of semiconductor devices. The life is sufficiently long. 4) The solder material has excellent wettability with respect to the electrode material and metal member of the Si pellet.

本発明の目的は、Pbを含まないはんだ材を用いて、ペレット付け後の冷却過程や温度サイクル試験におけるSiチップ割れを防止し、パッケージを配線基板に２次実装するときの加熱に耐え、かつ繰り返しの熱ストレスにおけるはんだ接合部の疲労寿命に優れたトランジスタパッケージを提供することにある。   The object of the present invention is to use a solder material that does not contain Pb to prevent cracking of the Si chip in the cooling process after pelleting and the temperature cycle test, to withstand heating when the package is secondarily mounted on the wiring board, and It is an object of the present invention to provide a transistor package with excellent fatigue life of solder joints under repeated thermal stress.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

上記目的を達成するために、半導体チップとリードフレーム等の金属部材とを接合する接合材が、固相温度225℃のSnSbAgCu系を主成分とし、合金の構成比率がAg、Cuで10〜35重量％で、かつSb/(Sn+Sb)の重量比率が0.23〜0.38であり、半導体チップ裏面の電極材をTi/Ni/(AgまたはAu)あるいはNi/Ti/Ni/(AgまたはAu)とし、金属部材の表面はCuあるいはCu上に厚さ1μm以上のNiめっきを施して、半導体チップ/接合材/金属部材の構成とし、還元雰囲気中で300-370℃に加熱して接合し、半導体チップと金属部材の少なくとも一部を線膨張係数5ppm/℃〜9ppm/℃の樹脂で封止する構成を発案し、本発明に至った。   In order to achieve the above object, a bonding material for bonding a semiconductor chip and a metal member such as a lead frame is mainly composed of SnSbAgCu based on a solid phase temperature of 225 ° C., and the composition ratio of the alloy is 10 to 35 with Ag and Cu. The weight ratio of Sb / (Sn + Sb) is 0.23 to 0.38, and the electrode material on the back surface of the semiconductor chip is Ti / Ni / (Ag or Au) or Ni / Ti / Ni / (Ag or Au). And the surface of the metal member is Cu or Ni plated with a thickness of 1 μm or more on Cu, and it is configured as a semiconductor chip / bonding material / metal member, heated to 300-370 ° C. in a reducing atmosphere and bonded, A configuration in which at least a part of a semiconductor chip and a metal member is sealed with a resin having a linear expansion coefficient of 5 ppm / ° C. to 9 ppm / ° C. was conceived and the present invention was achieved.

図４は、Sn-Sb系で低濃度のSbを含むはんだ材の液相温度と260℃における固相比率を調べたもので、本発明の根拠となった評価結果を示している。図４では、はんだ付け温度を360℃と従来のPb-Sn系はんだの場合と同等にしたため、液相温度はそれより30℃低い330℃以下のものを良（〇）として評価した。通常、液相温度より、約30℃プラスしたものをはんだ付け温度としている。   FIG. 4 shows the evaluation results on which the liquid phase temperature and the solid phase ratio at 260 ° C. of a solder material containing a low concentration of Sb in the Sn—Sb system are based. In FIG. 4, since the soldering temperature is 360 ° C., which is the same as that of the conventional Pb—Sn solder, the liquid phase temperature is 30 ° C., which is 330 ° C. or less. Usually, the soldering temperature is about 30 ° C higher than the liquidus temperature.

固相比率は260℃におけるはんだの溶融状態を示すもので、その値が高いほど260℃リフロー耐性があるといわれている。ここでは固相比率50％以上のものを良とした。図４から、目標とする液相温度と260℃における固相比率の双方を満足するのは、はんだ組成の比率がAgとCuを合わせて10〜35重量％で、Sb/(Sn+Sb)の重量比率が0.23〜0.38であることが分かる。かかる構成のはんだ材の硬さはHv40〜60と低く、Siチップ接合後の冷却過程や温度サイクル試験におけるチップの割れは発生しない。   The solid phase ratio indicates the molten state of the solder at 260 ° C., and it is said that the higher the value, the higher the 260 ° C. reflow resistance. Here, a solid phase ratio of 50% or more was regarded as good. From FIG. 4, the target liquid phase temperature and the solid phase ratio at 260 ° C. satisfy both the solder composition ratio of 10 to 35% by weight of Ag and Cu, and Sb / (Sn + Sb). It can be seen that the weight ratio is 0.23 to 0.38. The hardness of the solder material having such a structure is as low as Hv 40 to 60, and chip cracking does not occur in the cooling process after the Si chip bonding or in the temperature cycle test.

また、260℃リフロー耐性の効果をさらに高めるため、トランジスタパッケージの封止樹脂について検討を進め、樹脂の線膨張係数αが5ppm/℃〜9ppm/℃の樹脂でモールドすることで、260℃リフローを数回繰り返してもはんだ接合部が剥離せず、耐熱信頼性の高いトランジスタパッケージが得られることを、初めて見出した。   In addition, in order to further enhance the effect of 260 ° C reflow resistance, investigations have been made on the sealing resin for transistor packages, and 260 ° C reflow can be achieved by molding the resin with a resin whose linear expansion coefficient α is 5 ppm / ° C to 9 ppm / ° C. It has been found for the first time that a transistor package with high heat resistance and reliability can be obtained without peeling the solder joints even after repeated several times.

さらに、Siペレットの電極材や、半導体チップとチップ裏面電極に接続される第１の金属部材に対して、本発明のはんだ材にNi、P、Geの微量成分を添加することで、はんだ濡れ性をさらに向上させると良い。また、封止樹脂と第１の金属部材との剥離防止について種々検討の結果、上記トランジスタパッケージに用いられる第１の金属部材の側面部に角溝、V溝あるいはL型のザクリ部等の封止樹脂と第１の金属部材とが係合する凹部を設けて樹脂モールドすることで、樹脂界面と金属部材との剥離を効果的に防止できることを見出した。かかる構成により、はんだ接合部の熱疲労寿命が大幅に向上したトランジスタパッケージを実現することができる。   Furthermore, by adding trace components of Ni, P, and Ge to the solder material of the present invention to the Si pellet electrode material and the first metal member connected to the semiconductor chip and the chip back electrode, solder wetting It is better to further improve the nature. In addition, as a result of various studies on the prevention of peeling between the sealing resin and the first metal member, the side surface portion of the first metal member used in the transistor package is sealed with a square groove, a V groove, or an L-shaped counterbore portion. It has been found that peeling between the resin interface and the metal member can be effectively prevented by providing a recess in which the stop resin and the first metal member are engaged and resin molding. With this configuration, it is possible to realize a transistor package in which the thermal fatigue life of the solder joint is greatly improved.

本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。   Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

すなわち、本発明によれば、PbフリーのSn-Sb系で融点の低いはんだ材を用いても、260℃リフロー耐性に優れ、かつペレット接合後の冷却過程や温度サイクル試験におけるSiチップ割れが防止できる信頼性の高いトランジスタパッケージを提供することができる。   In other words, according to the present invention, even when using a Pb-free Sn-Sb solder material with a low melting point, it has excellent 260 ° C reflow resistance and prevents Si chip cracking in the cooling process and temperature cycle test after pellet bonding. A highly reliable transistor package that can be provided can be provided.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の部材には原則として同一の符号を付し、その繰り返しの説明は省略する場合がある。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof may be omitted.

図１（ａ）は、本発明のトランジスタパッケージの一実施例の構成において封止樹脂を透視した状態を示す上面図であり、（ｂ）は同じく封止樹脂を透視した状態を示す側面図である。図１において、トランジスタパッケージＡでは、トランジスタチップ１がドレイン用リード２のヘッダ３に固相温度228℃のSnSbAgCu系のはんだ材４により接着され、トランジスタチップ１のソース電極５及びゲート電極６は外部接続端子のソースリード７及びゲートリード８にAlワイヤ９により結線されている。トランジスタパッケージＡの底面はヘッダ３が露出して、配線基板に接続可能な構造になっている。   FIG. 1A is a top view showing a state in which the sealing resin is seen through in the configuration of an embodiment of the transistor package of the present invention, and FIG. 1B is a side view showing the state in which the sealing resin is seen through. is there. In FIG. 1, in a transistor package A, a transistor chip 1 is bonded to a header 3 of a drain lead 2 by a SnSbAgCu solder material 4 having a solid phase temperature of 228 ° C., and a source electrode 5 and a gate electrode 6 of the transistor chip 1 are externally connected. An Al wire 9 is connected to the source lead 7 and the gate lead 8 of the connection terminal. The bottom surface of the transistor package A has a structure in which the header 3 is exposed and can be connected to a wiring board.

トランジスタチップ１及びリード端子としてのドレイン用リード２、ソースリード７、ゲートリード８とヘッダ３の一部が、図１（ａ）、（ｂ）に示すように、封止用の樹脂１０でモールドされている。封止用の樹脂１０は、線膨張係数が50℃から150℃の温度範囲で5ppm/℃以上、9ppm/℃以下のものを用いた。樹脂には、例えば、エポキシ樹脂のような固化タイプの使用が好ましい。   As shown in FIGS. 1A and 1B, the transistor chip 1 and the drain lead 2, the source lead 7, the gate lead 8 and a part of the header 3 as lead terminals are molded with a sealing resin 10, as shown in FIGS. Has been. As the sealing resin 10, a resin having a linear expansion coefficient of 5 ppm / ° C. or more and 9 ppm / ° C. or less in a temperature range of 50 ° C. to 150 ° C. was used. For the resin, it is preferable to use a solidified type such as an epoxy resin.

かかる構成では、トランジスタチップ１とヘッダ３とをリフロー温度の260℃より低いはんだ材４で接合しているが、低熱膨張の樹脂１０でモールドしているので、ヘッダ３と樹脂１０との界面で剥離は生じない。したがって、260℃のリフロー耐性のあるトランジスタパッケージを提供することができる。   In such a configuration, the transistor chip 1 and the header 3 are joined by the solder material 4 having a reflow temperature lower than 260 ° C. However, since it is molded by the resin 10 having a low thermal expansion, the interface between the header 3 and the resin 10 is used. No peeling occurs. Therefore, a transistor package having a reflow resistance of 260 ° C. can be provided.

また、用いたはんだ合金は硬度がHv 40〜60であることから、接合後の冷却や温度サイクル試験での熱歪によるSiチップ割れ等の損傷は発生しない。そのため、トランジスタパッケージＡにおけるはんだ接合部の熱疲労寿命を大幅に向上させることができる。   Moreover, since the used solder alloy has a hardness of Hv 40 to 60, damage such as Si chip cracking due to cooling after joining and thermal strain in a temperature cycle test does not occur. Therefore, the thermal fatigue life of the solder joint in the transistor package A can be significantly improved.

図２は、本発明のトランジスタチップ１とヘッダ３との接合構造の一実施例を示す断面図である。図２において、トランジスタチップ１の裏面電極のTi膜１１／Ni膜１２は、ヘッダ３のCuリード１３に形成されたNiめっき膜１４に、はんだ材４としてのSnSbAgCu系合金を接合材として使用することで接合された構造となっている。図に示す場合は、トランジスタチップ１の大きさは4×5mmで、厚さは0.2mmt、Cuリード１３の厚さは0.2mmtで、Niめっき１４の厚さは5μmである。ここで、はんだ材４はヘッダ３へのはんだ濡れ性向上のため、SnSbAgCu系合金にNi、P、Ge等を微量添加しても良い。   FIG. 2 is a cross-sectional view showing an embodiment of the junction structure between the transistor chip 1 and the header 3 of the present invention. In FIG. 2, the Ti film 11 / Ni film 12 of the back electrode of the transistor chip 1 uses a SnSbAgCu alloy as the solder material 4 as a bonding material for the Ni plating film 14 formed on the Cu lead 13 of the header 3. It becomes the structure joined by. In the case shown in the figure, the size of the transistor chip 1 is 4 × 5 mm, the thickness is 0.2 mmt, the thickness of the Cu lead 13 is 0.2 mmt, and the thickness of the Ni plating 14 is 5 μm. Here, the solder material 4 may add a small amount of Ni, P, Ge or the like to the SnSbAgCu-based alloy in order to improve the solder wettability to the header 3.

図３は、図２の接合構造を得るのに用いたトランジスタチップ１の断面構造を示す。図３において、Si基板１５の片面にはトランジスタ素子で構成された回路領域１６が形成され、他方の面にはペレット接合のための裏面電極膜としてSi側からTi膜１１／Ni膜１２／Au膜１７の多層膜が形成されている。   FIG. 3 shows a cross-sectional structure of the transistor chip 1 used to obtain the junction structure of FIG. In FIG. 3, a circuit region 16 composed of transistor elements is formed on one side of a Si substrate 15, and a Ti film 11 / Ni film 12 / Au is formed on the other side as a back electrode film for pellet bonding from the Si side. A multilayer film of the film 17 is formed.

次に、上記構成の本発明に係わるトランジスタパッケージＡにおけるはんだ材４等の接合材としての適切な接合材組成について検討した結果を説明する。図５は、接合材のSb量及びAg、Cuの添加量を変えたはんだ材でトランジスタパッケージＡを作製し、Siチップ割れ及び260℃リフロー耐性を調べた結果である。また、はんだ材の硬さ及び260℃における固相比率を調べた結果も併記した。   Next, a description will be given of the result of study on an appropriate bonding material composition as a bonding material such as the solder material 4 in the transistor package A according to the present invention having the above-described configuration. FIG. 5 shows the results of examining the Si chip cracking and 260 ° C. reflow resistance by fabricating a transistor package A using a solder material in which the amount of Sb and the addition of Ag and Cu were changed. The results of examining the hardness of the solder material and the solid phase ratio at 260 ° C. are also shown.

高濃度のSbを含むはんだ材（Sb32.5〜35wt％）は、260℃の固相比率（90％、100％）は満足するが、硬さがHv81、Hv108付近にあり、Siチップのはんだ付け後にチップ割れが生じる。しかし、260℃リフロー耐性には問題が無い。一方、低濃度のSbを含むはんだ材（Sb17.5〜25wt％）は、はんだ付け後にSiチップ割れは生じないが、260℃における固相率が小さいために、リフロー耐性に問題がある。   Solder material containing high-concentration Sb (Sb32.5-35wt%) satisfies the solid phase ratio (90%, 100%) at 260 ° C, but the hardness is around Hv81 and Hv108. Chip cracking occurs after attaching. However, there is no problem with 260 ° C reflow resistance. On the other hand, the solder material containing low concentration of Sb (Sb 17.5 to 25 wt%) does not cause Si chip cracking after soldering, but has a problem in reflow resistance because of its low solid phase rate at 260 ° C.

そこで、本発明者らはSiチップ割れ防止と260℃リフロー耐性の双方を満足するはんだ材及びトランジスタパッケージに用いる樹脂について検討した。Siチップ割れ防止には、上記の如く、硬度が低い低濃度のSbを含むはんだ材であることが望ましい。しかし、かかる低濃度のSbを含むはんだ材は、リフロー耐性に問題があるが、本発明者は、かかるリフロー耐性の問題は、使用する樹脂の熱膨張と大いに関係があると着眼し、熱膨張を抑制することでリフロー耐性の問題点が解決できないかと考えた。   Therefore, the present inventors examined a solder material that satisfies both the prevention of Si chip cracking and 260 ° C. reflow resistance and a resin used for a transistor package. In order to prevent Si chip cracking, as described above, it is desirable to use a solder material containing a low concentration of Sb with low hardness. However, the solder material containing such a low concentration of Sb has a problem in the reflow resistance, but the present inventor has noticed that the problem of the reflow resistance is greatly related to the thermal expansion of the resin used. We thought that the problem of reflow resistance could be solved by suppressing the above.

Sbを低濃度に含む種々の組成のはんだ材に対して、種々の線膨張係数αを有する樹脂を用いて樹脂封止し、それぞれについてチップ割れ、リフロー耐性を検討した。その結果、従来の樹脂より線膨張係数αが低い樹脂を使用することで、リフロー耐性を獲得することができることを見出した。すなわち、図５に示すように、線膨張係数αが5ppm/℃以上、9ppm/℃以下の樹脂を用いることによって十分なリフロー耐性が得られ、260℃のリフロー試験で、リードフレームと樹脂との接合界面に剥離は生じなかった。線膨張係数αが10〜15ppm/℃の従来の封止樹脂では、図５に示すように、いずれのはんだ材を用いても接合界面に剥離が生じた。   With respect to solder materials having various compositions containing Sb at a low concentration, resin sealing was performed using resins having various linear expansion coefficients α, and chip cracking and reflow resistance were examined for each. As a result, it was found that reflow resistance can be obtained by using a resin having a lower linear expansion coefficient α than conventional resins. That is, as shown in FIG. 5, sufficient reflow resistance is obtained by using a resin having a linear expansion coefficient α of 5 ppm / ° C. or more and 9 ppm / ° C. or less. No peeling occurred at the bonding interface. With a conventional sealing resin having a linear expansion coefficient α of 10 to 15 ppm / ° C., as shown in FIG. 5, even if any solder material was used, peeling occurred at the joint interface.

使用する樹脂の線膨張係数αが5ppm/℃未満では、樹脂の流動性が極端に悪くなり、トランジスタパッケージとしての成型が難しくなる。一方、線膨張係数αが10ppm/℃を越える場合には、従来の如く、リードフレームと樹脂との接合界面が剥離してしまう。低濃度のSbを含むはんだ材をトランジスタパッケージに用いる場合には、線膨張係数αが5ppm/℃以上、9ppm/℃以下の樹脂を用いることが最適であることが、本発明者の実験から初めて分かった。   When the linear expansion coefficient α of the resin to be used is less than 5 ppm / ° C., the fluidity of the resin becomes extremely poor, and it becomes difficult to mold as a transistor package. On the other hand, when the linear expansion coefficient α exceeds 10 ppm / ° C., the bonding interface between the lead frame and the resin is peeled off as in the prior art. When using a solder material containing a low concentration of Sb for a transistor package, it is the first time from the inventors' experiments that it is optimal to use a resin having a linear expansion coefficient α of 5 ppm / ° C or more and 9 ppm / ° C or less. I understood.

図６は、トランジスタチップ１の金属電極構造が異なる本発明に係わるトランジスタパッケージＡの変形例を示す断面図である。図６において、トランジスタチップ１の裏面電極のNi膜１８／Ti膜１９は、ヘッダのCuリード１３に形成されたNiめっき膜１４にSnSbAgCu合金４によって接合された構造となっている。トランジスタチップ１の形状、Cuリード１３の厚さ及びNiめっき膜１４の厚さは図２の場合と同じである。   FIG. 6 is a cross-sectional view showing a modification of the transistor package A according to the present invention in which the metal electrode structure of the transistor chip 1 is different. In FIG. 6, the Ni film 18 / Ti film 19 on the back electrode of the transistor chip 1 has a structure in which it is joined to the Ni plating film 14 formed on the Cu lead 13 of the header by the SnSbAgCu alloy 4. The shape of the transistor chip 1, the thickness of the Cu lead 13, and the thickness of the Ni plating film 14 are the same as those in FIG.

図７は、図６に示す接合構造を得るのに用いたトランジスタチップ１の断面構造を示す。図７において、Si基板２１の片面にはトランジスタ素子で構成された回路領域２２が形成され、他方の面にはペレット接合のための裏面電極膜としてSi側からNi膜１８／Ti膜１９／Ni膜２３／Ag膜２４の多層膜が形成されている。かかる構成によれば、図２及び図３に示す場合と同様に、耐熱性、高温信頼性、温度サイクル信頼性に優れたPbフリーのトランジスタパッケージを提供することができる。   FIG. 7 shows a cross-sectional structure of the transistor chip 1 used to obtain the junction structure shown in FIG. In FIG. 7, a circuit region 22 composed of transistor elements is formed on one side of a Si substrate 21, and a Ni film 18 / Ti film 19 / Ni is formed on the other side as a back electrode film for pellet bonding from the Si side. A multilayer film of film 23 / Ag film 24 is formed. According to such a configuration, a Pb-free transistor package having excellent heat resistance, high temperature reliability, and temperature cycle reliability can be provided, as in the case shown in FIGS.

図８は、図２及び図６の接合構造を実現するための接合方法を示す説明図である。接合は、水素を含む還元雰囲気が可能なコンベア炉２５で行った。接合工程では、まずリードフレームのNiめっき面にSnSbAgCu合金のワイヤ２６から所定量をチップサイズより小さい領域に溶融させて供給する。その溶融した合金上にチップの裏面電極を軽く一度押し付け、その後荷重を開放する方式でチップを搭載する。合金はチップのある領域だけ濡れ拡がって、フィレットを形成して接合される。SnSbAgCu合金は固相温度228℃のものを用いた。かかる構成では、ヘッダにCu合金にNiめっきを施したものを用いたが、Cu合金そのものにはんだ付けしても何ら差し支えなく、同様な効果が得られる。   FIG. 8 is an explanatory view showing a joining method for realizing the joining structure of FIGS. 2 and 6. The joining was performed in a conveyor furnace 25 capable of a reducing atmosphere containing hydrogen. In the bonding process, first, a predetermined amount is supplied from the SnSbAgCu alloy wire 26 to the Ni-plated surface of the lead frame in a region smaller than the chip size. The chip is mounted by pressing the back electrode of the chip once onto the molten alloy and then releasing the load. The alloy wets and spreads only in certain areas of the chip, forming a fillet and joining. SnSbAgCu alloy with a solid phase temperature of 228 ° C was used. In such a configuration, a Cu alloy with a Ni plating applied to a Cu alloy is used, but there is no problem even if the Cu alloy itself is soldered, and the same effect can be obtained.

図９（ａ）は、本発明に係わるトランジスタパッケージＡの構造の他の変形例を樹脂を透視した状態で示す上面図であり、（ｂ）は樹脂を透視した状態を示す側面図である。図９において、トランジスタチップ１はSnSbAgCu系及びSnSbAgCuNi系のはんだ材４を接合材として用いることによりヘッダ３に接合されている。   FIG. 9A is a top view showing another modification of the structure of the transistor package A according to the present invention in a state where the resin is seen through, and FIG. 9B is a side view showing the state where the resin is seen through. In FIG. 9, the transistor chip 1 is joined to the header 3 by using a SnSbAgCu-based and SnSbAgCuNi-based solder material 4 as a bonding material.

図９に示す構成は、図１の構成と異なり、ヘッダ３の側面に角溝２７ａ等の凹部が設けられている。角溝２７ａは、ヘッダ３と封止用の樹脂１０とが係合して剥離の防止効果を発揮するように設けた剥離防止部２７として機能する。剥離防止部２７の凹部の構成は、角溝２７ａに限定する必要はなく、例えば、図示はしないが、V溝あるいはL型にしてザクリ加工しても同じ効果が得られる。この場合でも、モールド用の樹脂１０には熱膨張係数5ppm/℃〜9ppm/℃のものを用いた。樹脂形態は前述の如く、例えば、エポキシ樹脂のような固化タイプが良い。   The configuration shown in FIG. 9 is different from the configuration of FIG. 1 in that a concave portion such as a square groove 27 a is provided on the side surface of the header 3. The square groove 27a functions as a peeling prevention portion 27 provided so that the header 3 and the sealing resin 10 are engaged to exhibit a peeling prevention effect. The configuration of the concave portion of the peeling preventing portion 27 is not necessarily limited to the square groove 27a. For example, although not shown, the same effect can be obtained even if a V-groove or an L-shape is counterbored. Even in this case, a resin having a thermal expansion coefficient of 5 ppm / ° C. to 9 ppm / ° C. was used as the molding resin 10. As described above, the resin form is preferably a solidified type such as an epoxy resin.

図１０は、本発明に係わるトランジスタパッケージＡの他の変形例の断面図を示す。図１０において、トランジスタチップ１はAl電極２８と貴金属めっき２９が施されたリード端子３０はAuバンプ３１によって強固に接合されている。トランジスタチップ１の裏面電極とダイ端子３２は、SnSbAgCu系またはSnSbAgCuNi系のはんだ材４を接合材として使用することによって接着されている。ダイ端子３２はCuヘッダにNiめっきされた構造で、Cuヘッダの周囲には封止用の樹脂１０へのアンカー効果が働くように係合部として機能する剥離防止部３３としての角溝３３ａが設けられている。リード端子はモールドした樹脂１０で構成される樹脂筐体１０ａの片側サイドから取り出されている。   FIG. 10 shows a sectional view of another modification of the transistor package A according to the present invention. In FIG. 10, the transistor chip 1 has an Al electrode 28 and a lead terminal 30 on which noble metal plating 29 is applied, and is firmly joined by an Au bump 31. The back electrode of the transistor chip 1 and the die terminal 32 are bonded together by using a SnSbAgCu-based or SnSbAgCuNi-based solder material 4 as a bonding material. The die terminal 32 has a structure in which a Cu header is plated with Ni, and a square groove 33a as a separation preventing portion 33 that functions as an engaging portion so that an anchoring effect to the sealing resin 10 works around the Cu header. Is provided. The lead terminal is taken out from one side of the resin casing 10a made of the molded resin 10.

また、ダイ端子３２は樹脂筐体１０ａの底面に露出しており、ダイ端子３２の下面（配線基板上の接続端子との接続面）と曲げ加工されたソース及びゲート用リード端子の下面（同接続面）は同じ高さになるように加工されている。樹脂１０には熱膨張係数5ppm/℃〜9ppm/℃のものを用い、樹脂形態はエポキシ樹脂のような固化タイプが良い。   The die terminal 32 is exposed on the bottom surface of the resin casing 10a, and the bottom surface of the die terminal 32 (the connection surface with the connection terminal on the wiring board) and the bottom surface of the bent source and gate lead terminals (same as the above). The connection surface is processed to have the same height. A resin 10 having a thermal expansion coefficient of 5 ppm / ° C. to 9 ppm / ° C. is used, and the resin form is preferably a solidified type such as an epoxy resin.

かかる構成によれば、図１の場合と同様の効果が得られる。また、ダイ端子３２の側面には、樹脂１０が食い込む形状の剥離防止部３３の加工を施してあるため、樹脂封止に際しては、モールド成型後の樹脂１０が冷却されて収縮する際に、樹脂１０の収縮力でダイ端子３２をチップ裏面に押し付けることができ、かかる剥離防止部３３の構成を有しない構成とは異なり、格段に信頼性のあるトランジスタパッケージを提供することができる。   According to such a configuration, the same effect as in the case of FIG. 1 can be obtained. Further, since the side surface of the die terminal 32 is processed with the peeling preventing portion 33 in which the resin 10 bites in, the resin 10 is sealed when the resin 10 after molding is cooled and contracted. The die terminal 32 can be pressed against the back surface of the chip with a contraction force of 10, and unlike the configuration without the configuration of the peeling preventing portion 33, a transistor package with much higher reliability can be provided.

図１１は、本発明に係わるパワー半導体モジュールの断面構造の一実施例を示す。図１１において、Siチップに構成されたトランジスタチップ１は、SnSbAgCu系またはSnSbAgCuNi系のはんだ材４を接合材として使用することによりセラミック基板３４の上に形成された導体パターン３５に接合されている。Siチップの裏面にはTiまたはTi/Ni層が形成されており、導体パターン表面にはNiめっきが施されている。Siチップの回路面側の電極はAlのワイヤ３６、３７によって導体パターン３５に電気的に接続されている。   FIG. 11 shows an embodiment of a cross-sectional structure of a power semiconductor module according to the present invention. In FIG. 11, the transistor chip 1 configured as a Si chip is bonded to a conductor pattern 35 formed on a ceramic substrate 34 by using a SnSbAgCu-based or SnSbAgCuNi-based solder material 4 as a bonding material. A Ti or Ti / Ni layer is formed on the back surface of the Si chip, and Ni plating is applied to the conductor pattern surface. The electrodes on the circuit surface side of the Si chip are electrically connected to the conductor pattern 35 by Al wires 36 and 37.

裏面にメタライズが施されたセラミック基板３４、Pbフリーの低融点はんだ材３８によって金属の放熱板３９にはんだ接合されている。低融点はんだ材には、SnAg系、SnAgCu系、SnZn系、SnBi系などを用いることが可能である。モジュール全体は樹脂１０で覆われて保護されている。樹脂１０の形態は、エポキシ樹脂のような固化タイプが良い。セラミック基板３４の周囲にはモールドした樹脂１０へのアンカー効果が働くように角溝４０ａが、剥離防止部４０として設けられている。   The metal substrate is soldered to a metal heat sink 39 by a ceramic substrate 34 having a metallized back surface and a Pb-free low melting point solder material 38. As the low melting point solder material, SnAg, SnAgCu, SnZn, SnBi, or the like can be used. The entire module is covered and protected with resin 10. The form of the resin 10 is preferably a solidified type such as an epoxy resin. Around the ceramic substrate 34, a square groove 40a is provided as a peeling prevention part 40 so that an anchor effect to the molded resin 10 works.

図１１に示す構成によれば、パワー半導体モジュールのPbフリー化が可能となる。また、セラミック基板３４と放熱板３９の接合にSnAgCu系はんだを用い、樹脂１０に耐熱エポキシタイプを採用すれば、耐熱性に優れたパワー半導体モジュールを提供することができる。   According to the configuration shown in FIG. 11, the power semiconductor module can be made Pb-free. Further, if SnAgCu solder is used for joining the ceramic substrate 34 and the heat sink 39 and a heat-resistant epoxy type is adopted for the resin 10, a power semiconductor module having excellent heat resistance can be provided.

以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

本発明は、半導体チップをPbフリーのSn-Sb系の接合材で金属部材に搭載したトランジスタパッケージに有効に利用することができる。   The present invention can be effectively used for a transistor package in which a semiconductor chip is mounted on a metal member with a Pb-free Sn—Sb-based bonding material.

（ａ）は本発明のトランジスタパッケージの一実施例の構成において封止樹脂を透視した状態を示す上面図であり、（ｂ）は同じく封止樹脂を透視した側面図である。(A) is the top view which shows the state which saw through sealing resin in the structure of one Example of the transistor package of this invention, (b) is the side view which also saw through sealing resin similarly. 本発明のトランジスタパッケージにおけるトランジスタチップとヘッダとの接合構造の一実施例を示す断面図である。It is sectional drawing which shows one Example of the junction structure of the transistor chip | tip and header in the transistor package of this invention. 図２に示す接合構造におけるトランジスタチップの一実施例の断面構成を示す断面図である。FIG. 3 is a cross-sectional view illustrating a cross-sectional configuration of an example of a transistor chip in the junction structure illustrated in FIG. 2. 本発明で用いるはんだ材の物性を示す図である。It is a figure which shows the physical property of the solder material used by this invention. 本発明で用いるはんだ材と樹脂の線膨張係数との適正な組合せ関係を示す図である。It is a figure which shows the appropriate combination relation of the solder material used by this invention, and the linear expansion coefficient of resin. 本発明のトランジスタパッケージにおける接合構造の一変形例を示す断面図である。It is sectional drawing which shows the modification of the junction structure in the transistor package of this invention. 図６に示す接合構造におけるトランジスタチップの一実施例の断面構成を示す断面図である。It is sectional drawing which shows the cross-sectional structure of one Example of the transistor chip in the junction structure shown in FIG. 本発明で採用する接合構造における接合方法の一実施例を示す説明図である。It is explanatory drawing which shows one Example of the joining method in the joining structure employ | adopted by this invention. （ａ）は本発明のトランジスタパッケージの一変形例の構成において封止樹脂を透視した状態を示す上面図であり、（ｂ）は同じく封止樹脂を透視した側面図である。(A) is the top view which shows the state which saw through sealing resin in the structure of the modification of the transistor package of this invention, (b) is the side view which also saw through sealing resin similarly. 本発明のトランジスタパッケージの一変形例の構成を、封止樹脂を透視した状態で示す側面図である。It is a side view which shows the structure of the modification of the transistor package of this invention in the state which saw through sealing resin. 本発明のトランジスタパッケージの一変形例の構成を、封止樹脂を透視した状態で示す側面図である。It is a side view which shows the structure of the modification of the transistor package of this invention in the state which saw through sealing resin.

符号の説明Explanation of symbols

１…トランジスタチップ、２…ドレイン用リード、３…ヘッダ、４…はんだ材、５…ソース電極、６…ゲート電極、７…ソースリード、８…ゲートリード、９…Alワイヤ、１０…樹脂、１０ａ…樹脂筐体、１１…Ti膜、１２…Ni膜、１３…Cuリード、１４…Niめっき膜、１５…Si基板、１６…回路領域、１７…Au膜、１８…Ni膜、１９…Ti膜、２１…Si基板、２２…回路領域、２３…Ni膜、２４…Ag膜、２５…コンベア炉、２６…ワイヤ、２７…剥離防止部、２７ａ…角溝、２８…Al電極、２９…貴金属めっき、３０…リード端子、３１…Auバンプ、３２…ダイ端子、３３…剥離防止部、３３ａ…角溝、３４…セラミック基板、３５…導体パターン、３６…ワイヤ、３７…ワイヤ、３８…はんだ材、３９…放熱板、４０…剥離防止部、４０ａ…角溝、Ａ…トランジスタパッケージ。   DESCRIPTION OF SYMBOLS 1 ... Transistor chip, 2 ... Drain lead, 3 ... Header, 4 ... Solder material, 5 ... Source electrode, 6 ... Gate electrode, 7 ... Source lead, 8 ... Gate lead, 9 ... Al wire, 10 ... Resin, 10a ... Resin housing, 11 ... Ti film, 12 ... Ni film, 13 ... Cu lead, 14 ... Ni plating film, 15 ... Si substrate, 16 ... Circuit region, 17 ... Au film, 18 ... Ni film, 19 ... Ti film 21 ... Si substrate, 22 ... Circuit region, 23 ... Ni film, 24 ... Ag film, 25 ... Conveyor furnace, 26 ... Wire, 27 ... Peeling prevention part, 27a ... Square groove, 28 ... Al electrode, 29 ... Precious metal plating 30 ... Lead terminal, 31 ... Au bump, 32 ... Die terminal, 33 ... Detachment prevention part, 33a ... Square groove, 34 ... Ceramic substrate, 35 ... Conductor pattern, 36 ... Wire, 37 ... Wire, 38 ... Solder material, 39 ... Radiating plate, 40 ... Peeling prevention part, 40a ... Square groove, A ... transistor package.

Claims (5)

半導体チップとチップ裏面電極に接続される第１の金属部材と、チップ上回路形成面の主電流電極に電気的に接続される第２の金属部材と、制御用電極に電気的に接続される第３の金属部材とを有し、前記金属部材の少なくとも一部が封止樹脂で覆われているトランジスタパッケージであって、
前記半導体チップと前記第１の金属部材とを接合する接合材は、固相温度225℃以上、245℃以下のSn、Sb、Ag、Cuを主成分とする合金であり、
前記合金には、AgとCuとが合わせて10〜35重量％、SbとSnとがSb/(Sn+Sb)の重量比率が0.23〜0.38で含まれており、
前記半導体チップと前記金属部材の少なくとも一部が線膨張係数5ppm/℃〜9ppm/℃の前記封止樹脂で封止されていることを特徴とするトランジスタパッケージ。 A first metal member connected to the semiconductor chip and the chip back surface electrode, a second metal member electrically connected to the main current electrode on the circuit formation surface on the chip, and electrically connected to the control electrode And a third metal member, wherein at least a part of the metal member is covered with a sealing resin,
The bonding material for bonding the semiconductor chip and the first metal member is an alloy mainly composed of Sn, Sb, Ag, and Cu having a solid phase temperature of 225 ° C. or higher and 245 ° C. or lower,
The alloy contains 10 to 35% by weight of Ag and Cu, Sb and Sn are included in a weight ratio of Sb / (Sn + Sb) of 0.23 to 0.38,
A transistor package, wherein at least a part of the semiconductor chip and the metal member is sealed with the sealing resin having a linear expansion coefficient of 5 ppm / ° C. to 9 ppm / ° C. 請求項１記載のトランジスタパッケージにおいて、
前記接合材による接合部分は、(NiまたはTi)/前記接合材/(NiまたはCu)で構成されていることを特徴とするトランジスタパッケージ。 The transistor package of claim 1, wherein
A transistor package characterized in that a bonding portion by the bonding material is constituted by (Ni or Ti) / the bonding material / (Ni or Cu). 請求項１または２記載のトランジスタパッケージにおいて、
前記接合材には、微量成分としてNi、P、Geが含まれることを特徴とするトランジスタパッケージ。 The transistor package according to claim 1 or 2,
A transistor package characterized in that the bonding material contains Ni, P, and Ge as trace components. 請求項１または２記載のトランジスタパッケージにおいて、
前記第１の金属部材の側面に、前記封止樹脂との剥離を防止する剥離防止部が設けられていることを特徴とするトランジスタパッケージ。 The transistor package according to claim 1 or 2,
A transistor package, wherein a side surface of the first metal member is provided with a peeling preventing portion for preventing peeling from the sealing resin. 請求項４記載のトランジスタパッケージにおいて、
前記剥離防止部は、前記第１の金属部材の側面に前記封止樹脂が係合する溝等の凹部に形成されていることを特徴とするトランジスタパッケージ。 The transistor package according to claim 4, wherein
The transistor package, wherein the peeling preventing portion is formed in a concave portion such as a groove that engages with the sealing resin on a side surface of the first metal member.
JP2004153305A 2004-05-24 2004-05-24 Transistor package Pending JP2005340268A (en)

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