JP2005235978A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable a yield to be improved and to enable reliability to be improved by preventing a bonded insulating films from being separated by raising the adhesiveness between the insulating films used for a multilayer wiring structure. <P>SOLUTION: In a semiconductor device 1 having the multilayer wiring structure on a substrate 11, the insulating film for electrically insulating between the wiring layers of the multilayer wiring structure is made of a laminate of the first insulating film 21 and the second insulating film 22. Between the first insulating film 21 and the second insulating film 22, a chemical which raises the adhesiveness of the first insulating film 21 and the second insulating film 22 is applied on the periphery of the first insulating film 21. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a semiconductor device and a method of manufacturing the same, in which peeling of an insulating film does not occur at the time of chemical mechanical polishing (hereinafter referred to as CMP) in which copper as a wiring material is embedded in a wiring groove or via hole. The present invention relates to a semiconductor device manufactured by:

  In the manufacturing method of a semiconductor device having a multilayer wiring structure, an insulating film that electrically insulates between wirings is formed in a structure in which two or more kinds of insulating films are stacked. In particular, in order to reduce the value of dielectric constant (k) of the insulating film, various insulating films having weaker adhesion than those of conventionally used silicon oxide films and silicon nitride films are used.

  As a technique for manufacturing the multilayer wiring structure, there is disclosed a so-called dual damascene method in which copper serving as a conductive material is embedded in grooves and holes formed in an insulating layer (see, for example, Patent Document 1). The insulating layer disclosed in Patent Document 1 has a laminated structure, and in FIG. 3 and Paragraph No. 0032 of Patent Document 1, “dielectric insulating layers 2, 3 and 4 are attached to form a high conductivity interconnect. A pair of insulating layers can be deposited by ECR, sputtering, plasma CVD, CVD, spin coating, or any combination of these methods, for example, these insulating layers can be polyimide, silicon nitride, It can be made of alumina, silicon dioxide, phosphosilicate glass, yttrium oxide, magnesium oxide, airgel, or any combination of these materials. "

  Also, it has a laminated structure of an insulating film of a wiring (line) layer and an insulating film of a via layer, the insulating film of the via layer is a laminated film of a TEOS oxide film / organic polymer spin-on material film, and insulation of the wiring layer A semiconductor device in which the film is a laminated film of a TEOS oxide film / organic polymer spin-on material film is disclosed (for example, see Non-Patent Document 1).

  Also disclosed is a semiconductor device having a laminated structure of an insulating film of a wiring (line) layer and an insulating film of a via layer, and further having an insulating film of a wiring layer having a laminated structure (see, for example, Patent Document 2). ). Specifically, as the insulating film for the via layer, the passivation film 111 is formed of a silicon nitride film, the first interlayer insulating film 112 is formed of a silicon oxide film thereon, and the insulating film of the wiring layer is It is disclosed that the second interlayer insulating film 114 is formed of an organic polymer and the mask layer 115 is formed of a silicon oxide film.

  When such thin films having low adhesion are used in a stacked manner, there has been a problem that peeling occurs in the mechanical force in the semiconductor device manufacturing process or the thermal process. Specifically, as a process in which adhesion is a problem, a CMP process for planarizing an oxide film, a CMP process for forming a trench wiring structure in which wiring is embedded in a trench, and a low dielectric constant film ( Among those skilled in the semiconductor process technology, there are an annealing step for crosslinking (also referred to as a low-k film), a copper film annealing step, a packaging step, and the like.

Japanese Patent No. 3057054 JP 2001-44189 A “Organic Low-k / Cu integration technology based on CD control” written by Yasutaka Nishioka, sponsored by Global Net Co., Ltd. “Basic theory and wiring application technology of Low-k film damascene process for k <2.5” p. 4-1-1 to 4-1-8, February 20, 2002

  The problem to be solved is that the insulating film is peeled off in the CMP process. In particular, it is impossible to prevent the peeling of the insulating film near the edge of the wafer or the edge of the insulating film where pressure is concentrated during CMP.

  The first semiconductor device of the present invention is a semiconductor device having a multilayer wiring structure on a substrate, and the insulating film that electrically insulates the wiring layers of the multilayer wiring structure is formed by laminating a first insulating film and a second insulating film. A chemical solution for improving the adhesion between the first insulating film and the second insulating film is applied between the first insulating film and the second insulating film on the periphery of the first insulating film. The main feature is that the chemical treatment area is formed.

  The second semiconductor device of the present invention is a semiconductor device having a multilayer wiring structure on a substrate, and the insulating films that electrically insulate the wiring layers of the multilayer wiring structure are a first insulating film, a second insulating film, and a second insulating film. And an edge of the second insulating film is formed so as to be inside the edge of the third insulating film, and between the first insulating film and the third insulating film, and Between the second insulating film and the third insulating film, the first insulating film, the third insulating film, and the second on the peripheral portion of the first insulating film and on the peripheral portion of the second insulating film. The main feature is that a chemical solution treatment region is formed in which a chemical solution for improving the adhesion between the insulating film and the third insulating film is applied.

  A first manufacturing method of a semiconductor device of the present invention is a manufacturing method of a semiconductor device having a multilayer wiring structure on a substrate, and the insulating film that electrically insulates the wiring layers of the multilayer wiring structure is a first insulating film. The first insulating film and the first insulating film are formed on the periphery of the first insulating film after forming the first insulating film and before forming the second insulating film. 2 The main feature is that it includes a step of applying a chemical solution that enhances adhesion to the insulating film.

  A second manufacturing method of a semiconductor device of the present invention is a manufacturing method of a semiconductor device having a multilayer wiring structure on a substrate, and the insulating film that electrically insulates the wiring layers of the multilayer wiring structure is the same as the first insulating film. After the second insulating film and the third insulating film are laminated, the edge of the second insulating film is formed to be inside the edge of the third insulating film, and the second insulating film is formed. Before forming the third insulating film, the first insulating film, the second insulating film, and the third insulating film are formed on the peripheral portion of the first insulating film and on the peripheral portion of the second insulating film. The main feature is that it includes a step of applying a chemical solution for improving the adhesion of the material.

  In the first semiconductor device of the present invention, the first insulating film and the second insulating film are formed on the periphery of the first insulating film between the first insulating film and the second insulating film constituting the insulating film between the wiring layers. Since the chemical | medical solution which improves adhesiveness of this is applied, the adhesiveness of the 2nd insulating film is improved with respect to the 1st insulating film. For this reason, since the second insulating film is not peeled off, there is an advantage that the yield can be improved and the reliability of the insulating film can be improved.

  According to the second semiconductor device of the present invention, the periphery of the first insulating film is between the first insulating film and the third insulating film constituting the insulating film between the wiring layers and between the second insulating film and the third insulating film. Since the chemical solution for improving the adhesion between the first insulating film and the third insulating film and the second insulating film and the third insulating film is applied on the peripheral portion of the first insulating film and the second insulating film. The adhesion of the third insulating film to the two insulating films is improved. For this reason, since the third insulating film is not peeled off, there is an advantage that the yield can be improved and the reliability of the insulating film can be improved.

  According to the first method of manufacturing a semiconductor device of the present invention, the first insulating film is formed on the periphery of the first insulating film after forming the first insulating film constituting the insulating film between the wiring layers and before forming the second insulating film. Since the step of applying a chemical solution for improving the adhesion between the insulating film and the second insulating film is provided, the adhesion of the second insulating film to the first insulating film can be enhanced at the peripheral portion. After the film is formed, even if, for example, a CMP process is performed and a load in a direction substantially parallel to the surface of the first insulating film is applied between the first and second insulating films, the second insulating film is formed from the first insulating film. There is an advantage that peeling can be prevented. In particular, the adhesion at the periphery of the film where film peeling is likely to occur is enhanced, which is effective in preventing film peeling. Therefore, the yield can be improved and the reliability of the insulating film can be improved.

  According to the second method of manufacturing a semiconductor device of the present invention, the second insulating film constituting the insulating film between the wiring layers is formed and then the second insulating film is formed on the peripheral portion of the first insulating film and before the second insulating film is formed. Since the chemical | medical solution which improves the adhesiveness of a 1st insulating film and a 2nd insulating film, and a 3rd insulating film is apply | coated on the peripheral part of an insulating film, the 3rd insulating film with respect to a 1st insulating film and a 2nd insulating film Therefore, after forming the third insulating film, for example, a CMP process is performed so that the surface of the first insulating film is between the first and second insulating films and the second insulating film. There is an advantage that the third insulating film can be prevented from peeling off from the first and second insulating films even when a load in a direction substantially parallel to the first and second insulating films is applied. In particular, the adhesion at the periphery of the film where film peeling is likely to occur is enhanced, which is effective in preventing film peeling. Therefore, the yield can be improved and the reliability of the insulating film can be improved.

  By applying a chemical solution that improves adhesion to the periphery of the insulating film for the purpose of preventing the peeling of the insulating film near the edge of the wafer or the edge of the insulating film where pressure is concentrated during CMP, The film was improved to prevent film peeling during the CMP process.

  One embodiment of the semiconductor device of the present invention will be described with reference to the schematic sectional view of FIG.

  As shown in FIG. 1, an insulating film 12 is formed on a substrate (wafer) 11 on which transistors, wirings, etc. (not shown) are formed. For example, a silicon substrate is used as the substrate 11. The insulating film 12 is made of a silicon oxide film and has a thickness of, for example, 500 nm. On the insulating film 12, a first insulating film 21 constituting an insulating film between wiring layers is formed. Here, the first insulating film 21 is formed of a SiC-based film. For example, a SiOC film or a film containing nitrogen or hydrogen in the SiOC film. The first insulating film 21 is formed to a thickness of 200 nm by, for example, plasma CVD.

  A chemical treatment is performed on the peripheral portion of the first insulating film 21 (for example, a range within 4 mm from the outer periphery of the wafer). This chemical treatment is a treatment for improving the adhesion with the second insulating film 22 formed on the first insulating film 21, and is a chemical for enhancing the adhesion on the peripheral portion of the first insulating film 21. Is a process of coating. The chemical solution may be any chemical solution having an action of oxidizing the surface of the first insulating film 21, in other words, an action of further promoting the oxidation of the surface of the first insulating film 21. Such a chemical solution includes an oxidizing agent, and for example, hydrogen peroxide water can be used. Therefore, a chemical treatment region 33 that is oxidized from the surface of the other first insulating film 21 is formed in an annular shape around the first insulating film 21.

  Further, a second insulating film 22 constituting an insulating film between the wiring layers is formed on the first insulating film 21. For example, an organic film is used for the second insulating film 22. As this organic film, a polyaryl ether film can be used. Examples of the polyaryl ether film include SiLK-J (Dow Chemical Co.), and other examples include p-SiLK manufactured by Dow Chemical, FLARE manufactured by Allied Signal, VE manufactured by Schumacker, and the like. Other polyaryl ether films may be used. The film thickness of the organic film was set to 100 nm, for example.

The edge portion of the second insulating film 22 may be removed as illustrated. The edge removal of the second insulating film 22 is performed in order to remove the second insulating film 22 on the outer periphery of the substrate 11. Further, a third insulating film 23 may be formed so as to cover the second insulating film 22. The third insulating film 23 is formed of, for example, a silicon oxide (SiO ₂ ) film. When the third insulating film 23 includes the third insulating film 23 and the first and second insulating films 21 and 22 are formed with connection portions (for example, vias) for connecting groove wirings and wiring layers, an organic film is used. The second insulating film 22 formed of the polyaryl ether is formed to avoid direct chemical mechanical polishing (CMP).

  Further, the edges of the first to third insulating films 21 to 23 are removed so that the chemical solution processing portion remains on the peripheral portion of the first insulating film 21. In addition, the first to third insulating films 21 to 23 may be formed with connection portions (for example, vias) connected to the trench wirings and lower conductor portions (for example, electrodes, wirings, elements, etc., not shown). .

  In the semiconductor device 1, the first insulating film 21 is formed on the periphery of the first insulating film 21 before the second insulating film 22 is formed after the first insulating film 21 constituting the insulating film between the wiring layers is formed. Since a chemical solution that improves the adhesion between the first insulating film 22 and the second insulating film 22 is applied, the dangling bonds of hydrogen on the film surface can be replaced with OH groups to bond oxygen to silicon in the SiC-based film. As a result, the oxidation of the surface of the first insulating film 21 is promoted. Accordingly, the adhesion of the second insulating film 22 to the first insulating film 21 can be enhanced in the peripheral portion. Therefore, after the second insulating film 22 is formed, for example, a CMP process is performed to perform the first and second processes. Even if a load in a direction substantially parallel to the surface of the first insulating film 21 is applied between the insulating films 21 and 22, there is an advantage that the second insulating film 22 can be prevented from being peeled off from the first insulating film 21. In particular, the adhesion at the periphery of the film where film peeling is likely to occur is enhanced, which is effective in preventing film peeling. Therefore, the yield can be improved and the reliability of the insulating film can be improved.

  An embodiment according to the first method for manufacturing a semiconductor device of the present invention will be described with reference to manufacturing process diagrams of FIGS. 2 to 6, (1) shows a schematic configuration perspective view, and (2) shows a schematic configuration cross-sectional view in the substrate diameter direction. The schematic cross-sectional view is enlarged in the thickness direction for easy understanding. Moreover, the arrow drawn on the board | substrate in a figure shows an example of the rotation direction of a board | substrate, This rotation direction may be a reverse direction.

  As shown in FIG. 2, an insulating film 12 is formed on the substrate 11. For example, a silicon substrate is used as the substrate 11. The insulating film 12 is made of a silicon oxide film and has a thickness of, for example, 500 nm. The film forming method is based on, for example, a plasma CVD method. Next, a first insulating film 21 is formed on the insulating film 12. Here, the first insulating film 21 is formed of a SiC-based film. For example, a SiOC film, a film containing nitrogen or hydrogen in the SiOC film, and the like. The first insulating film 21 is formed to a thickness of 200 nm, for example. In this film forming method, for example, a parallel plate type plasma CVD apparatus is used, and methylsilane is used as a silicon source of the source gas. As film forming conditions, the substrate temperature is set to 300 ° C. to 400 ° C., the plasma power is set to 150 W to 350 W, and the pressure of the film forming atmosphere is set to about 100 Pa to 1000 Pa. Hereinafter, the substrate 11 on which various insulating films are formed is referred to as a wafer.

Next, a chemical treatment is performed on the peripheral portion of the first insulating film 21 (for example, a range within 4 mm from the outer periphery of the wafer) (the hatched area in the perspective view is the chemical treatment region). In this chemical solution processing method, the chemical solution 31 improves the adhesion with the second insulating film formed in the subsequent step on the peripheral portion of the first insulating film 21 while rotating the substrate 11 in the direction of the arrow A in the drawing. In addition, the nozzle 41 for supplying the chemical solution 31 is scanned in the direction of the arrow A in the drawing, for example, in order to secure a chemical treatment region with a desired width w. At this time, pure water (not shown) is dropped onto the surface of the first insulating film 21 from the center of the substrate 11 so that the chemical solution 31 is not applied to the surface of the first insulating film 21 other than the peripheral portion of the first insulating film 21. Protect. Here, 5 wt% hydrogen peroxide (H ₂ O ₂ ) was used as the chemical solution 31, and the chemical treatment time was 60 seconds. In order to terminate the chemical treatment, the supply of the chemical solution 31 may be stopped, and the chemical solution 31 remaining on the surface of the first insulating film 21 may be washed with pure water. As a result, a chemical solution processing portion 33 that is oxidized from the surface of the other first insulating film 21 is formed in an annular shape around the first insulating film 21.

  Next, as shown in FIG. 3, a second insulating film 22 is formed on the first insulating film 21. An organic film was used for the second insulating film 22. For example, as an organic film, a polyaryl ether film is formed to a thickness of, for example, 100 nm. Examples of the polyaryl ether film include SiLK-J (Dow Chemical Co.), and other examples include FLARE manufactured by Allied Signal, VE manufactured by Schumacker, and the like. For example, when the polyaryl ether film is formed of SiLK, it can be formed by depositing the precursor by spin coating and then performing a curing process at 400 ° C. to 450 ° C.

  Next, as shown in FIG. 4, the edge portion of the second insulating film 22 is removed. In this edge portion removing method, the solvent 35 of the second insulating film 22 is supplied from the nozzle 43 onto the removal region of the second insulating film 22 while rotating the substrate 11 in the direction of the arrow C in the drawing, and the nozzle 43 is turned on. By scanning within an edge removal range (for example, in the direction of arrow D in the drawing). At this time, pure water (not shown) is supplied onto the second insulating film 22 from above the center of the substrate 11 to protect the chemical solution 35 from being applied to the surface of the second insulating film 22 other than the peripheral portion of the second insulating film 22. To do. When the second insulating film 22 is a polyaryl ether film, cyclohexanone can be used as the solvent. The removal width w of the peripheral portion of the second insulating film 22 can be easily changed by changing the scanning width of the nozzle 43. This time, the edge removal width w2 of the second insulating film 22 is set to 2 mm. The removal of the edge of the second insulating film 22 is performed in order to remove the second insulating film 22 on the outer periphery of the substrate 11.

Next, as shown in FIG. 5, a third insulating film 23 is formed so as to cover the second insulating film 22. The third insulating film 23 is formed of, for example, a silicon oxide (SiO ₂ ) film, and a plasma CVD method can be employed as the film forming method. In the present embodiment, the third insulating film 23 is formed so that the second insulating film 22 formed of organic polyaryl ether does not need to be directly subjected to chemical mechanical polishing (CMP) in a later process. A film is formed.

  Next, a photoresist film 51 is formed on the third insulating film 23 by a coating method. Then, the edge portion of the photoresist film 51 is removed. As a method for removing the edge portion of the photoresist film 51, when a positive resist is used for the photoresist 51, only the edge portion to be removed is irradiated with the light L while rotating the substrate 11 in the direction of the arrow O. The resist film 51 is exposed (the shaded area in the perspective view is the photosensitive area). Thereafter, through a development process, a rinse process, and a baking process, the photoresist film 51 from which the edge portion has been removed is obtained. When the photoresist film 51 is formed of a negative resist, only a region that is not to be removed is subjected to a photosensitive process, and then a development, a rinsing process, and a baking process are performed to obtain a photoresist film 51 from which the edge portion has been removed. It is done. The edge removal width w3 is 3 mm, for example.

  Next, as shown in FIG. 6, the third insulating film 23, the second insulating film 22, and the first insulating film 21 are etched in this order, and the edge portions of the third to first insulating films 23 to 21 are formed. Removed. Thereafter, the photoresist film 51 [see FIG. 5] was removed by ashing or stripping. In the drawing, the state where the photoresist film 51 is removed is shown.

  In the case where trench wirings and vias are formed in the first to third insulating films 21 to 23, a developing process is performed after performing an exposure process for removing edge portions of the first to third insulating films 21 to 23. Before patterning, for example, wiring grooves, via holes, etc. may be performed. The structure of the present invention can also be used for an insulating film having a so-called dual damascene structure in which a trench wiring and a via are formed simultaneously. For example, connection portions (vias) that connect the wirings are formed in the first insulating film 21, and groove wirings are formed in the second and third insulating films 22 and 23. There are many known examples of the technology for simultaneously forming the trench wiring and the via. For example, JP 2001-44189A discloses a detailed description. Also for these known insulating films, as in the present invention, the second insulating film 22 in which the trench wiring is formed is formed by performing chemical treatment on the peripheral portion of the first insulating film 21 in which the via is formed. A configuration can be employed.

  Next, the effect of the present invention was confirmed. As shown in FIG. 6, the method is to prepare an inventive sample in which the first to third insulating films 21 to 23 are formed on the substrate 11, and perform CMP on the third insulating film 23 of the inventive sample. went. In addition, as a sample to be compared with the inventive sample, a comparative sample in which the second and third insulating films 22 and 23 were formed on the first insulating film 21 without performing chemical treatment on the first insulating film 21 was prepared.

Next, the third insulating film 23 of each of the inventive sample and the comparative sample was subjected to CMP. In this CMP, for example, a polishing pad having an upper layer made of foamed polyurethane and a lower layer made of PET (polyethylene terephthalate) was used. As an example of such a polishing pad, there is a laminated polishing pad in which the upper layer is made of Rodale IC1000 having a thickness of 1.2 mm and the lower layer is made of SUBA400 having a thickness of 1.2 mm made by the same company. A polishing liquid (polishing slurry) obtained by adding hydrogen peroxide (H ₂ O ₂ ) as an oxidizing agent to colloidal silica dispersed in an alkaline solvent is used. For example, there is CMS8301 manufactured by JSR. The polishing liquid supply flow rate is, for example, 150 ml / min, the polishing pad rotation speed is, for example, 100 rpm, the wafer (substrate) rotation speed is, for example, 110 rpm, the polishing pressure is, for example, 300 g / cm ² , and the polishing time is, for example, 60 seconds. As a result, the thickness of the surface layer of the SiO ₂ film of the third insulating film 23 of about 70 nm was removed.

  The polishing was performed under the same conditions for both the inventive sample and the comparative sample. After polishing, the periphery of the insulating film was observed with a microscope, and the peeled state of the second insulating film with respect to the first insulating film 21 was observed. As a result, in the inventive sample, no film peeling occurred. On the other hand, in the comparative sample, film peeling occurred in almost all of the peripheral portion (region of 20% or more). Further, the comparative sample was peeled further inward than 4 mm from the peripheral portion of the wafer. On the other hand, in the inventive sample, film peeling did not occur in a region other than the peripheral portion of the wafer where no chemical treatment was performed.

  Therefore, in the first and second embodiments, not only the wafer peripheral portion with improved adhesion (for example, the range subjected to the chemical treatment) but also the region inside the wafer peripheral portion not subjected to the chemical treatment with improved adhesion. However, the effect of preventing film peeling was obtained. This is a chemical treatment that enhances the adhesion of the wafer peripheral portion to the surface of the first insulating film 21 at the interface between the polyaryl ether film of the second insulating film 22 and the SiC-based film of the first insulating film 21 with weak adhesion. This is because the oxidation of the surface of the first insulating film 21 around the wafer is promoted. Therefore, it can be said that the wafer peripheral portion where the pressure is concentrated at the time of CMP is not easily peeled off, thereby protecting the wafer surface.

  Next, an embodiment of the second semiconductor device according to the present invention will be described with reference to the schematic sectional view of FIG.

  As shown in FIG. 7, an insulating film 12 is formed on a substrate (wafer) 11 on which transistors, wirings, etc. (not shown) are formed. For example, a silicon substrate is used as the substrate 11. The insulating film 12 is made of a silicon oxide film and has a thickness of, for example, 500 nm. On the insulating film 12, a first insulating film 21 constituting an insulating film between wiring layers is formed. Here, the first insulating film 21 is formed of a SiC-based film. For example, a SiOC film or a film containing nitrogen or hydrogen in the SiOC film. The first insulating film 21 is formed to a thickness of 200 nm by, for example, plasma CVD. The first insulating film 21 has a peripheral portion (for example, a width of 2 mm from the wafer edge) removed.

  Further, a second insulating film 22 constituting an insulating film between the wiring layers is formed on the first insulating film 21. For example, an organic film is used for the second insulating film 22. As this organic film, a polyaryl ether film can be used. Examples of the polyaryl ether film include SiLK-J (Dow Chemical Co.). In addition, for example, FLARE manufactured by Allied Signal, VE manufactured by Schumacker, or the like can be used. The film thickness of the organic film was set to 100 nm, for example. The second insulating film 22 has a peripheral portion (for example, a width of 4 mm from the wafer edge) removed. The edge removal of the second insulating film 22 is performed in order to remove the second insulating film 22 on the outer periphery of the substrate 11.

  Chemical treatment is performed on the peripheral portion of the first insulating film 21 and the peripheral portion of the second insulating film 22 (for example, within a range of 4 mm from the outer periphery of the wafer). This chemical treatment is a treatment for improving adhesion with the third insulating film 23 formed on the first insulating film 21 and the second insulating film 22, and includes a peripheral portion of the first insulating film 21 and This is a process of applying a chemical solution for improving the adhesion on the periphery of the second insulating film 22. The chemical solution may be any chemical solution that has an action of oxidizing the surface of the first insulating film 21, in other words, an action of further promoting oxidation of the surfaces of the first insulating film 21 and the second insulating film 22. Such a chemical solution includes an oxidizing agent, and for example, hydrogen peroxide water can be used. Accordingly, the peripheral portions of the first insulating film 21 are oxidized immediately after the film formation, and the peripheral portions of the second insulating film 22 are oxidized from the surface of the other second insulating film 22. Formed.

Further, a third insulating film 23 may be formed so as to cover the second insulating film 22. The third insulating film 23 is formed of, for example, a silicon oxide (SiO ₂ ) film. When the third insulating film 23 includes the third insulating film 23 and the first and second insulating films 21 and 22 are formed with connection portions (for example, vias) for connecting groove wirings and wiring layers, an organic film is used. The second insulating film 22 formed of the polyaryl ether is formed to avoid direct chemical mechanical polishing (CMP).

  Furthermore, the edges of the first to third insulating films 21 to 23 are removed so that the chemical treatment portion remains on the peripheral portion of the first insulating film 21 and the peripheral portion of the second insulating film 22. . In addition, the first to third insulating films 21 to 23 may be formed with connection portions (for example, vias) connected to the trench wirings and lower conductor portions (for example, electrodes, wirings, elements, etc., not shown). .

  In the semiconductor device according to the third embodiment, the first insulating film 21 is formed after the first insulating film 21 and the second insulating film 22 constituting the insulating film between the wiring layers are formed and before the third insulating film 23 is formed. Since the first insulating film 21 and the chemical solution for improving the adhesion between the second insulating film 22 and the third insulating film 23 are applied on the peripheral portion and the peripheral portion of the second insulating film 22, hydrogen dangling on the film surface is applied. Since oxygen can be bonded by substituting ring bonds with OH groups, oxidation of the peripheral surface of the first insulating film 21 and the peripheral surface of the second insulating film 22 is promoted. From this, the adhesion of the third insulating film 23 to the first and second insulating films 21 and 22 can be improved in the peripheral portion. Therefore, after the third insulating film 23 is formed, for example, a CMP process is performed. Even if a load in a direction substantially parallel to the surface of the second insulating film 22 is applied between the first and third insulating films 21 and 23 and between the second and third insulating films 22 and 23, for example, There is an advantage that it is possible to prevent the third insulating film 23 from being peeled off from the insulating films 21 and 22. In particular, the adhesion at the periphery of the film where film peeling is likely to occur is enhanced, which is effective in preventing film peeling. Therefore, the yield can be improved and the reliability of the insulating film can be improved.

  An embodiment of the second method for manufacturing a semiconductor device according to the present invention will be described with reference to the manufacturing process diagrams of FIGS. 8 to 11, (1) shows a schematic configuration perspective view, and (2) shows a schematic configuration sectional view in the substrate diameter direction. The schematic cross-sectional view is enlarged in the thickness direction for easy understanding. Moreover, the arrow drawn on the board | substrate in a figure shows an example of the rotation direction of a board | substrate, This rotation direction may be a reverse direction.

  As shown in FIG. 8, an insulating film 12 is formed on a substrate (wafer) 11. For example, a silicon substrate is used as the substrate 11. The insulating film 12 is made of a silicon oxide film and has a thickness of, for example, 500 nm. The film forming method is based on, for example, a plasma CVD method. Next, a first insulating film 21 is formed on the insulating film 12. Here, the first insulating film 21 is formed of a SiC-based film. For example, a SiOC film, a film containing nitrogen or hydrogen in the SiOC film, and the like. The first insulating film 21 is formed to a thickness of 200 nm, for example. In this film forming method, for example, a parallel plate type plasma CVD apparatus is used, and methylsilane is used as a silicon source of the source gas. As film forming conditions, the substrate temperature is set to 300 ° C. to 400 ° C., the plasma power is set to 150 W to 350 W, and the pressure of the film forming atmosphere is set to about 100 Pa to 1000 Pa.

  Next, a second insulating film 22 is formed on the first insulating film 21. An organic film was used for the second insulating film 22. For example, as an organic film, a polyaryl ether film is formed to a thickness of, for example, 100 nm. Examples of the polyaryl ether film include SiLK-J (Dow Chemical Co.), and other examples include FLARE manufactured by Allied Signal, VE manufactured by Schumacker, and the like. For example, when the polyaryl ether film is formed of SiLK, it can be formed by depositing the precursor by spin coating and then performing a curing process at 400 ° C. to 450 ° C.

  Next, the edge portion of the second insulating film 22 is removed. In this edge portion removal method, the solvent 35 of the second insulating film 22 is supplied from the nozzle 43 onto the removal region of the second insulating film 22 (the region indicated by hatching in the drawing) while rotating the substrate 11 in the direction of the arrow, for example. At the same time, the nozzle 43 is scanned in the direction of the arrow within the edge removal range. At this time, pure water (not shown) is supplied onto the second insulating film 22 from above the center of the substrate 11 to protect the surface of the second insulating film 22 other than the periphery of the second insulating film 22 from being exposed to the solvent 35. To do. When the second insulating film 22 is a polyaryl ether film, cyclohexanone can be used as the solvent. The removal width w4 of the peripheral portion of the second insulating film 22 can be easily changed by changing the scanning width of the nozzle 43. This time, the edge removal width of the second insulating film 22 is set to 3 mm. The removal of the edge of the second insulating film 22 is performed in order to remove the second insulating film 22 on the outer periphery of the substrate 11.

Next, as shown in FIG. 9, chemical treatment is performed on the peripheral portion of the first insulating film 21 and the peripheral portion of the second insulating film 22. For example, the chemical treatment area is within a range of 4 mm from the outer periphery of the wafer (area shown by hatching in the drawing). In this chemical processing method, a third insulation formed in a later step on the peripheral portion of the first insulating film 21 and the peripheral portion of the second insulating film 22 while rotating the substrate 11 in the direction of an arrow, for example. While dropping the chemical solution 31 for improving the adhesion to the film, the nozzle 41 for supplying the chemical solution is scanned, for example, in the direction indicated by the arrow in the drawing in order to secure a chemical treatment region with a desired width w5. At this time, by supplying pure water (not shown) from the central portion of the substrate 11 to the surface of the second insulating film 22, the chemical solution 31 is not applied to the surface of the second insulating film 22 other than the peripheral portion of the second insulating film 22. Protect. Here, 5 wt% hydrogen peroxide (H ₂ O ₂ ) was used as the chemical solution 31, and the chemical treatment time was 60 seconds. In order to finish the chemical treatment, the supply of the chemical solution 31 is stopped, and cleaning with pure water is performed to remove the chemical solution 31 remaining on the surfaces of the first insulating film 21 and the second insulating film 22. Good. As a result, a chemical treatment unit 33 oxidized from the surface at the time of forming the first insulating film 21 is formed in the peripheral portion of the first insulating film 21, and in the peripheral portion of the second insulating film 22. A chemical processing unit 34 that is oxidized from the surface other than the peripheral portion of the second insulating film 22 is formed.

Next, as shown in FIG. 10, a third insulating film 23 is formed so as to cover the second insulating film 22. The third insulating film 23 is formed of, for example, a silicon oxide (SiO ₂ ) film, and a plasma CVD method can be employed as the film forming method. In the present embodiment, the third insulating film 23 is formed so that the second insulating film 22 formed of organic polyaryl ether does not need to be directly subjected to chemical mechanical polishing (CMP) in a later process. A film is formed.

  Next, a photoresist film 51 is formed on the third insulating film 23 by a coating method. Then, the edge portion of the photoresist film 51 is removed. In the method of removing the edge portion of the photoresist film 51, when a positive resist is used as the photoresist 51, only the edge portion to be removed is irradiated with light L to the area indicated by the oblique lines in the drawing to expose the photoresist film 51. Let Thereafter, through a development process, a rinse process, and a baking process, the photoresist film 51 from which the edge portion has been removed is obtained. When the photoresist film 51 is formed of a negative resist, only a region that is not to be removed is subjected to a photosensitive process, and then a development, a rinsing process, and a baking process are performed to obtain a photoresist film 51 from which the edge portion has been removed. It is done. The edge removal width w6 is set to 2 mm, for example.

  Next, as shown in FIG. 11, the third insulating film 23, the second insulating film 22, and the first insulating film 21 are etched in this order, and the edge portions of the third to first insulating films 23 to 21 are formed. Removed. Thereafter, the photoresist film 51 [see FIG. 10] was removed by ashing or stripping. In the drawing, the state where the photoresist film 51 is removed is shown.

  In the case where trench wirings and vias are formed in the first to third insulating films 21 to 23, a developing process is performed after performing an exposure process for removing edge portions of the first to third insulating films 21 to 23. Before patterning, for example, wiring grooves, via holes, etc. may be performed. Thereafter, as shown in FIG. 12, a barrier metal layer (not shown) and a copper film 61 are formed. Next, for example, the substrate 11 is rotated in the direction of the arrow S, and the solvent 37 of the copper film 61 is supplied from the nozzle 45 onto the removal region of the copper film 61 (the region indicated by the oblique lines in the schematic configuration perspective view). By scanning the nozzle 45 in the edge removal range, for example, in the direction of the arrow. At this time, pure water (not shown) is supplied onto the second insulating film 22 from above the center of the substrate 11 to protect the surface of the copper film 61 other than the periphery of the copper film 61 from being exposed to the solvent 37. The removal width w7 of the peripheral portion of the copper film 61 can be easily changed by changing the scanning width of the nozzle 43. Thereafter, although not shown, the excess copper film 61 and the barrier metal layer are removed by CMP to form trench wirings and vias.

  In the manufacturing method of the present invention, an insulating film having a so-called dual damascene structure in which a trench wiring and a via are simultaneously formed can also be used. For example, connection portions (vias) that connect the wirings are formed in the first insulating film 21, and groove wirings are formed in the second and third insulating films 22 and 23. There are many known examples of the technology for simultaneously forming the trench wiring and the via. For example, JP 2001-44189A discloses a detailed description. Also for these known insulating films, as in the present invention, the second insulating film 22 in which the trench wiring is formed is formed by performing chemical treatment on the peripheral portion of the first insulating film 21 in which the via is formed. A configuration can be employed.

  Next, the effect of the present invention was confirmed. As shown in FIG. 11, the method is to prepare an inventive sample in which the first to third insulating films 21 to 23 are formed on the substrate 11, and perform CMP on the third insulating film 23 of the inventive sample. went. Further, as a comparison with the inventive sample, a comparative sample in which the first and second insulating films 21 and 22 are not subjected to the chemical treatment and the third insulating film 23 is formed on the first and second insulating films 21 and 22 is used. Prepared.

Next, the third insulating film 23 of each of the inventive sample and the comparative sample was subjected to CMP. In this CMP, for example, a polishing pad having an upper layer made of foamed polyurethane and a lower layer made of PET (polyethylene terephthalate) was used. As an example of such a polishing pad, there is a laminated polishing pad in which the upper layer is made of Rodale IC1000 having a thickness of 1.2 mm and the lower layer is made of SUBA400 having a thickness of 1.2 mm made by the same company. As the polishing liquid, one obtained by adding hydrogen peroxide (H ₂ O ₂ ) as an oxidizing agent to colloidal silica dispersed in an alkaline solvent is used. For example, there is CMS8301 manufactured by JSR. The polishing liquid supply flow rate is, for example, 150 ml / min, the polishing pad rotation speed is, for example, 100 rpm, the wafer (substrate) rotation speed is, for example, 110 rpm, the polishing pressure is, for example, 300 g / cm ² , and the polishing time is, for example, 60 seconds. As a result, the thickness of the surface layer of the SiO ₂ film of the third insulating film 23 of about 70 nm was removed.

  The polishing was performed under the same conditions for both the inventive sample and the comparative sample. After polishing, the periphery of the insulating film was observed with a microscope, and the film peeling state was observed. As a result, in the inventive sample, no film peeling occurred. On the other hand, in the comparative sample, film peeling occurred in almost all of the peripheral portion (region of 20% or more). Further, the comparative sample was peeled further inward than 4 mm from the peripheral portion of the wafer. On the other hand, in the inventive sample, film peeling did not occur in a region other than the peripheral portion of the wafer where no chemical treatment was performed.

  Further, when the second insulating film 22 is formed of, for example, a p-SiLK film in addition to the SiLK film, and when the first insulating film 21 is formed of various SiOC-based films, the same result as described above is obtained. It was. Therefore, the present invention is applicable to all cases where a SiOC film is used for the first insulating film 21, a polyaryl ether film is used for the second insulating film, and a silicon oxide film is used for the third insulating film 23. It can be said that it is effective.

  Therefore, in the third and fourth embodiments, not only the wafer peripheral portion (for example, a range where chemical treatment is performed) with improved adhesion, but also the region inside the wafer peripheral portion where chemical treatment for improving adhesion is not performed. However, the effect of preventing film peeling was obtained. This is because the surface of the first insulating film 21 and the surface of the second insulating film 22 at the periphery of the wafer at the interface between the polyaryl ether film of the second insulating film 22 having weak adhesion and the SiOC-based film of the first insulating film 21. This is because the surface of the first insulating film 21 and the surface of the second insulating film 22 in the peripheral portion of the wafer is promoted by the chemical treatment that improves the adhesion to the surface. Therefore, it can be said that the wafer peripheral portion where the pressure is concentrated at the time of CMP is not easily peeled off, thereby protecting the wafer surface.

  In addition, it was found that Examples 3 and 4 were more effective than Examples 1 and 2. For example, a p-SiLK film is used for the first insulating film 21 and an SiOC film having a dielectric constant k = 3.0 formed by, for example, a CVD method (for example, manufactured by AMAT Corporation) is used as the SiOC-based film for the second insulating film 22. When a BD (black diamond) is formed, a SiLK film is used for the first insulating film 21, and a SiOC-based film is used for the second insulating film 22 as a SiOC film having a dielectric constant k = 2.5, for example, formed by CVD. When a film (for example, BD (Black Diamond) 2 manufactured by AMAT) was formed, peeling was confirmed in the region of 2% or less in Examples 1 and 2, but peeling occurred in Examples 3 and 4. I didn't. On the other hand, in the conventional configuration in which no chemical treatment is performed, peeling was confirmed in an area exceeding 20%. Further, when a p-SiLK film is used for the first insulating film 21 and a SiOC-based BD2 film is formed for the second insulating film 22, in the first and second embodiments, the region is more than 2% and not more than 20%. In Examples 3 and 4, no peeling occurred. On the other hand, in the conventional configuration in which no chemical treatment is performed, peeling was confirmed in an area exceeding 20%. Therefore, in Examples 1 and 2, the film peeling can be improved as compared with the conventional case where the chemical treatment process of the present invention is not performed, but in Examples 3 and 4, the film peeling can be eliminated significantly. Improvement effect is obtained.

Next, the adhesion of various insulating films was investigated. As a lower layer film, a silicon oxide (SiO ₂ ) film, a silicon nitride (SiN) film, a silicon nitride carbide (SiCN) film, a silicon carbide (SiC) film, a SiOC film (BD), a SiOC film (Coral: manufactured by Novellus) MSC film formed by spin coating with an MSQ film made by SiOC film of SiOC film of about k = 3.0), SiOC film (BD2), porous silica (LKD5109: LKD (JSR)). ), Porous silica (for example, Nanoglass manufactured by Nanoglass), porous silica (for example, Nanoglass-E manufactured by Nanoglass), polyaryl ether (SiLK), polyaryl ether (FLARE), polyaryl ether (p-SiLK) Was used. Further, as an upper layer film, a silicon oxide (SiO ₂ ) film, a silicon nitride (SiN) film, a silicon nitride carbide (SiCN) film, a silicon carbide (SiC) film, a SiOC film (BD), a SiOC film (Coral), Uses SiOC film (BD2), porous silica (LKD5109), porous silica (Nanoglass), porous silica (Nanoglass-E), polyaryl ether (SiLK), polyaryl ether (FLARE), polyaryl ether (p-SiLK) It was.

  Then, one type of the lower layer film and one type of the upper layer film were selected to form a laminated film, and the adhesion of the upper layer film to the lower layer film was examined.

  The film peeling was inspected by visual inspection using a microscope. The results of the inspection are shown in Tables 1 to 4.

  In Tables 1 to 4, ◎ indicates no peeling, ○ indicates peeling in an area of 2% or less, Δ indicates peeling in an area exceeding 2% and 20% or less, and X indicates an area exceeding 20%. It shows that there is peeling. In the above evaluation, the reason why 20% is used as the boundary is that empirical peeling in an area exceeding 20% is considered to be essential because of good reproducibility of peeling. When actually observing the peeling state, “no peeling”, “almost not peeled but peeled in about 1% area”, “peeled in about 5% to 10% area”, “peeled in almost all areas” Observed in four distinct stages, the difference between ◎, ○, △, and X was recognized as a clear difference.

As shown in Tables 1 to 4, it can be seen that the adhesion deteriorates when the underlying insulating film is an insulating film having a dielectric constant k ≦ 3.0. It can also be seen that the adhesion deteriorates particularly when the first insulating film is an insulating film containing carbon (C). An insulating film having a dielectric constant k ≦ 3.0 or an insulating film containing carbon (C) has fewer OH groups on the surface than an ordinary insulating film such as silicon oxide (SiO ₂ ). The adhesion of is getting worse.

Therefore, as in the present invention, by treating with an oxidizing agent such as hydrogen peroxide (H ₂ O ₂ ) water in order to improve adhesion, the surface is oxidized to increase OH groups, and the lower film and Adhesion with the upper film is improved. In the above description, hydrogen peroxide water was used as the oxidizing agent. For example, ozone water, other chemicals having oxidizing properties (for example, potassium permanganate (KMnO ₄ ), manganese dioxide (MnO ₂ ), potassium dichromate) (K ₂ Cr ₂ O ₇ ), concentrated sulfuric acid (H ₂ SO ₄ ), nitric acid (HNO ₃ ) and the like can be used.

  Further, as shown in Table 1, it was found that the adhesion between the organic insulating film and other insulating films was particularly weak. That is, it can be said that the organic insulating film is particularly easily peeled off as the lower insulating film. Therefore, the present invention is particularly effective in performing chemical treatment on the organic insulating film and improving the adhesion with the upper insulating film.

  Next, an example in which a multilayer wiring structure is formed by applying the configuration and manufacturing method of the present invention will be described with reference to the schematic configuration cross-sectional view of FIG.

As shown in FIG. 13, a SiOC film (thickness is, for example, 200 nm) / SiCN film (thickness is, for example, 35 nm) is used as the insulating film of the via layer that becomes the first insulating film 21, and an organic film is used as the second insulating film 22. As the third insulating film 23, a silicon oxide (SiO ₂ ) film (thickness at the time of film formation is, for example, 200 nm, and thickness after CMP is about 150 nm) is used. A polyaryl ether film was used as the organic film, and a SiLK film (with a thickness of, for example, 100 nm) was used here as the polyaryl ether film. The removal width of the edge portion of the second insulating film 22 (SiLK film) was set to 3 mm, and the removal width of the edge portion of the third insulating film 23 (SiO ₂ film) and the first insulating film 21 was set to 2 mm. Then, using the manufacturing method described in Example 4, the semiconductor device having the five-layer groove wiring 71 and the connecting portion (via) 72 as illustrated was formed. As a result, the semiconductor device could be manufactured without causing edge peeling.

  The semiconductor device manufacturing method and the semiconductor device of the present invention are preferably applied to the use of multilayer wiring of various semiconductor devices.

1 is a schematic cross-sectional view showing an embodiment of the first semiconductor device of the present invention. It is the schematic structure perspective view and schematic structure sectional drawing which showed one Example which concerns on the 1st manufacturing method of the semiconductor device of this invention. It is the schematic structure perspective view and schematic structure sectional drawing which showed one Example which concerns on the 1st manufacturing method of the semiconductor device of this invention. It is the schematic structure perspective view and schematic structure sectional drawing which showed one Example which concerns on the 1st manufacturing method of the semiconductor device of this invention. It is the schematic structure perspective view and schematic structure sectional drawing which showed one Example which concerns on the 1st manufacturing method of the semiconductor device of this invention. It is the schematic structure perspective view and schematic structure sectional drawing which showed one Example which concerns on the 1st manufacturing method of the semiconductor device of this invention. FIG. 5 is a schematic cross-sectional view showing an embodiment of the second semiconductor device of the present invention. It is the schematic structure perspective view and schematic structure sectional drawing which showed one Example which concerns on the 2nd manufacturing method of the semiconductor device of this invention. It is the schematic structure perspective view and schematic structure sectional drawing which showed one Example which concerns on the 2nd manufacturing method of the semiconductor device of this invention. It is the schematic structure perspective view and schematic structure sectional drawing which showed one Example which concerns on the 2nd manufacturing method of the semiconductor device of this invention. It is the schematic structure perspective view and schematic structure sectional drawing which showed one Example which concerns on the 2nd manufacturing method of the semiconductor device of this invention. It is the schematic structure perspective view and schematic structure sectional drawing which showed one Example which concerns on the 2nd manufacturing method of the semiconductor device of this invention. 1 is a schematic cross-sectional view showing an embodiment of a semiconductor device according to the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 11 ... Board | substrate, 21 ... 1st insulating film, 22 ... 2nd insulating film, 33 ... Chemical-solution processing area | region

Claims (19)

A semiconductor device having a multilayer wiring structure on a substrate,
The insulating film that electrically insulates the wiring layers of the multilayer wiring structure is formed by laminating a first insulating film and a second insulating film,
A chemical solution treatment in which a chemical solution for improving the adhesion between the first insulating film and the second insulating film is applied between the first insulating film and the second insulating film on the periphery of the first insulating film. A semiconductor device characterized in that a region is formed. The semiconductor device according to claim 1, wherein the chemical solution is made of an oxidizing agent. A semiconductor device having a multilayer wiring structure on a substrate,
The insulating film that electrically insulates the wiring layers of the multilayer wiring structure is formed by laminating a first insulating film, a second insulating film, and a third insulating film,
The edge of the second insulating film is formed to be inside the edge of the third insulating film,
Between the first insulating film and the third insulating film and between the second insulating film and the third insulating film, on the peripheral portion of the first insulating film and on the peripheral portion of the second insulating film A chemical solution treatment region is formed in which a chemical solution for improving adhesion between the first insulating film, the third insulating film, and the second insulating film and the third insulating film is applied. . The semiconductor device according to claim 3, wherein the chemical solution is made of an oxidizing agent. A method of manufacturing a semiconductor device having a multilayer wiring structure on a substrate,
The insulating film that electrically insulates the wiring layers of the multilayer wiring structure is formed by laminating a first insulating film and a second insulating film,
Before forming the second insulating film after forming the first insulating film, a chemical solution for improving the adhesion between the first insulating film and the second insulating film is formed on the periphery of the first insulating film. A method for manufacturing a semiconductor device, comprising the step of applying. Forming a third insulating film on the second insulating film;
Before forming the third insulating film, the peripheral portion of the second insulating film is removed so that the edge of the second insulating film is inside the edge of the third insulating film. Item 6. A method for manufacturing a semiconductor device according to Item 5. The method for manufacturing a semiconductor device according to claim 5, wherein the chemical solution is made of an oxidizing agent. The method for manufacturing a semiconductor device according to claim 5, wherein a peripheral portion of the first insulating film is within 5 mm inward from an outer peripheral portion of the first insulating film. The method of manufacturing a semiconductor device according to claim 5, wherein the first insulating film is a low dielectric constant insulating film having a relative dielectric constant of 3.0 or less. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the first insulating film is made of a material containing silicon and carbon. The method for manufacturing a semiconductor device according to claim 5, wherein the second insulating film is an organic film. The wiring of the multilayer wiring structure is formed by embedding a wiring material containing copper in a recess formed in an insulating film that electrically insulates between the wiring layers, and then chemicals excess wiring material on the insulating film. The method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor device is formed by removing by mechanical mechanical polishing. A method of manufacturing a semiconductor device having a multilayer wiring structure on a substrate,
The insulating film that electrically insulates the wiring layers of the multilayer wiring structure is formed by laminating a first insulating film, a second insulating film, and a third insulating film,
Forming an edge of the second insulating film so as to be inside the edge of the third insulating film;
After forming the second insulating film and before forming the third insulating film, the first insulating film and the second insulating film are formed on the peripheral portion of the first insulating film and on the peripheral portion of the second insulating film. A method of manufacturing a semiconductor device, comprising: applying a chemical solution that enhances adhesion between the insulating film and the third insulating film. The method of manufacturing a semiconductor device according to claim 13, wherein the chemical solution is made of an oxidizing agent. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the peripheral portion of the first insulating film and the peripheral portion of the second insulating film are within 5 mm inward from the outer peripheral portion of the first insulating film. . The method of manufacturing a semiconductor device according to claim 13, wherein the first insulating film is a low dielectric constant insulating film having a relative dielectric constant of 3.0 or less. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the first insulating film is made of a material containing silicon and carbon. The method for manufacturing a semiconductor device according to claim 13, wherein the second insulating film is an organic film. The wiring of the multilayer wiring structure is formed by embedding a wiring material containing copper in a recess formed in an insulating film that electrically insulates between the wiring layers, and then chemicals excess wiring material on the insulating film. The method of manufacturing a semiconductor device according to claim 13, wherein the semiconductor device is formed by removing by mechanical mechanical polishing.

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