JP2005216455A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory where stress to a memory cell is reduced by reliably reducing the number of times of erasing and writing more than that in conventional technique in consideration of the relation between already written data and data to be written as new one (new writing data, hereafter). <P>SOLUTION: When rewriting data, the already written data which is written already is compared with the new writing data, and it is judged by each block whether the new writing data can be expressed without erasing the already written data. By erasing the already written data only when erasing is required, the number of times of erasing is reduced. When writing data, data requiring a smaller number of writing bits between new writing inverted data obtained by inverting each bit of the new writing data and the new writing data is written to reduce the number of times of writing to the memory cell. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a nonvolatile semiconductor memory, and relates to a data writing method and a data reading method for the nonvolatile semiconductor memory.

  The rewritable non-volatile memory has the features that the contents do not disappear even when the power is turned off, and the reading speed is fast. For example, the flash memory is a BIOS storage memory of a PC, an image storage memory of a digital still camera, and a control microcomputer. It is used as a memory for instruction / data storage.

  In addition, the rewritable nonvolatile memory has a limit of, for example, 10,000 times of writing. This is because when the bit state of each memory is changed from 1 (high level) to 0 (low level) or from 0 to 1, stress is applied to the elements constituting each bit of the nonvolatile memory.

  In a flash memory, erasing (a bit is set to 1) can be performed on a plurality of memory cells sharing a word line, but general erasing is performed in units called sectors including a plurality of word lines. Only specific memory cells are not selectively erased. On the other hand, writing (setting the bit state to 0) is performed selectively for a specific memory cell.

  When such erasure (sets the bit state to 1 in sector units) and write (sets the bit state of a specific memory cell to 0), stress is applied to the elements constituting each bit, and the number of rewrites increases. There was a problem that the reliability of the system deteriorated.

Therefore, in the prior art, 0 or 1 of all newly written data is counted, and when the number of 0 <number, the data is written as it is, and when the number of 0> 1, the data is inverted and written. As a result, stress is reduced by reducing writing (bit state is set to 0) (see Patent Document 1). Further, the probability of writing data to the same address is reduced by inverting and using specific address data when all data erasure is detected (see Patent Document 2).
JP 7-45085 A JP 2001-56785 A

  However, in the above prior art, when data is rewritten, new data is written after erasing all data to be rewritten without considering the relationship between written data and new written data. However, the degree of reduction in the number of erase and write operations is small, and the degree of reduction in stress on the memory cell is also small.

  In consideration of the relationship between already written data and new written data, the present invention can reduce stress on the memory cell by reliably reducing the number of times of erasing and writing, as compared with the prior art. A non-volatile semiconductor memory is provided.

  A nonvolatile semiconductor memory according to the present invention includes a memory cell array having a plurality of memory cells that store different 1-bit data in a write state and an erase state, and divides the memory cell array into blocks that store a plurality of bits of data. Non-volatile semiconductor memory that writes data to memory cells in units of blocks, and when new data is stored for each block, the existing data stored in the block is compared with the new data, and the existing data in the block A new data determination process for determining whether or not new data can be written without changing any one of a plurality of memory cells constituting data from a write state to an erase state; and a block Compare the existing data stored in the machine and the processed data generated by applying the predetermined calculation processing to the new data Processing data determination for determining whether or not processing data can be written without changing any of the plurality of memory cells constituting the existing data of the block from the writing state to the erasing state Processing, data erasure processing for erasing all memory cells constituting the existing data of the block when new data determination processing and processed data determination processing are both impossible, and new data determination processing When the judgment result of only the new data judgment processing is possible among the machining data judgment processing, new data is written to the block, and when the judgment result of only the processing data judgment processing is possible, the processing data is written to the block and the new data When the judgment results of both the judgment process and the machining data judgment process are possible, or after the erasure process, new data or addition is added to the block. And performing the writing data write processing data.

  According to this configuration, when rewriting data, for each block, the existing data is compared with the new data and the existing data is compared with the processed data to determine whether the existing data needs to be erased. By erasing existing data and writing new data or processed data only when necessary, the number of times of erasing and writing can be reduced to reduce stress on the memory cells.

  Further, in the present invention, the data writing process performed when the determination result of both the new data determination process and the processed data determination process is possible is that the processed data written in the new data and processed data is within the block. When the number of memory cells to be changed from the erased state to the written state decreases, the processed data is written, and in other cases, new data is written.

  Thus, by selecting and writing either new data or processed data, the total number of erases and writes to the memory cell can be reduced, and the stress on the memory cell can be further reduced.

  Further, in the present invention, the data writing process performed after the erasing process is performed when the number of memory cells in the writing state in the block is smaller when the processed data is written out of the new data and the processed data. Is written, otherwise new data is written.

  Thus, by selecting and writing either new data or processed data, the total number of erases and writes to the memory cell can be reduced, and the stress on the memory cell can be further reduced.

  Further, in the present invention, when reading the data of the block in which the machining data is written, the calculation process reverse to the calculation process performed when the machining data is generated is read. By reading in this way, the same data as the new data that should have been originally written can be read.

  Further, in the present invention, an arithmetic processing flag indicating an arithmetic processing performed when generating the processed data is provided in the memory cell array, and the arithmetic processing is processing for inverting each bit data of the new data. The calculation flag is reset when writing new data, and the calculation flag is set when writing machining data. When reading block data, if the calculation flag is reset, the data is read as is. If the processing flag is set, the data is inverted and read.

  In this configuration, each bit data is inverted as a calculation process when generating processed data from new data. As in the above-described invention, the number of times of erasing and writing to the memory cell is reduced to reduce the memory cell. Can reduce stress on In addition, since an operation processing flag indicating the operation content is provided, the same data as the new data that should have been originally written can be read from the block based on the operation processing flag.

  Further, in the present invention, an arithmetic processing flag indicating an arithmetic processing performed when generating processed data is provided in the memory cell array, and the arithmetic processing is processing for reversing the bit arrangement direction of new data, and data writing processing When writing new data, reset the arithmetic processing flag, and when processing data is written, set the arithmetic processing flag. When reading the block data, if the arithmetic processing flag is reset, the data is read as it is. If the arithmetic processing flag is set, the data is read with the bits arranged in the up-down direction.

  This configuration is designed to reverse the bit top-and-bottom alignment direction as an arithmetic process when generating processed data from new data, and, like the above-described invention, reduces the number of times of erasing and writing to memory cells. The stress on the memory cell can be reduced. In addition, since an operation processing flag indicating the operation content is provided, the same data as the new data that should have been originally written can be read from the block based on the operation processing flag.

  The arithmetic processing flag is composed of a plurality of bits of memory cells, and the number of memory cells in the writing state or the number of memory cells in the erasing state among the memory cells forming the arithmetic processing flag is an odd number. By determining whether or not the arithmetic processing flag is set or reset depending on whether the arithmetic processing flag is an even number, the number of times of erasing the flag area of the arithmetic processing flag can be reduced.

  Further, in the present invention, an arithmetic processing flag indicating an arithmetic processing performed when processing data is generated is provided in the memory cell array, and the arithmetic processing is processing for shifting new data by N bits in a predetermined direction (N is an integer of 1 or more). In the data writing process, the processing flag is reset when new data is written, and the processing flag is set when processing data is written. When the block data is read, the processing flag is reset. If so, the data is read as it is, and if the arithmetic processing flag is set, the data is read by shifting N bits in the direction opposite to the predetermined direction.

  This configuration is such that N bits are shifted in a predetermined direction as a calculation process when generating processed data from new data, and as in the above invention, the number of times of erasing and writing to memory cells is reduced and the memory is reduced. The stress on the cell can be reduced. In addition, since an operation processing flag indicating the operation content is provided, the same data as the new data that should have been originally written can be read from the block based on the operation processing flag.

  In addition, by configuring the arithmetic processing flag with a plurality of bits, it is possible to increase the effective determination range of the number of shift movement bits when processing data is generated.

  As described above, according to the present invention, by considering the relationship between already written data and newly written data, the number of times of erasure and writing can be reduced more reliably than in the prior art, and stress on the memory cell can be reduced. This can reduce the life of the nonvolatile semiconductor memory.

  Hereinafter, an embodiment when the present invention is applied to a flash memory will be described.

(First embodiment)
FIG. 1A is an example of a data rewrite flow according to the first embodiment of the present invention, and FIG. 1B is a signal or data when data is written according to the rewrite flow of FIG. It shows the transition of variables in the writing program. When the function is realized by hardware, it becomes a value of the signal line, and when realized by the program, it becomes the value of the variable in the program.

  In FIG. 1B, 117 indicates the number of rewrites. Reference numeral 118 denotes a memory state in a certain block before rewriting. In this explanation, for the sake of simplicity, it is assumed to be 4-bit data, and the written portion (bit state is 0) is underlined. Reference numeral 119 denotes new write data as it is, and the underlined portion corresponds to the position where the data has been written in the memory state 118 (bit state is 0). Reference numeral 120 denotes a determination result obtained by the determination 102 in FIG. 121 is the first write bit number counted in the process 104 of FIG. 1A. When the new write data 119 is written as it is, the memory state 118 is not erased. This is the number of bits to be newly written (set the bit state to 0). 122 is the second write bit number counted in the process 103 in FIG. 1A. When the data 119 is written as the new write data as it is, it is erased from the memory state 118 (all bits are changed). This is the number of bits to be newly written (to set the bit state to 0) after performing (to 1).

  123 is data obtained by reversing each bit of the new write data (new write inverted data), and the underlined portion corresponds to the position where the data has been written (bit state is 0) in the memory state 118 To do. Reference numeral 124 denotes a determination result obtained by the determination 105 in FIG. 125 is the third write bit number counted in the process 107 of FIG. 1A. When the new write inversion data 123 is to be written, the memory state 118 is newly erased without being erased. This is the number of bits to be written (bit state is set to 0). 126 is the fourth number of write bits counted in the processing 106 of FIG. 1A. When the new write inverted data 123 is written, the memory state 118 is erased (all bits are set to 1). This is the number of bits to be newly written (set the bit state to 0) after performing

  Reference numeral 127 denotes actual write data, which is data to be written in any one of the process 110, the process 111, the process 114, and the process 115 in FIG. Reference numeral 128 denotes an inversion flag indicating whether or not the actual write data 127 is inverted.

  The flow of data rewriting will be described with reference to FIGS. 1 (a) and 1 (b).

  In the first rewrite 129, the memory state 118 before rewrite is “1111”. In the first rewrite 129, the new write data is “1111”.

  In decision 102, it is determined whether or not the corresponding bit of data 119 is written as it is (new bit is written) as to the already written bit (bit whose state is 0) in the memory state 118. If it is NG, the process proceeds to process 103. In the first rewrite 129, since there is no already written bit in the memory state 118, the first determination is OK and the processing proceeds to step 104. In process 104, the first write bit number 121 is counted. The first write bit number 121 is obtained by subtracting the number of zeros in the memory state 118 from the number of zeros in the data 119 as it is. It becomes 0 at the first rewrite 129.

  Next, it is determined in decision 105 whether or not the corresponding bit of the new write inverted data 123 is also written for the already written bit in the memory state 118 (the bit state is set to 0). If it is NG, the process proceeds to processing 106. In the first rewrite 129, since there is no already written bit in the memory state 118, the second determination is OK and the processing 107 is performed. In process 107, the number of third write bits is counted. The third write bit number 125 is obtained by subtracting the number of zeros in the memory state 118 from the number of zeros in the inverted data 123. It is 4 in the first rewrite 129.

  Next, in the determination 108, it is determined whether both the first determination 120 and the second determination 124 are NG. If both are NG, the process proceeds to the process 112, and if not, the process proceeds to the determination process 109. In the first 129 rewriting times, since both the first determination 120 and the second determination 124 are OK, the process proceeds to determination 109.

  In the determination 109, the first write bit number 121 and the third write bit number 125 are compared. If the first write bit number 121 ≦ the third write bit number 125, the process 111 (the same process as the process 115) is performed. If not, the process proceeds to process 110 (the same process as process 114). In the first rewrite operation 129, since the first write bit number <the third write bit number, the process proceeds to processing 111, and the new write data as it is is written into the memory cell as the write data 127. The inversion flag 128 is set to 1. This completes the first rewrite 129.

  When reading this memory data, since the inversion flag 128 is 1, the memory state “1111” is read as it is.

  The second rewrite 130, the third 131, and the fourth 132 are also performed based on the flow of FIG. In the second and third rewrite times 130 and 131, the first write bit number> the third write bit number in the determination 109, so the process advances to 110, and the new write inverted data 123 is set as the write data 127. Writing to the memory cell is performed, and the inversion flag 128 is set to zero. When reading the memory data whose inversion flag 128 is 0, the memory state is inverted and read. Further, in the fourth rewrite number 132, the first write bit number 121 and the third write bit number 125 are compared in the determination 109, but in the case of the fourth rewrite number 132, the second determination 124 is NG. Therefore, since the process 107 is not performed and the third write bit number 125 is not counted, a sufficiently large number is set as the initial value of the third write bit number 125. The initial value of the third write bit number 125 is larger than the number of bits constituting the block. Here, since the block is composed of 4 bits, it is set to 5 or more. Therefore, in the fourth rewrite operation 132, the first write bit number is smaller than the third write bit number, and the process proceeds to processing 111, where the new write data 119 is written to the memory cell as the write data 127, The inversion flag 128 is set to 1.

  Next, the fifth rewrite operation 133 will be described. In the fifth rewrite operation 133, the memory state 118 before rewriting is “1000”. In the fifth rewrite operation 133, the new rewrite data is “1111”.

  In decision 102, it is determined whether or not the corresponding bit of data 119 is written as it is for the already written bit in memory state 118 (bit state is set to 0). In the fifth rewrite 133, the lower 3 bits of the memory state 118 are already written (“0”), and the corresponding lower 3 bits are “1” in the data 119, so the first determination is NG. Proceed to processing 103. In process 103, the second write bit number 122 is counted. The second write bit number 122 is the number of zeros of the data 119 as it is. It becomes 0 at the fifth rewrite operation 133.

  Next, in the determination 105, it is determined whether or not the corresponding bit of the new write inverted data 123 is also written (the bit state is set to 0) for the already written bit in the memory state 118. In the fifth rewrite operation 133, the lower 3 bits of the memory state 118 are already written (“0”), and the corresponding lower 3 bits of the inverted data 123 are also “0”, so the second determination is OK. Proceed to step 107. In process 107, the number of third write bits is counted. The third write bit number 125 is obtained by subtracting the number of zeros in the memory state 118 from the number of zeros in the inverted data 123. It is 1 at the fifth rewrite operation 133.

  Next, in the determination 108, it is determined whether both the first determination 120 and the second determination 124 are NG. In the fifth rewrite operation 133, the first determination 120 is NG, but the second determination 124 is OK.

  In the determination 109, the first write bit number 121 and the third write bit number 125 are compared. In the case of the fifth rewrite 133, since the first determination 120 is NG, the process 104 is not performed and the first write bit number 121 is not counted. Therefore, as the initial value of the first write bit number 121, Set a sufficiently large number. The initial value of the first write bit number 121 is set to a value larger than the number of bits constituting the block. Here, since the block is composed of 4 bits, it is set to 5 or more. Therefore, in the fifth rewrite operation 133, the first write bit number> the third write bit number, the process proceeds to processing 110, and the new write inversion data 123 is written to the memory cell as the write data 127, and the inversion is performed. The flag 128 is set to 0. This completes the fifth rewrite 133.

  When reading this memory data, since the inversion flag 128 is 0, the memory state “0000” is inverted and “1111” is read.

  Next, the sixth rewrite 134 will be described. In the sixth rewrite operation 134, the memory state 118 before the rewrite is “0000”. In the sixth rewrite 134, the new rewrite data is “0001”.

  In decision 102, it is determined whether or not the corresponding bit of data 119 is written as it is for the already written bit in memory state 118 (bit state is set to 0). At the sixth rewrite 134, all 4 bits of the memory state 118 are already written (“0”), and the lower 1 bit is “1” in the data 119, so the first determination is NG and the process 103 Proceed. In process 103, the second write bit number 122 is counted. The second write bit number 122 is the number of zeros of the data 119 as it is. The value is 3 in the sixth rewrite 134.

  Next, in the determination 105, it is determined whether or not the corresponding bit of the new write inverted data 123 is also written (the bit state is set to 0) for the already written bit in the memory state 118. At the sixth rewrite 134, all 4 bits of the memory state 118 are already written (“0”), and the upper 3 bits are “1” in the inverted data 123, so the second determination is NG and the process 106 Proceed to In process 106, the number of fourth write bits is counted. The fourth write bit number 126 is the number of 0s of the inverted data 123 itself. It is 1 at the sixth rewrite 134.

  Next, in the determination 108, it is determined whether both the first determination 120 and the second determination 124 are NG. In the sixth rewrite 134, the first determination 120 is NG, and the second determination 124 is also NG.

  In the process 112, the memory is erased and the memory state 118 is set to "1111", and then the process proceeds to the determination 113.

  In the determination 113, the second write bit number 122 and the fourth write bit number 126 are compared. If the second write bit number 122 ≦ the fourth write bit number 126, the process 115 (the same process as the process 111) is performed. If not, the process proceeds to process 114 (the same process as process 110). In the sixth rewrite operation 134, since the second write bit number> the fourth write bit number, the process proceeds to step 114, and the new write inversion data 123 is written to the memory cell as the write data 127, and the inversion is performed. The flag 128 is set to 0. This completes the sixth rewrite 134.

  When reading this memory data, since the inversion flag 128 is 0, the memory state “1110” is inverted and “0001” is read.

  As described above, when data rewriting as shown in FIG. 1B is performed in the first embodiment of the present invention, data is erased for the first time at the sixth rewriting number 134, and writing is also required to be minimal. Limited to memory cells. That is, in the present embodiment, by considering the relationship between already written data and newly written data, the number of times of erasing and writing is reduced more reliably than in the prior art, the stress on the memory cell is reduced, and the nonvolatile memory The lifetime of the semiconductor memory can be extended.

(Second Embodiment)
FIG. 2A is an example of a data rewrite flow in the second embodiment of the present invention, and FIG. 2B is a signal or data when data is written according to the rewrite flow of FIG. It shows the transition of variables in the writing program. When the function is realized by hardware, it becomes a value of the signal line, and when realized by the program, it becomes the value of the variable in the program.

  In FIG. 2B, reference numerals 217 to 222 are the same as 117 to 122 in FIG. 223 is data obtained by reversing the bit arrangement direction of new write data (new write upside down data). The underlined portion is written in the memory state 218 (bit state is 0). Corresponds to the position. Reference numeral 224 denotes a determination result obtained by the determination 205 in FIG. 225 is the third number of write bits counted in the process 207 of FIG. 2A. When the new write up / down inverted data 223 is to be written, it is newly erased without erasing from the memory state 218. Is the number of bits to be written (sets the bit state to 0). 226 is the fourth write bit number counted in the process 206 in FIG. 2A. When the new write up / down inverted data 223 is to be written, the memory state 118 is erased (all bits are set to 1). This is the number of bits to be newly written (set the bit state to 0). Reference numeral 227 denotes actual write data, which is data to be written in any one of the process 210, the process 211, the process 214, and the process 215 in FIG. 228 is an up / down inversion flag indicating whether or not the actual write data 227 is inverted in the bit vertical arrangement direction. In the case of 1, the data 219 is written as the write data 227 as it is newly written, When reading, the state of the memory is read as it is, and when it is 0, the newly written upside down data 223 is written as the write data 227, and when reading, the state of the memory is reversed in the bit up and down direction. Read (in reverse).

  The flow of data rewriting will be described with reference to FIGS. 2 (a) and 2 (b).

  In the second embodiment, new write upside down data 223 and upside down flag 228 are used in place of the new write inversion data 123 and the inversion flag 128 in the first embodiment. This is the same as the flow of data rewriting in the first embodiment.

  For example, the fifth rewrite operation 233 will be described. In the fifth rewrite 233, the memory state 218 before the rewrite is “1000”. In the fifth rewrite 233, the new rewrite data is “1110”.

  In decision 202, it is determined whether or not the corresponding bit of data 219 is written as it is (new bit is written) with respect to the already written bit in memory state 218. In the fifth rewrite 233, the lower 3 bits of the memory state 218 are already written (“0”), and in the data 219, the second and third bits from the lower are “1”. The determination is NG and the process 203 is proceeded. In the process 203, the second write bit number 222 is counted. The second write bit number 222 is the number of zeros of the data 219 as it is. It is 1 at the fifth rewrite 233.

  Next, in the determination 205, it is determined whether or not the corresponding bit of the newly written upside down data 223 is also written (the bit state is set to 0) for the already written bit in the memory state 218. In the fifth rewrite 233, the lower 3 bits of the memory state 218 are already written (“0”), and the lower 3 bits of the upside down data 223 are “1”, so the second determination is NG. Proceed to 206. In process 206, the number of fourth write bits is counted. The fourth write bit number 226 is the number of zeros of the upside down data 223 itself. It is 1 at the fifth rewrite 233.

  Next, in the determination 208, it is determined whether both the first determination 220 and the second determination 224 are NG. In the fifth rewrite 233, the first determination 220 is NG, and the second determination 224 is also NG.

  In process 212, the memory is erased, the memory state 218 is set to “1111”, and the process proceeds to decision 213.

  In the determination 213, the second write bit number 222 and the fourth write bit number 226 are compared. In the fifth rewrite operation 233, since the second write bit number = the fourth write bit number, the process proceeds to the process 215, and the new write data 219 is directly written into the memory cell as the write data 227. The inversion flag 228 is set to 1. This completes the fifth rewrite 233.

  When reading the memory data, since the upside down flag 228 is 1, the memory state “1110” is read as it is.

  As described above, when data rewriting as shown in FIG. 2B is performed in the second embodiment of the present invention, data erasure is performed for the first time at the fifth rewriting number 233, and writing is also required to be minimal. Limited to memory cells. That is, in the present embodiment, by considering the relationship between already written data and newly written data, the number of times of erasing and writing is reduced more reliably than in the prior art, the stress on the memory cell is reduced, and the nonvolatile memory The lifetime of the semiconductor memory can be extended.

(Third embodiment)
FIG. 3A is an example of a data rewrite flow according to the third embodiment of the present invention, and FIG. 3B is a signal or data when data is written according to the rewrite flow of FIG. It shows the transition of variables in the writing program. When the function is realized by hardware, it becomes a value of the signal line, and when realized by the program, it becomes the value of the variable in the program.

  In FIG.3 (b), 317-322 is respectively the same as 117-122 in FIG.1 (b). 323 is data (new write shift movement data) obtained by shifting the new write data in a predetermined direction by 1 bit, and the underlined portion has been written in the memory state 318 (bit state is 0). Corresponds to the position of. Reference numeral 324 denotes a determination result based on the determination 305 in FIG. 325 is the third write bit number counted in the process 307 of FIG. 3A. When the new write shift movement data 323 is to be written, it is newly erased from the memory state 318 without being erased. Is the number of bits to be written (sets the bit state to 0). Reference numeral 326 denotes a fourth write bit number counted in the process 306 of FIG. 3A. When new write shift movement data 323 is to be written, erasure is performed from the memory state 318 (all bits are set to 1). This is the number of bits to be newly written (set the bit state to 0). Reference numeral 327 denotes actual write data, which is data to be written in any one of the process 310, the process 311, the process 314, and the process 315 of FIG. Reference numeral 328 denotes a shift operation flag indicating whether or not the actual write data 327 is data obtained by shifting the new write data by 1 bit in a predetermined direction. 327 is written, and when reading, the state of the memory is read as it is, when it is 0, the new write shift movement data 323 is written as the write data 327, and when reading, the state of the memory is The new write shift movement data 323 is generated from the new write data 319 and read by shifting by 1 bit in the opposite direction to the 1 bit shift movement.

  The flow of data rewriting will be described using FIGS. 3 (a) and 3 (b).

  The third embodiment uses new write shift movement data 323 and shift operation flag 328 instead of the new write inversion data 123 and inversion flag 128 in the first embodiment. This is the same as the flow of data rewriting in the first embodiment.

  For example, the fourth rewrite 332 will be described. In the fourth rewrite 332, the memory state 318 before the rewrite is “0100”. In the fourth rewrite 332, the new rewrite data is “1100”.

  In decision 302, it is determined whether or not the corresponding bit of data 319 is written as it is for the already written bit in the memory state 318 (the bit state is set to 0). In the fourth rewrite 332, the first, second, and fourth bits from the lower state of the memory state 318 are already written (“0”), and the upper two bits are “1” in the data 319 as it is. The determination is NG and the process 303 is proceeded to. In the process 303, the second write bit number 322 is counted. The second write bit number 322 is the number of zeros of the data 319 as it is. It becomes 2 in the fourth rewrite 332.

  Next, in the determination 305, it is determined whether or not the corresponding bit of the new write shift movement data 323 is also written (the bit state is set to 0) for the already written bit in the memory state 318. In the fourth rewrite 332, the first, second, and fourth bits from the lower order of the memory state 318 are already written (“0”), and in the shift movement data 323, the first and fourth bits from the lower order are “1”. Therefore, the determination is NG, and the process proceeds to process 306. In process 306, the number of fourth write bits is counted. The fourth write bit number 326 is the number of zeros of the shift movement data 323 itself. It becomes 2 in the fourth rewrite 332.

  Next, in the determination 308, it is determined whether both the first determination 320 and the second determination 324 are NG. In the fourth rewrite 332, the first determination 220 is NG and the second determination 324 is also NG.

  In process 312, the memory is erased, the memory state 318 is set to “1111”, and the process proceeds to decision 313.

  In decision 313, the second write bit number 322 is compared with the fourth write bit number 326. In the fourth rewrite operation 332, since the second write bit number = the fourth write bit number, the process proceeds to the process 315, and the new write data 319 is directly written into the memory cell as the write data 327 and shifted. The operation flag 328 is set to 1. This completes the fourth rewrite 332.

  When reading the memory data, the shift operation flag 328 is 1, so the memory state “1100” is read as it is.

  As described above, when data rewriting as shown in FIG. 3B is performed in the third embodiment of the present invention, data is erased for the first time at the fourth rewriting number 332, and writing is also required to be minimal. Limited to memory cells. That is, in the present embodiment, by considering the relationship between already written data and newly written data, the number of times of erasing and writing is reduced more reliably than in the prior art, the stress on the memory cell is reduced, and the nonvolatile memory The lifetime of the semiconductor memory can be extended.

  In each of the first to third embodiments, the case where 01 inverted data, bit up / down alignment data, and shift movement data are used as actual write data other than data as newly written is individually described. However, it goes without saying that the number of times of writing / erasing can be further reduced by combining the respective methods. Further, the calculation method is not limited to 01 inversion, bit up / down alignment direction shift, and shift calculation, and any calculation method may be used as long as data can be converted and restored.

  Next, an example in which the flag has a multi-bit configuration in the first to third embodiments will be described.

  FIG. 4 (a) shows an example in which the flag has a multi-bit configuration in the first and second embodiments. 401 is a multi-bit configuration of an inversion flag and an up / down inversion flag. In this case, a 5-bit configuration is used. Yes. Reference numeral 402 is an inversion flag / upper / lower inversion flag having a 3-bit configuration, and 403 is an inversion flag / up / down inversion flag having 1 bit as in the case of the first and second embodiments described above. is there. Reference numeral 404 represents the operation content of data to be represented by an inversion flag / upside-down inversion flag, and the determination is made based on whether the number of 0s or the number of 1s in the flags 401, 402, 403 is even or odd.

  The flow of flag data during data rewriting will be described with reference to FIG.

  The second rewrite count 407 in FIG. 4A will be described.

  In the second rewrite 407, the memory state of the flag data before rewriting is “11110” for the 5-bit configuration flag 401, “110” for the 3-bit configuration flag 402, and “0” for the 1-bit configuration flag 403.

  In the second rewrite 407, the new write flag data is “11100” for the 5-bit configuration flag 401, “100” for the 3-bit configuration flag 402, and “1” for the 1-bit configuration flag 403.

  In the second rewrite 407, the 5-bit configuration flag 401 and the 3-bit configuration flag 402 do not have a bit that changes from 0 to 1, so that new write flag data can be represented only by writing without erasing data. However, the 1-bit configuration flag 403 requires erasing the flag area.

  As described above, when rewriting the flag data as shown in FIG. 4A, the 1-bit configuration flag 403 needs to be erased in the second rewrite, whereas the 5-bit configuration flag 401 and the 3-bit configuration flag 402 It can be seen that no erasure is required. By having a plurality of flags as described above, the number of times of erasing the flag area can be reduced. Therefore, an increase in the number of erasures can be expected by increasing the number of flag constituting bits.

  In the above example, the data calculation contents are determined by the even / odd numbers of the inversion flags 401, 402, and 403. However, any determination method can be used as long as the binary can be determined from a plurality of bits. It may be used.

  Next, FIG. 4B shows an example in which the flag has a multi-bit configuration in the third embodiment, and reference numeral 411 denotes a multi-bit configuration of the shift calculation flag. In this case, the flag has a 3-bit configuration. Reference numeral 412 denotes a shift operation flag having a 2-bit configuration, and reference numeral 413 denotes a shift operation flag having a 1-bit configuration, as described in the third embodiment. Reference numeral 414 represents a shift amount of data desired to be represented by the shift calculation flag.

  The shift movement amount that can be represented by the flag data will be described with reference to FIG.

  When the shift calculation flag has a 1-bit configuration 413, the shift movement amounts that can be expressed are two patterns of 0 bit 415 and 1 bit 416. By increasing the number of bits of the shift operation flag to the 2-bit configuration 412 and the 3-bit configuration 411, the range of the shift movement amount that can be expressed as 414 is expected to be expanded.

  Next, FIG. 5 shows a system to which the present invention is applied, and reference numeral 501 denotes a CPU that controls the system 500. Reference numeral 509 denotes a flash memory in the system 500, which is divided into a plurality of blocks of blocks 0 to m, and a calculation content flag indicating the calculation content of the data area 510 and the write data written in the data area for each block. It has a storage area 511 (the above-described inversion flag, upside-down inversion flag or shift calculation flag).

  507 is a data input to the flash memory 509, 508 is an operation content flag input, 503 is an address input, 512 is a read result of already written data, and 513 is a read result of the operation content flag.

  Reference numeral 504 denotes a data comparison / determination block, which compares new write data 502 with already written data 512 at the time of writing, and determines whether there is an operation result in which data can be written without erasing. Further, if there are a plurality of calculation results, data having fewer write bits is selected.

  The write data calculation block 506 receives the determination result 505 of the comparison / determination block 504, generates data 507 and a calculation content flag 508 that are actually written to the flash memory from the new write data 502, and writes them to the flash memory 509. .

  At the time of reading, the read data calculation block 514 generates data 515 from the calculation content flag 513 of the same data as the already written data 512 and transfers it to the CPU 501 as read data from the flash memory 509.

  For example, in the case of FIG. 1A, the CPU 501 performs the processing of 108 and 112 and the control of 101 to 116. The comparison / determination block 504 performs processes 102, 105, 109, and 113. The write data operation block 506 performs processes 103, 104, 106, 107, 110, 114, 111, and 115. The read data calculation block 514 reads the already written bits 102 and 105. The same applies to FIGS. 2A and 3A.

  The present invention can reduce stress on a memory cell due to new data writing to a nonvolatile semiconductor memory that stores, for example, instructions of a control microcomputer. For example, an instruction / data / program can be written to a rewritable nonvolatile memory. It is useful for the memory writer to be embedded and the algorithm at the time of memory rewriting of the system LSI with nonvolatile memory.

Flowchart and signal / variable transition diagram at the time of data rewriting in the first embodiment of the present invention Flowchart and signal or variable transition diagram at the time of data rewriting in the second embodiment of the present invention Flowchart and signal or variable transition diagram at the time of data rewriting in the third embodiment of the present invention The figure which shows the structural example of the flag in the 1st-3rd embodiment of this invention. Configuration diagram of data writing and reading in a system to which the present invention is applied

Explanation of symbols

501 CPU
502 Write data 503 Access address 504 Data comparison and determination block 506 Write data operation block 507 Write data 508 Write flag 509 Flash memory 510 Memory data area 511 in block units Operation flag area 512 corresponding to the memory data area Read data 513 Read flag 514 Read data operation block

Claims (9)

A memory cell array having a plurality of memory cells each storing different 1-bit data in a writing state and an erasing state, and dividing the memory cell array into blocks storing a plurality of bits of data; A non-volatile semiconductor memory for writing data to a cell,
When storing new data for each block,
The existing data stored in the block is compared with the new data, and any one of the plurality of memory cells constituting the existing data of the block is not changed from the written state to the erased state. A new data determination process for determining whether the new data can be written;
Comparing the existing data stored in the block and the processed data generated by performing a predetermined arithmetic process on the new data, any one of the plurality of memory cells constituting the existing data of the block A machining data determination process for determining whether or not the machining data can be written without changing the memory cell from the written state to the erased state;
A data erasing process for erasing all memory cells constituting the existing data of the block when determination results of both the new data determining process and the processed data determining process are not possible,
When the determination result of only the new data determination processing is possible among the new data determination processing and the processing data determination processing, the new data is written in the block, and the determination result of only the processing data determination processing is possible. When the processing data is written to the block, the determination result of both the new data determination processing and the processing data determination processing is possible, or after the erasure processing, the new data or the processing data is written to the block. A non-volatile semiconductor memory characterized by performing data writing processing for writing.   The data writing process performed when the determination results of both the new data determination process and the processed data determination process are possible is that the block in which the processed data is written out of the new data and the processed data is the block. 2. The nonvolatile memory according to claim 1, wherein the processed data is written when the number of memory cells to be changed from the erased state to the written state is reduced, and the new data is written otherwise. Semiconductor memory.   The data writing process performed after the erasing process is performed when the number of memory cells in the writing state in the block is smaller when the processed data is written out of the new data and the processed data. 3. The nonvolatile semiconductor memory according to claim 1, wherein data is written and the new data is written in other cases.   4. The data of the block in which the processed data is written is read out by performing a calculation process opposite to the calculation process performed when the processed data is generated. Non-volatile semiconductor memory. An arithmetic processing flag indicating an arithmetic processing performed when generating the processed data is provided in the memory cell array, and the arithmetic processing is processing for inverting each bit data of the new data,
In the data writing process, the arithmetic processing flag is reset when the new data is written, and the arithmetic processing flag is set when the machining data is written,
4. The data of the block is read when the arithmetic processing flag is reset, when the arithmetic processing flag is reset, and when the arithmetic processing flag is set, the data is inverted and read. Non-volatile semiconductor memory. An arithmetic processing flag indicating an arithmetic processing to be performed when generating the processed data is provided in the memory cell array, and the arithmetic processing is processing for reversing the bit vertical alignment direction of the new data,
In the data writing process, the arithmetic processing flag is reset when writing the new data, and the arithmetic processing flag is set when writing the machining data.
2. When reading the data of the block, if the arithmetic processing flag is reset, the data is read as it is, and if the arithmetic processing flag is set, the data is read in the reverse bit-up / down direction. 2. The nonvolatile semiconductor memory according to 2 or 3.   Whether the arithmetic processing flag is composed of a plurality of bits of memory cells, and the number of memory cells in the writing state or the number of memory cells in the erasing state among the memory cells constituting the arithmetic processing flag is an odd number 7. The non-volatile semiconductor memory according to claim 5, wherein it is determined whether the arithmetic processing flag is set or reset depending on whether it is an even number. An arithmetic processing flag indicating an arithmetic processing to be performed when generating the processed data is provided in the memory cell array, and the arithmetic processing is processing for shifting the new data by N bits in a predetermined direction (N is an integer of 1 or more). ,
In the data writing process, the arithmetic processing flag is reset when the new data is written, and the arithmetic processing flag is set when the machining data is written,
When reading the data of the block, if the arithmetic processing flag is reset, the data is read as it is, and if the arithmetic processing flag is set, the data is read by shifting N bits in the direction opposite to the predetermined direction. The nonvolatile semiconductor memory according to claim 1, 2 or 3.   9. The nonvolatile semiconductor memory according to claim 8, wherein the arithmetic processing flag is composed of a plurality of bits.

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