JP2005209925A - Lamination semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a lamination semiconductor substrate suitable for nitride semiconductor device formation wherein a nitride semiconductor device of high quality can be obtained with a good yield and at a low cost. <P>SOLUTION: In the lamination semiconductor substrate for forming a nitride semiconductor device like an LED, a GaN layer 12 wherein a lattice constant is greater than that of an AIN 11 and a plane direction is equal to a c-axial direction is grown and formed on the AlN 11 in which a plane direction is equal to the c-axial direction, and an n-type Al<SB>0.07</SB>Ga<SB>0.93</SB>N layer 53 whose lattice constant is smaller than that of the GaN layer 12, an activity layer 54 having a multiple quantum well (MQW) texture, a p-type Al<SB>0.38</SB>Ga<SB>0.62</SB>N layer 55 and a p-type Al<SB>0.07</SB>Ga<SB>0.93</SB>N layer 56 are formed in order on the GaN layer 12. Further, a p-type ohmic contact electrode 57 is formed, and bonding is performed on a CuW substrate 59 having high thermal conductivity through an Au/Sn film 58. After that, a sapphire substrate 1, the AlN layer 11 and the GaN layer 12 are eliminated, the n-type Al<SB>0.07</SB>Ga<SB>0.93</SB>N layer 53 is exposed, CMP polishing is performed, and an n-electrode 60 is formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a laminated semiconductor substrate, and more particularly to a laminated semiconductor substrate for forming a nitride semiconductor device, and emits light from a light emitting diode (LED), a short wavelength laser diode (LD) such as blue or violet. It is used for devices, light receiving elements, high frequency transistors, high voltage transistors, and the like.

  Light emitting devices using nitride semiconductors among III-V group compound semiconductors have already been put into practical use for blue LEDs and the like. Nitride semiconductor light-emitting devices that use gallium nitride (GaN) semiconductor layers do not have a suitable lattice constant or thermal expansion coefficient as a growth substrate for GaN. In many cases, a substrate is used and a single crystal film of GaN is grown thereon. However, when there is a large difference in physical mismatch between the substrate and the single crystal film deposited on the substrate, linear defects (dislocations) may occur in the single crystal film due to differences in lattice constant or crystal structure. A penetrating defect (threading dislocation) occurs. Since this threading dislocation acts as a non-light-emitting recombination center, the light emission characteristics are deteriorated by the influence of the density of threading dislocations.

  In order to alleviate the mismatch between the substrate and the single crystal film lattice constant deposited on the substrate, a buffer layer made of aluminum nitride (AlN) or GaN is formed on the sapphire substrate at a lower temperature than before, and the buffer layer is formed thereon. A two-stage film forming method for forming a GaN single crystal film is known. Patent Document 1 discloses a method of manufacturing a GaN-based semiconductor light-emitting element that uses this method, suppresses the occurrence of threading dislocations, maintains the flatness of the film, and has excellent light emission characteristics.

  On the other hand, it is considered that the material of the substrate of the GaN-based semiconductor device is preferably the same type of GaN substrate as the material of the GaN-based single crystal film to be formed thereon. That is, the GaN substrate is considered to be an optimal substrate for the GaN-based semiconductor device because the problem of mismatch of lattice constants does not occur when a GaN-based single crystal thin film is grown thereon.

  In addition, since the GaN substrate has a cleaving property, the process of cutting out the element chip from the wafer becomes easy, and when the LD is formed, the cleavage surface can be used as a mirror surface of the resonator. In addition, since the GaN substrate is conductive, it is possible to disperse the p electrode (anode electrode) and the n electrode (cathode electrode) vertically by providing an n electrode on the bottom surface of the GaN substrate. Therefore, it is not necessary to provide these two electrodes on the same plane, so that the electrode arrangement can be simplified and the chip area can be saved. Moreover, since the GaN substrate has high thermal conductivity, the heat dissipation is good.

  Such a GaN substrate is considered suitable as a substrate material for a GaN-based semiconductor device. However, further reduction in dislocation density is required for high-power LEDs whose characteristics are greatly influenced by the dislocation density, LEDs that emit light in the ultraviolet region, or LD in which high-density current flows.

  In view of such a problem, Patent Document 2 discloses a manufacturing method capable of controlling crystal defects when manufacturing a GaN substrate and realizing a low dislocation density. In this manufacturing method, dislocations are generated by allowing a single crystal GaN vapor phase growth surface to have a three-dimensional facet structure instead of a planar state, and to grow without embedding the facet structure while maintaining the facet structure. Then, planarity is imparted by mechanical processing, and a flat surface is obtained by polishing the surface. Patent Document 2 also discloses a manufacturing method in which single-crystal GaN is vapor-grown on a GaN substrate to a thickness of a plurality or more and then sliced in the thickness direction. Further, Patent Document 2 introduces a method of performing lateral overgrowth of GaN using a stripe mask or the like as a crystal growth method for reducing the dislocation density of the GaN substrate.

  In Patent Document 3, when a GaN substrate formed using lateral overgrowth is evaluated in detail with a microscope, the substrate surface is observed to have a width of about 10 μm to 40 μm corresponding to a dislocation concentration region (high dislocation density region). Are present at a pitch of the order of several hundred μm.

  However, when there is a depression (recess) corresponding to the dislocation concentration region on the upper surface of the GaN substrate, an attempt to form a GaN-based crystal film in order to form a desired element on the GaN substrate results in a normal single crystal. Under the reaction conditions for the vapor phase growth of GaN, the groove in the high dislocation density region is taken over as it is (film growth direction), so that a GaN-based crystal film cannot be grown on the groove, and a deep recess corresponding to the groove Occurs, and the flatness of the upper surface cannot be obtained sufficiently. The substrate in such a state is not suitable for an LED that requires a large area of the light emitting region. Further, the presence of this depression also has an adverse effect on the flat portion during crystal growth. Even if the GaN substrate is flattened by means such as processing, the orientation is not uniform in the c-axis direction. This means that there are different portions of crystal information in the plane. For this reason, when various growth conditions are changed, impurity doping and mixed crystallization are performed, crystal growth becomes non-uniform, and pits are regenerated.

  In addition, when such a deep recess is generated, the subsequent process is adversely affected, and the device characteristics are adversely affected. For example, in the photolithography process, the resist film thickness distribution is adversely affected, and the resist patterning accuracy by reactive etching is lowered. In particular, when manufacturing an LD, there is a problem that the patterning formation accuracy of the ridge portion is lowered, and the cleavage plane is displaced in the cleavage process, or the quantum well emission wavelength is periodically changed.

  Even if there is no depression in the dislocation concentration region, flatness is maintained, and an element such as an LED can be formed, an LED requiring a large area of the light emitting region has a high dislocation density portion in the chip surface. This deteriorates the characteristics of the device.

  GaN-based semiconductor devices also have an important role as light emitting devices in the ultraviolet region. For this purpose, AlInGaN, AlGaN, and GaN with a small In composition are used as the light emitting layer, and a laminated semiconductor structure that takes band offset and absorption into consideration in accordance with them is obtained. In many cases, the laminated semiconductor includes AlGaN. However, since AlGaN is a mixed crystal system, the crystal quality is currently poor. Further, cracks are likely to occur, and there are limitations on the Al composition ratio and film thickness.

AlN, which is considered as a nitride semiconductor substrate, requires a high temperature growth because of the high binding energy of the raw material Al, and it is difficult to control the growth. Therefore, high-quality AlN with a low dislocation density has not been obtained.
JP 2000-357820 A JP 2001-102307 A JP 2003-133650 A

  In the two-step film formation method in which a buffer layer made of AlN or GaN is formed on a sapphire substrate at a lower temperature than before, and a GaN single crystal film is formed on the buffer layer, the orientation of the three-dimensional nucleus generated at the initial stage of crystal growth Therefore, distortion occurs at the time of nuclear coalescence, and crystal grain boundaries are generated in a mosaic shape. As a result, threading dislocations occur at the boundaries of the crystal grain boundaries of the GaN layer obtained, and edge dislocations and spiral dislocations exist corresponding to rotation (twist) and tilt (tilt) with respect to the c-axis.

  In order to reduce the above threading dislocations, it can be achieved by reducing the density of crystal grain boundaries, that is, by reducing the density of three-dimensional nuclei (nuclear density), thereby reducing the overall dislocation density. It becomes possible. However, reducing the nuclear density slows the nuclear coalescence and enlarges the nucleus during the nuclear coalescence. On the other hand, at the time of nuclear coalescence, compressive stress is generated by the interaction, and the stress is considered to have a function of suppressing tilt and promoting twist. Such an effect is considered to be more remarkable as the size of the nucleus at the time of nuclear coalescence is smaller. Therefore, if the nucleus density is reduced and the nucleus at the time of nuclear coalescence is increased, a large tilt remains at the time of nuclear coalescence. As a result, the screw dislocation having a large Burger spectrum remains despite the decrease in the overall dislocation density, resulting in the occurrence of growth pits and the characteristics of the light-emitting element formed on the GaN layer. It is a cause of worsening. This effect is greater for helical dislocations and / or mixed dislocations than for edge dislocations.

  As described above, when a buffer layer made of conventional AlN or GaN deposited at a low temperature is formed and a GaN layer is grown on the buffer layer, screw dislocations remain, and generation of growth pits resulting therefrom There has been a problem of deteriorating the characteristics of the light emitting device formed on the GaN layer.

  In addition, when AlGaN or the like having a lattice constant smaller than that of GaN is laminated on GaN as a light emitting device in the ultraviolet region, there is a critical film thickness that causes relaxation due to the occurrence of cracks and the like, so there are limitations on the Al composition ratio and film thickness. It was.

  The present invention has been made in view of the above problems, and a semiconductor layer having a lattice constant larger than that of the semiconductor substrate is grown on a semiconductor substrate having a plane orientation aligned in the c-axis direction, and the semiconductor layer Is to improve the quality. Accordingly, it is possible to realize a high-quality nitride semiconductor device with high yield and low cost, and an object is to provide a laminated semiconductor substrate suitable for use in forming a nitride semiconductor device. . It is another object of the present invention to provide a light-emitting element including a crystal having a lattice constant smaller than that of the semiconductor substrate.

  A first aspect of the laminated semiconductor substrate of the present invention includes a first semiconductor layer having a plane orientation aligned in the c-axis direction, and a lattice constant that is formed on the first semiconductor layer and has a lattice constant greater than that of the first semiconductor layer. And a large second semiconductor layer. The semiconductor device further includes a third semiconductor layer formed on the second semiconductor layer and having a lattice constant smaller than that of the second semiconductor layer.

  A second aspect of the laminated semiconductor substrate of the present invention includes a first semiconductor layer having a plane orientation aligned in the c-axis direction, and a lattice constant greater than that of the first semiconductor layer formed on the first semiconductor layer. And a second semiconductor layer having a plane orientation aligned in the c-axis direction. The semiconductor device further includes a third semiconductor layer formed on the second semiconductor layer, having a lattice constant smaller than that of the second semiconductor layer and having a plane orientation aligned in the c-axis direction. .

  According to the laminated semiconductor substrate of the present invention, a high-quality nitride semiconductor device can be realized with good yield and low cost, and is suitable for use in forming a nitride semiconductor device. Further, by using the laminated semiconductor substrate of the present invention, an LED or LD capable of high output in a wide range from the ultraviolet region to visible light can be formed.

First Embodiment (Multilayer Semiconductor Substrate)
FIG. 1 schematically shows a cross-sectional structure of the laminated semiconductor substrate according to the first embodiment. In FIG. 1, for example, a first semiconductor layer 11 having a plane orientation aligned in the c-axis direction is grown on a sapphire substrate 1 having a C-plane as a main surface, and a lattice is formed on the first semiconductor layer 11. A second semiconductor layer 12 having a large constant is grown. These constitute a laminated semiconductor substrate 10 for laminating nitride semiconductors.

(First Semiconductor Layer) The first semiconductor layer 11 is a III-V group compound semiconductor, and is preferably a nitride semiconductor. Nitride semiconductor of the present invention have the general formula _{In x Al y Ga 1-xy} N can be represented by (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y ≦ 1), Al -containing nitride in this example It is a physical semiconductor and is an AlN single crystal, particularly an AlN layer having a smooth flat upper surface (mirror surface) whose plane orientation is aligned in the c-axis direction. Hereinafter, reference numeral 11 is commonly used for the first semiconductor layer and the AlN layer.

  (Second Semiconductor Layer) The second semiconductor layer 12 is a III-V group compound semiconductor and grows a single crystal layer having a lattice constant larger than that of the first semiconductor layer 11. The III-V group compound semiconductor is preferably a nitride semiconductor. Thereby, since the lattice mismatch is large at the interface between the first semiconductor layer 11 and the second semiconductor layer 12, the lattice-matched two-dimensional growth does not occur, and the lattice relaxation three-dimensional growth occurs from the initial growth stage. However, since the strain is not completely relieved, the second semiconductor layer 12 is microscopically compressed and strained in the a-axis direction. As a specific example of the second semiconductor layer 12, a GaN layer having a lattice constant larger than that of the AlN layer is desirable. Hereinafter, reference numeral 12 is commonly used for the second semiconductor layer and the GaN layer.

  Incidentally, the lattice constant (length of crystal axis a) of hexagonal AlN is 3.112 angstroms, and the lattice constant of GaN is 3.189 angstroms, and the difference between the two is about 2.5%.

  As described above, according to the first embodiment, when the GaN layer 12 is grown on the AlN layer 11 whose plane orientation is aligned in the c-axis direction, the lattice mismatch between AlN and GaN is large. Dimensional growth does not occur, and three-dimensional growth with lattice relaxation occurs from the beginning of growth. At that time, since the growth nuclei have the c-axis orientation of the AlN layer 11, it is possible to suppress the tilt even during the subsequent nuclear coalescence and further reduce the dislocation by reducing the nuclear density. As a result, it is possible to reduce the dislocation density of the GaN layer 12 and to suppress the occurrence of screw dislocations, and the GaN layer 12 has fewer edge dislocations and / or screw dislocations than the AlN layer 11. Formed to be. In this case, the edge dislocations are reduced by two digits or more, and at the same time, the screw dislocations are also reduced. Considering that it has been difficult to reduce the screw dislocations conventionally, the effect is great. FIG. 1 schematically shows dislocations (edge dislocations, spiral dislocations, and mixed dislocations) D existing in the GaN layer 12.

  As described above, in order to improve the orientation of initial growth nuclei in the GaN layer 12 using the c-axis orientation of the AlN layer 11, a full width at half maximum (Full Width at Half Maximum) of the AlN layer 11 by XRC (0002) diffraction is used. : FWHF) is preferably 90 arc seconds or less. This is generally about half or less than the half-value angle of 180 seconds or more for a GaN layer grown on sapphire via a low-temperature buffer layer. The AlN layer 11 has a high c-axis orientation of 60 arc seconds or less, and is suitable for further quality improvement. In producing the AlN layer 11, it is also effective to make a mixed crystal of several percent or less of GaN in order to obtain high c-axis orientation and surface flatness.

  As described above, when the GaN layer 12 is grown on the AlN layer 11 whose plane orientation is aligned in the c-axis direction, by devising the process so that the density of crystal nuclei at the initial stage of growth is controlled low, Even if the nucleation is delayed, the c-axis orientation of the nuclei is good, so there is no large distortion of screw dislocation or mixed dislocation due to tilt during merging, so it is possible to form a flat surface without pits or the like It is.

Second Embodiment (Multilayer Semiconductor Substrate)
FIG. 2 is a cross-sectional view schematically showing the laminated semiconductor substrate according to the second embodiment. When the laminated semiconductor substrate shown in FIG. 2 realizes a nitride semiconductor device such as an LED or a light receiving element using the laminated semiconductor substrate 10 according to the first embodiment, a third semiconductor substrate is formed on the GaN layer 12. A semiconductor layer 13 is formed.

  The third semiconductor layer 13 has a lattice constant close enough to allow lattice matching on the second semiconductor layer 12. The second semiconductor layer 12 undergoes three-dimensional growth simultaneously with lattice relaxation with respect to the first semiconductor layer 11, and at this time, dislocation propagation is suppressed. Since the third semiconductor layer 13 is lattice-matched on the second semiconductor layer 12, the dislocation of the second semiconductor layer 12 is taken over. Therefore, if the second semiconductor layer 12 is low dislocation, the third semiconductor layer 13 is also low dislocation.

Here, the second semiconductor layer 12 is formed so that the screw dislocation density is 3 × 10 ⁷ / cm ² or less, more preferably 3 × 10 ⁶ / cm ² or less. The third semiconductor layer 13 is formed to have the same screw dislocation density as the second semiconductor layer 12. Further, when the second semiconductor layer 12 has a mirror surface whose plane orientation is aligned in the c-axis direction, the third semiconductor layer 13 having a lattice constant smaller than that of the second semiconductor layer 12 may be grown thereon. Cracks, pits and dislocations are suppressed.

  (Third Semiconductor Layer) When a single crystal layer having a lattice constant smaller than that of the second semiconductor layer 12 is grown as the third semiconductor layer 13, the second semiconductor layer 12 and the third semiconductor layer 13 Lattice strain is generated at the interface, and tensile strain is applied to the third semiconductor layer 13. In this case, since the second semiconductor layer 12 is subjected to compressive stress from the first semiconductor layer 11, the tensile strain from the second semiconductor layer 12 is reduced in the third semiconductor layer 13. Therefore, the tensile strain of the third semiconductor layer 13 is relaxed, and the generation of cracks, pits, and dislocations is suppressed. Here, when the magnitude relationship between the lattice constants G1, G2, and G3 of the first semiconductor layer 11, the second semiconductor layer 12, and the third semiconductor layer 13 is arranged, G2 ≧ G3> G1. .

As a specific example of the third semiconductor layer 13, a GaN-based material of the same kind as the GaN layer 12 and having a lattice constant smaller than that of a GaN single crystal is Al _x Ga _1-x N (0 <x ≦ 0.1) layer. Here, the mixed crystal ratio of Al is 0.1 or less, and x> 0.01, preferably x = 0.03 to 0.08. Incidentally, the lattice constant (crystal axis length) of the Al _x Ga _1-x N (0 <x ≦ 0.1) layer 13 is 3.185 angstroms when x = 0.05, and the lattice constant of GaN is 3.189 angstroms. The difference between them is about 0.125%. This is mainly used when forming an ultraviolet light emitting device of 370 nm or less. In addition, the same lattice constant as that of a GaN single crystal indicates a structure used for a light emitting device in the visible region, and is composed of GaN / InGaN, which tends to increase the lattice constant as a whole. The strain in this case is a compression system, and since it does not cause cracks, it is unlikely to be a big problem, so it is treated as the same lattice constant.

  When the GaN layer 12 is grown on the AlN layer 11, an ELO (Epitaxial Lateral Overgrown) growth method may be combined. In this case, for example, five variations (I) to (V) as schematically shown in FIGS. 11 to 15 can be considered as the ELO growth method.

In the ELO growth method (I), first, as shown in FIG. 11A, a mask (for example, made of a SiO ₂ film) 90 having an opening on the upper surface of the AlN layer 11 with good c-axis orientation on the sapphire substrate 1. Form. In this case, the opening width of the mask 90 is about 3 μm to 10 μm, and the mask width between the openings is about 5 μm to 30 μm. Next, as shown in FIG. 11 (b), when the GaN layer 12a is grown from the AlN layer 11 through the mask opening in the c-axis direction, the GaN layer eventually becomes c-axis as shown in FIG. 11 (c). While growing in the direction, it grows in the lateral direction (on the mask) and the adjacent GaN layers merge together. As a result, the GaN layer 12 having a flat upper surface is formed. In this case, since the GaN layer grown on the opening inherits the c-axis orientation of the AlN layer 11 and has good c-axis orientation, the dislocation density is low, and the GaN layer on the mask also has good c-axis orientation. Distortion (tilt) is suppressed, and the dislocation density is low.

  In the ELO growth method (II), first, as shown in FIG. 12A, an etching mask 100 having an opening on the upper surface of the AlN layer 11 with good c-axis orientation on the sapphire substrate 1 is formed. In this case, the opening width of the etching mask 100 is about 3 μm to 30 μm, and the mask width between the openings is about 3 μm to 15 μm. Then, as shown in FIG. 12B, the AlN layer 11 is selectively etched by anisotropic etching to form a groove in the AlN layer 11. Next, after removing the etching mask 100, when the GaN layer 12a is grown on the AlN layer 11, the GaN layer grows in the c-axis direction as shown in FIG. The GaN layers which grow also on the upper part of the groove and are adjacent in the lateral direction are combined. As a result, the GaN layer 12 having a flat upper surface and good c-axis orientation is formed. Note that the groove portion of the AlN layer 11 may be in a hollow state.

  In the ELO growth method (III), first, a GaN layer 12a is formed on an AlN layer 11 with good c-axis orientation on the sapphire substrate 1, as shown in FIG. Then, an etching mask (not shown) having an opening is formed on the upper surface of the GaN layer 12a. Next, as shown in FIG. 13B, the GaN layer 12a and the AlN layer 11 are selectively etched by anisotropic etching to form grooves in the GaN layer 12a and the AlN layer 11. Then, after removing the etching mask, when the GaN layer 12a is regrown, the GaN layer grows in the c-axis direction as shown in FIG. 13C, and also in the lateral direction (above the groove). The grown GaN layers adjacent in the lateral direction are combined. As a result, the GaN layer 12 having a flat upper surface and good c-axis orientation is formed. Note that the groove portion of the AlN layer 11 may be in a hollow state.

  In the ELO growth method (IV), first, as shown in FIG. 14A, a GaN layer 12a is formed on an AlN layer 11 with good c-axis orientation on the sapphire substrate 1, and an opening is formed on the upper surface of the GaN layer 12a. An etching mask (not shown) having a portion is formed. Then, as shown in FIG. 14B, the GaN layer 12a is selectively etched to an intermediate depth by anisotropic etching to form a groove in the GaN layer 12a. Then, after removing the etching mask, when the GaN layer 12a is regrown, as shown in FIG. 14C, the GaN layer grows in the c-axis direction and also grows in the lateral direction. GaN layers adjacent to each other are combined. As a result, the GaN layer 12 having a flat upper surface and good c-axis orientation is formed.

  In the ELO growth method (V), first, as shown in FIG. 15A, a GaN layer 12a is formed on an AlN layer 11 with good c-axis orientation on the sapphire substrate 1, and an opening is formed on the upper surface of the GaN layer 12a. An etching mask (not shown) having a portion is formed. Then, as shown in FIG. 15B, the GaN layer 12a is selectively etched to the bottom by anisotropic etching to form a groove in the GaN layer 12a. When the GaN layer 12a is regrown after removing the etching mask, the GaN layer grows in the c-axis direction and grows in the lateral direction as shown in FIG. 15C. GaN layers adjacent to each other are combined. As a result, the GaN layer 12 having a flat upper surface and good c-axis orientation is formed.

(Impurity concentration of second semiconductor layer) For example, the second semiconductor layer 12 may be used as an n-contact layer. In that case, the impurity concentration of the second semiconductor layer is set to 1 × 10 ¹⁸ / cm ³ or more and 5 × 10 ¹⁸ / cm ³ or less. As the n-type impurity, elements of Group IVB and VIB of the periodic table such as Si, Ge, Se, S, and O are selected, and Si, O, Ge, and S are preferably n-type impurities.

(Function of Third Semiconductor Layer) The Si—Al _x Ga _1-x N (0 <x ≦ 0.1) layer 13 formed on the GaN layer 12 can be used as a cladding layer and an n contact layer. Become. In this case, the impurity concentration of the third semiconductor layer 13 is 1 × 10 ¹⁸ / cm ³ or more and 1 × 10 ²⁰ / cm ³ or less. This upper limit value is larger than the upper limit value of the impurity concentration of the second semiconductor layer 12. This is because AlGaN has a larger allowable amount with respect to the impurity concentration than GaN, and is effective in reducing the resistance of the device.

  Here, there is a method in which the semiconductor substrate is bonded to a supporting substrate, and then the sapphire substrate and some semiconductor layers are removed to form an element. In that case, since the GaN layer 12 contains an n-type impurity and can be used as an n-contact layer that provides a good ohmic contact when an n-electrode is formed on the back surface thereof, the sapphire substrate 1 and the AlN layer 11 are used. When the n electrode is formed on the back surface of the GaN layer 12, the thickness of the entire light emitting element is reduced and heat generated by light emission is easily dissipated. Here, in order to remove the AlN layer 11 and the like, methods such as polishing, grinding, and laser irradiation are used. Further, when the emission wavelength of the active layer of the light emitting element is set to a wavelength range of 400 nm or less, it is preferable to use the AlGaN layer as the n contact layer and remove the GaN layer 12.

  According to the second embodiment described above, the third semiconductor layer 13 is lattice-matched on the second semiconductor layer 12 of the laminated semiconductor substrate 10 having the effects described in the first embodiment. If the second semiconductor layer 12 is a low dislocation, the third semiconductor layer 13 is also a low dislocation.

  Therefore, when a nitride semiconductor device is formed by laminating a nitride semiconductor layer having good crystallinity on the laminated semiconductor substrate of the second embodiment, the device manufacturing process is stabilized, and a desired device can be obtained with a high yield. Can be realized at a cost.

In the first embodiment and the second embodiment, the heterogeneous substrate for growing the nitride semiconductor is not particularly limited as long as it is a substrate made of a material different from the nitride semiconductor. An insulating substrate such as sapphire or spinel (MgAl ₂ O ₄ ) having any one of the plane, R plane, and A plane, or SiC (including 6H, 4H, 3C), ZnS, ZnO, Si, Examples include GaAs, diamond, and oxide substrates such as lithium niobium oxide and neodymium gallate that are lattice-bonded to a nitride semiconductor. Of the different substrates, sapphire is preferable, and a sapphire substrate having a C-plane as a main surface is more preferable. The C-plane of sapphire may be off-angle, and the off-angle angle θ is in the range of 0.01 ° to 0.5 °, preferably 0.05 ° to 0.2 °.

Further, a nitride semiconductor may be grown on a different substrate via a buffer layer. As this buffer layer, a nitride semiconductor represented by the general formula Al _a Ga _1-a N (0 ≦ a ≦ 0.8) is used. The thickness of the buffer layer is preferably 0.002 to 0.5 μm. The growth temperature of the buffer layer is preferably 200 to 900 ° C. Thereby, dislocations and pits on the nitride semiconductor layer can be reduced.

  In addition, a nitride semiconductor substrate can be used as the first semiconductor layer. In this case, as the thick film of the nitride semiconductor substrate, a thick film (several tens of μm or more) that can be processed by the device is required.

<Third Embodiment> (Multilayer Semiconductor Substrate)
In the third embodiment, after the first semiconductor layer 11 is grown on the heterogeneous substrate and the second semiconductor layer 12 is grown thereon, a mask 90 for performing ELO growth as described above is formed. The third semiconductor layer 13 is grown in the lateral direction. Thus, the third semiconductor layer 13 grown on the mask also has good c-axis orientation and a low dislocation density.

<First Application Example> (Nitride Semiconductor Device)
When realizing a nitride semiconductor device such as an LED or a light receiving element using the laminated semiconductor substrate according to the present invention, at least an n-type nitride semiconductor layer and a p-type nitride semiconductor layer are included on the laminated semiconductor substrate. By forming the semiconductor layer with good crystallinity, a high-quality nitride semiconductor device can be obtained with a high yield.

<Second Application Example> (Nitride LD)
When realizing a nitride LD using the laminated semiconductor substrate according to the present invention, at least an n-type nitride semiconductor layer and / or a p-type nitride used as an optical guide layer for forming an optical waveguide region on the laminated semiconductor substrate. By forming a semiconductor layer including a semiconductor layer with good crystallinity, a high-quality nitride LD can be obtained with a high yield.

[Example]
Hereinafter, although several examples of the present invention are shown, the present invention is not limited to these examples.

[Embodiment 1] FIG. 3 is a sectional view schematically showing the structure of an LED as an example of a nitride semiconductor device using the laminated semiconductor substrate of the present invention. In this LED, on a sapphire substrate 1 having a C-plane as a main surface, an AlN layer 11 having a plane orientation aligned in the c-axis direction is formed as a nitride semiconductor substrate having a plane orientation aligned in the c-axis direction. The upper surface is a mirror surface. On the AlN layer 11, a GaN layer 12 having a larger lattice constant is grown. A nitride semiconductor layer is laminated on the laminated semiconductor substrate 10 composed of the sapphire substrate 1, the AlN layer 11, and the GaN layer 12 to constitute an LED.

  Next, a process for continuously growing the AlN layer 11, the GaN layer 12, and the nitride semiconductor layer thereon, for example, in the same apparatus will be described.

(First semiconductor layer)
The sapphire substrate 1 is set in the reaction vessel of the MOCVD apparatus, and the temperature is raised to 1000 ° C. or higher, preferably 1200 ° C. During the temperature increase, nitrogen (N ₂ ) and / or hydrogen (H ₂ ) is allowed to flow as a carrier gas. Next, at least 1100 ° C., preferably after reaching 1200 ° C., at least ammonia (NH ₃ ) gas and source gas are supplied. At this time, the supply amount of NH ₃ is 0.0005 mol to 0.01 mol, preferably 0.0008 mol to 0.008 mol. The supply amount of the raw material gas, for example, TMA (trimethylaluminum) is 0.1 μmol to 10 μmol, preferably 0.5 μmol to 5 μmol. Here, the V / III ratio is 50 to 100,000, and the pressure is 50 to 100 torr. An AlN film having a thickness of about 0.2 to 3 μm is grown by the growth for 3 hours or more under the above conditions.

  Note that when the AlN film contains Ga, the surface can be easily mirror-finished. Specifically, when about 0.1 μmol to 10 μmol of TMG (trimethylgallium) is supplied during the growth of the AlN film, AlGaN is obtained. The AlN film preferably contains Ga in an amount of 0.1 to 2%.

Note that the timing of starting the supply of the NH ₃ gas is preferably the same as the source gas or slightly delayed. Further, the source gas and the NH ₃ gas may be supplied alternately.

(Second semiconductor layer)
As a first step, the supply amount of NH ₃ is set to 0.0005 mol to 0.05 mol, and the supply amount of TMG is set to 30 μmol to 100 μmol. Here, the V / III ratio is 5 to 1650, and the pressure is 700 to 850 torr. By growing for 5 minutes or longer under the above conditions, a three-dimensional growth nucleus of GaN having a thickness of 0.05 to 0.3 μm grows.

As a second step, the supply amount of NH ₃ is set to 0.005 mol to 0.3 mol, and the supply amount of TMG is set to 20 μmol to 200 μmol. Here, the V / III ratio is 2.5 to 15000, and the pressure is 700 to 850 torr. Under the above conditions, a low dislocation GaN film having a thickness of 1 μm to 10 μm is grown by growth for 0.5 hour or more.

  In addition, it is preferable that the temperature and pressure in the first step and the second step, or the V / III ratio are individually changed to match conditions suitable for three-dimensional nucleus growth and planarization. For example, by setting the condition that the density of three-dimensionally grown nuclei is low in the initial stage of crystal growth, it is possible to keep the dislocation density generated at the time of nuclear coalescence low, and since the c-axis orientation of the nuclei is high, This tilt is also suppressed. In other words, the GaN layer 12 inherits the information in the c-axis direction of the AlN layer 11 but has a relaxed crystal state in the a-axis direction, and has edge dislocations and / or helical dislocations compared to the AlN layer 11. It is formed so as to decrease.

(Nitride semiconductor layer)
First, the n-type contact layer 44 is grown on the GaN layer 12. The n-type contact layer 44 has a composition that is larger than the band gap energy of the active layer 45 to be formed later, and is preferably Al _j Ga _1-j N (0 <j <0.3). The thickness of the n-type contact layer 44 is not particularly limited, but is preferably 1 μm or more, more preferably 3 μm or more. The impurity concentration of the n-type contact layer 44 is not particularly limited, but is preferably 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ , more preferably 5 × 10 ^{18 to} 5 × 10 ¹⁹ / cm ^3. It is. Further, the n-type impurity concentration may be inclined. In addition, by tilting the composition of Al, it also functions as a cladding layer for confining carriers.

Next, a light emitting layer (active layer) 45 is formed. The active layer 45 includes a well layer composed of at least Al _a In _b Ga _1-ab N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, a + b ≦ 1), and Al _c In _d Ga _1-cd N (0 ≦ c ≦ 1, 0 ≦ d ≦ 1, and c + d ≦ 1).

  The thickness of the well layer is preferably 1 nm to 30 nm, more preferably 2 nm to 20 nm, and still more preferably 3.5 nm to 20 nm. The number of well layers is not particularly limited, but it is preferable to control the thickness of the entire active layer in consideration of the minority carrier diffusion length.

The barrier layer is preferably doped with p-type impurities or n-type impurities or undoped, and more preferably doped with n-type impurities or undoped, as in the case of the well layer. . For example, when an n-type impurity is doped in the barrier layer, the concentration needs to be at least 5 × 10 ¹⁶ / cm ³ or more. For example, the ^{LED, 5 × 10 16 / cm} 3 or more, preferably 1 × 10 ²⁰ / cm ³ or less.

In the LED of Example 1, the barrier layer needs to use a nitride semiconductor having a larger band gap energy than the well layer. In particular, AlInGaN emission wavelength of the well layer is in the following regions 380 nm, represented by as a barrier layer, the general formula _{Al c In d Ga 1-cd} N (0 <c ≦ 1,0 ≦ d ≦ 1, c + d <1) It is preferable to use a quaternary mixed crystal of GaN or a ternary mixed crystal of AlGaN.

Next, a plurality of p-type nitride semiconductor layers are formed on the active layer 45. First, the p-type cladding layer 46 has a composition larger than the band gap energy of the active layer 45, and is not particularly limited as long as carriers can be confined in the active layer 45, but Al _k Ga _1-k N (0 ≦ k < 1) is used, in particular _{Al k Ga 1-k N (} 0 <k <0.4) is preferable. The film thickness of the p-type cladding layer 46 is not particularly limited, but is preferably 0.005 to 0.3 μm, more preferably 0.01 to 0.2 μm. The p-type impurity concentration of the p-type cladding layer 46 is preferably 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , more preferably 1 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ . When the p-type impurity concentration is in the above range, the bulk resistance can be reduced without reducing the crystallinity. The p-type cladding layer 46 may be a single layer or a multilayer film layer (superlattice structure). In the case of a multilayer film layer, it may be a multilayer film layer composed of the above Al _k Ga _1-k N (0 ≦ k <1) and a nitride semiconductor layer having a smaller band gap energy. For example, as a nitride semiconductor layer having a small band gap energy, as in the case of the n-type cladding layer 44, In _l Ga _1-l N (0 ≦ l ≦ 1), Al _m Ga _1-m N (0 ≦ m <1, m> l). In the case of a superlattice structure, the thickness of each layer forming the multilayer layer is preferably 10 nm or less, more preferably 7 nm or less, and even more preferably 1 to 4 nm. When the p-type cladding layer 46 is a multilayer film composed of a layer having a large band gap energy and a layer having a small band gap energy, one of the layer having a large band gap energy and the layer having a small band gap energy is doped with a p-type impurity. May be. Further, when impurities are doped into both the layer having a large band gap energy and the layer having a small band gap energy, the doping amount may be the same or different.

A p-type contact layer 47 is formed on the p-type cladding layer 46. The p-type contact layer 47 is made of Al _f Ga _1-f N (0 ≦ f <1). In particular, the p-type contact layer 47 is made of Al _f Ga _1-f N (0 ≦ k <0.3). Good ohmic contact is possible with the p-type electrode 48 which is an ohmic electrode to be formed. The p-type impurity concentration of the p-type contact layer 47 is preferably 1 × 10 ¹⁸ / cm ³ or more.

  Thereafter, a part of the n-type contact layer 44 is exposed by etching away a part of the p-type contact layer 47, the p-type cladding layer 46, the active layer 45, and the n-type contact layer 44, and n is exposed on the exposed surface. An electrode 50 is formed to obtain an LED.

  The formation of the nitride semiconductor layer is not limited to the metal organic chemical vapor deposition (MOCVD) method, and can be performed using a halide vapor phase epitaxy (HVPE) method, a molecular beam epitaxy (MBE) method, or the like.

[Example 2] Example 2 is Daisuke Morita et.al, "High Output Power 365 nm ULTRAVIOLET Light Emitting Diode of Gan-Free Structure" jpn.j.Appl.Phys.Vol.41 (2002) pp.L 1434- An LED manufactured using the laminated semiconductor substrate of the present invention with reference to the structure disclosed in L1436.

4A and 4B schematically show the manufacturing process of the LED of Example 2. FIG. First, as shown in FIG. 4A, after the AlN layer 11 and the GaN layer 12 are grown on the sapphire substrate 1 by the same process as in the first embodiment, the following layers are sequentially grown. First, an n-type Al _0.07 Ga _0.93 N layer 53 is formed with a thickness of 2.5 μm. Here, the n-type impurity is Si. Next, an active layer (MQW active layer) 54 having a multi-quantum well (MQW) structure composed of five pairs of a well layer and a barrier layer is formed. Here, the well layer is made of undoped In _0.01 Ga _0.99 N and has a thickness of about 5 nm. The barrier layer is Si—Al _0.09 Ga _0.91 N and has a thickness of 20 nm. Next, a p-type Al _0.38 Ga _0.62 N layer 55 is formed with a thickness of 30 nm. Here, the p-type impurity is Mg. Next, a p-type Al _0.07 Ga _0.93 N layer 56 is formed with a thickness of 0.12 μm. Here, the p-type impurity is Mg. Next, the p-type ohmic contact electrode 57 is formed by vapor deposition. At this time, by using Rh so that the p-type ohmic contact electrode 57 has high reflection characteristics, a high reflectivity is obtained at the interface with the p-type Al _0.07 Ga _0.93 N layer 56 for an emission wavelength of 365 nm. It is done. Next, a thin Au / Sn film 58 is formed on the p-type ohmic contact electrode 57.

Next, as shown in FIG. 4B, the p-type ohmic contact electrode 57 side is bonded to a substrate having high thermal conductivity (for example, a CuW substrate 59) through an Au / Sn film 58. Thereafter, the n-type Al _0.07 Ga _0.93 N layer 53 is exposed by removing the sapphire substrate 1, the AlN layer 11, and the GaN layer 12 by performing laser irradiation from the back side of the sapphire substrate 1, for example. After the exposed surface of the n-type Al _0.07 Ga _0.93 N layer 53 is polished by, for example, CMP (Chemical Mechanical Polishing), the n-electrode 60 is formed on the polished surface in a predetermined mesh shape, for example. Then, the CuW substrate 59 is mounted on a lead frame (not shown) having a low thermal resistance.

According to the structure of the LED manufactured through such a process, heat dissipation by the CuW substrate 59 is good, and a high light emission output can be obtained. As described above, the structure of the LED after the sapphire substrate 1, the AlN layer 11, and the GaN layer 12 are removed is similar to the structure of the conventional LED, but the n-type Al _0.07 Ga _0.93 N layer 53 is used. The MQW active layer 54, the p-type Al _0.38 Ga _0.62 N layer 55, and the p-type Al _0.07 Ga _0.93 N layer 56 were sequentially grown on the AlN layer 11 and the GaN layer 12 having the same plane orientation in the c-axis direction. There is a difference in that it is.

[Example 3] An LED according to Example 3 was obtained by modifying part of Example 2 to form a p-type ohmic contact electrode 57, and then p-type Al _0.07 Ga _0.93 N layer 56, p-type Al _0.38 Ga _0.62 The N layer 55, the MQW active layer 54, and the n-type Al _0.07 Ga _0.93 N layer 53 are partially etched away to expose a part of the GaN layer 12, and an n electrode (not shown) is formed on the exposed surface. It is also possible to obtain an LED having the above structure.

[Example 4] Compared with the LED according to Example 2 described above, the LED according to Example 4 is characterized in that the well layer (undoped In _0.01 Ga _0.99 N) of the MQW active layer has a thickness of 7 nm. The difference is that the Al composition of the layer is 11%, the Al composition of the p-type Al _0.38 Ga _0.62 N layer is 23%, and the thickness is 25 nm, and the others are the same. With such a structure, an LED having substantially the same characteristics as in Example 2 can be obtained.

[Embodiment 5] A structure in which a part of the embodiment 4 is changed and a part of the upper surface of the GaN layer 12 is exposed and an n-electrode (not shown) is formed on the exposed surface as in the embodiment 3. It is also possible to obtain an LED with.

[Example 6] Example 6 is an example of the laminated semiconductor substrate shown in FIG. 2, and has a lattice constant smaller than that on the GaN layer 12 of the laminated semiconductor substrate (wafer) 10 shown in FIG. An Al _x Ga _1-x N (0 <x ≦ 0.1) layer 13 is grown as a third semiconductor layer. These sapphire substrate 1, AlN layer 11, GaN layer 12 and Al _x Ga _1-x N (0 <x ≦ 0.1) layer 13 constitute a laminated semiconductor substrate for laminating a nitride semiconductor thereon. doing.

When forming the laminated semiconductor substrate of Example 6, first, after forming the GaN layer 12 as described in Example 1, an Al _x Ga _1-x N (0 <x ≦ 0.1) layer is formed thereon. 13 are stacked. Specifically, the substrate temperature is set to a predetermined temperature, and the Al _0.05 Ga _0.95 N layer 13 is grown to about 10 μm using hydrogen as the carrier gas and ammonia, TMG and TMA as the source gas. The average growth direction of the Al _0.05 Ga _0.95 N layer 13 is the c-axis direction.

  Therefore, when a nitride semiconductor device (LED, LD, etc.) is formed by laminating a nitride semiconductor layer with good crystallinity on this laminated semiconductor substrate, the device manufacturing process is stabilized, the device yields and the cost is low. Can be realized.

[Example 7] Example 7 is an LED manufactured using the laminated semiconductor substrate of the present invention with reference to the nitride semiconductor light emitting device disclosed in Japanese Patent Application Laid-Open No. 9-153642 of the present applicant. FIG. 5 is a cross-sectional view schematically showing the structure of the LED of Example 7. The LED shown in FIG. 5 is an element using a laminated semiconductor substrate including the sapphire substrate 1, the AlN layer 11, the GaN layer 12, and the Al _x Ga _1-x N layer 13 in Example 6 described above with reference to FIG. After being formed, it is cut out into chips. In this case, the GaN layer 12 of the laminated semiconductor substrate obtained in Example 6 is used as a buffer layer, and the Si—Al _b Ga _1-b N layer 13 thereon is used as an n-type contact layer and an n-type cladding layer. doing. On the _{Si-Al b Ga 1-b} N layer 13, a single quantum well (SQW: Single-Quantum-Well ) active layer 16 having the structure or a MQW structure, p-type cladding layer 17, p-type contact layer 18 is formed Has been. A part of the p-type contact layer 18, the p-type cladding layer 17 and the active layer 16 is removed by etching, and the n-type cladding layer 13 is exposed. A p-electrode 14 is formed on the p-type contact layer 18, and an n-electrode 15 is formed on the n-type cladding layer 13.

  Then, after the wafer is cut into 320 μm square chips, it is placed on a lead frame having a cup shape and molded with an epoxy resin to constitute an LED element.

When the active layer 16 has an SQW structure or an MQW structure, a light emitting element having a very high output can be obtained. Here, SQW and MQW are structures of active layers that can emit light between quantum levels by non-doped InGaN. For example SQW active layer having a single composition _{In x Al y Ga 1-xy} N (0 ≦ X, y <1), be a layer that is made of, for example, _{In x Ga 1-x N (} 0 ≦ X <1) Intensity light emission between quantum levels can be obtained by setting the film thickness of In _x Ga _1-x N to 10 nm or less, more preferably 7 nm or less. The MQW active layer is a multilayer film in which a plurality of thin films of In _x Ga _1-x N (including X = 0, X = 1) having different composition ratios are stacked. In this way, when the active layer has the SQW structure or the MQW structure, light emission of about 365 nm to 660 nm can be obtained by light emission between quantum levels. As described above, the thickness of the quantum well layer is preferably 7 nm or less. In the MQW structure, the well layer is preferably composed of In _x Ga _1-x N, and the barrier layer is also composed of In _y Ga _1-y N (y <x, y = 0 included). Particularly preferably, when the well layer and the barrier layer are formed of InGaN, the active layer having good crystallinity can be obtained because it can be grown at the same temperature. When the thickness of the barrier layer is 15 nm or less, more preferably 12 nm or less, a high-power light-emitting element can be obtained.

  As described above, when the thickness of the quantum structure well layer is 7 nm or less, more preferably 5 nm or less, an element having a high light emission output can be realized. This indicates that this film thickness is less than the critical film thickness of the InGaN active layer. Similarly, in the case of the MQW structure, it is desirable to adjust the thickness of the well layer to 7 nm or less and the thickness of the barrier layer to 15 nm or less. Here, in the ultraviolet light emitting active layer, the thickness of the barrier layer is 10 to 20 nm.

The p-type cladding layer 17 in contact with the active layer 16 needs to be p-type Al _y Ga _1-y N (0 ≦ y <1), and particularly preferably a high output element when the y value is 0.05 or more. Is obtained. Furthermore, AlGaN is easy to obtain a p-type with a high carrier concentration, is hardly decomposed during growth, and has an action of suppressing decomposition of the InGaN active layer 16. In addition, the band offset and the refractive index difference with respect to the InGaN active layer 16 can be increased as compared with other nitride semiconductors, which is the most excellent. Further, if the p-type cladding layer is made of p-type GaN, the light emission output is reduced to about 1/3 compared with p-type AlGaN. This is because AlGaN is effective as an electron barrier layer. Therefore, as the p-type cladding layer, Mg-doped p-type Al _y Ga _1-y N having a y value of 0.05 or more is most preferable. The thickness of the p-type cladding layer 17 is desirably 1 nm or more and 2 μm or less, more preferably 5 nm or more and 0.5 μm or less. If the thickness of the p-type cladding layer 17 is less than 1 nm, the p-type cladding layer 17 is almost absent, and the light emission output tends to decrease. If the thickness is larger than 2 μm, the p-type cladding layer is grown during crystal growth. This is because cracks are likely to occur in the layer itself, and even if the next layer is laminated on the cracked layer, a semiconductor layer with good crystallinity cannot be obtained and the output tends to decrease. In order to obtain a p-type nitride semiconductor, it can be obtained by doping an acceptor impurity such as Mg, Zn, C, Be, Ca, Ba during crystal growth. More preferably, after doping with acceptor impurities, annealing is performed at 400 ° C. or higher in an inert gas atmosphere such as nitrogen or argon. By performing annealing, a carrier concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ is usually obtained with p-type AlGaN. In addition, an electron beam irradiation process may be performed. The p-type contact layer 18 is p-type GaN, particularly preferably Mg-doped p-type GaN. Since this p-type GaN is a layer in contact with the p-electrode 14, it is important to obtain an ohmic contact in the case of a light-emitting element. The p-type GaN can easily form an ohmic contact with many metals, and examples of the most preferable electrode material for the contact layer include Ni—Au and Ni—Ti. The thickness of the p-type contact layer 18 is not particularly limited, but it is usually desirable to grow with a thickness of about 50 nm to 2 μm.

According to the device structure shown in FIG. 5, it is possible to obtain a nitride LED having an excellent light emission output with a minimum necessary structure. The reason is that each layer works effectively. First, the n-type cladding layer made of the Si—Al _0.05 Ga _0.95 N layer 13 serves as both a current injection layer and a carrier confinement layer. The Si—Al _0.05 Ga _0.95 N layer 13 contains an appropriate amount of n-type impurities as a current injection layer to the light emitting layer, and does not contain excessive n type impurities, so heat generated from the light emitting layer is generated from the substrate side. It becomes possible to dissipate heat efficiently, and an LED having an excellent element lifetime can be obtained.

[Example 8] Example 8 is a modification 1 of the LED of Example 7, in which an element is formed using the laminated semiconductor substrate shown in Example 6, and after removing the sapphire substrate and the AlN layer, the chip is formed. Is cut out.

  FIG. 6 is a cross-sectional view schematically showing the structure of the LED of Example 8. The structure of the LED shown in FIG. 6 is (1) the upper surface of the n-type cladding layer 13 is not exposed, and (2) the sapphire substrate 1 and the AlN layer 11 are removed, compared with the LED shown in FIG. (3) The back surface side of the GaN layer 12 is polished and adjusted to a predetermined thickness, and then the n electrode 15 is formed, and the GaN layer 12 is used as an n contact layer. Since they are the same, they are given the same reference numerals.

  With such a structure, it is possible to obtain a thin LED having substantially the same characteristics as those of the third embodiment.

[Example 9] Example 9 refers to an LED which is one of the nitride semiconductor elements disclosed in Japanese Patent No. 3063757 of the present applicant, and is manufactured using the laminated semiconductor substrate of the present invention. It is.

FIG. 7 is a cross-sectional view schematically showing the structure of the LED of Example 9. The LED shown in FIG. 7 uses a laminated semiconductor substrate composed of the sapphire substrate 1, the AlN layer 11, the GaN layer 12, and the Al _x Ga _1-x N layer 13 of Example 6 described above with reference to FIG. After being formed, it is cut out into chips. In this case, the GaN layer 12 of the laminated semiconductor substrate obtained in Example 6 is used as a buffer layer, and the Si—Al _b Ga _1-b N layer 13 thereon is used as an n-type contact layer. On the Si—Al _b Ga _1-b N layer 13, an undoped nitride semiconductor lower layer 5 a, an n-type impurity doped nitride semiconductor intermediate layer 5 b, and an undoped nitride semiconductor upper layer 5 c are stacked in order. N-side first multilayer film 5, n-side second multilayer film layer 6 made of first and second nitride semiconductor layers, MQW structure active layer 7, p-side cladding layer 8, (Mg-doped) p-side GaN Contact layers 9 are sequentially stacked. p-side GaN contact layer 9, p-side cladding layer 8, MQW structure active layer 7, n-side second multi-film layer 6, n-side first multi-layer film 5 and the n-type contact layer _{(Si-Al b Ga 1-} b A part of the N layer 13) is removed by etching, and a part of the upper surface of the n-type contact layer is exposed. A p-electrode and a p-pad electrode 14 are formed on the p-side GaN contact layer 9, and an n-electrode 15 is formed on the exposed portion of the n-type contact layer.

The active layer 7 has an MQW structure containing In _a Ga _1-a N (0 ≦ a <1). The p-side cladding layer 8 is a p-side multilayer film in which a third nitride semiconductor layer and a fourth nitride semiconductor layer having different bandgap energy and different p-type impurity concentrations (or the same) are laminated. It is a clad layer or a p _- side single film clad layer made of Al _b Ga _1-b N (0 ≦ b ≦ 1) containing p-type impurities.

According to the device structure shown in FIG. 7, a nitride LED excellent in light emission output can be obtained. The reason is that each layer works effectively. The Si—Al _0.05 Ga _0.95 N layer 13 serves as both a current injection layer and a carrier confinement layer.

  Next, the n-side first multilayer film 5, the n-side second multilayer film layer 6, the active layer 7 having the MQW structure, the p-side cladding layer 8, the p-side GaN contact layer 9, the p-electrode and the p-pad electrode 14, and the n-electrode The process of forming 15 will be described.

(N-side first multilayer film layer 5) On the laminated semiconductor substrate obtained in Example 2, a lower layer 5a made of undoped GaN is grown to a thickness of 2000 angstroms at 1050 ° C. using TMG and ammonia gas. Subsequently, silane gas is added at the same temperature, an intermediate layer 5b made of GaN doped with Si of 4.5 × 10 ¹⁸ / cm ³ is grown to a thickness of 300 Å, and then only silane gas is stopped. The upper layer 5c made of undoped GaN is grown to a thickness of 50 angstroms at a temperature, and the first multilayer film layer 5 having a total thickness of 2350 angstroms made of three layers is grown.

(N-side second multilayer film layer 6) Next, a second nitride semiconductor layer made of undoped GaN is grown by 40 angstroms at the same temperature, and then the temperature is raised to 800 ° C., and TMG, TMI (trimethylindium ), Using ammonia, the first nitride semiconductor layer made of undoped In _0.13 Ga _0.87 N is grown to 20 Å. Then, these operations are repeated, and 10 layers are alternately laminated in the 2 + first order. Finally, the second nitride semiconductor layer made of GaN is grown to a thickness of 40 Å. The second multilayer layer 6 is grown to a thickness of 640 angstrom.

(Active layer 7) Next, a barrier layer made of undoped GaN is grown to a thickness of 200 angstroms, followed by a temperature of 800 ° C., and a well layer made of undoped In _0.4 Ga _0.6 N using TMG, TMI, and ammonia. Is grown at a film thickness of 30 Å. Then, five barrier layers and four well layers are alternately stacked in the order of barrier + well + barrier + well... + Barrier to form an active layer 7 having an MQW structure with a total film thickness of 1120 angstroms. Grow.

Next, p-type Al doped with 1 × 10 ²⁰ / cm ^{3 of} Mg at a temperature of 1050 ° C. using TMG, TMA, ammonia, Cp ₂ Mg (cyclopentadienylmagnesium). _A third nitride semiconductor layer made of _0.2 Ga _0.8 N is grown to a thickness of 40 angstroms, followed by a temperature of 800 ° C., using TMG, TMI, ammonia, Cp ₂ Mg, and 1 × 10 ²⁰ Mg. A fourth nitride semiconductor layer made of In _0.03 Ga _0.97 N doped with / cm ³ is grown to a thickness of 25 Å. Then, these operations are repeated, and 5 layers are alternately stacked in the order of 3 + 4, and finally, the third nitride semiconductor layer is grown to a thickness of 40 angstroms and is formed of a superlattice multilayer film. The side multilayer clad layer 8 is grown to a film thickness of 365 angstroms.

(P-side GaN contact layer 9) Subsequently, at 1050 ° C., p-side contact layer (Mg-doped p-side GaN contact) made of p-type GaN doped with 1 × 10 ²⁰ / cm ^{3 of} Mg using TMG, ammonia, and Cp 2 Mg. Layer) 9 is grown to a thickness of 700 Å.

  After the completion of the reaction, the temperature is lowered to room temperature, and the wafer is annealed in a reaction vessel at 700 ° C. in a nitrogen atmosphere to further reduce the resistance of the p-type layer. Thereafter, the wafer is taken out from the reaction container, a mask having a predetermined shape is formed on the surface of the uppermost p-side contact layer 9, and etching is performed from the p-side contact layer side by an RIE (reactive ion etching) apparatus. As shown in FIG. 7, the surface of the n-side contact layer is exposed. Thereafter, a translucent p-electrode containing Ni and Au having a thickness of 200 angstroms and a p-pad electrode 14 made of Au for bonding thereon is formed on the entire surface of the p-side contact layer 9 as the uppermost layer by 0.5 μm. The film thickness is formed. On the other hand, an n-electrode 15 containing W and Al was formed on the surface of the n-side contact layer exposed by etching to obtain an LED element.

[Example 10] Example 10 is a modification example 1 of the LED of Example 9, in which an element is formed using the laminated semiconductor substrate shown in FIG. 2, and after the sapphire substrate and the AlN layer are removed, the chip is formed. It is cut out.

FIG. 8 is a cross-sectional view schematically showing the structure of the LED of Example 10. The structure of the LED shown in FIG. 8 is (1) the upper surface of the Si—Al _0.05 Ga _0.95 N layer 13 is not exposed, and (2) the sapphire substrate 1 and the AlN layer 11 as compared with the LED shown in FIG. (3) The back side of the GaN layer 12 is polished and adjusted to a predetermined thickness, and then the n-electrode 15 is formed, and the GaN layer 12 is used as an n-contact layer. Are different, and the others are the same, and are therefore given the same reference numerals.

  With such a structure, a thin LED having substantially the same characteristics as those of Example 10 can be obtained.

  Next, a different part from the process shown in Example 9 will be described.

  After the wafer is taken out of the reaction vessel, the process of performing etching from the p-side contact layer 9 side to expose a part of the surface of the n-side contact layer is omitted. Thereafter, a p-pad electrode 14 made of p-electrode and Au for bonding thereon is formed. Further, after removing the sapphire substrate 1 and the AlN layer 11, the back surface side of the GaN layer 12 is lapped and polished to adjust to a predetermined thickness, and then an n electrode 15 containing Ti and Al is formed. Thereafter, the wafer is cut into LD chips and then assembled into an LD.

[Examples 11 to 15]
Next, a nitride semiconductor laser device manufactured using the laminated semiconductor substrate shown in Example 6 will be described in three forms.

  The first mode is a mode in which the third semiconductor layer 13 of the laminated semiconductor substrate shown in Example 6 is used as a cladding layer, and is considered to be the best mode.

  The second mode is a mode in which an n-side superlattice cladding layer is formed on the third semiconductor layer 13 of the laminated semiconductor substrate shown in the sixth embodiment. In this case, the third semiconductor layer 13 is formed as a single film.

  In the third mode, a crack prevention layer and an n-side superlattice cladding layer are stacked on the third semiconductor layer 13 of the stacked semiconductor substrate shown in FIG. When the mixed crystal ratio of Al in the third semiconductor layer 13 becomes relatively high, cracks tend to occur in the nitride semiconductor layer grown thereon, so that a crack prevention layer is formed.

[Example 11]
FIG. 9 shows an LD laser manufactured using the laminated semiconductor substrate of the present invention with reference to an LD, which is one of the nitride semiconductor elements disclosed in Japanese Patent Application Laid-Open No. 10-326943. It is sectional drawing which shows typically the structure at the time of cut | disconnecting in the position perpendicular | vertical to the resonance direction of light. This LD is formed by cutting a chip after forming an element using the laminated semiconductor substrate shown in the sixth embodiment.

The LD shown in FIG. 9 uses the n-type GaN layer 12 of the laminated semiconductor substrate obtained in Example 6 as an n contact layer and the Si—Al _b Ga _1-b N layer 13 as a cladding layer. On the _{Si-Al b Ga 1-b} N layer 13, stacked n-side optical guide layer 26, active layer 27, the cap layer 28, p-side optical guide layer 29, p-side cladding layer 30, p-side contact layer 31 in this order Has been. The p-side contact layer 31 and the p-side cladding layer 30 are etched so as to form a ridge stripe having a stripe width of 4 μm. The center of the stripe width of the ridge stripe is close to the negative electrode 22 to be formed later. As described above, the layer above the p-type nitride semiconductor layer containing Al in particular above the active layer is formed into a ridge shape, whereby the light emission of the active layer is concentrated at the bottom of the ridge, and the transverse mode is single. And the threshold value is likely to decrease.

  Further, the surface of the ridge stripe and the exposed surface of the p-side cladding layer 30 are covered with a mask pattern and etched by the RIE method, whereby the n-side contact layer (n-type GaN) on which the negative electrode 22 is to be formed. Part of the surface of layer 12) is exposed. A positive electrode 20 is formed on the entire top surface of the ridge stripe of the p-side contact layer 31 on the top layer, and a negative electrode 22 is formed on the exposed n-side GaN layer 12 in parallel with the ridge stripe. Yes.

Then, an insulating film 32 made of SiO ₂ is formed so as to cover the upper surface excluding the positions where the positive electrode 20 and the negative electrode 22 are formed, and the extraction pad electrode 21 is electrically connected to the positive electrode 20. Is formed. In this case, the pad electrode 21 is formed with an area larger than the surface area of the positive electrode 20 via the insulating film 32, so that heat dissipation is improved and wire bonding is facilitated. Further, the pad electrode 21 is formed thicker than the positive electrode 20, and prevents the positive electrode 20 from peeling off.

  Then, after the substrate back surface is lapped so that the thickness of the substrate 1 becomes 100 μm, the substrate back surface is mirror-finished by 1 μm polishing with a finer abrasive. Thus, by reducing the thickness of the substrate to 100 μm or less, the heat dissipation of the laser element is enhanced.

Thereafter, the polished surface side of the substrate is scribed and cleaved in a bar shape in a direction perpendicular to the ridge stripe, thereby producing a resonator having a resonator length of 500 μm on the cleaved surface. Further, a dielectric multilayer film (not shown) made of SiO ₂ and TiO ₂ is formed on the resonator surface, and finally the bar is cut in a direction parallel to the ridge stripe to form an LD chip. The LD chip is placed on the heat sink in a face-up state (a state where the substrate 1 and the heat sink face each other), and each electrode is bonded and connected by a wire 33 made of a gold wire. At this time, as shown in FIG. 9, the position at the time of wire bonding is a position away from the position of the ridge stripe while avoiding the position directly above the ridge stripe. As a result, no impact is applied to the ridge portion, so that the crystal of the ridge portion is not broken. When laser oscillation of this LD chip was attempted, continuous oscillation with an oscillation wavelength of 405 nm was confirmed at room temperature.

  Note that the pad electrode 21 may not be in ohmic contact with the p-side contact layer 31 and may simply be electrically connected to the positive electrode 20. The pad electrode 21 is thicker than the positive electrode 20 to prevent peeling of the positive electrode 20 and has a surface area larger than that of the positive electrode 20. In this case, it is easy to wire bond the pad electrode 21 on the positive electrode 20 side, and when the positive electrode 20 side is connected to a heat sink such as a heat sink or a submount, the bonding area is increased. Improve heat dissipation.

According to the device structure shown in FIG. 9, an LD having excellent light emission output can be obtained. The reason is that each layer works effectively. The n-type cladding layer composed of the Si—Al _0.05 Ga _0.95 N layer 13 serves as both a current injection layer and a carrier confinement layer.

  Next, the n-side light guide layer 26, the active layer 27, the cap layer 28, the p-side light guide layer 29, the p-side cladding layer 30, the p-side contact layer 31, the insulating film 32, the positive electrode 20, the pad electrode 21, and the negative A process of forming the electrode 22 will be described.

  (N-side light guide layer 26) With the impurity gas stopped, the n-side light guide layer 26 made of undoped GaN is grown at 1050 ° C. to a thickness of 0.2 μm.

(Active layer 27) Next, the active layer 27 is grown using TMG, TMI, ammonia, and silane gas as source gases. The active layer 27 is maintained at a temperature of 800 ° C., and a well layer made of In _0.2 Ga _0.8 N doped with Si at 8 × 10 ¹⁸ / cm ³ is first grown to a thickness of 25 Å. Next, a barrier layer made of In _0.01 Ga _0.95 N doped with 8 × 10 ¹⁸ / cm ^{3 of} Si is grown to a thickness of 50 Å at the same temperature only by changing the molar ratio of TMI. This operation is repeated twice, and finally a multiple quantum well structure in which a well layer is stacked is obtained.

(P-side cap layer 28) Next, the temperature is raised to 1050 ° C., TMG, TMA, ammonia, Cp ₂ Mg (cyclopentadienyl magnesium) is used, and p-type Al doped with 1 × 10 ²⁰ / cm ^{3 of} Mg. _A p-side cap layer 28 made of _0.1 Ga _0.9 N is grown to a thickness of 300 Å.

  (P-side light guide layer 29) The impurity gas is stopped, and a p-side light guide layer 29 made of undoped GaN is grown to a thickness of 0.2 μm at 1050 ° C.

(P-side cladding layer 30) Subsequently, at 1050 ° C., an A layer made of p-type Al _0.20 Ga _0.80 N doped with 1 × 10 ²⁰ / cm ^{3 of} Mg is doped with 20 Å and Mg is doped with 1 × 10 ²⁰ / cm ³ The B layer made of p-type GaN is grown to 20 Å. This pair is grown 125 times to grow a p-side cladding layer 30 having a superlattice structure with a total thickness of 0.5 μm (5000 angstroms).

(P-side contact layer 31) Finally, a p-side contact layer 31 made of p-type GaN doped with Mg at 1 × 10 ²⁰ / cm ³ at 1050 ° C. is formed on the p-side cladding layer 30 to a thickness of 150 Å. Grow.

  After the completion of the reaction, the temperature is lowered to room temperature, and the wafer is annealed in a reaction vessel at 700 ° C. in a nitrogen atmosphere to further reduce the resistance of the p-type layer. After annealing, the wafer is taken out of the reaction vessel, etched by an RIE apparatus, and the uppermost p-side contact layer 31 and p-side cladding layer 30 are etched to form a ridge stripe having a stripe width of 4 μm. When forming the ridge stripe, it is designed in advance so that the center of the stripe width is close to the negative electrode 22 to be formed later. When forming a ridge stripe, in particular, by forming a layer over the p-type nitride semiconductor layer containing Al above the active layer into a ridge shape, the emission of the active layer is concentrated at the bottom of the ridge, and the transverse mode is It is easy to unify, and the threshold value tends to decrease. Further, when an insulating substrate is used as in this embodiment, the threshold is lowered when the center of the stripe of the ridge portion is shifted from the center of the stripe of the active layer and approaches the negative electrode 22 side. Is preferable.

  Next, a mask is formed on the surface of the ridge stripe and the exposed surface of the p-side cladding layer 30, and etching is performed by RIE to form an n-side contact layer (GaN layer 12) on which the negative electrode 22 is to be formed. Expose part of the surface. Thereafter, a positive electrode having at least one selected from Ni, Pt, Au and the like, here a positive electrode 20 made of Ni / Au, is formed on the entire uppermost surface of the ridge stripe of the p-side contact layer 31 as the uppermost layer. , With a film thickness of 500 angstroms.

  Next, a negative electrode 22 made of Ti and Al is formed on the exposed surface of the n-side contact layer in a thickness of 0.5 μm in parallel with the ridge stripe. In addition, as a material of the negative electrode 22 from which a preferable ohmic can be obtained with the n-side contact layer (GaN layer 12), metals or alloys such as Al, Ti, W, Cu, Zn, Sn, In, and V can be cited. .

Next, an insulating film 32 made of SiO ₂ is formed to a thickness of 0.5 μm on the entire surface of the nitride semiconductor layer excluding the positions where the positive electrode 20 and the negative electrode 22 are formed. Thereafter, an extraction pad electrode 21 containing Ru and Au electrically connected to the positive electrode 20 via the insulating film 32 on the p-side cladding layer 30 is wider than the surface area of the positive electrode 20. Thus, it is formed with a film thickness of 2 μm. The pad electrode 21 may not be in ohmic contact with the p-side contact layer 31, and may simply be electrically connected to the positive electrode 20. The pad electrode 21 is thicker than the positive electrode 20 to prevent peeling of the positive electrode and has a larger surface area than the positive electrode. In addition to facilitating wire bonding from the pad electrode to the positive electrode side, when connecting the positive electrode side to a heat sink such as a heat sink or a submount, the bonding area is increased to improve heat dissipation.

  As described above, the wafer on which the negative electrode 22 and the positive electrode 20 are formed is transferred to a polishing apparatus, and the substrate on the side where the nitride semiconductor is not formed is lapped using a diamond abrasive, The thickness is 100 μm. After lapping, the substrate surface is mirror-finished by polishing with 1 μm with a finer abrasive. Thus, by reducing the thickness of the substrate to 100 μm or less, the heat dissipation of the LD is enhanced.

After polishing the substrate, the polished surface side is scribed and cleaved in a bar shape in a direction perpendicular to the ridge stripe to produce a resonator having a resonator length of 500 μm on the cleaved surface. Further, a dielectric multilayer film made of SiO ₂ and TiO ₂ is formed on the resonator surface, and finally a bar is cut in a direction parallel to the ridge stripe to form an LD chip.

  Finally, the LD chip is placed face up (the substrate and the heat sink face each other) on the heat sink, and each electrode is bonded by a wire 33 made of a gold wire. The position at the time of wire bonding is a position away from the position of the ridge stripe. By avoiding the portion directly above the ridge stripe, the ridge portion is not shocked, so that the crystal of the ridge portion is not broken. When laser oscillation of this laser chip was attempted, continuous oscillation with an oscillation wavelength of 405 nm was confirmed at room temperature.

[Embodiment 12] Embodiment 12 is a modification 1 of the LD of Embodiment 11, in which an n-side superlattice cladding layer is formed before the n-side light guide layer 26 described in Embodiment 11 is formed. The others are the same.

(N-side superlattice cladding layer) It is made of n-type Al _0.20 Ga _0.80 N doped with Si at 1 × 10 ¹⁹ / cm ³ using TMA, TMG, NH ₃ , SiH ₄ as source gas at a temperature of 1050 ° C. An A layer is grown to 20 angstroms, and a B layer made of n-type GaN doped with Si at 1 × 10 ¹⁹ / cm ^{3 is} grown to 20 angstroms. Then, this pair is grown 125 times to grow an n-side cladding layer having a superlattice structure with a total film thickness of 0.5 μm (5000 Å). The n-side light guide layer 26 forming step described in the fourth embodiment is then performed. As a result, an LD having substantially the same characteristics as those of Example 11 can be obtained.

[Embodiment 13] Embodiment 13 is a modification 2 of the LD of Embodiment 11, and before the n-side superlattice cladding layer described in Embodiment 12 is formed, a crack prevention layer is formed. It has been changed and the others are the same.

(Crack prevention layer) The crack prevention layer made of In _0.1 Ga _0.9 N doped with 1 × 10 ¹⁹ / cm ^{3 of} Si using TMG, TMI, ammonia, silane gas as the source gas at a temperature of 800 ° C. is 500 angstroms. Grow with film thickness. The n-side superlattice cladding layer described in the fifth embodiment is formed thereon, and the n-side light guide layer 26 described in the fourth embodiment is formed on the n-side superlattice cladding layer. As a result, an LD having substantially the same characteristics as those of Example 11 can be obtained. [Embodiment 14] Embodiment 14 is a modification 3 of the LD of Embodiment 11, in which elements are formed using the laminated semiconductor substrate shown in Embodiment 6, and the sapphire substrate is removed and then cut into chips. Is. In this case, the sapphire substrate is omitted, and the back side of the AlN layer is polished and adjusted to a predetermined thickness. With such a structure, a thin LED having substantially the same characteristics as those of Example 11 can be obtained.

[Embodiment 15] Embodiment 15 is a modification 4 of the LD of Embodiment 11, in which elements are formed using the laminated semiconductor substrate shown in Embodiment 6, and after removing the sapphire substrate and the AlN layer, a chip is formed. It is LED cut out.

FIG. 10 is a cross-sectional view schematically showing the structure of the LED of Example 15. The structure of the LED shown in FIG. 10 is (1) the upper surface of the Si—Al _0.05 Ga _0.95 N layer 13 is not exposed, and (2) the sapphire substrate 1 and the AlN layer 11 as compared with the LED shown in FIG. (3) After the back side of the GaN layer 12 is polished and adjusted to a predetermined thickness, a negative electrode (n electrode) 22 is formed, and the GaN layer 12 is used as an n contact layer Since the other points are the same, the same reference numerals are given.

  With such a structure, a thin LED having substantially the same characteristics as those of Example 11 can be obtained.

  Next, a different part from the process shown in Example 11 will be described.

After forming the ridge stripe, the process of exposing a part of the surface of the n-side contact layer (GaN layer 12) is omitted. Then, an insulating film 32 made of SiO ₂ is formed so as to cover the upper surface excluding the position of the positive electrode 20, and the pad electrode 21 is formed in an electrically connected state on the positive electrode 20. Further, the wafer back side (GaN layer 12 side) is lapped and polished, and the wafer is thinned to improve heat dissipation, and then the negative electrode 22 made of Ti and Al is formed on the back side of the GaN layer 12. In addition, as a material of the negative electrode 22 from which the n-side contact layer made of the GaN layer 12 and a preferable ohmic can be obtained, metals or alloys such as Al, Ti, W, Cu, Zn, Sn, In, and V can be cited. . Thereafter, the wafer is cut into LD chips and then assembled into an LD.

The figure which shows typically the cross-section of the laminated semiconductor substrate of the 1st Embodiment of this invention. The figure which shows typically the cross-section of the laminated semiconductor substrate of the 2nd Embodiment of this invention. Sectional drawing which shows typically the structure of LED of Example 1 of this invention. Sectional drawing which shows typically the manufacturing process of LED of Example 2 of this invention. Sectional drawing which shows typically the structure of LED of Example 7 of this invention. Sectional drawing which shows typically the structure of LED of Example 8 of this invention. Sectional drawing which shows typically the structure of LED of Example 9 of this invention. Sectional drawing which shows typically the structure of LD of Example 10 of this invention. Sectional drawing which shows typically the structure of LD of Example 11 of this invention. Sectional drawing which shows typically the structure of LD of Example 15 of this invention. The figure which shows typically the process in the case of using it combining ELO growth method (I) when forming the GaN layer in FIG. The figure which shows typically the process in the case of using it combining ELO growth method (II) when forming the GaN layer in FIG. The figure which shows typically the process in the case of using it combining ELO growth method (III) when forming the GaN layer in FIG. The figure which shows typically the process in the case of using it combining ELO growth method (IV) when forming the GaN layer in FIG. The figure which shows typically the process in the case of using it combining ELO growth method (V) when forming the GaN layer in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Sapphire substrate 10 ... Laminated semiconductor substrate 11 ... 1st semiconductor layer (AlN layer)
12 ... Second semiconductor layer (GaN layer)
53 ... Third semiconductor layer (n-type Al _0.07 Ga _0.93 N layer)
54 ... MQW active layer 55 ... p-type Al _0.38 Ga _0.62 N layer 56 ... p-type Al _0.07 Ga _0.93 N layer 57 ... p-type ohmic contact electrode 58 ... Au / Sn film 59 ... CuW substrate 60 ... n electrode

Claims (16)

a first semiconductor layer having a plane orientation aligned in the c-axis direction; and a second semiconductor layer provided on the first semiconductor layer and having a lattice constant larger than that of the first semiconductor layer. A feature of a laminated semiconductor substrate. 2. The laminated semiconductor substrate according to claim 1, wherein the upper surface of the first semiconductor layer is a mirror surface. The laminated semiconductor substrate according to claim 1, wherein the first semiconductor layer has a half width of 90 arcsec or less in XRC (0002) diffraction. The laminated semiconductor substrate according to claim 1, wherein the second semiconductor layer is compressive strained in the a-axis direction. The laminated semiconductor substrate according to claim 1, wherein the second semiconductor layer has fewer edge dislocations and / or spiral dislocations than the first semiconductor layer. The laminated semiconductor substrate according to claim 1, wherein the first semiconductor layer is aluminum nitride. The stacked semiconductor substrate according to claim 1, wherein the second semiconductor layer is gallium nitride. The stacked semiconductor according to claim 7, further comprising a third semiconductor layer formed on the second semiconductor layer and made of Al _x Ga _1-x N (0 <x ≦ 0.1). substrate. 9. The laminated semiconductor substrate according to claim 8, wherein the second semiconductor layer and / or the third semiconductor layer has a screw dislocation density of 3 × 10 ⁷ / cm ² or less. a first semiconductor layer having a plane orientation aligned in the c-axis direction, and a lattice constant larger than that of the first semiconductor layer provided on the first semiconductor layer and having a plane orientation aligned in the c-axis direction; A laminated semiconductor substrate comprising: a second semiconductor layer. The laminated semiconductor substrate according to claim 10, wherein the second semiconductor layer has fewer edge dislocations and / or spiral dislocations than the first semiconductor layer. The laminated semiconductor substrate according to claim 10, wherein the first semiconductor layer is aluminum nitride. The laminated semiconductor substrate according to claim 10, wherein the second semiconductor layer is gallium nitride. 14. The semiconductor device according to claim 10, further comprising a third semiconductor layer formed on the second semiconductor layer and having tensile strain in the direction of the second semiconductor layer. The laminated semiconductor substrate according to 1. The laminated semiconductor substrate according to claim 14, wherein the third semiconductor layer is made of Al _x Ga _1-x N (0 <x ≦ 0.1). The laminated semiconductor substrate according to claim 14, wherein the second semiconductor layer and / or the third semiconductor layer has a screw dislocation density of 3 × 10 ⁷ / cm ² or less.

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