JP2005260589A - Stereo demodulator circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stereo demodulator circuit for maximizing a separation characteristic by matching the phases of a main channel signal and a subchannel signal. <P>SOLUTION: In this stereo demodulator circuit having a matrix circuit for generating and outputting an L signal and an R signal on the basis of the main channel signal and the subchannel signal in a stereo signal, The preceding stage of the matrix circuit is provided with a first phase adjustment circuit for adjusting the phase of the main channel signal and a second phase adjustment circuit for adjusting the phase of the subchannel signal to match the phase with the phase of an output of the first phase adjustment circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a stereo demodulation circuit.

FM stereo makes use of high-quality sound transmission of FM broadcasting, and maintains compatibility between stereo broadcasting and monaural broadcasting with a single radio wave.
For this compatibility, the transmission side generates an (L + R) signal and an (LR) signal obtained by matrix processing of the L signal and the R signal in the stereo signal, and further, the (LR) signal is generated with a 38 kHz multi-carrier. A stereo composite signal obtained by mixing a modulated signal, an (L + R) signal, and a 19 kHz pilot signal used for identifying stereo broadcast is generated and transmitted.

  In the FM receiver, a stereo demodulating circuit is configured to generate a main channel signal (L + R: hereinafter referred to as a main channel signal) and a sub channel signal (LR: hereinafter referred to as a sub channel) from a stereo composite signal demodulated by detection of the received signal. And the matrix processing of the main channel signal and the sub-channel signal is performed, and the L signal and the R signal are separated and output.

The degree of separation between the L signal and the R signal is referred to as separation degree (hereinafter referred to as separation). For example, in the left-to-right separation (Sl) in the FM receiver, assuming that the left output based only on the L signal is Ll and the right output based only on the L signal is Rl,
Sl = 20logLl / Rl (dB)
It is represented by If the separation is small, the stereo characteristics are not utilized and the sense of reality is reduced.

  In order to increase the separation, it is necessary for the matrix processing to have the same size of the main channel signal and the sub channel signal. In practice, however, the main channel signal and the sub channel signal generated from the stereo composite signal are As will be described later, the signal size is different.

Therefore, in the conventional stereo demodulation circuit, in order to increase the separation characteristics by combining the magnitudes of the main channel signal and the subchannel signal, an amplifier for amplifying the signal magnitude is provided on the subchannel signal side to increase the magnitude of the subchannel signal. I was adjusting it.
JP-A-9-36821

The above-described main channel signal and sub-channel signal are extracted from a stereo composite signal that has passed through a filter provided in the FM receiver, for example, an IIR (Infinite Impulse Response) type low-pass filter. The IIR filter does not have a linear phase characteristic, and a phase difference is generated according to the frequency of a signal passing through the filter.
Since the composite signal includes a main channel signal having a modulation frequency of 20 Hz to 15 kHz and a sub channel signal having a modulation frequency of 23 kHz to 53 kHz, the main channel signal and the sub channel signal separated from the composite signal by the stereo demodulation circuit are included. There is a phase difference in the channel signal. As will be described later, the phase difference is also caused by the difference in the separation path between the main channel signal and the sub-channel signal.
Thus, if the phases of the main channel signal and the sub-channel signal are different, even if the amplification factor is adjusted by the sub-channel signal side amplifier circuit, the separation cannot be increased.
As described above, the conventional stereo demodulation circuit has a problem in that the phase difference between the main channel signal and the sub-channel signal is generated, so that the separation between the L signal and the R signal cannot be increased in stereo demodulation.

  An object of the present invention is to provide a stereo demodulation circuit that increases separation by matching the phases of a main channel signal and a subchannel signal.

A main invention according to the present invention is a stereo demodulation circuit having a matrix circuit that generates and outputs an L signal and an R signal based on a main channel signal and a subchannel signal in a stereo signal, and adjusts the phase of the main channel signal. And a second phase adjustment circuit that adjusts the phase of the sub-channel signal and matches the phase of the output of the first phase adjustment circuit in the previous stage of the matrix circuit. .
Other features of the present invention will become apparent from the accompanying drawings and the description of this specification.

  According to the present invention, the separation can be increased by matching the phases of the main channel signal and the sub-channel signal.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

=== FM receiver configuration ===
FIG. 1 is a block diagram showing an example of the configuration of an FM receiver using the stereo demodulation circuit 26 of the present invention. The FM receiver shown in the figure includes a front end unit 100, an intermediate frequency amplification unit 200, an FM detection circuit 24, a stereo demodulation circuit 26, de-emphasis circuits 28 and 30, and low frequency amplification circuits 32 and 34.

  The front end unit 100 converts the received signal obtained from the antenna 1 into an intermediate frequency signal of 10.7 MHz and outputs the converted signal. The front-end unit 100 includes a high-frequency amplifier circuit 10 that selectively amplifies a reception signal received from the antenna 1 only in a specific frequency band, a local oscillation circuit 12 that outputs a local oscillation signal necessary for frequency conversion, And a mixing circuit 14 that mixes the output signal of the high-frequency amplifier circuit 10 and the local oscillation signal output from the local oscillation circuit 12 and outputs the mixed signal as an intermediate frequency signal. As the local oscillation circuit 12, a PLL frequency synthesizer including a PLL circuit 18 is used, for example. The PLL frequency synthesizer compares the frequency output from the voltage controlled oscillation circuit (not shown) based on the reference frequency with a phase comparison circuit (not shown), and if there is a difference, generates a signal corresponding to the difference of the phase comparison circuit To generate a stable frequency.

  The intermediate frequency amplifier 200 amplifies the intermediate frequency signal and removes unnecessary signals other than a predetermined frequency. The intermediate frequency amplifier 200 includes an intermediate frequency amplifier circuit 20 having a filter (not shown) that removes an input intermediate frequency signal other than a predetermined frequency and an amplifier circuit (not shown) that amplifies the intermediate frequency signal, A limiter circuit 22 is provided for removing a non-predetermined amplitude portion of the signal output from the frequency amplifier circuit 20.

  Since the filter in the intermediate frequency amplifier circuit 20 has a large influence on the sound quality by the phase characteristic, it is required that the group delay characteristic is flat within the pass band of the filter. There is a phase delay corresponding to the frequency. As this filter, for example, a ceramic filter is used. Further, the limiter circuit 22 has a function of removing an amplitude portion other than a predetermined amplitude of the received signal, and even if the received signal is subjected to an amplitude change due to noise or the like, the noise portion is removed and output.

  The FM detection circuit 24 demodulates and outputs the stereo composite signal by performing FM detection on the output of the limiter circuit 22. As the FM detection circuit 24, for example, a PLL detection circuit that feedback-controls a voltage-controlled oscillation circuit (not shown) so as to follow a change in frequency and extracts an amplitude signal from the control voltage is used. Other detection circuits include a Foster-Sealey type detection circuit, a ratio detection circuit, and the like. Any detection method can be applied to the stereo demodulation circuit 26 of the present invention.

  The stereo demodulation circuit 26 extracts the main channel signal and the sub channel signal included in the stereo composite signal, and further generates and outputs the L signal and the R signal by performing matrix processing of the main channel signal and the sub channel signal.

  The de-emphasis circuits 28 and 30 attenuate the high frequency portions of the L signal and R signal strengthened by pre-emphasis on the transmission side to return to flat frequency characteristics by the frequency characteristics opposite to those on the transmission side, and the low frequency amplification circuit 32 , 34 respectively.

  The low frequency amplifier circuits 32 and 34 amplify the input L signal and R signal and supply necessary power to the speaker.

  With the above configuration, the L signal and the R signal are demodulated from the received signal, and the sound based on the L signal is output from the left speaker and the sound based on the R signal is output from the right speaker.

  When receiving as monaural broadcasting, the stereo demodulation circuit 26 selects only the main channel signal and outputs it from the left and right speakers. In this case, since the main channel signal is an L + R signal, information on both the L signal and the R signal is output, and no problem occurs.

=== Stereo demodulation circuit ===
FIG. 2 is a block diagram showing an example of the configuration of the stereo demodulation circuit 26 of the present invention.
The stereo demodulation circuit 26 includes low-pass filters (hereinafter referred to as LPF) 40 and 50, band-pass filters (hereinafter referred to as BPF) 42 and 44, a subcarrier generation circuit 46, a MIX circuit 48, and a stereo signal processing circuit 52. ing.

The LPF 40 receives the stereo composite signal demodulated by the FM detection circuit 24, extracts the main channel signal, and outputs it.
The BPF 44 receives a stereo composite signal, extracts a 19 kHz pilot signal, and outputs it.
The subcarrier generation circuit 46 outputs the input pilot signal as a doubled 38 kHz subcarrier.
The BPF 42 outputs a signal obtained by extracting a predetermined frequency region from the stereo composite signal.
The MIX circuit 48 multiplies the output of the BPF 42 and the subcarrier and outputs the result to the LPF 50.
The LPF 50 extracts the subchannel signal from the output of the MIX circuit 48 and outputs it.
The stereo signal processing circuit 52 inputs the main channel signal and the sub-channel signal, generates an L signal and an R signal, and outputs them.
In the stereo demodulation circuit 26 having the above configuration, an L signal and an R signal are generated from the stereo composite signal.

Next, stereo demodulation operation will be described.
If the stereo composite signal input to the stereo demodulation circuit 26 is COMP, the main channel signal is (L + R), the subchannel signal is (LR), and the subcarrier frequency is fc, the stereo composite signal COMP excludes the pilot signal. When,
COMP = (L + R) + sin (2π · fc · t) · (LR)
It is expressed.
By passing this COMP through the LPF 40, the subcarrier component is removed and (L + R) is obtained as the main channel signal.

In addition, sin (2π · fc · t) · (LR) is extracted from COMP by extracting the frequency of 23 to 53 kHz by the BPF filter 42. When the MIX circuit 48 multiplies the extracted signal by the subcarrier sin (2π · fc · t),
sin (2π · fc · t) · sin (2π · fc · t) · (LR)
= 1/2. (LR) -1 / 2cos (4.pi.fc.t). (LR)
It becomes.
By passing this signal through the LPF 50, the subcarrier component is removed and 1/2 · (LR) is obtained as the subchannel signal. As described above, the sub-channel signal input to the stereo signal processing circuit 52 is ½ the magnitude of the main channel signal. Therefore, the signal is normally amplified to twice as large by the amplifier circuit 62 of the stereo signal processing circuit 52 described later. Note that the amplification factor is adjusted according to variations in filter characteristics and separation characteristics of the intermediate amplifier circuit 20.
The main channel signal and the sub-channel signal input to the stereo signal processing circuit 52 are separated into an L signal and an R signal by matrix processing and output.

=== Stereo Signal Processing Circuit ===
FIG. 3 is a block diagram showing the configuration of the stereo signal processing circuit 52 in the stereo demodulation circuit 26 of the present invention.

  The stereo signal processing circuit 52 generates and outputs an L signal and an R signal based on the main channel signal and the subchannel signal in the stereo signal, and an FIR (Finite Impulse Response) for adjusting the phase of the main channel signal. A filter 54 ("first phase adjustment circuit"), an FIR filter 56 ("second phase adjustment circuit") that adjusts the phase of the subchannel signal to match the phase of the output of the FIR filter 54, and the subchannel signal And an amplifying circuit 62 that amplifies the signal. The phase adjustment means that the phase of the input signal is corrected and output in accordance with the set value of the multiplication coefficient of FIR filters 54 and 56 described later.

  The matrix circuit 53 includes an adder circuit 58 that outputs an L signal based on the main channel signal and the subchannel signal, and a subtractor circuit 60 that outputs an R signal based on the main channel signal and the subchannel signal. .

The main channel signal is input to the FIR filter 54, the phase of which is adjusted, and input to the adder circuit 58 and the subtractor circuit 60. The subchannel signal is amplified to a predetermined magnitude by the amplifier circuit 62, input to the FIR filter 56, adjusted to match the phase of the output of the FIR filter 54, and input to the adder circuit 58 and the subtractor circuit 60. . Then, an L signal is generated by addition processing of each signal input to the addition circuit 58. In addition, the R signal is generated by the subtraction process of each signal input to the subtraction circuit 58. In the embodiment of the present invention, the amplifier circuit 62 is provided in the previous stage of the FIR filter 56, but in the subsequent stage of the FIR filter 56. It may be provided.

=== FIR filter ===
FIG. 4 is a block diagram showing the configuration of the FIR filters 54 and 56.
The FIR filters 54 and 56 delay input signals (Xn: n is the number of samples) for each sampling cycle unit (“predetermined period”) and output delay circuits D1 to D (k−1), and inputs. Multipliers A1 to Ak that have arbitrary multiplication coefficients corresponding to the signals and outputs of the delay circuits D1 to D (k-1), multiply the input signals by the multiplication coefficients, and output the multiplication circuits A1 to Ak. And an adder circuit 80 for adding the outputs and outputting the sum. Here, k is a filter order and is an integer of 2 or more.

The delay circuit D (k−1) outputs a signal delayed by n− (k−1) sampling periods with respect to the input signal Xn. For example, when the input signal is Xn, D1 outputs Xn-1, and D2 outputs Xn-2.
The input signal Xn and the outputs from the delay circuits D1 to D (k-1) are multiplied by the multiplication coefficients a1 to ak in the corresponding multiplication circuits A1 to Ak, respectively. Later, all are added by the adder circuit 80 and output. For example, when the multiplication coefficient a1 is 1 and the other values are 0, the output Xn becomes the output Xn with respect to the input Xn, and the phase remains unchanged. When the multiplication coefficient a2 is 1 and the other values are 0, the output Xn-1 is obtained with respect to the input Xn, and a value delayed by one sample period phase is output.
In this manner, the FIR filters 54 and 56 can adjust the input signal to an arbitrary phase and output it according to the set values of the multiplication coefficients a1 to ak of the multiplication circuits A1 to Ak.

  FIG. 5 is a diagram for explaining the characteristics of phase correction of the FIR filters 54 and 56. FIG. 5 is an example of a case where the multiplication coefficient of the FIR filter 54 on the main channel side is fixed and the multiplication coefficient of the FIR filter 56 on the secondary channel side is adjusted in the 10th-order filter with k = 10. The vertical axis represents each set value of the multiplication coefficients a1 to a10, and this set value corresponds to the output when the impulse is input. The horizontal axis represents the number of samples at the time of impulse input, and these values correspond to the multiplication circuits A1 to A10, respectively.

  First, only the multiplication coefficient a5 of the FIR filter 54 on the main channel signal side is set to 1, and the others are set to 0. When an impulse is input to the FIR filter 54, the output of the FIR filter 54 becomes a solid line portion in FIG. By setting the multiplication coefficients a1 to a10 of the FIR filter 56 to optimum values for the output of the FIR filter 54, the phases of the outputs of the FIR filter 54 and the FIR filter 56 can be matched. For example, in FIG. 5, the multiplication coefficients a1 to a10 of the FIR filter 56 are set values as indicated by the dotted line portion in FIG.

FIG. 6 is a diagram illustrating an example of the relationship between the phase correction amount of the stereo demodulation circuit 26 using the FIR filters 54 and 56 and the separation characteristics.
The vertical axis represents the separation (dB), and the horizontal axis represents the phase correction amount (sample period) between the main channel signal and the subchannel signal. As shown in the figure, the separation changes as the phase correction amount changes. In the case of FIG. 6, the separation is maximum when phase correction is performed with a 0.5 sample period. The phase of the main channel signal and that of the sub channel signal coincide with each other at the place where the separation is maximum.
In this way, the separation can be increased by adjusting the phase of the main channel signal and the sub-channel signal to be equal.

  In the case of only the amplifier circuit 62, if the phase of the main channel signal and the sub-channel signal is shifted, the separation cannot be increased even if the amplification factor is changed. However, the separation can be increased by providing FIR filters 54 and 56 on the main channel signal side and the sub channel signal side, respectively, and setting multiplication coefficients a1 to ak in which the phases of the main channel signal and the sub channel signal are equal. .

=== Other Embodiments ===
FIG. 7 is a block diagram of a stereo signal processing circuit 82 in a stereo demodulation circuit according to another embodiment of the present invention.

  The stereo signal processing circuit 82 generates and outputs an L signal and an R signal based on the main channel signal and the sub channel signal in the stereo signal, an FIR filter 84 that adjusts the phase of the main channel signal, and a sub signal. And an LMS (Least Mean Square) type adaptive filter 86 that adjusts the phase of the channel signal to match the phase of the output of the FIR filter 84.

  The matrix circuit 83 includes an adder circuit 88 that outputs an L signal based on the main channel signal and the subchannel signal, and a subtractor circuit 90 that outputs an R signal based on the main channel signal and the subchannel signal. .

  The adaptive filter 86 responds to an FIR filter (not shown) having a multiplication circuit of multiplication coefficients a1 to ak and an error signal (“error signal”) that is a difference between the output of the FIR filter 84 and the output of the adaptive filter 86 itself. And an LMS algorithm unit (not shown) for changing the multiplication coefficients a1 to ak. In FIG. 7, the arrow of the adaptive filter 86 indicates that the adaptive filter 86 automatically sets the multiplication coefficients a <b> 1 to ak according to the error signal of the subtracting circuit 90.

Next, the setting operation of the multiplication coefficients a1 to ak will be described.
When the separation adjustment is performed, that is, when the multiplication coefficients a1 to ak are set, signal processing using only the solid line portion is performed.
First, white noise is applied only to the L signal. White noise is noise in which the intensity of components included in a unit frequency band is constant regardless of frequency. The adaptive filter 86 inputs the difference between its own output and the output of the FIR filter 84, that is, the R signal of the output of the subtraction circuit 90, as an error signal. The LMS algorithm unit in the adaptive filter 86 changes the multiplication coefficients a1 to ak so that the error signal is minimized. Then, the adaptive filter 86 sets the values of the multiplication coefficients a1 to ak when the error signal is minimized as the set value. Note that the adaptive filter 86 can also automatically set the amplification factor of the subchannel signal by this setting.
After the setting is completed, the adaptive filter 86 operates as an FIR filter. Further, the stereo signal processing circuit 82 separates the L signal and the R signal by normal signal processing including the dotted line portion of FIG.

  As described above, by setting the FIR filter on the sub-channel side as the adaptive filter 86, it is possible to automatically set the multiplication coefficients a1 to ak as shown in FIG. The adaptive filter 86 can also automatically adjust the amplification factor, and an amplifier on the subchannel signal side is not necessary.

  As described above, the stereo demodulation circuit of the present invention can match the phases of the main channel signal and the sub-channel signal by providing the FIR filters 54 and 56 on the main channel side and the sub-channel side, respectively. Can be bigger.

  Further, these FIR filters 54 and 56 are provided in the previous stage of the matrix circuit, and addition processing and subtraction processing are performed on the signals that have passed through the FIR filters 54 and 56. Therefore, when the main channel signal and the subchannel signal are added and subtracted, The phase of the signal and the subchannel signal can be matched.

  Furthermore, the separation characteristic can be controlled by providing an amplifier circuit 62 on the sub-channel signal side and adjusting the gain of the sub-channel signal.

  In addition, the phase of the main channel signal and the subchannel signal can be adjusted with a simple configuration of the FIR filters 54 and 56, and the phases are matched by setting the multiplication coefficients of the FIR filters 54 and 56 to optimum values. be able to.

  Further, by setting the adaptive filter 86 having the algorithm unit as the FIR filter on the sub-channel side, the multiplication coefficient of the FIR filter can be automatically set when the multiplication coefficient is set.

  When the stereo demodulation circuit 26 of the present invention is applied to an FM receiver, FM stereo reception with a sense of reality with a large separation between L and R can be performed.

  As mentioned above, although embodiment of this invention was described concretely based on the embodiment, it is not limited to this and can be variously changed in the range which does not deviate from the summary.

It is a block diagram of the FM receiver using the stereo demodulation circuit of this invention. It is a block diagram which shows the structure of the stereo demodulation circuit of this invention. It is a block diagram which shows the structure of the stereo signal processing circuit in the stereo demodulation circuit of this invention. It is a block diagram which shows the structure of a FIR filter. It is a figure for demonstrating the characteristic of the phase correction of a FIR filter. It is a figure for demonstrating the relationship between a phase correction amount and a separation characteristic. It is a block diagram of the stereo signal processing circuit in the stereo signal processing circuit which concerns on other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 High frequency amplifier circuit 12 Local oscillator circuit 14 Mixer circuit 18 PLL circuit 20 Intermediate frequency amplifier circuit 22 Limiter circuit 24 FM detection circuit 26 Stereo demodulation circuit 28, 30 De-emphasis circuit 32, 34 Low frequency amplifier circuit 40, 50 Low pass filter 42, 44 Band pass filter 46 Subcarrier generation circuit 48 MIX circuit 52, 82 Stereo signal processing circuit 53, 83 Matrix circuit 54, 56, 84 FIR filter 58, 88 Addition circuit 60, 90 Subtraction circuit 62 Amplification circuit 80 Addition circuit 86 Adaptive filter 100 front end 200 intermediate frequency amplifier

Claims (6)

In a stereo demodulation circuit having a matrix circuit that generates and outputs an L signal and an R signal based on a main channel signal and a sub-channel signal in a stereo signal,
A first phase adjustment circuit for adjusting the phase of the main channel signal;
A second phase adjustment circuit that adjusts the phase of the subchannel signal to match the phase of the output of the first phase adjustment circuit;
A stereo demodulator circuit comprising: a matrix demodulator in front of the matrix circuit. The matrix circuit is
An adder circuit that outputs an L signal based on the main channel signal and the subchannel signal;
A subtracting circuit for outputting an R signal based on the main channel signal and the sub channel signal;
With
The output of the first phase adjustment circuit is input to the addition circuit and the subtraction circuit,
The stereo demodulation circuit according to claim 1, wherein the output of the second phase adjustment circuit is input to the addition circuit and the subtraction circuit.   3. The stereo demodulation circuit according to claim 1, wherein an amplification circuit that amplifies the sub-channel signal to a predetermined magnitude is provided at a front stage or a rear stage of the second phase adjustment circuit. The first phase adjustment circuit and the second phase adjustment circuit are:
A plurality of delay circuits for outputting an input signal after a predetermined period of time;
A plurality of multiplication circuits in which multiplication coefficients corresponding to outputs of the plurality of delay circuits are respectively set;
An addition circuit for adding and outputting the outputs of the plurality of multiplication circuits;
Have
4. The stereo demodulation circuit according to claim 1, wherein the phase is adjusted according to a set value of the multiplication coefficient. The second phase adjustment circuit includes:
An algorithm unit for changing the multiplication coefficient according to an error signal between the output of the first phase adjustment circuit and the output of the second phase adjustment circuit;
5. The stereo demodulation circuit according to claim 4, wherein the multiplication coefficient when the error signal is minimized is set in the multiplication circuit. The stereo demodulation circuit according to claim 1, wherein the stereo signal is an FM reception signal.

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