JP2005260235A - Embedded bit line type nonvolatile floating gate memory cell having independently controllable control gate in trench, array of cell, and method for manufacturing cell - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an embedded bit line type read/program nonvolatile memory cell and an array of the cells capable of achieving high density. <P>SOLUTION: The cell and the array are formed in a semiconductor substrate having a plurality of separated trenches wherein a flat surface is formed between respective trenches. The respective trenches have sidewalls and bottom walls. The respective memory cells have floating gates for storing charge. The cell has separated source/drain regions, and a channel which has two portions is formed between the regions. One side of the source/drain regions is situated on the bottom wall of the trench. The floating gate covers a first area of the channel, and is separated from the sidewall of the trench. A gate electrode controls the conductivity of the channel in a second area in the flat surface of the substrate. The other side of the source/drain regions is situated on the flat surface of the substrate. An independently controllable control gate is situated in the trench isolated from the floating gate, and capacitively coupled with the floating gate. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  This application is a continuation-in-part of pending application Ser. No. 10 / 409,407, filed Apr. 7, 2003, the disclosure of which is incorporated herein by reference.

  The present invention relates to a buried bit line read / program nonvolatile memory cell that uses a floating gate in a trench to store charge. In particular, the present invention relates to a non-volatile memory cell having an independently controllable control gate that is also capacitively coupled to a floating gate in a trench, an array of such cells, and a method of manufacturing.

  Read / program non-volatile memory cells that use floating gates for storage formed on the plane of a semiconductor substrate are well known in the art. See, for example, US Pat. Nos. 5,029,130 and 6,426,896. In general, this type of memory cell is formed on a horizontal plane of a semiconductor substrate and includes programming of the floating gate by hot electron injection and erasure of electrons from the floating gate by Fowler-Nordheim tunneling between polys. The floating gate stores or does not store charge. The charge stored in the floating gate controls the conduction of charge in the planar channel of the transistor. As the degree of integration of semiconductor processing increases, it is desirable to increase the density of such storage devices.

US Pat. No. 5,029,130 US Pat. No. 6,426,896

  However, as the demand for high density storage devices increases, it is necessary to increase the density of such cells in the semiconductor substrate.

In the present invention, a non-volatile memory cell is formed in a substantially single crystal semiconductor material of a first conductivity type having a substantially flat surface with a trench. The trench has a side wall and a bottom wall. The first region of the second conductivity type different from the first conductivity type exists in the semiconductor material along the plane. A second region of the second conductivity type is present in the semiconductor material along the bottom wall of the trench. The channel region has a first portion and a second portion and connects the first region and the second region for charge conduction. The first portion is along the surface adjacent to the first region, and the second portion is along the sidewall adjacent to the second region. There is a dielectric over the channel region. The floating gate covers the dielectric of the trench and is spaced from the second portion of the channel region. The first gate electrode covers the dielectric and is spaced from the first portion of the channel region. The second gate electrode is in the trench and is capacitively coupled to the floating gate.
The present invention also relates to an array of the nonvolatile memory cells, the nonvolatile memory cells, and a method for manufacturing the array.

  1A to 1F and FIGS. 2A to 2R illustrate the method of the present invention and illustrate the process steps for forming the memory cell array of the present invention. The method starts with a semiconductor substrate 10, which is preferably P-type and well known in the art. The thickness of each layer described below will depend on the design rules and the generation of processing technology. In this specification, 0.10 micron processing is described. However, those skilled in the art will appreciate that the present invention is not limited to any particular generation of processing technology, or to any specific value of any of the processing parameters described below. I will.

Formation of Isolation Region FIGS. 1A through 1F show a known STI method for forming an isolation region on a substrate. Referring to FIG. 1A, a plan view of a semiconductor substrate 10 (or semiconductor well) is shown, preferably P-type, as is known in the art. The first material layer 12 and the second material layer 14 are formed on a substrate (for example, a growth method or a vapor deposition method). For example, the first layer 12 can be silicon dioxide (hereinafter referred to as “oxide”), and can be formed by any known method such as oxidation or oxide deposition (eg, chemical vapor deposition or CVD). Formed on top with a thickness of about 60 to 150 Angstroms. The second layer 14 may be silicon nitride (hereinafter referred to as “nitride”), and is preferably formed on the oxide layer 12 with a thickness of about 1000 to 2000 angstroms by CVD. FIG. 1B shows a cross-sectional view of the resulting structure.

  After the formation of the first layer 12 and the second layer 14, a suitable photoresist material 16 is applied on the nitride layer 14, and then a masking process is performed, as shown in FIG. The photoresist material is selectively removed from the specific region (band 18) extending in the vertical direction. Where the photoresist material 16 has been removed, a standard etch process (ie, an anisotropic nitride and oxide etch process) is used to expose the exposed nitride layer 14 and oxide layer 12 in the strip 18. Are etched away, and a trench 20 is formed in the structure. The distance W between adjacent bands 18 can be as small as the minimum lithographic shape size of the processing steps used. Next, as shown in FIG. 1D, a silicon etch process is used to extend the trench 20 down into the silicon substrate 10 to a depth of about 500 to 4000 angstroms. Where the photoresist material 16 has not been removed, the nitride layer 14 and the oxide layer 12 remain. The resulting structure shown in FIG. 1D has active regions 22 alternating with isolation regions 24.

  The structure is further processed to remove residual photoresist material 16. Next, as shown in FIG. 1E, the isolation material, such as silicon dioxide, is chemically mechanically polished to remove oxide layers other than the oxide block 26 in the first trench 20 after depositing a thick oxide layer. The first trench 20 is formed by CMP (using the nitride layer 14 as an etching stopper). Next, as shown in FIG. 1F, the residual nitride layer 14 and oxide layer 12 are removed by a nitride / oxide etch process leaving an STI oxide block 26 extending along isolation region 24.

  The aforementioned STI isolation method is a preferred method for forming the isolation region 24. However, known LOCOS isolation methods (eg, LOCOS, polybuffer LOCOS, etc.) can also be used, in which case the trench 20 does not extend into the substrate and the isolation material forms on the substrate surface in the band region 18. be able to. 1A to 1F show a memory cell array region of a substrate, and a column of memory cells is formed in an active region 22 separated by a separation region 24. FIG. It should be noted that the substrate 10 includes at least one peripheral region, in which a control circuit for operating the memory cells formed in the memory cell array region is formed. Also, the isolation block 26 is preferably formed in the peripheral region during the same STI or LOCOS process described above.

Memory Cell Formation The structure shown in FIG. 1F is further processed as follows. 2A to 2Q show cross-sectional views of the active region 22 of the structure viewed from a direction orthogonal to the structure of FIG. 1F (along line 2A-2A shown in FIGS. 1C and 1F).

  As shown in FIG. 2A, an insulating layer 30 (preferably an oxide) is first formed on the substrate 10. At this point, the active region 22 portion of the substrate 10 can be doped for good independent control over the peripheral region of the cell array portion of the storage device. This doping process is often called Vt implantation or cell well implantation and is well known in the art. During this implantation, the peripheral region is protected by a photoresist layer that is deposited over the entire structure and removed only from the memory cell array region of the substrate.

  Next, a thick layer 32 of hard mask material such as nitride (eg, a thickness of ˜3500 mm) is formed on the oxide layer 30. The plurality of parallel second trenches 34 apply a photoresist (masking) material over the nitride layer 32 and then perform a masking process to remove the photoresist material from the selected parallel strip region. Thus, the nitride layer 32 is formed. An anisotropic nitride etch process is used to remove the exposed portion of the nitride layer 32 in the band region and form a second trench 34 that extends down to the oxide layer 30 and exposes it. . After removing the photoresist material, an anisotropic oxide etch process is used to remove the exposed portions of the oxide layer 30 and extend the second trench 34 down to the substrate 10. Next, a silicon anisotropic etch process is used to extend the second trenches 34 down into the substrate 10 of each active region 22 (eg, about 0.15 um for about 0.15 um technology). Down to a depth corresponding to a shape size of about 1). Alternatively, the photoresist material can be removed after the trench 34 is formed in the substrate 10. FIG. 2B shows the resulting active region 22.

  Next, an insulator layer 36 (eg, a thickness of ~ 70 to 120 inches) is formed along the exposed silicon of the second trench 34 that forms the bottom and lower sidewalls of the second trench 34 (see FIG. Preferably by thermal oxidation treatment). Next, a thick layer 38 of polysilicon (hereinafter referred to as “poly”) filling the second trench 34 is formed on the structure. The poly layer 38 can be doped by ion implantation or by an in-situ process (eg, n +). FIG. 2C shows the resulting active region 22.

  A poly etch process (eg, a CMP process using the nitride layer 32 as an etch stop) is used to remove the poly layer 38 other than the block 40 of polysilicon 38 remaining in the second trench 34. Next, a controlled poly etch process is used to reduce the height of the polyblock 40, and the top of the polyblock 40 is located above the substrate surface but is separated as shown in FIG. 2D. It is located below the upper end of 24 STI blocks 26.

  Next, another poly etching is performed to form an inclined portion 42 at the upper end of the poly block 40 (adjacent to the side wall of the second trench). Next, the nitride spacer 44 is formed along the sidewall of the second trench above the inclined portion 42 of the polyblock 40. Forming the spacer is well known in the art and includes the deposition of a specific material that covers the entire outline of the structure, followed by an anisotropic etch, whereby the material is removed from the horizontal plane of the structure. Is removed, but the material remains almost intact on the vertical surface of the structure. The spacer 44 can be formed of an arbitrary dielectric such as oxide or nitride. In the present invention, the insulating spacer 44 is anisotropic such as known reactive ion etching (RIE) for depositing a nitride layer over the entire structure and then removing the deposited nitride layer other than the spacer 44. It is formed by performing a reactive nitride etching process. FIG. 2E shows the resulting active region 22. Note that the formation of nitride spacers 44 is optional if the spacers 44 are used to increase the sharpness of the tip formed by the ramp 42 of the polyblock 40. That is, FIGS. 2 through 2R illustrate the remaining processing steps without the optional nitride spacer 44.

  Next, a thermal oxidation process is performed, and as shown in FIG. 2F, the exposed upper surface of the polyblock 40 is oxidized (the oxide layer 46 is formed on the upper surface). Next, an oxide spacer is deposited along the sidewall of the second trench 34 by depositing an oxide on the structure (eg, about 350 mm thick) followed by an anisotropic oxide etch process. 48 (shown in FIG. 2G) is formed. Further, the oxide etching process removes the central portion of each oxide layer 46 of the second trench 34. FIG. 2G shows the resulting active region 22.

  Next, an anisotropic polyetching process is performed to remove the central portion of the polyblock 40 that is not protected by the oxide spacers 48, and as shown in FIG. Polyblock 40 remains. Next, an insulating layer 50 is formed along the exposed side surface of the polyblock 40a inside the second trench 34 using insulating vapor deposition and anisotropic etching back processing (shown in FIG. 2I). The insulating material can be any insulating material (eg, oxide / nitride / oxide (ONO) or other high dielectric). The insulating material is deposited on the substrate as shown in FIG. 2J by the oxide deposition / etching process again thickening the oxide spacers 48 and removing the exposed portion of the oxide layer 36 at the bottom of each of the second trenches 34. It is preferably an oxide so that 10 is exposed. In addition, this process also removes STI oxide between adjacent columns of active region 22 in trench 34 as oxide layer 36 at the bottom of each of trenches 34 is removed.

  Appropriate ion implantation (and possible annealing) is then performed across the surface of the structure to form a first (source) region 52 in the exposed substrate portion at the bottom of the second trench 34. The source region 52 is self-aligned with respect to the second trench 34 and forms a continuous row that is substantially orthogonal to the column of the active region 22 and has a first conductivity type (eg, P-type) of the substrate. Different from the second conductivity type (for example, N type). The ions have no effect on the nitride layer 32. FIG. 2K shows the resulting active region 22.

  Subsequently, an oxidation deposition process is performed, and the bottom of each trench 34 is filled with an oxide layer 35. This oxide layer 35 is at least about 100 angstroms and is to be formed so that capacitive coupling can occur between the control gate 54 to be deposited and the polyblock 40. Thinner than 40 height. Next, a poly vapor deposition step and subsequent poly CMP etching (using the nitride layer 32 as an etching stopper) is performed, and the second trench 34 is filled with poly blocks 40 as shown in FIG. 2L. . Thus, poly 54 fills each trench 34 in a continuous row. Next, a nitride etching process is performed to remove the nitride layer 32 and expose the upper edge of the polyblock 40. Next, the tunnel oxide layer 56 is formed on the exposed upper edge of the polyblock 40 by thermal oxidation, oxide deposition, or both. This oxide formation step will also increase the thickness of the oxide layer 30 of the substrate 10 while simultaneously forming the oxide layer 58 on the exposed top surface of the polyblock 40. At this stage, the active region 22 is masked, so that optional ion implantation can be performed on the peripheral region. 2M and 2N show the resulting active region 22.

  Next, a nitride spacer 70 is formed adjacent to the structure shown in FIG. 2N. This can be achieved by depositing silicon nitride 70 over the entire surface and then anisotropically etching the nitride to form spacers 70. FIG. 2O shows the resulting structure.

  Implantation is performed throughout the structure. Specifically, drain regions 72 are formed in regions between the nitride spacers 70. The implantation energy is large enough to spread below the isolation oxide. That is, the drain region 72 is continuous in the row direction. FIG. 2P shows the resulting structure.

  Nitride spacer 70 has been removed and FIG. 2Q shows the resulting structure.

  Finally, a poly layer 62 (for example, a thickness of about 500 mm) is formed on the structure by a poly deposition process. Subsequently, a photoresist deposition and masking process is performed to form a plurality of strip-like poly layers 62 spaced apart from each other in the active region 22. FIG. 2R shows the resulting active region 22. Each poly layer 62 functions as a word line of the memory array.

  As shown in FIG. 2R, the process of the present invention forms an array of memory cells in which each memory cell 15 is between a source region 52 and a drain region 72. It will be understood that it can be switched during operation). The non-planar channel region connects the source region 52 and the drain region 72, and the channel region has two parts, a first part and a second part. The first portion of the channel region extends along one side wall of one trench 34 and is adjacent to the first source region 52a. A second portion of the channel region is along the plane of the substrate 10 and between the trench 34 and the drain region 72. The dielectric layer covers the channel region. The dielectric covering the first portion of the channel is layer 36a. The dielectric covering the second part of the channel is layer 30. The floating gate 40a covers the layer 36a and covers the first portion of the channel region adjacent to the first source region 52a. A gate electrode 62 formed by the poly layer 62 is on the dielectric layer 30 and covers the second portion of the channel region. The control gate 54 is insulated from the source region 52 and capacitively coupled to the floating gate 40a. Each floating gate 40 is substantially orthogonal to the gate electrode 62 and the surface of the substrate 10. Finally, the source region such as the source region 52a and the control gate such as the control gate 54a related thereto are shared with the memory cell 15 adjacent on one side in the same active region 22, and the drain region 72 is on the other side. It is shared with the adjacent memory cell 15.

  All the floating gates 40 are disposed in the trenches 34, and each floating gate 40 faces a part of the channel region and is insulated. In addition, each floating gate 40 includes an upper portion that extends above the substrate surface, terminates at one end of the gate electrode 62 and is insulated, and terminates in an oxide layer. 56 provides a route for Fowler Nordheim tunneling via 56. Each control gate 54 extends along the floating gate 44 and is insulated from the floating gate 44 (by the oxide layer 50) to provide enhanced voltage coupling with the floating gate 44. .

  The interconnections associated with the plurality of memory cells 15 forming the array are as follows. In the memory cell 15 in the same column, that is, in the same active region 22, the word line 62 forming the gate electrode for each memory cell 15 extends to each memory cell 15 in the Y direction. For memory cells 15 across the same row, ie, active region 22 and STI 26, source line 52 and its associated control gate 54 extend continuously to each of these memory cells 15 in the X direction. Further, the drain line 72 continuously extends to each memory cell 15 in the X direction. Finally, as can be seen from the above description, adjacent row memory cells 15 share the same source region 52 and associated same control gate 54 on one side and the same drain region 72 on the other side. . Each of the memory cells 15 has a word line 62, a control gate 54, a drain region 72, and a source region 52, which are four terminals that can be independently controlled.

  As can be understood by those skilled in the art, the lines 52a, 52b, 52c and the like are buried diffusion lines, and the connection to these lines needs to be made outside the memory cell array. One way is to use a polyblock 54 similar to the control gate 54, but this polyblock 54 is in electrical contact with buried diffusion lines 52a, 52b, 52c, etc. outside the array. Further, polyblocks 54 that contact buried diffusion lines 52a, 52b, 52c, etc. outside the array should not be in electrical contact with independent control gates 54 in the array. Further, the lines 72a, 72b, and 72c are also buried diffusion lines, and it is necessary to make a connection to these lines. That is, the array of memory cells 15 is a virtual ground array.

Operation of Memory Cell The operation of the memory cell 15 shown in FIG. 2R will be described below.

There are two methods for erasing the erase memory cell 15. In the first method, the memory cell 15 can be erased by applying 0 V to the drain region 72 and 0 V to the source region 52. Since the same voltage is applied to the source region 5 and the drain region 72, no charge is conducted in the channel region. A negative voltage of about −8 to −15 V is applied to the control gate 54. Finally, a positive voltage of about +2 to +4 V is applied to the word line 62. Since the control gate 54 is highly capacitively coupled to the floating gate 40, a high negative voltage is generated in the floating gate 40. This causes a large voltage difference between the floating gate 40 and the word line 62. All electrons stored in the floating gate 40 are bounced back by the control gate 54, attracted by the positive voltage applied to the word line 62, and removed from the floating gate 40 by the mechanism of the Fowler-Nordheim tunneling phenomenon. 56 passes through the word line 62. This poly-poly tunneling mechanism for erasure is described in US Pat. No. 5,029,130, the entire disclosure of which is incorporated herein by reference.

  A second method for erasing the memory cell 15 is to apply a low positive voltage of about 0 V to the drain region 72 and a low voltage of about +2 to +5 V to the source region 52. A negative voltage of about −8 to −15 V is applied to the control gate 54. Finally, a zero or low negative voltage of about 0 to −2V is applied to the word line 62. Since a positive voltage is not applied to the word line 62, the channel region is not turned on. Furthermore, since the control gate 54 is highly capacitively coupled to the floating gate 40, a low negative voltage is generated in the floating gate 40. As a result, a large voltage difference is generated between the floating gate 40 and the source region 52. All electrons stored in the floating gate 40 are bounced back by the control gate 54, attracted by the positive voltage applied to the source region 52, and removed from the floating gate 40 by the mechanism of the Fowler-Nordheim tunnel phenomenon to remove the oxide 35. Pass through to source region 52.

Programming of the programming memory cell 15 can be performed as follows. The source region 52 is held at a positive voltage of +3 to + 5V. The control gate 54 is held at a positive voltage of +8 to + 10V. The word line 62 is held at a positive voltage of 1 to 3V. The drain region 72 is held at the ground potential. Since the control gate 54 is highly capacitively coupled to the floating gate 40, a positive voltage of +8 to + 10V on the control gate 54 causes the floating gate 40 to turn on the first portion of the channel region. Produces a sufficiently high positive potential. A positive voltage of 1 to 3V on the word line 62 is sufficient to turn on the second portion of the channel region. That is, electrons flow from the drain region 72 to the source region 52 in the channel region. However, the electrons will experience a sudden voltage increase due to the high positive voltage of the floating gate 40 at the junction in the channel region where the channel region changes substantially 90 ° from the plane to the trench 34. . As a result, electrons are hot channel injected into the floating gate 40. This hot channel electron injection mechanism for programming is described in US Pat. No. 5,029,130, the entire disclosure of which is incorporated herein by reference.

Reading of the read memory cell 15 can be performed as follows. Source region 52 is held at ground potential. The control gate 54 is held at a positive voltage Vdd. Word line 62 is normally held at a positive voltage Vdd sufficient to turn on the second portion of the channel region. The drain region 72 is held at a low positive voltage such as + 1.0V. The positive voltage Vdd on the control gate 54 is sufficient to turn on the first portion of the channel region when the floating gate 40 is not programmed. In this case, electrons flow from the source region 52 to the drain region 72 in the channel region. However, when the floating gate 40 is programmed, the positive voltage Vdd on the control gate 54 is not sufficient to turn on the first portion of the channel region. In this case, the channel remains non-conductive. That is, the magnitude of the current detected in the drain region 72 or the presence / absence of the current determines the programming state of the floating gate 40.

Operation of Memory Cell Array Next, the operation of the array of memory cells 15 will be described. FIG. 3 schematically shows an array of memory cells. As shown in FIG. 3, the array of memory cells 15 comprises a plurality of columns, ie 15a (1-3) and 15b (1-3), a plurality of rows, ie 15 (ab) 1, 15 (a- b) and a plurality of memory cells arranged in 15 (ab) 3. The word line 62 connected to the memory cell 15 is also connected to another memory cell 15 in the same column. The source region 52 and the control gate 54 are connected to the cell 15 in the same row and are shared by the memory cells 15 on both sides. The drain region 72 is connected to cells in the same row and is shared by the memory cells 15 on both sides. The memory cell 15 in one row has a common drain region 72 in contact with the memory cell 15 on one side, and a common source region 52 and a control gate 54 in contact with the memory cell on the other side.

As described above, the erase / erase operation has two possible operation modes. In the first mode, individual memory cells 15 can be erased. The voltages applied to the various lines are as follows. A ground potential is applied to the drain region 72 relating to the selected memory cell 15. Similarly, the ground potential is applied to the drain region 72 relating to the unselected memory cell 15. A ground potential is applied to the source region 52 relating to the selected memory cell 15. Similarly, the ground potential is applied to the source region 52 relating to the memory cell 15 that is not selected. A positive voltage of about +2 to +4 V is applied to the word line 62 related to the selected memory cell 15. A ground potential is applied to the word line 62 related to the unselected memory cell 15. Finally, a high negative voltage of about −8 to −15 V is applied to the control gate 54 related to the selected memory cell 15. A ground potential is applied to the control gate 54 related to the memory cell 15 which is not selected.

  As described above, for the selected memory cell 15, the large capacitance of the control gate 54 relative to the floating gate 40 results in a high negative voltage on the floating gate 40. The positive voltage on the adjacent word line 62 causes the electrons to be attracted to the word line 62, and the electrons are removed from the floating gate 40 by the Fowler-Nordheim tunneling mechanism. For unselected memory cells 15 in the same column, a low positive voltage of +2 to +4 V is applied to the word line 62, but the control gate 54 of the unselected memory cells 15 is held at ground potential. The electrons on the floating gate 40 of the unselected memory cell 15 in the same column will not be attracted to the word line 62. For the non-selected memory cell 15 in the same row, a high negative voltage is applied to the control gate 54, but the corresponding word line 62 is held at the ground potential. That is, there is no positive voltage that draws electrons from the floating gate 40 of the unselected memory cell 15. In this mode, erasing is bit selectable.

  In the second mode of erasing, the various voltages applied are as follows. A drain potential 72 for the selected memory cell 15 is supplied with a ground potential. Similarly, the ground potential is supplied to the drain region 72 related to the unselected memory cell 15. A low positive voltage of +2 to +4 V is supplied to the source region 52 related to the selected memory cell 15. A ground potential is supplied to the source region 52 related to the memory cell 15 that is not selected. A low negative voltage of about 0 to −2 V from the ground potential is supplied to the word line 62 related to the selected memory cell 15. A low negative voltage of about 0 to −2 V from the ground potential is supplied to the word line 62 related to the unselected memory cell 15. Finally, a high negative voltage of about −8 to −15 V is supplied to the control gate 54 related to the selected memory cell 15. A ground potential is supplied to the control gate 54 related to the memory cell 15 which is not selected.

  In this operating mode, all memory cells 15 in the same row are erased simultaneously. That is, in this mode, erasing can be selected in a row. For the selected row of memory cells 15, the large capacitance of control gate 54 relative to floating gate 40 results in a high negative voltage on floating gate 40. The positive voltage on the adjacent source region 52 causes the electrons to be attracted to the source region 52, and the electrons are removed from the floating gate 40 by the Fowler-Nordheim tunneling mechanism. For the memory cell 15 in the unselected row, the control gate 54 is held at the ground potential. Finally, the channel regions of all the memory cells 15 are not reliably turned on by the negative voltage from the ground potential supplied to all the word lines 62.

Assume that floating gate 40 of program memory cell 15 is programmed. In this case, based on the above discussion, the voltages applied to the various lines are as follows. Line 72b is at ground potential, but all other drain regions 72a are at Vdd. Line 52a is between +3 and + 5V, but all other source lines 52b are at ground potential. Line 62b is +1 to + 3V, but all word lines 62a are -2V from ground potential. Line 62b is +1 to + 3V, but all other word lines 62a are -2V from ground potential. Line 54a is between +8 and + 10V, but all other lines 54b are at ground potential. The “disturbance” on the unselected memory cell 15 is as follows.

  For the memory cells 15 in the unselected columns, applying 0 to −2 V to the word line 62a is because the second part of the channel region (the part controlled by the word line 62a) is not in the ON state. This means that all the channel regions related to the memory cells 15a (1-n) and 15c (1-n) are not turned on. In other words, there is no disturbance. For the unselected row memory cell 15b1 in the same selected column but having the same source region 52 and control gate 54 as the selected memory cell 15, applying Vdd to the line 72a means that the memory cell It means that little or no current flows through 15b1. Finally, for an unselected row memory cell 15b3 in the same selected column but having a common drain region 72 with the selected memory cell 15, applying a ground potential to the lines 54b and 52b means that the memory This means that little or no current flows through the cell 15b3.

It is assumed that reading the floating gate 40 of reading the memory cell 15. Based on the above discussion, the voltages applied to the various lines are as follows. Drain region line 72b is held at a positive voltage of about + 1V, while unselected drain line 72a is held at ground potential. The control gate line 54a is held at the positive voltage Vdd, while the unselected control gate 54b is held at the ground potential. The selected word line 62b is held at the positive voltage Vdd, while the unselected word line 62a is held at the ground potential. Finally, the selected source line 52a is held at ground potential, while the unselected source line 52b directly adjacent to the selected drain line 72b is held at 1V, and the unselected source line 52 directly adjacent to the unselected drain line 72a is Held at ground potential. That is, all the memory cells 15 on one side of the selected memory cell 15 have the same voltage as the voltage applied to the source 52 and the drain 72, and similarly, all the memory cells on the other side It has the same voltage as the voltage applied to the drain 72. The “disturbance” on the unselected memory cell 15 is as follows.

  For the memory cells 15 in the unselected column, applying 0 V to the word line 62a means that the channel regions related to the memory cells 15 are not all turned on. In other words, there is no disturbance. For memory cells 15b1 and 15b3 in the same selected row but in an unselected row, applying the same voltage to the source 52 and drain 72 of those memory cells means that the channel region does not turn on. To do. That is, there is little or no disturbance to the memory cell 15b2.

  From the above description, a novel high density non-volatile memory cell, array, and manufacturing method should be understood. Although a preferred embodiment has been described in which a single bit is stored in each floating gate of a memory cell, multiple bits can be stored in the floating gate of a single memory cell to increase storage density. It should be understood that it is within the spirit of the present invention.

1 is a plan view of a semiconductor substrate used in the first step of the method of the present invention to form an isolation region. FIG. 1B is a cross-sectional view of the structure taken along line 1B-1B of FIG. 1A, illustrating the first processing step of the present invention. FIG. 4 is a plan view of the structure, showing the next step of processing the structure of FIG. 1B, in which an isolation region is formed. 1C is a cross-sectional view of the structure viewed along line 1D-1D of FIG. 1C, showing isolation trenches formed in the structure. FIG. 1D is a cross-sectional view of the structure of FIG. 1D illustrating the formation of an isolation block material in an isolation trench. FIG. 1E is a cross-sectional view of the structure of FIG. 1E, showing the final structure of the isolation region. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A in FIG. 1F and illustrates the processing steps of the semiconductor structure in forming the nonvolatile storage array of floating gate memory cells of the present invention. 1 is a schematic circuit diagram of a memory cell array of the present invention.

Explanation of symbols

10 Semiconductor substrate 15a Memory cell 15b Memory cell 30 Oxide layer (dielectric layer)
36a dielectric layer 36b dielectric layer 40a floating gate 40b floating gate 52a source region 52b source region 54a control gate 54b control gate 56 tunnel oxide layer 58a oxide layer 58b oxide layer 62 gate electrode 72 drain region

Claims (20)

A substantially monocrystalline semiconductor material of a first conductivity type comprising a substantially planar surface having trenches with sidewalls and bottom walls;
A first region of a second conductivity type different from the first conductivity type along the plane of the semiconductor material;
A second region of the second conductivity type along the bottom wall of the trench of the semiconductor material;
A first portion along the surface adjacent to the first region and a second portion along the sidewall adjacent to the second region, the first region for conducting charge; And a channel region connecting the second region;
A dielectric on the channel region;
A floating gate in the trench, on the dielectric, and spaced from the second portion of the channel region;
A first gate electrode overlying the dielectric and spaced from the first portion of the channel region;
A second gate electrode in the trench and capacitively coupled to the floating gate;
A non-volatile memory cell comprising:   The cell of claim 1, wherein the substantially single crystal semiconductor material is single crystal silicon.   The cell according to claim 1, wherein the floating gate has a tip substantially adjacent to the first gate electrode.   A second dielectric material that enables Fowler-Nordheim tunneling of electrons from the floating gate to the first gate electrode is further provided between the tip portion and the first gate electrode. The cell according to claim 3.   The second dielectric material further comprising a Fowler-Nordheim tunnel phenomenon from the floating gate to the second region between the floating gate and the bottom wall of the trench. The cell according to 1. A substantially monocrystalline semiconductor material of a first conductivity type comprising a substantially planar surface having a plurality of trenches each having a sidewall and a bottom wall;
A plurality of nonvolatile memory cells arranged in a plurality of rows and columns in the semiconductor substrate material;
An array of non-volatile memory cells arranged in a plurality of rows and columns, each cell comprising:
A first region of a second conductivity type different from the first conductivity type along the surface of the semiconductor material;
A second region of the second conductivity type along a bottom wall of the trench of the semiconductor material;
A first portion along the surface adjacent to the first region and a second portion along the sidewall adjacent to the second region, the first region for conducting charge; And a channel region connecting the second region;
A dielectric on the channel region;
A floating gate overlying the dielectric and spaced apart from the second portion of the channel region;
A first gate electrode overlying the dielectric and spaced from the first portion of the channel region;
A second gate electrode in the trench and capacitively coupled to the floating gate;
With
The cells in the same row share the first gate electrode;
The cells in the same column share the first region, the second region, and the second gate electrode;
An array of non-volatile memory cells, wherein the cells of adjacent columns share the first region on one side and share the second gate electrode and the second region on the other side.   7. The array of claim 6, wherein the substantially single crystal semiconductor material is single crystal silicon.   7. The array of claim 6, wherein in each cell the floating gate has a tip substantially adjacent to the first gate electrode.   Each cell further includes a second dielectric between the tip and the first gate electrode that enables Fowler-Nordheim tunneling of electrons from the floating gate to the first gate electrode. 9. The array of claim 8, comprising an array.   Each cell further comprises a second dielectric between the floating gate and the bottom wall of the trench that enables Fowler-Nordheim tunneling of electrons from the floating gate to the second region. The array of claim 6.   The array of claim 6 wherein the isolation region isolates adjacent rows of cells. A method of manufacturing an array having a plurality of non-volatile memory cells arranged in a plurality of rows and columns in a substantially single crystal semiconductor substrate material of a first conductivity type, comprising:
Forming an isolation region on the semiconductor substrate having a substantially flat surface, extending in the column direction, substantially parallel to and spaced apart from each other, and forming an active region between each pair; When,
Forming a plurality of memory cells in each of the active regions;
Forming each of the memory cells comprises:
Forming a trench having a sidewall and a bottom wall in the surface of the semiconductor substrate;
Forming a floating gate in the trench that is insulated from the sidewall along the sidewall;
Forming a first region of a second conductivity type different from the first conductivity type in the substrate along the bottom wall of the trench;
Forming a first gate electrode in the trench that is insulated from the first region and capacitively coupled to the floating gate;
Forming in the substrate a second region of a second conductivity type along the surface and spaced from the trench;
Forming a second gate electrode spaced from the surface between the second region and the trench;
A method of manufacturing an array of non-volatile memory cells, comprising:   The method of claim 12, wherein the step of forming the first gate electrode comprises the step of forming the second gate electrode continuously in the row direction across a plurality of columns. .   The method of claim 12, wherein forming the second gate electrode comprises forming the second gate electrode continuously across the plurality of rows in the column direction. .   The step of forming the first region and the second region includes the step of forming the first region and the second region continuously in the row direction across a plurality of columns. The method according to claim 14.   The cells in the same row share the second gate electrode, and the cells in the same column share the first region, the second region, and the first gate electrode and are adjacent to each other. 16. The method of claim 15, wherein the cells in a column share the second region on one side and share the first gate electrode and the first region on the other side. A method of manufacturing a non-volatile memory cell in a substantially single crystal semiconductor substrate material of a first conductivity type having a substantially flat surface comprising:
Forming a trench having a sidewall and a bottom wall in the surface of the semiconductor substrate;
Forming a floating gate in the trench that is insulated from the sidewall along the sidewall;
Forming a first region of a second conductivity type different from the first conductivity type in the substrate along the bottom wall of the trench;
Forming a first gate electrode in the trench that is insulated from the first region and capacitively coupled to the floating gate;
Forming in the substrate a second region of a second conductivity type along the surface and spaced from the trench;
Forming a second gate electrode spaced from the surface between the second region and the trench;
A method of manufacturing a non-volatile memory cell comprising:   An insulating material having a thickness that enables Fowler-Nordheim tunneling of electrons from the second floating gate to the second gate electrode is formed between the second gate electrode and the floating gate. The method of claim 17 further comprising the step.   And further comprising forming an insulating material between the floating gate and the bottom wall of the trench to enable Fowler-Nordheim tunneling of electrons from the floating gate to the second region. The method according to claim 17.   The method of claim 18, wherein forming the floating gate comprises forming the floating gate on a surface of the substrate.

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