JP2005260125A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of improving the reliability of wiring and decreasing capacities between wirings and between layers. <P>SOLUTION: The method for manufacturing the semiconductor device comprises steps of laminating a first interlayer insulating film 22 and a second interlayer insulating film 23 on a substrate 21 in this order, and applying treatments to the surface of the second film 23 and the surface of the wiring 28 using a neutral radical with a via 27 formed in a via hole 24 formed in the first film 22 and with the wiring 28 communicating to the via 27 formed in a trench 25 formed on the second film 23. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for forming a multilayer wiring structure using a material having a lower dielectric constant than silicon oxide for an interlayer insulating film.

  In recent years, with the high integration of semiconductor integrated circuit devices (LSIs), wiring process technology has become increasingly important for high-speed operation of LSIs. This is because an increase in wiring delay time has become remarkable due to miniaturization of semiconductor elements. In order to suppress the increase in the wiring delay time, it is necessary to reduce the wiring resistance, the capacitance between the wirings, and the interlayer capacitance.

  For reducing the wiring resistance, a copper (Cu) wiring having a low resistance compared to an aluminum alloy wiring conventionally used has been studied. In addition, with respect to the reduction of inter-wiring capacitance and inter-layer capacitance, an insulating film (low dielectric constant film) having a low dielectric constant compared to silicon oxide conventionally used as an inter-layer insulating film has been studied. Introduction of multilayer wiring technology using low dielectric constant films is considered important.

  As this multilayer wiring technique, since Cu dry etching is generally not easy, so-called trench wiring methods such as a single damascene method and a dual damascene method are considered promising.

Here, an example in which a Cu wiring structure using a low dielectric constant film is manufactured by a single damascene method will be described with reference to FIG. First, a low dielectric constant film 12a made of methyl silsesquioxane (MSQ) is formed on the substrate 11, and a protective film 12b made of silicon oxide (SiO ₂ ) is formed on the low dielectric constant film 12a. Is deposited. Thereby, an interlayer insulating film 12 composed of a laminated film of the low dielectric constant film 12 a and the protective film 12 b is formed on the substrate 11.

  Next, a groove pattern 13 is formed in the interlayer insulating film 12, and a barrier film 14 is formed on the interlayer insulating film 12 so as to cover the inner wall of the groove pattern 13. Thereafter, a conductive film (not shown) made of Cu is formed on the interlayer insulating film 12 in a state where the groove pattern 13 provided with the barrier film 14 is embedded. Thereafter, the conductive film and the barrier film 14 are removed by chemical mechanical polishing (CMP) until the surface of the interlayer insulating film 12 is exposed, whereby the barrier film 14 is formed in the groove pattern 13. Vias 15 are formed. At this time, the protective film 12b functions as a CMP stopper.

  Thereafter, a diffusion prevention film 16 made of silicon oxynitride (SiON) is formed on the interlayer insulation film 12 including the wiring 15. Before this diffusion prevention film 16 is formed, the surface of the interlayer insulation film 12 and It has been reported that the surface of the wiring 15 is reduced and cleaned by performing hydrogen plasma treatment or ammonia plasma treatment on the surface of the wiring 15 (see, for example, Patent Document 1).

JP 2002-110679 A

As an example of the conditions for such a hydrogen plasma treatment, the radio frequency (RF) power is set to 250 W, the pressure of the treatment atmosphere is set to about 530 Pa, the substrate temperature is set to 350 ° C., and the hydrogen gas flow rate is set to 600 cm ³ / min.

  In the wiring structure shown in FIG. 4A, the protective film 12b functions as a CMP stopper, but this protective film 12b is usually formed of silicon oxide. In order to further reduce the inter-wiring capacitance and the interlayer capacitance in the multilayer wiring structure of the 90 nm generation and beyond, attempts have been made to further lower the dielectric constant of the interlayer insulating film 12. That is, as shown in FIG. 4B, a configuration in which the low dielectric constant film 12c having high CMP resistance is used as the interlayer insulating film 12 and the diffusion prevention film 16 is formed on the low dielectric constant film 12c has been studied. Yes.

  However, as described above, when the surface of the wiring 15 is reduced and cleaned by performing hydrogen plasma treatment or ammonia plasma treatment on the surface of the interlayer insulating film 12 and the wiring 15, not only neutral radicals but also energy Ions are also present and the electron temperature is high. For this reason, the surface of the interlayer insulating film 12 and the surface of the wiring 15 are easily damaged by ions and high-temperature electrons.

  In particular, when the interlayer insulating film 12 is formed of the low dielectric constant film 12c as described with reference to FIG. 4B, the plasma processing is performed with the low dielectric constant film 12c exposed. However, the low dielectric constant film 12c has a coarser film density and lower heat resistance than silicon oxide, and therefore its surface tends to be easily damaged by ions and high-temperature electrons (D portion in the figure). was there. As a result, the dielectric constant increases due to the change in the surface of the low dielectric constant film 12c, the leakage current between wirings increases, and the inter-wiring voltage resistance such as TDDB (Time Dependence on Dielectric Breakdown) between wirings decreases. . In addition, the electromigration resistance tends to deteriorate due to the surface of the wiring 15 being damaged by ions or high-temperature electrons.

  In order to solve the above-described problems, a method of manufacturing a semiconductor device according to the present invention includes an insulating film and an insulating film provided on a substrate and a conductive layer exposed substantially on the same surface as the insulating film. The surface of the film and the surface of the conductive layer are characterized by performing treatment using neutral radicals.

  According to such a method for manufacturing a semiconductor device, since the surface of the substrate is subjected to a treatment using neutral radicals, ions having a higher energy than those in the conventional plasma treatment are performed. The reduction cleaning of the surface of the conductive layer is performed in a state where damage to the surface of the insulating film and the surface of the conductive layer due to high-temperature electrons is suppressed. Thereby, even when the insulating film is formed of a low dielectric constant film having a lower film density than that of silicon oxide, damage to the surface of the insulating film is suppressed.

  As described above, according to the method for manufacturing a semiconductor device of the present invention, damage to the surface of the insulating film due to ions or high-temperature electrons is suppressed. For this reason, it is possible to prevent an increase in dielectric constant due to alteration of the insulating film, and to suppress an increase in leakage current between wirings and a decrease in withstand voltage between wirings. In addition, since damage to the surface of the insulating film is suppressed, it is possible to form the insulating film with a low dielectric constant film having a structure that is easily damaged. Thereby, it is possible to further reduce the inter-wiring capacitance and the interlayer capacitance. In addition, since damage to the wiring surface due to ions and high-temperature electrons is suppressed, electromigration resistance can be improved.

  Therefore, since the wiring reliability can be improved and the wiring capacitance and interlayer capacitance can be reduced, a high-performance CMOS device can be realized, and the performance of computers, game machines, mobile products, etc. can be significantly improved. it can.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  An example of an embodiment of a semiconductor device according to the present invention will be described with reference to a manufacturing process sectional view of FIG. In the present embodiment, a method for forming a wiring structure made of Cu using a dual damascene method will be described.

  As shown in FIG. 1A, a first interlayer insulating film 22 is formed on a substrate 21 on which a semiconductor element such as a transistor is formed, and a second interlayer is formed on the first interlayer insulating film 22. An insulating film 23 is formed. Here, the first interlayer insulating film 22 and the second interlayer insulating film 23 are formed of a material film (low dielectric constant film) having a dielectric constant lower than that of silicon oxide. Specifically, the first interlayer insulating film 22 is formed by MSQ, for example, by a coating method, and the second interlayer insulating film 23 is formed by, for example, a hydrogenated silsesquioxane, by a coating method. (HSQ)). Here, although the first interlayer insulating film 22 and the second interlayer insulating film 23 are formed of different materials, they may be formed of the same material.

Here, as a material for forming the first interlayer insulating film 22 and the second interlayer insulating film 23, conventionally used silicon oxide (SiO ₂ ) may be used, but the dielectric constant is higher than that of silicon oxide. By using a low dielectric constant film having a low thickness, it is possible to reduce inter-wiring capacitance and interlayer capacitance, which is preferable.

  As such a low dielectric constant film, in addition to MSQ and HSQ used in the present embodiment, silicon oxycarbide (SiOC) -based material, silicon oxyfluoride (SiOF) -based material, or polyallyl ether (PAE), There are organic material films such as polyimide, porous films of these low dielectric constant films, and porous films of silicon oxide. These may be provided as a single layer film or may be a laminated film. Moreover, the laminated structure of the silicon oxide mentioned above and a low dielectric constant film | membrane may be sufficient.

  In particular, in the second interlayer insulating film 23, via holes and trenches provided in the first interlayer insulating film 22 and the second interlayer insulating film 23 are filled with a conductive film in a later step, and this conductive film is CMP-processed. Since it is polished by the method, it is preferably formed of a low dielectric constant film having high CMP resistance. Examples of such materials include SiOC-based materials other than MSQ and HSQ used in the present embodiment. Here, the SiOC-based material is formed by, for example, a chemical vapor deposition (CVD) method.

  Next, after a via hole 24 reaching the substrate 21 is formed in the first interlayer insulating film 22 and the second interlayer insulating film 23 by a normal photolithography technique and reactive ion etching technique, the second interlayer insulating film A trench 25 communicating with the via hole 24 is formed in 23. Although the example in which the via hole 24 is formed first has been described here, the trench 25 may be formed first if a dual damascene structure can be finally obtained. Further, the via hole 24 and the trench 25 may be formed by a resist mask process, or may be formed by a multilayer mask process.

  Next, as shown in FIG. 1B, a barrier film 26 made of, for example, tantalum is formed on the second interlayer insulating film 23 so as to cover the inner walls of the trench 25 and the via hole 24. This barrier film 26 prevents diffusion of Cu from the conductive layer made of Cu filling the via hole 24 and the trench 25 into the first interlayer insulating film 22 and the second interlayer insulating film 23 in a later step. . Such a material is made of tantalum nitride, titanium, titanium nitride, or a laminated film thereof in addition to the tantalum described above. The barrier film 26 may be formed by a physical vapor deposition (PVD) method or a CVD method.

  Next, after a seed layer (not shown) made of Cu is formed in a state of covering the via hole 24 in which the barrier film 26 is formed and the inner wall of the trench 25 by, for example, PVD method, the via hole 24 and A conductive film (not shown) made of Cu is formed on the barrier film 26 in a state where the trench 25 is embedded. Thereafter, the conductive film and the barrier film 26 are polished and removed by CMP until the surface of the second interlayer insulating film 23 is exposed, whereby the via hole 24 and the wiring 28 made of Cu are formed in the via hole 24 and the trench 25. Respectively. As a result, the wiring 28 is exposed on substantially the same plane as the surface of the second interlayer insulating film 23. The wiring 28 corresponds to the conductive layer of the claims.

  Here, since an oxide film is easily formed on the surface of the wiring 28 made of Cu, the substrate 21 in this state is used as the processing substrate S, the processing substrate S is carried into the processing apparatus, and the second interlayer insulating film 23 is loaded. The surface of the metal and the surface of the wiring 28 are treated using neutral radicals. At this time, the processing is performed in a state where ions are not included in the processing atmosphere. Further, electrons may be included in the processing atmosphere as long as the electron temperature is low.

  Here, an example of the processing apparatus for performing this radical processing is shown in FIG. As shown in this figure, the processing apparatus 30 includes a processing chamber 31 for processing the surface of the processing substrate S with neutral radicals, a supply pipe 32 for supplying neutral radicals to the processing chamber 31, and a processing chamber 31. And an exhaust pipe 33 for exhausting the gas.

  The processing chamber 31 is configured to be able to depressurize the internal environment from the exhaust pipe 33 by a pressure adjusting mechanism (not shown). In the processing chamber 31, for example, a substrate holding member 34 for holding the processing substrate S is disposed at the bottom thereof. The substrate holding member 34 is provided with a temperature adjustment mechanism (not shown) so that the processing substrate S held on the substrate holding member 34 can be heated.

  In addition, for example, above the processing chamber 31, one end of a supply pipe 32 for supplying neutral radicals into the processing chamber 31 is connected. The other end of the supply pipe 32 is connected to a gas cylinder (not shown) in which a neutral radical source gas is stored. The supply pipe 32 is provided with a pipe-like radical generator 35 that generates neutral radicals from the source gas.

  The radical generator 35 is provided with a diameter larger than the diameter of the supply pipe 32, for example, and its inner wall is covered with a catalyst body made of a metal such as tungsten. And the circumference | surroundings of this radical production | generation part 35 are covered with the heater (illustration omitted), and it is comprised so that the catalyst body which covers an inner wall can be heated.

  Here, when the raw material gas comes into contact with the catalyst body in a heated state, the catalyst body generates neutral radicals of the raw material due to its catalytic action. In addition, metals such as platinum, palladium, molybdenum, tantalum, and vanadium are used. Moreover, you may use a some catalyst body from these.

  As a result, the raw material gas introduced from the gas cylinder into the radical generator 35 via the supply pipe 32 is decomposed by contacting the heated catalyst body covering the inner wall of the radical generator 35. It becomes a radical and is supplied into the processing chamber 31 through the supply pipe 32.

  In this case, for example, hydrogen radical treatment is performed on the surface of the processing substrate S carried into the processing chamber 31 of the processing apparatus 30 and held on the substrate holding member 34. As an example of processing conditions in this case, the pressure of the processing chamber 31 is set to 50 Pa, and the temperature of the substrate holding member 34 is set to 200.degree. Here, the temperature of the substrate holding member 34 is set to a temperature lower than that in the case of performing the hydrogen plasma processing described in the background art.

Further, one end of the supply pipe 32 is connected to a hydrogen gas cylinder, and the flow rate of the hydrogen gas is adjusted to 150 cm ³ / min. In addition, the gas flow rate here shall show the volume flow rate in a standard state. Further, the temperature of the catalyst body made of tungsten is adjusted to about 1300 ° C. by a heater disposed around the radical generation unit 35. As a result, the hydrogen gas introduced into the radical generator 35 comes into contact with the catalyst body, whereby hydrogen radicals are generated and supplied into the processing chamber 31 from the supply pipe 32. Thus, the surface of the second interlayer insulating film 23 and the surface of the wiring 28 in the processing substrate S are processed using hydrogen radicals, whereby the surface of the wiring 28 is reduced and the oxide film is removed. .

  Here, the treatment is performed with hydrogen radicals, but neutral radicals that can modify the surface of the wiring 28 such as reduction cleaning of the surface of the wiring 28 may be used. As such a neutral radical, there is an ammonia radical or a nitrogen radical, and the treatment may be performed in a mixed state. Although only hydrogen gas is supplied here, a mixed gas with an inert gas may be supplied. Examples of such an inert gas include neon and argon. In this case, an inert gas is also introduced into the radical generator 35 to form a neutral radical, and these radicals may be included.

  In the above-described example, the example in which the radical generation unit 35 is disposed in the supply pipe 32 has been described. However, the radical generation unit 35 may be provided in the processing chamber 31. However, in this case, in order to prevent the influence of heat on the processing substrate S from heating the catalyst body at a high temperature, and in order to prevent contamination from the catalyst body made of metal from adhering to the processing substrate S, The inside of the processing chamber 31 is divided by a shielding plate or the like, and is provided in a space isolated from the substrate holding member 34.

After reducing and cleaning the surface of the wiring 28 in this way, as shown in FIG. 3, on the second interlayer insulating film 23 including the wiring 28, for example, silicon nitride (SiN) or silicon carbide (SiC) is used. A diffusion prevention film 29 is formed. The film formation here is performed by a catalytic CVD method using, for example, the processing apparatus 30 shown in FIG. For example, when the diffusion prevention film 29 made of silicon nitride (SiN) is formed, monosilane (SiH ₄ ) and ammonia (NH ₃ ) that are film formation gases are supplied to the supply pipe 32 of the processing apparatus 30. By bringing into contact with the catalyst body heated by the radical generator 35, radicals of the film forming components are generated. Then, radicals of film forming components are supplied from the supply pipe 32 into the processing chamber 31, and a diffusion preventing film is formed on the second interlayer insulating film 23 including the wiring 28 of the processing substrate S held by the substrate holding member 34. 29 is deposited. This diffusion prevention film 29 prevents Cu from diffusing from the via 27 and the wiring 28 made of Cu to the upper layer.

  Here, the diffusion prevention film 29 is formed by the catalytic CVD method, but may be formed by another film forming method such as a plasma CVD method. However, by forming the diffusion prevention film 29 by a film forming method that does not generate plasma, such as the above-described catalytic CVD method, the surface of the wiring 28 and the second interlayer insulating film 23 by ions or high temperature electrons in the plasma. It is preferable because damage to the surface is further suppressed. In the subsequent steps, a multilayer wiring structure is formed by repeating the above-described process.

  According to such a method of manufacturing a semiconductor device, since the surface of the wiring 28 and the surface of the second interlayer insulating film 23 of the processing substrate S are processed using hydrogen radicals, plasma has been conventionally performed. Compared with the case where the treatment is performed, the surfaces of the wiring 28 and the second interlayer insulating film 23 are prevented from being damaged by ions or high-temperature electrons, and the surface of the wiring 28 made of Cu is reduced and cleaned. Can do.

  As a result, an increase in dielectric constant due to the alteration of the second interlayer insulating film 23 made of a low dielectric constant film can be prevented, and an increase in inter-wiring leakage current and a decrease in inter-wiring voltage resistance can be suppressed. Further, since the damage on the surface of the second interlayer insulating film 23 is suppressed, the interlayer insulating film can be formed with a low dielectric constant film having a structure susceptible to damage. Further reduction is possible. In addition, since damage to the surface of the wiring 28 due to ions and high-temperature electrons is suppressed, electromigration resistance can be improved.

  Therefore, since the wiring reliability can be improved, a high-performance CMOS device can be realized, and the performance of computers, game machines, mobile products and the like can be significantly improved.

  In addition, according to the method for manufacturing a semiconductor device of the present embodiment, the temperature of the substrate holding member 34 can be set lower than in the case of performing the plasma processing, and therefore the first interlayer insulating film 22 and the second interlayer insulating film 22 can be set. The deterioration of the interlayer insulating film 23 due to heat can also be suppressed.

  Here, the case where the via 27 and the wiring 28 are made of Cu has been described. However, the present invention is not particularly limited, and a conductive material containing Cu or a material other than Cu, such as silver (Ag), can be used. The present invention can be applied to a conductive material in which an oxide film is easily formed on the surface.

  Further, in the present embodiment, neutral radicals are generated by bringing a neutral radical source gas into contact with the catalyst body, and the surface of the processing substrate S is processed in a state that does not include ions and electrons. The present invention is not limited to this. For example, ions or high-temperature electrons may be removed from the generated plasma, and the surface of the processing substrate S may be processed with a radical component. In this case, for example, using the fact that radicals have a longer lifetime than ions and electrons, the distance between the generated plasma and the processing substrate S may be a distance from which ions and electrons do not reach.

  Furthermore, in this embodiment, an example in which the Cu wiring structure is formed by the dual damascene method has been described. However, as described in the background art, after forming the wiring or via by the single damascene method, a diffusion prevention film is formed on the upper layer. The present invention is also applicable when surface treatment is performed before film formation. Furthermore, instead of the embedded wiring method such as the damascene method, after patterning the conductive layer on the substrate, an insulating film is formed on the substrate in a state of covering the conductive layer until the surface of the conductive layer is exposed. The present invention can also be applied as a pretreatment for forming a diffusion prevention film on the wiring structure formed by the method of removing the insulating film.

FIG. 6 is a manufacturing process cross-sectional view (No. 1) for describing the first embodiment of the semiconductor device manufacturing method of the present invention; It is a block diagram for demonstrating the processing apparatus used for the manufacturing method of the semiconductor device of this invention. FIG. 6 is a manufacturing process sectional view (No. 2) for describing the first embodiment of the manufacturing method of the semiconductor device of the invention; It is sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 21 ... Board | substrate, 22 ... 1st interlayer insulation film, 23 ... 2nd interlayer insulation film, 24 ... Via hole, 25 ... Trench, 27 ... Via, 28 ... Wiring, 29 ... Diffusion prevention film, S ... Processing board | substrate

Claims (6)

Neutral radicals were used on the surface of the insulating film and the surface of the conductive layer in a state where the insulating film and the conductive layer exposed substantially on the same surface as the surface of the insulating film were provided on the substrate. A method for manufacturing a semiconductor device, comprising performing a process. The method for manufacturing a semiconductor device according to claim 1, wherein the neutral radical is generated by bringing a source gas of the neutral radical into contact with a catalyst body. The method for manufacturing a semiconductor device according to claim 1, wherein the neutral radical is a hydrogen radical, an ammonia radical, or a nitrogen radical. The method for manufacturing a semiconductor device according to claim 1, wherein the conductive layer is formed of a material containing copper. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is made of a material having a dielectric constant lower than that of silicon oxide. The semiconductor device according to claim 5, wherein the insulating film is formed of at least one selected from the group consisting of methyl silsesquioxane, hydrogenated silsesquioxane, and silicon oxycarbide material. Method.

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