JP2005252498A - Analog/digital converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an A/D converter which is provided with a plurality of amplifier circuits and the precision of which is enhanced. <P>SOLUTION: The A/D converter includes a plurality of the amplifier circuits such as a first amplifier circuit 11, a second amplifier circuit 15, a third amplifier circuit 19, and a fourth amplifier circuit 21. The amplifier circuits meeting higher precision requirements among a plurality of the amplifier circuits are arranged remoter from circuits acting like noise sources. Further, the amplifier circuit first receiving an input analog signal is arranged remoter from the noise source circuits than the other amplifier circuits. That is, the first amplifier circuit 11 is arranged remotest from the noise source circuits. Moreover, the amplifier circuit first receiving the input analog signal is arranged remoter from the noise source circuits than the other amplifier circuits. That is, the amplifier circuits are arranged in the closer order to the noise source circuits, in the order of the fourth amplifier circuit 21, the third amplifier circuit 19, and the first amplifier circuit 11. The noise source circuits are a clock generating circuit and a digital circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an analog-digital converter. In particular, the present invention relates to a pipeline-type or cyclic-type analog-digital converter that converts an analog signal divided into a plurality of times.

In recent years, various additional functions such as an image photographing function, an image reproducing function, a moving image photographing function, and a moving image reproducing function have been installed in portable devices such as mobile phones. Along with this, there is an increasing demand for miniaturization, high accuracy, high speed, and power saving of analog-digital converters (hereinafter referred to as “AD converters”). As a form of such an AD converter, there is known an AD converter that is downsized by converting an analog signal into a plurality of times and providing a cyclic stage (see, for example, Patent Document 1).
JP-A-4-26229

  In FIG. 1 of Patent Document 1, a sample-and-hold circuit S / H1 and a subtracting circuit SUB1 having an amplification function are provided in the previous stage, and a sample-and-hold circuit S / H3, a sample-and-hold circuit are provided in the subsequent stage. A hold circuit S / H4 and a subtraction circuit SUB2 having an amplification function are provided. These circuits are assumed to be configured using operational amplifiers. When these circuits are constituted by integrated circuits, noise components may be carried on the substrate. In such a case, the operational amplifier is affected and its characteristics deteriorate. As described above, when the characteristics of the operational amplifier are deteriorated due to noise, the accuracy of the entire AD converter is lowered.

  The present invention has been made in view of such circumstances, and an object thereof is to improve the accuracy of the AD converter.

  One embodiment of the present invention is an analog-digital converter. This analog-to-digital converter divides an input analog signal into a plurality of times and converts it into a multi-bit digital signal. The analog-digital converter has a plurality of amplifier circuits. The circuit was placed away from the circuit that was the source of noise.

  A plurality of amplifier circuits of a pipeline type, a cyclic type, or a mixed type analog-digital converter that converts a plurality of times into a digital signal of multiple bits are not necessarily required to have uniform accuracy. An amplifier circuit that amplifies a portion close to the upper bits is required to have higher accuracy, and the closer to the lower bits, the lower the accuracy requirement. According to this aspect, the amplifier circuit that requires higher accuracy is arranged away from the circuit that becomes the noise source, thereby increasing the distance from the circuit that becomes the noise source, and the low-pass effect using the resistance component and the capacitance component of the substrate. Therefore, noise can be reduced. Therefore, the accuracy of the amplifier circuit is increased, and the accuracy of the entire AD converter is improved. The “amplifier circuit” includes a one-time amplification factor, that is, a sample hold circuit.

  The amplifier circuit to which the input analog signal is first input may be arranged farther from the circuit that becomes a noise source than the other amplifier circuits. According to this, the accuracy of the amplifier circuit that handles the largest signal can be improved. In addition, a plurality of amplifier circuits may be arranged away from a circuit serving as a noise source in the order in which the input analog signals are transmitted. As the transition from the upper bit conversion to the lower bit conversion is made, the accuracy requirement of the constituent element is reduced, but the amplifier circuit can also be adjusted to the accuracy corresponding thereto. Here, the noise source circuit includes a clock generation circuit that generates a clock signal or a digital circuit that performs digital signal processing. In particular, when an analog circuit and a digital circuit are mixed in an integrated circuit, the analog circuit is easily affected when noise occurs. Since a large current flows through the clock generation circuit, it becomes a large noise source. Therefore, the noise characteristic is improved as the amplifier circuit is further away from the clock generation circuit.

  A plurality of stages for converting an input analog signal into a digital value of a predetermined number of bits, and at least one of the plurality of stages includes an amplifier circuit of the plurality of amplifier circuits, and the amplifier circuit In this case, the difference between the input analog signal and the signal obtained by converting the converted digital value of its own stage into an analog value may be amplified and fed back to the input of its own stage. Thus, the accuracy of the entire AD converter is improved by arranging the arrangement of the amplifier circuit of the pipeline type AD converter composed of a plurality of stages including the cyclic stage of one-step amplification in the above-described manner. Can be made.

  There are a plurality of stages for converting an input analog signal into a digital value of a predetermined number of bits, and at least one of the plurality of stages includes two amplification circuits of the plurality of amplification circuits, and two amplifications A first amplifier circuit in the circuit amplifies an input analog signal with a predetermined amplification factor, and a second amplifier circuit in the two amplifier circuits includes an output analog signal of the first amplifier circuit and the predetermined amplifier signal. When the difference between the converted digital value of the own stage and the analog value converted to the analog value is amplified at the same amplification factor as the amplification factor, and is fed back to the input of the own stage Good. As described above, the arrangement of the amplifier circuit of the pipeline type AD converter composed of a plurality of stages including the cyclic stage of the two-step amplification is arranged in the above-described manner, thereby improving the accuracy of the entire AD converter. Can be made. The “first amplifier circuit” includes a one-time amplification factor, that is, a sample hold circuit.

  An AD converter circuit that converts an input analog signal into a digital value having a predetermined number of bits, a DA converter circuit that converts an output of the AD converter circuit into an analog signal, and a first amplifier circuit among the plurality of amplifier circuits The analog signal to be amplified is amplified at a predetermined amplification factor, and the second amplification circuit among the plurality of amplification circuits amplifies the output analog signal of the first amplification circuit at an amplification factor substantially the same as the predetermined amplification factor. The difference between the output analog signal of the DA conversion circuit and the output analog signal may be amplified with a predetermined amplification factor and output to the AD conversion circuit and the first amplification circuit. As described above, by arranging the amplification circuit of the cyclic AD converter in the above-described manner, the accuracy of the entire AD converter can be improved. The “first amplifier circuit” includes a one-time amplification factor, that is, a sample hold circuit.

  Note that any combination of the above-described constituent elements, and those in which the constituent elements and expressions of the present invention are mutually replaced between methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, it is possible to improve the accuracy of an AD converter including a plurality of amplifier circuits.

(First embodiment)
The first embodiment is an example of an AD converter that converts 4 bits at the preceding stage of the acyclic type, converts 2 bits at the subsequent stage of the cyclic type, and outputs a total of 10 bits by the third round of the subsequent stage. is there.

  FIG. 1 shows a configuration of an AD converter according to the first embodiment. In this AD converter, first, the preceding stage will be described. The input analog signal Vin is input to the first amplifier circuit 11 and the first AD converter circuit 12. The first AD conversion circuit 12 is of a flash type, and its resolution, that is, the number of conversion bits is 4 bits. The first AD conversion circuit 12 converts an input analog signal into a digital value, extracts the upper 4 bits (D9 to D6), and outputs them to an encoder (not shown) and the first DA conversion circuit 13. The first DA conversion circuit 13 converts the digital value converted by the first AD conversion circuit 12 into an analog value. The first amplifier circuit 11 samples and holds the input analog signal and outputs the sampled analog signal to the first subtraction circuit 14 at a predetermined timing. The first amplifier circuit 11 functions as a sample and hold circuit without amplifying the analog signal. The first subtraction circuit 14 subtracts the output of the first DA conversion circuit 13 from the output of the first amplification circuit 11. The second amplification circuit 15 amplifies the output of the first subtraction circuit 14 by a factor of two. The first subtraction circuit 14 and the second amplification circuit 15 may be an integrated first subtraction amplification circuit 16. According to this, the circuit can be simplified.

  Next, the latter stage will be described. The first switch SW1 and the second switch SW2 are switches that are alternately turned on and off. When the first switch SW1 is on and the second switch SW2 is off, an analog signal input from the previous stage via the first switch SW1 is input to the third amplifier circuit 19 and the second AD converter circuit 17. The second AD conversion circuit 17 is also of a flash type, and its resolution, that is, the number of bits including one redundant bit is 3 bits. Further, the reference voltage supplied to the voltage comparison element constituting the second AD conversion circuit 17 is set to ½ of the reference voltage supplied to the voltage comparison element constituting the first AD conversion circuit 12. . Since the second AD conversion circuit 17 performs 2-bit conversion, the analog signal converted by the first AD conversion circuit 12 must be amplified by a factor of 4 (square of 2). However, since the second amplification circuit 15 has a double amplification factor, adjustment is made by reducing the reference voltage to ½. The second AD conversion circuit 17 converts the input analog signal into a digital value, extracts the 5th and 6th bits (D5 to D4) from the higher order, and outputs them to an encoder (not shown) and the second DA conversion circuit 18. The second DA conversion circuit 18 converts the digital value converted by the second AD conversion circuit 17 into an analog value.

  The third amplifier circuit 19 amplifies the input analog signal by a factor of 2 and outputs it to the second subtraction circuit 20. The second subtraction circuit 20 subtracts the output of the second DA conversion circuit 18 from the output of the third amplification circuit 19 and outputs the result to the fourth amplification circuit 21. Here, the output of the second DA converter circuit 18 is substantially doubled. This can be realized by setting the ratio of the reference voltage range of the second AD conversion circuit 17 and the reference voltage range of the second DA conversion circuit 18 to 1: 2. For example, if the input of the second AD converter circuit 17 is single and the output of the second DA converter circuit 18 is configured differentially, the ratio can be set to 1: 2.

  The fourth amplification circuit 21 amplifies the output of the second subtraction circuit 20 by a factor of two. At this stage, the first switch SW1 is turned off and the second switch SW2 is turned on. The analog signal amplified in the fourth amplifier circuit 21 is fed back to the third amplifier circuit 19 and the second AD converter circuit 17 via the second switch SW2. The second subtracting circuit 20 and the fourth amplifying circuit 21 may use an integrated second subtracting amplifying circuit 22. Thereafter, the above processing is repeated, and the second AD conversion circuit 17 extracts 7, 8 bits (D3 to D2) from the higher order and 9,10 bits (D1 to D0) from the upper order. In this way, a 10-bit digital value is obtained. The upper 5 to 10 bits are obtained by a cyclic subsequent stage.

  FIG. 2 is a time chart showing an operation process of the AD converter according to the first embodiment. Hereinafter, description will be made in order from the top of the figure. The three signal waveforms indicate the first clock signal CLK1, the second clock signal CLK2, and the switch signal CLKSW. The first clock signal CLK1 controls the operations of the first amplifier circuit 11, the second amplifier circuit 15, the first AD converter circuit 12, and the first DA converter circuit 13. The second clock signal CLK2 controls the operations of the third amplifier circuit 19, the fourth amplifier circuit 21, the second AD converter circuit 17, and the second DA converter circuit 18. The switch signal CLKSW performs on / off control of the first switch SW1 and the second switch SW2.

  The frequency of the second clock signal CLK2 is three times the frequency of the first clock signal CLK1. The second clock signal CLK2 may be generated by multiplying the first clock signal CLK1 using a PLL or the like based on the first clock signal CLK1. After the rise of the second clock signal CLK2 is synchronized with the rise of the first clock signal CLK1, the second fall of the second clock signal CLK2 is synchronized with the next fall of the first clock signal CLK1, and the next second time. The rising edge is synchronized with the next rising edge of the first clock signal CLK1. Since the frequency of the second clock signal CLK2 is three times the frequency of the first clock signal CLK1, the conversion processing speed by the subsequent stage is also three times the conversion processing speed by the previous stage. Since the accuracy of analog processing such as subtraction and amplification in conversion processing with higher bits greatly affects the overall conversion accuracy, higher accuracy is required for the previous stage responsible for this. Therefore, in the configuration of the present embodiment, the conversion processing speed of the subsequent stage, which does not require processing accuracy as much as the previous stage, can be increased from the processing speed of the previous stage.

  The first amplifier circuit 11 and the first AD converter circuit 12 sample the input analog signal Vin at the rising edge of the first clock signal CLK1. The first amplifier circuit 11 holds the sampled analog signal when the first clock signal CLK1 is Hi, and performs an auto-zero operation when the first clock signal CLK1 is Lo. The second amplifier circuit 15 samples the input analog signal at the falling edge of the first clock signal CLK1. An analog signal sampled when the first clock signal CLK1 is Lo is amplified and output to the third amplifier circuit 19 and the second AD converter circuit 17, and an auto-zero operation is performed when the first clock signal CLK1 is Hi. The first AD conversion circuit 12 performs a conversion operation when the first clock signal CLK1 is Hi and outputs digital values D9 to D6, and performs an auto-zero operation when the first clock signal CLK1 is Lo. The first DA conversion circuit 13 holds the conversion confirmation data when the first clock signal CLK1 is Lo, and becomes indefinite when the first clock signal CLK1 is Hi.

  The first switch SW1 is turned on when the switch signal CLKSW is Hi, and is turned off when the switch signal CLKSW is Lo. The second switch SW2 is turned on when the switch signal CLKSW is Lo, and is turned off when the switch signal CLKSW is Hi.

  The third amplifier circuit 19 and the second AD converter circuit 17 sample the input analog signal at the rising edge of the second clock signal CLK2. The third amplifier circuit 19 amplifies the sampled analog signal when the second clock signal CLK2 is Hi, and performs an auto-zero operation when the second clock signal CLK2 is Lo. During the period in which the second AD conversion circuit 17 converts the least significant bits D1 to D0, it is not amplified. The fourth amplifier circuit 21 samples the input analog signal at the falling edge of the second clock signal CLK2. The sampled analog signal is amplified when the second clock signal CLK2 is Lo, and the auto-zero operation is performed when the second clock signal CLK2 is Hi. No amplification is performed in the next half clock period after the second AD conversion circuit 17 converts D1 to D0.

  The second AD conversion circuit 17 performs a conversion operation when the second clock signal CLK2 is Hi, outputs 2 bits excluding redundant bits, and performs an auto-zero operation when the second clock signal CLK2 is Lo. The second DA conversion circuit 18 holds the conversion confirmation data when the second clock signal CLK2 is Lo, and becomes indefinite when the second clock signal CLK2 is Hi. When the output of the second AD conversion circuit 17 is D1 to D0, the conversion operation is not performed.

  In the auto-zero period of the first amplifier circuit 11, the second amplifier circuit 15, the third amplifier circuit 19, the fourth amplifier circuit 21, the first AD converter circuit 12, and the second AD converter circuit 17, an input signal is being sampled. is there. As shown in the figure, while the second AD conversion circuit 17 performs conversion processing on D5 to D4 and D3 to D2, the first AD conversion circuit 12 simultaneously converts the next input analog signal Vin. By such pipeline processing, the AD converter as a whole can output a 10-bit digital value once per cycle with reference to the first clock signal CLK1.

  Next, detailed configurations of the first amplifier circuit 11, the second amplifier circuit 15, the third amplifier circuit 19, and the fourth amplifier circuit 21 will be described. FIG. 3 is a diagram showing a case where these amplifier circuits are configured by single-ended switched capacitor operational amplifiers. FIG. 4 is a time chart for explaining the operation of the switched capacitor operational amplifier. In FIG. 3, the input capacitor C1 is connected to the inverting input terminal of the operational amplifier 100, the input voltage Vin1 is input through the Vin1 switch SW12, and the input voltage Vin2 is input through the Vin2 switch SW13. The The input voltage Vin1 corresponds to an input analog signal Vin or an analog signal input from the previous stage, and the input voltage Vin2 corresponds to an output analog signal or a reference voltage of the first DA conversion circuit 13 and the second DA conversion circuit 18. The non-inverting input terminal of the operational amplifier 100 is connected to the auto-zero potential. The output terminal and the inverting input terminal of the operational amplifier 100 are connected via a feedback capacitor C2. Further, an auto-zero switch SW11 is connected to the outside thereof, and the output terminal and the inverting input terminal of the operational amplifier 100 can be short-circuited.

  Next, the operation of the single-ended switched capacitor operational amplifier shown in FIG. 3 will be described with reference to FIG. First, the auto-zero switch SW11 is turned on in order to set the auto-zero potential Vag. In this state, both the input side node N1 and the output side node N2 are at the auto-zero potential Vag. In order to sample the input voltage Vin1, the switch SW12 for Vin1 is turned on and the switch SW13 for Vin2 is turned off. At this time, the charge QA of the input side node N1 is expressed by the following equation (A1).

  QA = C2 (Vin1-Vag) (A1)

  Next, the auto-zero switch SW11 is turned off for virtual grounding and amplification. Thereafter, in order to subtract the input voltage Vin2, the Vin1 switch SW12 is turned off and the Vin2 switch SW13 is turned on. At this time, the charge QB of the input side node N1 is represented by the following equation (A2).

  QB = C2 (Vin2-Vag) + C1 (Vout-Vag) (A2)

  Since the input node N1 does not have a path through which charges escape, QA = QB is obtained from the law of conservation of charge, and the following expression (A3) is established.

  Vout = C2 / C1 (Vin1-Vin2) + (C1Vag) (A3)

  Therefore, in the single-ended switched capacitor operational amplifier, if the auto-zero potential Vag is ideally the ground potential, the difference between the input voltage Vin1 and the input voltage Vin2 is determined by the capacitance ratio between the input capacitor C1 and the feedback capacitor C2. Can be amplified. Of course, even if the auto-zero potential Vag is not the ground potential, an approximate value can be obtained.

  Next, an example in which the operational amplifier 100 is configured by a CMOS (Complementary Metal-Oxide Semiconductor) process will be described. FIG. 5 is a diagram illustrating an equivalent circuit of a differential amplification portion of the operational amplifier 100 in a single end. The operational amplifier 100 includes P-channel MOS (Metal-Oxide Semiconductor) field effect transistors (hereinafter referred to as PMOS transistors) M3 and M4, N-channel MOS field effect transistors (hereinafter referred to as NMOS transistors) M1 and M2, A current source 101 is provided.

  In the pair of PMOS transistors M3 and M4, the power supply voltage Vdd is applied to the drain and the bias voltage is applied to the gate. The pair of PMOS transistors M3 and M4 form a current mirror circuit, and an equal drain current flows through both sources. The pair of NMOS transistors M1 and M2 has drains connected to the pair of PMOS transistors M3 and M4, respectively, and sources connected to the constant current source 101. Differential inputs IN1 and IN2 are applied to the gate. An output OUT is obtained from a connection point between the PMOS transistor M4 and the NMOS transistor M2. The gain is determined by the mutual conductance and output resistance of the NMOS transistors M1 and M2 and the PMOS transistors M3 and M4. An NMOS transistor can be used for the constant current source 101. A bias voltage is applied to the gate of the NMOS transistor to operate in a saturation region.

  FIG. 6 is a diagram showing a case where a fully-differential switched capacitor operational amplifier is used. The fully differential method is more resistant to noise and has a larger output amplitude than the single-ended method. In FIG. 6, an input capacitor C1a is connected to the non-inverting input terminal of the operational amplifier 110. An input voltage Vin1 (+) is input through the Vin1 switch SW12a, and an input voltage is input through the Vin2 switch SW13a. Vin2 (+) is input. An input capacitor C1b is connected to the inverting input terminal of the operational amplifier 110, and the input voltage Vin1 (−) is input through the Vin1 switch SW12b, and the input voltage Vin2 (−) is input through the Vin2 switch SW13b. Entered. The inverting output terminal and the non-inverting input terminal of the operational amplifier 110 are connected via a feedback capacitor C2a. The non-inverting output terminal and the inverting input terminal of the operational amplifier 110 are connected via a feedback capacitor C2b. The auto-zero switches SW11a to SW11d are connected to the input-side nodes N1a and N1b and the output-side nodes N2a and N2b. The auto-zero switches SW11a to SW11d operate at the same timing, and when turned on, the potentials of the input-side nodes N1a and N1b and the output-side nodes N2a and N2b become the auto-zero potential Vag.

  Next, the operation of the fully differential switched capacitor operational amplifier of FIG. 6 will be described. The operation timing is the same as the timing shown in FIG. First, the auto zero switches SW11a to SW11d are turned on in order to set the auto zero potential Vag. In this state, the input side nodes N1a, b and the output side nodes N2a, b are both at auto-zero potential Vag. In order to sample the input voltage Vin1, the Vin1 switches SW12a and SW12b are turned on, and the Vin2 switches SW13a and SWb are turned off. At this time, the charge QAA of the input side node N1a is represented by the following equation (A4), and the charge QAB of the input side node N1b is represented by the following equation (A5).

QAA = C2 {Vin1 (+)-Vag} (A4)
QAB = C2 {Vin1 (−) − Vag} (A5)

  Next, the auto-zero switches SW11a to SW11d are turned off to amplify the virtual ground state. Thereafter, in order to subtract the input voltage Vin2, the Vin1 switches SW12a, b are turned off and the Vin2 switches SW13a, b are turned on. At this time, the charge QBA of the input side node N1a is represented by the following equation (A6), and the charge QBB of the input side node N1b is represented by the following equation (A7).

QBA = C2 {Vin2 (+) − Vag} + C1 {Vout (+) − Vag} (A6)
QBB = C2 {Vin2 (−) − Vag} + C1 {Vout (−) − Vag} (A7)

  Since the input side node N1 does not have a path through which charges escape, QAA = QBA and QAB = QBB are obtained from the charge conservation law, and the following expressions (A8) and (A9) are satisfied.

Vout (+) = C2 / C1 {Vin1 (+) − Vin2 (+)} + (C1Vag) (A8)
Vout (−) = C2 / C1 {Vin1 (−) − Vin2 (−)} + (C1Vag) (A9)

  The differential voltage Vout between the two output nodes N2a and N2b is expressed by the following equation (A10).

  Vout = Vout (+) − Vout (−) = C2 / C1 [{Vin1 (+) − Vin1 (−)} − {Vin2 (+) − Vin2 (−)}] (A10)

  Therefore, the fully differential switched capacitor operational amplifier can amplify the difference between the input voltage Vin1 and the input voltage Vin2 by the capacitance ratio of the input capacitor C1 and the feedback capacitor C2.

  FIG. 7 is a diagram showing an equivalent circuit of a differential amplification portion of the operational amplifier 110 in the fully differential system. This is basically the same as the description of FIG. The differential outputs OUT1 and 2 are obtained from the connection point between the PMOS transistor M3 and the NMOS transistor M1 and the connection point between the PMOS transistor M4 and the NMOS transistor M2. Also, a through current flows from the power supply side to the ground side.

  Next, the arrangement pattern of the first amplifier circuit 11, the second amplifier circuit 15, the third amplifier circuit 19, and the fourth amplifier circuit 21 will be described. In the AD converter shown in FIG. 1, the accuracy required for the first amplifier circuit 11, the second amplifier circuit 15, the third amplifier circuit 19, and the fourth amplifier circuit 21 is generally a path through which an analog signal is transmitted. In the order. That is, the first amplifier circuit 11 → the second amplifier circuit 15 → the third amplifier circuit 19 → the fourth amplifier circuit 21. This is because higher accuracy is required when converting bits closer to the higher order bits.

  FIG. 8 is a diagram conceptually showing a first arrangement pattern of a plurality of amplifier circuits in the first embodiment. The clock generation circuit 2 and the digital circuit 3 serve as noise sources. The clock generation circuit 2 generates a clock signal and supplies operation timing to at least the first amplification circuit 11, the second amplification circuit 15, the third amplification circuit 19, and the fourth amplification circuit 21. As shown in FIG. 4, the timing of auto-zero operation and amplification operation is supplied. Since the clock generation circuit 2 drives a load due to clock wiring and gate capacitance, the clock generation circuit 2 includes many logic elements such as an inverter using a large-sized transistor. When the inverter is configured by a push-pull circuit in which two transistors are connected in series, a large through current may occur at the transition from the Lo level to the Hi level and from the Hi level to the Lo low level. When this through current is injected into the substrate, it becomes a large noise component. Even if a trap is provided in the substrate, the noise component may spread beyond the trap. These noise components fluctuate the substrate potential of elements such as the MOS transistors M1 to M4 constituting the operational amplifiers 100 and 110 shown in FIG. 5 and FIG. 7, so that the first amplifier circuit 11 and the second amplifier This causes a decrease in accuracy and speed of the circuit 15, the third amplifier circuit 19, and the fourth amplifier circuit 21.

  The digital circuit 3 is a circuit that performs various types of digital signal processing. An encoder that converts a digital value converted by the first AD conversion circuit 12 and the second AD conversion circuit 17 into a binary code, and an output timing of each stage are matched. Latch circuit or the like. Noise components are also generated from the digital circuit 3. However, since it is not driven by a current as large as that of the clock generation circuit 2, the level of the noise component is not as great as that of the clock generation circuit 2.

  In FIG. 8, the fourth amplifying circuit 21 → the third amplifying circuit 19 → the second amplifying circuit 15 → the first amplifying circuit 11 are arranged in the order closest to the clock generating circuit 2. Since the first amplifier circuit 11 requires the highest accuracy, the first amplifier circuit 11 is arranged at a position farthest from the clock generation circuit 2. The noise component transmitted through the substrate decreases as the distance from the noise source increases due to the effect of the low-pass filter formed by the resistance component R of the substrate and the capacitance component C such as parasitic capacitance and line-to-line capacitance. Go. Therefore, the first amplifier circuit 11 is least affected by the noise component. Further, the arrangement order described above is the reverse order of the path through which the analog signal is transmitted, and the influence of the noise component in the order of the first amplifier circuit 11 → the second amplifier circuit 15 → the third amplifier circuit 19 → the fourth amplifier circuit 21. It becomes difficult to receive.

  FIG. 9 is a diagram conceptually showing an arrangement pattern of a plurality of amplifier circuits in the comparative example. In FIG. 9, the first amplifier circuit 11, the second amplifier circuit 15, the third amplifier circuit 19, and the fourth amplifier circuit 21 are arranged at locations where the clock generation circuit 2 receives clock control with substantially the same clock wiring length. . This arrangement reduces the phase difference between clocks supplied to the first amplifier circuit 11, the second amplifier circuit 15, the third amplifier circuit 19, and the fourth amplifier circuit 21. The first amplifier circuit 11, the second amplifier circuit 15, the third amplifier circuit 19, and the fourth amplifier circuit 21 are equally affected by the noise component from the clock generation circuit 2. If the bias current shown in FIGS. 5 and 7 decreases due to the influence of the noise component, the operation speed of the operational amplifiers 100 and 110 decreases. Further, if the power supply voltage and the ground voltage are different between the bias unit that generates the bias current and the differential amplifier unit, the DC gain and the output voltage range may be deteriorated. In the comparative example, such a phenomenon occurs substantially equally in the first amplifier circuit 11, the second amplifier circuit 15, the third amplifier circuit 19, and the fourth amplifier circuit 21.

  On the other hand, in the arrangement pattern shown in FIG. 8, such a phenomenon hardly occurs in the first amplifier circuit 11, and the degree of such a phenomenon increases as the distance from the fourth amplifier circuit 21 becomes closer. However, in the AD converter shown in FIG. 1, accuracy is required in the order of the first amplifier circuit 11 → the second amplifier circuit 15 → the third amplifier circuit 19 → the fourth amplifier circuit 21. The first arrangement pattern shown in FIG. 8 with higher accuracy can improve the accuracy and speed of the entire AD converter than the arrangement pattern in the comparative example.

  FIG. 10 is a diagram conceptually showing a second arrangement pattern of a plurality of amplifier circuits in the first embodiment. The accuracy required for the first amplifier circuit 11, the second amplifier circuit 15, the third amplifier circuit 19, and the fourth amplifier circuit 21 is not limited to the order of the paths through which analog signals are transmitted. For example, when the amplification factor of the third amplification circuit 19 is increased by changing the number of conversion bits and the amplification factor of the second amplification circuit 15 is decreased, the second amplification is performed in order to increase the speed of the entire AD converter. It is better to supply a power supply voltage with higher accuracy to the third amplifier circuit 19 than to the circuit 15. In such a case, as shown in FIG. 10, the fourth amplifying circuit 21 → the second amplifying circuit 15 → the third amplifying circuit 19 → the first amplifying circuit 11 are arranged in order from the clock generating circuit 2. In this way, the analog signal transmission path is not limited to the order, and the clock generation circuit 2 can be arranged in the reverse order of the required accuracy.

  FIG. 11 is a diagram conceptually showing a third arrangement pattern of a plurality of amplifier circuits in the first embodiment. In FIG. 11, the first amplifying circuit 11 requiring the highest accuracy is arranged at a place farthest from the clock generation circuit 2 and the digital circuit 3. The second amplifier circuit 15 is disposed at a location away from the digital circuit 3 and is disposed at a location closest to the clock generation circuit 2. The third amplifier circuit 19 is disposed at a middle position with respect to the clock generation circuit 2 and the digital circuit 3. The fourth amplifying circuit 21, which may have the lowest accuracy, is disposed at a location closest to the clock generation circuit 2 and the digital circuit 3. With such a third arrangement pattern, the accuracy of the first amplifier circuit 11 becomes the best, and the accuracy and speed of the entire AD converter can be improved.

  FIG. 12 is a diagram conceptually showing a fourth arrangement pattern of a plurality of amplifier circuits in the first embodiment. In FIG. 12, the first amplifying circuit 11 requiring the highest accuracy is arranged at a place farthest from the clock generation circuit 2 and the digital circuit 3. The second amplifier circuit 15 is disposed at a position farthest from the clock generation circuit 2 and is disposed at a position closest to the digital circuit 3. The third amplifying circuit 19 is disposed at a position farthest from the digital circuit 3 and is disposed at a position closest to the clock generation circuit 2. The fourth amplifying circuit 21, which may have the lowest accuracy, is disposed at a location closest to the clock generation circuit 2 and the digital circuit 3. With such a fourth arrangement pattern, the accuracy of the first amplifier circuit 11 becomes the best, and the accuracy and speed of the entire AD converter can be improved. Further, as in the third arrangement pattern and the fourth arrangement pattern, the arrangement patterns of the first amplifier circuit 11, the second amplifier circuit 15, the third amplifier circuit 19, and the fourth amplifier circuit 21 depend on the accuracy required for each. The clock generation circuit 2 and the digital circuit 3 can be set flexibly.

  FIG. 13 is a diagram conceptually showing a fifth arrangement pattern of a plurality of amplifier circuits in the first embodiment. When the AD converter is configured by an integrated circuit, an external power source is connected to the power input terminal 1. In the integrated circuit, each component is supplied with power from the power input terminal 1 via the power wiring. The power supply wiring has a resistance component, and the power supply voltage drops as it becomes longer.

  In FIG. 13, the fourth amplifying circuit 21 → the third amplifying circuit 19 → the second amplifying circuit 15 → the first amplifying circuit 11 are arranged in the order closer to the clock generating circuit 2. On the contrary, the first amplifying circuit 11 → the second amplifying circuit 15 → the third amplifying circuit 19 → the fourth amplifying circuit 21 are arranged in the order closer to the power input terminal 1. Since the first amplifier circuit 11 requires the highest accuracy, the first amplifier circuit 11 is disposed at a position farthest from the clock generation circuit 2. At the same time, since the first amplifying circuit 11 is disposed at a position closest to the power supply input terminal 1, the power supply wiring resistance component becomes the smallest, that is, the supply of the power supply voltage with the smallest voltage drop can be received. . Further, the order of arrangement of the fourth amplifier circuit 21 → the third amplifier circuit 19 → the second amplifier circuit 15 → the first amplifier circuit 11 is not limited to the reverse order of the analog signal transmission path, and the order in which accuracy is not required. Any other order may be used.

  FIG. 14 is a diagram conceptually showing a sixth arrangement pattern of a plurality of amplifier circuits in the first embodiment. In FIG. 14, the first amplifying circuit 11 requiring the highest accuracy is disposed at a position farthest from the clock generation circuit 2 and the digital circuit 3, and is disposed at a position closest to the power input terminal 1. . The second amplifier circuit 15 is disposed at a location distant from the power input terminal 1 and the digital circuit 3, and is disposed at a location closest to the clock generation circuit 2. The third amplifier circuit 19 is arranged at a middle position with respect to the power input terminal 1, the clock generation circuit 2, and the digital circuit 3. The fourth amplifying circuit 21, which may have the lowest accuracy, is disposed at a position closest to the clock generation circuit 2 and the digital circuit 3, and is disposed at a position farthest from the power input terminal 1. With such a sixth arrangement pattern, the accuracy of the first amplifier circuit 11 becomes the best, and the accuracy and speed of the entire AD converter can be improved.

  FIG. 15 is a diagram conceptually showing a seventh arrangement pattern of a plurality of amplifier circuits in the first embodiment. In FIG. 15, the first amplifying circuit 11 requiring the highest accuracy is disposed at a position farthest from the clock generation circuit 2 and the digital circuit 3, and is disposed at a position closest to the power input terminal 1. . The second amplifying circuit 15 is disposed at a position farthest from the clock generation circuit 2, and is disposed at a position closest to the power input terminal 1 and the digital circuit 3. The third amplifying circuit 19 is disposed at a position farthest from the digital circuit 3 and the power supply input terminal 1, and is disposed at a position closest to the clock generation circuit 2. The fourth amplifying circuit 21, which may have the lowest accuracy, is disposed at a position closest to the clock generation circuit 2 and the digital circuit 3, and is disposed at a position farthest from the power input terminal 1. With such a seventh arrangement pattern, the accuracy of the first amplifier circuit 11 becomes the best, and the accuracy and speed of the entire AD converter can be improved. Further, as in the sixth arrangement pattern and the seventh arrangement pattern, the arrangement patterns of the first amplifier circuit 11, the second amplifier circuit 15, the third amplifier circuit 19, and the fourth amplifier circuit 21 depend on the accuracy required for each. The power input terminal 1, the clock generation circuit 2, and the digital circuit 3 can be set flexibly.

(Second Embodiment)
The second embodiment is a cyclic AD converter, which is an example in which 4 bits are converted first, then 3 rounds are converted and converted every 2 bits, and a total of 10 bits are output.

  FIG. 16 shows a configuration of an AD converter according to the second embodiment. The first switch SW3 and the second switch SW4 are switches that are alternately turned on and off. In the initial state, the first switch SW3 is on and the second switch SW4 is off. The input analog signal Vin is input to the first amplifier circuit 31 and the AD conversion circuit 32 via the first switch SW3. The AD conversion circuit 32 is of a flash type, and its maximum resolution, that is, the number of conversion bits is 4 bits. The AD conversion circuit 32 converts the analog signal input via the first switch SW3 into a digital value, extracts the upper 4 bits (D9 to D6), and outputs them to an encoder and DA conversion circuit 33 (not shown). The DA conversion circuit 33 converts the digital value converted by the AD conversion circuit 32 into an analog value. The first amplifier circuit 31 amplifies the input analog signal by a factor of 2 and outputs it to the subtraction circuit 34. The subtraction circuit 34 subtracts the output of the DA conversion circuit 33 from the output of the first amplification circuit 31. Here, the output of the DA conversion circuit 33 is substantially doubled. This can be realized by setting the ratio of the reference voltage range of the AD conversion circuit 32 and the reference voltage range of the DA conversion circuit 33 to 1: 2. The second amplification circuit 35 amplifies the output of the subtraction circuit 34 by a factor of two. The subtracting circuit 34 and the second amplifying circuit 35 may be an integrated subtracting amplifying circuit 36. According to this, the circuit can be simplified.

  At this stage, the first switch SW3 is turned off and the second switch SW4 is turned on. The output analog signal of the second amplifier circuit 35 is fed back to the first amplifier circuit 31 and the AD conversion circuit 32 via the second switch SW4. The AD conversion circuit 32 converts the analog signal input via the second switch SW4 into 2 bits, excluding the redundant 1 bit, and extracts the 5th and 6th bits (D5 to D4) from the higher order. The data is output to the conversion circuit 33. The operations of the DA conversion circuit 33, the first amplification circuit 31, the subtraction circuit 34, and the second amplification circuit 35 are the same as those in the first conversion. Since the AD conversion circuit 32 performs 2-bit conversion from the second time onward, the first amplification circuit 31 and the second amplification circuit 35 amplify substantially 4 (2 squared) times in total. Thereafter, the above-described processing is repeated, and the AD conversion circuit 32 extracts 7, 8 bits (D3 to D2) from the upper and 9,10 bits (D1 to D0) from the upper. In this way, a 10-bit digital value is obtained.

  The detailed configuration of the first amplifier circuit 31 and the second amplifier circuit 35 is the same as that described in the first embodiment. Next, the arrangement pattern of the first amplifier circuit 31 and the second amplifier circuit 35 will be described. In the AD converter shown in FIG. 16, the accuracy required for the first amplifier circuit 31 and the second amplifier circuit 35 is generally in the order of the path through which the analog signal is transmitted. That is, the order is the first amplifier circuit 31 → the second amplifier circuit 35. This is because the first amplifier circuit 31 handles a wider voltage range than the second amplifier circuit 35, and thus requires higher accuracy.

  FIG. 17 is a diagram conceptually showing a first arrangement pattern of two amplifier circuits in the second embodiment. In FIG. 16, the second amplifier circuit 35 → the first amplifier circuit 31 are arranged in the order of proximity to the clock generation circuit 2. Since the first amplifier circuit 31 requires higher accuracy than the second amplifier circuit 35, the first amplifier circuit 31 is disposed away from the second amplifier circuit 35 with respect to the clock generation circuit 2. Therefore, the first amplifier circuit 31 is less susceptible to the noise component transmitted through the substrate than the second amplifier circuit 35, and the accuracy and speed of the entire AD converter can be improved.

  FIG. 18 is a diagram conceptually showing a second arrangement pattern of two amplifier circuits in the second embodiment. In FIG. 18, the first amplifier circuit 31 that requires higher accuracy than the second amplifier circuit 35 is disposed near the power input terminal 1 and disposed away from the clock generation circuit 2. . The second amplifier circuit 35 is disposed at a location near the clock generation circuit 2 and is disposed at a location away from the power input terminal 1. The noise component transmitted through the substrate decreases with increasing distance from the noise source due to the effect of the low-pass filter formed by the resistance component of the substrate and the capacitance component such as parasitic capacitance and line capacitance. Further, the power supply voltage decreases as the distance from the power supply input terminal 1 increases. Therefore, the first amplifier circuit 31 arranged in this way is not affected by the noise component from the second amplifier circuit 35, and the accuracy of the power supply voltage is higher than that of the second amplifier circuit 35. Therefore, the first amplifier circuit 31 and the second amplifier circuit 35 are compared with a pattern arranged at substantially equal distances with respect to the power input terminal 1 and the clock generation circuit 2 to improve the accuracy and speed of the entire AD converter. Can do.

  In FIG. 18, the first amplifier circuit 31 and the second amplifier circuit 35 are arranged at substantially the same distance from the digital circuit 3, but the first amplifier circuit 31 is the second one with respect to the digital circuit 3. If the first amplifier circuit 31 is disposed away from the amplifier circuit 35, the accuracy of the first amplifier circuit 31 can be further improved.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications can be made to combinations of each component and each processing process. Those skilled in the art will appreciate that such modifications are also within the scope of the present invention.

  The number of conversion bits of the AD conversion circuit and its distribution, and the amplification factor parameters of the amplifier circuit described in each embodiment are merely examples, and other numerical values may be adopted for these parameters in the modification. Further, the number of stages is not limited to one or two stages, and can be applied to three or more stages. One or more of these stages may have a cyclic configuration.

  In the first embodiment, the first amplifier circuit 11 may be removed. The sample timing of the input analog signal Vin of the second amplifier circuit 15 or the first subtracting amplifier circuit 16 is adjusted, or the input analog signal Vin and the reference voltage are input to the voltage comparison element constituting the first AD converter circuit 12. If the timing is switched, the operation of the entire AD converter is guaranteed even if the first amplifier circuit 11 is removed. According to this, the circuit area can be reduced. In this case, the order in which accuracy is generally required is the second amplifier circuit 15 → the third amplifier circuit 19 → the fourth amplifier circuit 21. Similarly, the third amplifier circuit 19 may be removed. In this case, the order in which accuracy is generally required is the first amplifier circuit 11 → the second amplifier circuit 15 → the fourth amplifier circuit 21.

  In each embodiment, the example in which each amplifier circuit is configured with a switched capacitor operational amplifier has been described in order to improve the timing of the sample of the input signal. In this respect, the amplifier circuit is not limited to this, and a general amplifier circuit mainly using resistors may be used.

  Furthermore, in each embodiment, the example which comprises an amplifier circuit by a CMOS process was demonstrated. In this respect, a TTL (Transistor Transistor Logic) process may be used.

It is a figure which shows the structure of the AD converter in 1st Embodiment. It is a time chart which shows the operation | movement process of the AD converter in 1st Embodiment. It is a figure which shows the structure of a single end switched capacitor operational amplifier. It is a time chart for demonstrating operation | movement of a switched capacitor operational amplifier. It is a figure which shows the equivalent circuit of the differential amplification part of the operational amplifier in a single end. It is a figure which shows the structure of the switched capacitor operational amplifier of a fully differential system. It is a figure which shows the equivalent circuit of the differential amplification part of the operational amplifier in a fully differential system. It is a figure which shows notionally the 1st arrangement pattern of the amplifier circuit in 1st Embodiment. It is a figure which shows notionally the arrangement pattern of the amplifier circuit in a comparative example. It is a figure which shows notionally the 2nd arrangement pattern of the amplifier circuit in 1st Embodiment. It is a figure which shows notionally the 3rd arrangement pattern of the amplifier circuit in 1st Embodiment. It is a figure which shows notionally the 4th arrangement pattern of the amplifier circuit in 1st Embodiment. It is a figure which shows notionally the 5th arrangement pattern of the amplifier circuit in 1st Embodiment. It is a figure which shows notionally the 6th arrangement pattern of the amplifier circuit in 1st Embodiment. It is a figure which shows notionally the 7th arrangement pattern of the amplifier circuit in 1st Embodiment. It is a figure which shows the structure of the AD converter in 2nd Embodiment. It is a figure which shows notionally the 1st arrangement pattern of the amplifier circuit in 2nd Embodiment. It is a figure which shows notionally the 2nd arrangement pattern of the amplifier circuit in 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Power input terminal 1, 2 Clock generation circuit, 3 Digital circuit, 11, 31 1st amplifier circuit, 12 1st AD converter circuit, 13 1st DA converter circuit, 14 1st subtraction circuit, 15, 35 2nd amplifier circuit, 16 1st subtraction amplification circuit, 17 2nd AD conversion circuit, 18 2nd DA conversion circuit, 19 3rd amplification circuit, 20 2nd subtraction circuit, 21 4th amplification circuit, 22 2nd subtraction amplification circuit, 32 AD conversion circuit, 33 DA Conversion circuit, 34 subtraction circuit, 100, 110 operational amplifier, 101 constant current source, SW1-SW4, SW11-13 switch, C capacitance component, C1, C2 capacitor, M1, M2 NMOS transistor, M3, M4 PMOS transistor, R resistance component .

Claims (7)

An analog-to-digital converter that divides an input analog signal into multiple times and converts it into a multi-bit digital signal,
An analog-to-digital converter, comprising a plurality of amplifier circuits, wherein among the plurality of amplifier circuits, an amplifier circuit requiring accuracy is arranged away from a circuit that becomes a noise source.   2. The analog-to-digital converter according to claim 1, wherein an amplifier circuit to which the input analog signal is first input is arranged farther from the circuit serving as the noise source than other amplifier circuits.   3. The analog-digital converter according to claim 1, wherein the plurality of amplifier circuits are arranged apart from the circuit serving as the noise source in the order in which the input analog signals are transmitted.   4. The analog-digital converter according to claim 1, wherein the noise source circuit is a clock generation circuit that generates a clock signal or a digital circuit that performs digital signal processing. Having a plurality of stages for converting an input analog signal into a digital value of a predetermined number of bits;
One or more of the plurality of stages includes one amplifier circuit of the plurality of amplifier circuits;
The one amplifier circuit amplifies a difference between the inputted analog signal and a signal obtained by converting a converted digital value of its own stage into an analog value, and feeds back to the input of its own stage. Item 5. The analog-digital converter according to any one of Items 1 to 4. Having a plurality of stages for converting an input analog signal into a digital value of a predetermined number of bits;
One or more stages of the plurality of stages includes two amplifier circuits of the plurality of amplifier circuits;
A first amplifier circuit of the two amplifier circuits amplifies the input analog signal with a predetermined amplification factor,
The second amplifier circuit of the two amplifier circuits is an output analog signal of the first amplifier circuit and a converted digital value of its own stage amplified at an amplification factor substantially the same as the predetermined amplification factor. 5. The analog-digital converter according to claim 1, wherein a difference between the signal and the signal converted into an analog value is amplified at a predetermined amplification factor and fed back to an input of its own stage. An AD conversion circuit for converting an input analog signal into a digital value having a predetermined number of bits;
A DA conversion circuit for converting the output of the AD conversion circuit into an analog signal;
A first amplifier circuit of the plurality of amplifier circuits amplifies the input analog signal with a predetermined amplification factor,
The second amplifier circuit of the plurality of amplifier circuits includes an output analog signal of the first amplifier circuit and an output analog signal of the DA converter circuit that is amplified at an amplification factor substantially the same as the predetermined amplification factor. 5. The analog-digital converter according to claim 1, wherein the difference is amplified at a predetermined amplification factor and output to the AD converter circuit and the first amplifier circuit.

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