JP2005136152A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a structure having an air gap in a space area of Cu wiring at a high yield. <P>SOLUTION: When insulting films 33 and 32 above a first layer wiring 26 wherein an air gap 28 is formed in a space area are etched to form a wiring groove 38, an alumina mask 34 whose selection ratio is large relative to the insulating films 33 and 32 is used to dry-etch the insulating films 32 and 33 and form the wiring groove 38 with high accuracy. The insulating film 33 is formed of a nitride silicon film, a silicon carbide film or a silicon carbonitride film, and the insulating film 32 is made of such a material that can be etched by ammonia plasma treatment or N<SB>2</SB>/H<SB>2</SB>plasma treatment. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to the manufacture of a semiconductor device having a wiring composed of a conductor film containing copper (Cu) as a main component.

  As a technique for realizing a high-speed and high-performance LSI, it is becoming essential to reduce the dielectric constant of an interlayer insulating film and to use Cu wiring using a damascene method. In particular, lowering the dielectric constant of an interlayer insulating film is a very important technique because not only can the capacitance between wirings be reduced, but also the power consumption of an LSI can be reduced.

  Many low dielectric constant insulating films, also called Low-K films, are currently on the market, but recently, porous (porous) in which a large number of fine pores are formed in the film to further lower the dielectric constant. ) Low-K films have also been developed. In addition, when depositing the insulating film on the wiring, the cross-sectional shape of the wiring is formed in a reverse taper shape in advance, and by forming a void (dielectric constant = about 1.0) between the adjacent wirings where the insulating film is not deposited, A technique for effectively reducing the dielectric constant of an insulating film in a region between adjacent wirings has also been developed (Patent Document 1).

  In US Pat. No. 6,159,845 (Patent Document 2), Cu wiring is formed in a wiring groove formed in a low dielectric constant insulating film on a substrate by a damascene method, and then a low dielectric constant insulating film between adjacent Cu wirings is formed. After removing the Cu wiring and exposing the upper and side surfaces of the exposed Cu wiring with a barrier insulating film such as silicon nitride or silicon carbide, the step coverage (step coverage) is low on the barrier insulating film. A technique for forming a void (air gap) in which an insulating film is not deposited between adjacent Cu wirings by depositing a low dielectric constant insulating film is disclosed.

  In US Pat. Nos. 6,214,719 (Patent Document 3) and 6,406,992 (Patent Document 4), a wiring pattern is formed with a first insulating film on a substrate, and then a second insulating film is formed between the first insulating films. Discloses a technique related to an air gap wiring in which an air gap is formed and then the first insulating film is removed to embed the wiring in the removed space.

  In US Pat. No. 6,403,461 (Patent Document 5), after a wiring pattern is formed on an insulating film on a substrate, a wiring conductor is embedded in the insulating film, and then the insulating film is removed to make the wiring pattern independent. A technique relating to an air gap wiring in which an insulating film is embedded so that an air gap is formed between adjacent wirings when an insulating film is deposited again is disclosed.

A technique for forming a metal cap of wiring by selectively depositing tungsten or the like on the upper surface of the wiring embedded in the insulating film or CVD is disclosed (Patent Documents 6 and 7).
JP 2001-85519 A US Pat. No. 6,159,845 US Pat. No. 6,214,719 US Pat. No. 6,406,992 US Pat. No. 6,403,461 Japanese Patent Laid-Open No. 11-16906 JP 2003-179000 A

  As described above, the low dielectric constant insulating film (Low-K film) is an insulative film indispensable for reducing the capacitance between wirings and lowering the power consumption of LSIs. It is being advanced. However, various low dielectric constant insulating films that have been marketed so far have a lower withstand voltage than conventional insulating film materials such as silicon oxide films deposited by the CVD method. There is a problem that the lifetime of TDDB (Time Dependence on Dielectric Breakdown) deteriorates. Moreover, this problem becomes more prominent as the insulating film has a lower dielectric constant. In addition, in a porous Low-K film having a large number of fine vacancies in the film, various gases remain in the vacancies during the etching process for forming a wiring groove in the insulating film, which causes film leakage. There is also a specific problem of higher levels.

  The TDDB life is a measure for objectively measuring the time dependence of dielectric breakdown, and a relatively high voltage is applied between electrodes under a measurement condition of a predetermined temperature (for example, 140 ° C.). A time (life) obtained by creating a graph in which the time until dielectric breakdown is plotted against the applied electric field and extrapolating from this graph to the actual electric field strength (for example, 0.2 MV / cm).

  The present inventors previously made a detailed study on the TDDB life between Cu wirings and elucidated the deterioration mechanism (Japanese Patent Application No. 2002-361363). Briefly, when Cu wiring is formed by damascene method inside a wiring groove formed in an insulating film, CuO (copper oxide) is formed on the surface of the Cu wiring by a surface process after chemical mechanical polishing. Cu silicide is formed during the formation of the cap insulating film covering the Cu wiring. Such CuO or Cu silicide is easily ionized as compared with pure Cu, and thus is drifted by the electric field between the wirings and diffused into the insulating film. Further, the surface of the insulating film on which the Cu wiring is formed is a discontinuous surface due to the influence of chemical mechanical polishing, and the adhesion with the cap insulating film is not sufficient. Therefore, the leakage path of the Cu ions is formed at the interface between the insulating film between the Cu wirings and the cap insulating film. The leakage current flowing through this leakage path is then accelerated by the addition of thermal stress due to the current, causing dielectric breakdown. Therefore, in order not to deteriorate the TDDB life between Cu wirings of the low dielectric constant insulating film, it is necessary to adopt a structure in which the above-described leakage path is not formed between the Cu wirings.

  In the structure in which a gap (air gap) in which an insulating film is not deposited between adjacent Cu wirings is formed, the leakage path as described above is not formed between Cu wirings. Therefore, even when a low dielectric constant insulating film is used, the TDDB life is reduced. Degradation can be avoided. Further, since the dielectric constant of the insulating film in the region between adjacent wirings can be effectively lowered without using the porous Low-K film, the above-mentioned problems specific to the porous Low-K film can also be avoided. .

  An object of the present invention is to provide a technique capable of forming a structure having a void (air gap) in a space region of a Cu wiring with a high yield.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A manufacturing method of a semiconductor device according to the present invention includes the following steps.
(A) forming a plurality of first wiring grooves in the first insulating film on the semiconductor substrate;
(B) forming a first conductive film mainly composed of copper on the first insulating film including the inside of each of the plurality of first wiring grooves;
(C) removing the first conductive film outside the plurality of first wiring grooves by a chemical mechanical polishing method, thereby forming a first conductive film formed of the first conductive film inside each of the plurality of first wiring grooves. Forming one wiring;
(D) After the step (c), forming the first wirings separated on the semiconductor substrate by removing the first insulating film,
(E) After the step (d), a second insulating film having a function of suppressing or preventing diffusion of copper contained in the first wiring is formed on the upper and side portions of the first wiring. Forming with a film thickness such that the space region of the first wiring is not filled with an insulating film;
(F) forming a first interlayer insulating film including a third insulating film and a fourth insulating film above the third insulating film on the second insulating film;
(G) forming a void in the space region of the first wiring in the step (e) or the step (f);
(H) forming a via hole penetrating the third insulating film and the fourth insulating film above the first wiring;
(I) Before or after the step (h), using the alumina film formed on the fourth insulating film as a mask, etching the fourth insulating film in a region including the via hole forming region, thereby 4 forming a plurality of second wiring grooves in the insulating film;
(J) after removing the alumina film, forming a second conductive film containing copper as a main component on the fourth insulating film including the insides of the plurality of second wiring grooves and the via holes;
(K) The second conductive film outside the plurality of second wiring grooves is removed by a chemical mechanical polishing method, so that the second conductive film is formed inside each of the plurality of second wiring grooves and the via holes. Forming a second wiring comprising:

A manufacturing method of a semiconductor device according to the present invention includes the following steps.
(A) forming a plurality of first wiring grooves in the first insulating film on the semiconductor substrate;
(B) forming a first conductive film mainly composed of copper on the first insulating film including the inside of each of the plurality of first wiring grooves;
(C) removing the first conductive film outside the plurality of first wiring grooves by a chemical mechanical polishing method, thereby forming a first conductive film formed of the first conductive film inside each of the plurality of first wiring grooves. Forming one wiring;
(D) Between the step (a) and the step (b), or after the step (c), a lower region of a via hole that connects the first wiring and the second wiring formed in the subsequent step; Irradiating the first insulating film in the peripheral region with an energy beam to alter the first insulating film in the region irradiated with the energy beam;
(E) After the step (d), removing the first insulating film in a region other than the region irradiated with the energy beam, and leaving the altered first insulating film;
(F) After the step (e), a second insulating film having a function of suppressing or preventing diffusion of copper contained in the first wiring is formed on the upper and side portions of the first wiring. Forming with a film thickness such that the space region of the first wiring is not filled with an insulating film;
(G) forming a first interlayer insulating film including a third insulating film and a fourth insulating film above the third insulating film on the second insulating film;
(H) forming a void in the space region of the first wiring in the step (f) or the step (g);
(I) forming the via hole penetrating the third insulating film and the fourth insulating film above the first wiring;
(J) Before or after the step (i), using the alumina film formed on the fourth insulating film as a mask, etching the fourth insulating film in a region including the via hole forming region, thereby 4 forming a plurality of second wiring grooves in the insulating film;
(K) After removing the alumina film, forming a second conductive film mainly composed of copper on the fourth insulating film including each of the plurality of second wiring grooves and the via holes;
(L) The second conductive film outside the plurality of second wiring grooves is removed by a chemical mechanical polishing method, whereby the second conductive film is formed inside each of the plurality of second wiring grooves and the via holes. Forming a second wiring comprising:

A manufacturing method of a semiconductor device according to the present invention includes the following steps.
(A) forming a plurality of first wiring grooves in the first insulating film on the semiconductor substrate;
(B) forming a first conductive film mainly composed of copper on the first insulating film including the inside of each of the plurality of first wiring grooves;
(C) removing the first conductive film outside the plurality of first wiring grooves by a chemical mechanical polishing method, thereby forming a first conductive film formed of the first conductive film inside each of the plurality of first wiring grooves. Forming one wiring;
(D) a step of removing the first insulating film after the step (c);
(E) After the step (d), forming a second conductive film having a function of suppressing or preventing diffusion of copper contained in the first wiring on the upper surface and the side portion of the first wiring;
(F) forming a first interlayer insulating film including a third insulating film and a fourth insulating film above the third insulating film on the first wiring, and forming a void in a space region of the first wiring; Forming step,
(G) forming a via hole penetrating the third insulating film and the fourth insulating film above the first wiring;
(H) Before or after the step (g), using the alumina film formed on the fourth insulating film as a mask, etching the fourth insulating film in a region including the via hole forming region, thereby 4 forming a plurality of second wiring grooves in the insulating film;
(I) after removing the alumina film, forming a second conductive film containing copper as a main component on the fourth insulating film including each of the plurality of second wiring grooves and the via holes;
(J) The second conductive film outside the plurality of second wiring grooves is removed by a chemical mechanical polishing method, whereby the second conductive film is formed inside each of the plurality of second wiring grooves and the via holes. Forming a second wiring comprising:

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since a structure having a void (air gap) in the space region of the Cu wiring can be formed with a high yield, it is possible to promote an increase in speed and power consumption of the LSI.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  In the following embodiments, a relative dielectric constant lower than that of a silicon oxide film (for example, TEOS (Tetraethoxysilane) oxide film) deposited by the CVD method is lower than that of ε = about 4.1 to 4.2. For convenience, the insulating film having a low dielectric constant is referred to as a low dielectric constant insulating film or a Low-K film.

  As an organic polymer-based low dielectric constant insulating material, SiLK (manufactured by The Dow Chemical Co., USA, relative dielectric constant = 2.7, heat-resistant temperature = 490 ° C. or higher, dielectric breakdown voltage = 4.0-5.0 MV / Vm) And FLARE (manufactured by Honeywell Electronic Materials, USA, relative permittivity = 2.8, heat-resistant temperature = 400 ° C. or higher), which is a polyallyl ether (PAE) material. The PAE-based material is characterized by high basic performance and excellent mechanical strength, thermal stability and low cost.

  As an organic silica glass-based low dielectric constant insulating material, HSG-R7 (manufactured by Hitachi Chemical Co., Ltd., relative dielectric constant = 2.8, heat-resistant temperature = 650 ° C.), Black Diamond (manufactured by Applied Materials, Inc., USA, relative dielectric constant) = 3.0-2.4, heat-resistant temperature = 450 ° C.) and p-MTES (manufactured by Hitachi Development Co., Ltd., relative dielectric constant = 3.2). In addition to the above, the SiOC materials include CORAL (manufactured by Novellus Systems, Inc., USA, relative permittivity = 2.7 to 2.4, heat-resistant temperature = 500 ° C.), Aurora 2.7 (manufactured by Nippon ASM Co., Ltd.) , Relative dielectric constant = 2.7, heat-resistant temperature = 450 ° C.).

  Other low dielectric constant insulating materials include SiOF materials, HSQ (hydrogen silsesquioxane) materials, MSQ (methyl silsesquioxane) materials, porous HSQ materials, porous MSQ materials, and porous organic materials. Among these, HSQ-based materials include OCD T-12 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 3.4 to 2.9, heat-resistant temperature = 450 ° C.), FOx (manufactured by Dow Corning Corp., USA, relative dielectric constant). = 2.9) and OCL T-32 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative permittivity = 2.5, heat-resistant temperature = 450 ° C.). MSQ-based materials include OCD T-9 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.7, heat-resistant temperature = 600 ° C.), LKD-T200 (manufactured by JSR, relative dielectric constant = 2.7-2.5, Heat-resistant temperature = 450 ° C.), HOSP (manufactured by Honeywell Electronic Materials, USA, relative dielectric constant = 2.5, heat-resistant temperature = 550 ° C.), HSG-RZ25 (manufactured by Hitachi Chemical, relative dielectric constant = 2.5, heat-resistant temperature = 650 ° C.), OCL T-31 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative permittivity = 2.3, heat-resistant temperature = 500 ° C.), LKD-T400 (manufactured by JSR, relative permittivity = 2.2-2, heat-resistant temperature = 450) ° C). Porous HSQ materials include XLK (manufactured by Dow Corning Corp., USA, relative permittivity = 2.5-2), OCL T-72 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative permittivity = 2.2-1.9, heat resistance). Temperature = 450 ° C.), Nanoglass (manufactured by Honeywell Electronic Materials, USA, relative dielectric constant = 2.2 to 1.8, heat-resistant temperature = 500 ° C. or higher), MesoELK (US Air Products and Chemicals, Inc., relative dielectric constant = 2 or lower) There is. Porous MSQ materials include HSG-6221X (manufactured by Hitachi Chemical Co., Ltd., relative dielectric constant = 2.4, heat-resistant temperature = 650 ° C.), ALCAP-S (manufactured by Asahi Kasei Kogyo Co., Ltd., relative dielectric constant = 2.3-1.8). , Heat resistant temperature = 450 ° C.), OCL T-77 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.2 to 1.9, heat resistant temperature = 600 ° C.), HSG-6210X (manufactured by Hitachi Chemical Co., Ltd., relative dielectric constant = 2.1, heat-resistant temperature = 650 ° C.), silica aerogel (manufactured by Kobe Steel, relative dielectric constant: 1.4 to 1.1), and the like. Examples of porous organic materials include PolyELK (US Air Products and Chemicals, Inc., dielectric constant = 2 or less, heat-resistant temperature = 490 ° C.).

Of the low dielectric constant insulating materials, SiOC-based materials and SiOF-based materials can be formed by a CVD method. For example, Black Diamond is formed by a CVD method using a mixed gas of trimethylsilane and oxygen, and p-MTES is formed by a CVD method using a mixed gas of methyltriethoxysilane and N ₂ O. Other insulating materials are formed by a coating method.

(Embodiment 1)
This embodiment is applied to a CMOS-LSI having a multilayer wiring, and a manufacturing method thereof will be described in the order of steps with reference to FIGS.

  First, as shown in FIG. 1, an n-channel MISFET (Qn) and a p-channel MISFET (Qp) are formed on the main surface of a semiconductor substrate (hereinafter simply referred to as a substrate) 1 made of single crystal silicon using a known semiconductor manufacturing method. ). Reference numeral 2 in the figure denotes an element isolation groove formed by embedding a silicon oxide film 3 in a groove formed by etching the substrate 1. Reference numeral 4 denotes a p-type well and 5 denotes an n-type well, which are formed by ion-implanting impurities into the substrate 1 and then performing heat treatment.

  The n-channel type MISFET (Qn) includes a gate insulating film 6 made of a silicon oxide film or a silicon oxynitride nitride film formed on the surface of the p-type well 4, and a polycrystalline silicon film formed on the gate insulating film 6. A gate electrode 7 made of, a sidewall spacer 10 made of a silicon oxide film or the like formed on the side wall of the gate electrode 7, and a pair of n-type semiconductor regions (sources) formed in the p-type well 4 on both sides of the gate electrode 7. Drain) 11 and the like. The p-channel type MISFET (Qp) includes a gate insulating film 6, a gate electrode 7, a side wall spacer 10, a pair of p-type semiconductor regions (source and drain) 12 formed in the n-type well 5 on both sides of the gate electrode 7, etc. Consists of. P (phosphorus) is introduced into the polycrystalline silicon film constituting the gate electrode 7 of the n-channel type MISFET (Qn), and the polycrystalline silicon film constituting the gate electrode 7 of the p-channel type MISFET (Qp) is introduced into the polycrystalline silicon film. B (boron) is introduced. Further, the respective surfaces of the gate electrode 7 and the n-type semiconductor region (source, drain) 11 of the n-channel type MISFET (Qn), and the gate electrode 7 and the p-type semiconductor region (source, drain) of the p-channel type MISFET (Qp). ) 12 is formed with a Co (cobalt) silicide film 13 for the purpose of reducing the resistance of the gate electrode 7 and the source and drain.

  Next, as shown in FIG. 2, after depositing a silicon nitride film 15 and a silicon oxide film 16 on the substrate 1 by a CVD method, the surface of the silicon oxide film 16 is planarized by a chemical mechanical polishing method. Subsequently, the silicon oxide film 16 on each of the n-type semiconductor region (source, drain) 11 of the n-channel type MISFET (Qn) and the p-type semiconductor region (source, drain) 12 of the p-channel type MISFET (Qp) After the silicon nitride film 14 is etched to form contact holes 17, plugs 18 are formed in the respective contact holes 17. The plug 18 is composed of a laminated film of, for example, a barrier film made of TiN (titanium nitride) and a W (tungsten) film.

  Next, as shown in FIG. 3, after three layers of insulating films 20, 21, 22 are deposited on the silicon oxide film 16, a photoresist film 24 having an opening for forming a wiring region is formed on the insulating film 22. Form. An antireflection film 23 is formed below the photoresist film 24 as necessary.

The insulating film 20 is composed of a silicon nitride film, a silicon oxynitride (SiON) film, a silicon carbide (SiC) film, or a silicon carbonitride (SiCN) film deposited by plasma CVD, and the insulating film 22 is a silicon nitride film, It is composed of a silicon carbide or silicon carbonitride film. The silicon oxynitride film is deposited using, for example, a mixed gas of trimethoxysilane and N ₂ O (nitrogen oxide), and the silicon carbide film is deposited using, for example, a mixed gas of He (helium) and trimethylsilane. . The silicon carbonitride film is deposited using, for example, a mixed gas of He, ammonia, and trimethylsilane.

On the other hand, the insulating film 21 is made of a material that can be etched by ammonia plasma processing or N ₂ / H ₂ plasma processing, for example, an organic polymer low dielectric constant insulating material such as SiLK described above. The film thickness of the first layer wiring 26 formed in the upper part of the silicon oxide film 16 in the next step is defined by the film thickness of the insulating film 21.

Next, as shown in FIG. 4, the antireflection film 23 and the insulating films 22, 21, and 20 are dry-etched using the photoresist film 24 as a mask, thereby forming a wiring trench 25 on the silicon oxide film 16. . At this time, the insulating film 21 is removed by etching using reducing plasma such as ammonia plasma or N ₂ / H ₂ plasma.

  Next, after removing the photoresist film 24 and the antireflection film 23 by ashing, a first layer wiring 26 is formed inside the wiring groove 25 as shown in FIG. The first layer wiring 26 is connected to the source and drain (n-type semiconductor region 11) of the n-channel type MISFET (Qn) or the source and drain (p-type semiconductor region 12) of the p-channel type MISFET (Qp) via the plug 18 in the lower layer. ) And electrically connected.

  In order to form the first layer wiring 26, first, a thin (about 50 nm) TiN film that does not fill the inside of the wiring trench 25 is deposited by sputtering, and then the thick (800 nm) that completely fills the inside of the wiring trench 25 is deposited. After the Cu film is deposited by a sputtering method, a plating method, or a combination thereof, the Cu film and the TiN film outside the wiring trench 25 are removed by a chemical mechanical polishing method. The TiN film is a barrier film that prevents the Cu film from diffusing into the surrounding insulating film. The barrier film is a TiN film, a metal nitride film such as WN (tungsten nitride) or TaN (tantalum nitride), a film obtained by adding Si to these films, or a refractory metal film such as Ta, Ti, W, or TiW Various conductive films that do not easily react with Cu can be used alone or in a laminated structure. As will be described later, in the present embodiment, Cu in the first layer wiring 26 is diffused into the interlayer insulating film (30) by covering the surface of the first layer wiring 26 with the barrier insulating film (27). In order to prevent this, the conductive barrier film such as the TiN film described above is not always necessary, and the first layer wiring 26 may be formed of only the Cu film.

Next, as shown in FIG. 6, the insulating film 21 is removed by etching using reducing plasma such as ammonia plasma or N ₂ / H ₂ plasma. By removing the insulating film 21 by reducing plasma treatment, Cu oxide (CuO, CuO ₂ ) generated on the surface of the first layer wiring 26 in the course of the chemical mechanical polishing treatment is reduced to Cu. A thin protective film made of CuN (copper nitride) can be formed on the surface of the first layer wiring 26.

  Next, as shown in FIG. 7, a barrier insulating film 27 is deposited on the first layer wiring 26. The barrier insulating film 27 is an insulating film for preventing Cu in the first layer wiring 26 from diffusing into an interlayer insulating film (30) to be formed later. For example, a silicon nitride film deposited by a plasma CVD method, an acid film A silicon nitride film, a silicon carbide film, or a silicon carbonitride film is used.

  The barrier insulating film 27 is deposited under such film forming conditions that the film is not conformally deposited along the side wall and the upper surface of the first layer wiring 26 but overhangs in the vicinity of the upper portion of the side wall of the first layer wiring 26. That is, the deposition is performed under such a condition that the deposition rate of the barrier insulating film 27 in the vicinity of the upper portion of the side wall of the first layer wiring 26 is higher than the deposition rate in the vicinity of the lower portion of the sidewall. In this way, in a region where the pitch between adjacent first layer wirings 26 (a pitch between adjacent wirings) among the plurality of first layer wirings 26 is the smallest, a barrier insulating film is formed in the space region of the first layer wirings 26. Since the barrier insulating films 27 are in contact with each other in the vicinity of the upper portion of the side wall of the first layer wiring 26 before the 27 is completely buried, a gap (air gap) 28 is formed in the space region of the first layer wiring 26.

  This effectively reduces the dielectric constant of the barrier insulating film 27 interposed in the space region of the first layer wiring 26 in the region where the pitch between adjacent wirings is the smallest, that is, in the region where the capacitance between the wirings is the most problematic. Therefore, the inter-wiring capacity of the first layer wiring 26 can be reduced. In addition, even if the barrier insulating film 27 is not made of a porous Low-K material, the dielectric constant of the insulating film in the inter-wiring region can be effectively lowered, so that there is a problem when the porous Low-K material is used. An increase in leak level can also be avoided.

  Further, in the above structure, as in a normal damascene structure, not only the insulating film 21 does not remain in the space region of the first layer wiring 26 but also the upper end of the gap 28 is higher than the upper surface of the first layer wiring 26. Is located. As a result, a Cu ion leakage path is not formed in the space region of the first layer wiring 26, and therefore, the deterioration of the TDDB life can be prevented.

  Next, as shown in FIG. 8, an interlayer insulating film 30 and a cap insulating film 31 are deposited on the barrier insulating film 27, and then the surface of the cap insulating film 31 is planarized by a chemical mechanical polishing method. The interlayer insulating film 30 is formed of a low dielectric constant such as SiOF or SiOC in order to reduce a capacitance formed between the first layer wiring 26 and a second layer wiring (40) formed thereon in a later step. It is composed of an insulating film. The cap insulating film 31 is made of a silicon oxide film deposited by a CVD method and functions as a protective film when a low dielectric constant insulating film having a mechanical strength lower than that of the silicon oxide film is planarized by a chemical mechanical polishing method. . The cap insulating film 31 also functions as an etching stopper film when the upper insulating film (32) is etched in a later step.

  The space 28 in the space area of the first layer wiring 26 can also be formed by a method other than the above. That is, as shown in FIG. 9, the barrier insulating film 27 is stopped before the barrier insulating films 27 come into contact with each other in the vicinity of the upper portion of the side wall of the first layer wiring 26, and then the interlayer is formed on the upper portion of the barrier insulating film 27. An insulating film 30 may be deposited. In this case, in the region where the pitch between adjacent wirings is minimum, the opening area of the space region of the first layer wiring 26 is narrow, and the interlayer insulating film 30 cannot enter the gap, so that the air gap 28 is formed.

Next, as shown in FIG. 10, after depositing two layers of insulating films 32 and 33 on the cap insulating film 31, alumina (Al ₂ O) having a wiring groove forming region opened on the insulating film 33 is formed. ₃ ) A mask 34 is formed. The insulating film 32 is made of a material that can be etched by ammonia plasma processing or N ₂ / H ₂ plasma processing, such as SiLK described above. The insulating film 33 is a protective film that prevents the insulating film 32 having poor oxidation resistance such as SiLK from being deteriorated by direct contact with the alumina mask 34, for example, a silicon nitride film, silicon carbide, or silicon carbonitride film. It is made of an insulating material with strong oxidation resistance. The alumina mask 34 is formed by depositing an alumina film on the insulating film 33 by a sputtering method and then removing the alumina film in the wiring groove forming region by dry etching using the photoresist film as a mask.

Next, as shown in FIG. 11, an antireflection film 35 is formed on the insulating film 33, and a photoresist film 36 having a via hole formation region opened is formed on the antireflection film 35. Then, by using the photoresist film 36 as a mask, the antireflection film 23, the insulating films 33 and 32, the cap insulating film 31, the interlayer insulating film 30 and the barrier insulating film 27 are dry-etched, whereby via holes reaching the barrier insulating film 27 are formed. 37 is formed. At this time, the insulating film 32 is etched by ammonia plasma processing or N ₂ / H ₂ plasma processing.

Next, after removing the photoresist film 36 and the antireflection film 35 by ashing, as shown in FIG. 12, the insulating films 33 and 32 are dry-etched using the alumina mask 34 as a mask to form a wiring groove 38. To do. At this time, the insulating film 32 is etched by ammonia plasma processing or N ₂ / H ₂ plasma processing. The lower cap insulating film 31 functions as an etching stopper film when the insulating film 32 is etched.

  When etching the insulating film 33 made of the silicon nitride film, silicon carbide, or silicon carbonitride film, a high etching selectivity with respect to the insulating film 33 is obtained when a mask made of a photoresist or a silicon-based insulating film is used. I can't. In contrast, alumina can provide a high etching selectivity with respect to the insulating film 33 and the insulating film 32 made of the above-described materials. Therefore, by using the alumina mask 34, the wiring groove 38 can be formed with high accuracy. Can be formed. Here, the process of forming the wiring groove 38 after forming the via hole 37 has been described, but conversely, the via hole 37 may be formed after forming the wiring groove 38.

  Next, as shown in FIG. 13, after removing the alumina mask 34 with a hydrofluoric acid-based etchant, the barrier insulating film 27 at the bottom of the via hole 37 is dry-etched using the cap insulating film 31 as a mask. The surface of the first layer wiring 26 is exposed. At this time, the insulating film 33 on the insulating film 32 is also removed at the same time.

  Next, as shown in FIG. 14, the second layer wiring 40 is formed inside the wiring groove 38. The second layer wiring 40 is formed by the same method as when the first layer wiring 26 is formed inside the wiring groove 25. That is, a thin TiN film (barrier film) that does not fill the inside of the wiring trench 38 is deposited by sputtering, and then a thick Cu film that completely fills the inside of the wiring trench 38 is deposited by sputtering or plating. Then, the Cu film and the TiN film outside the wiring groove 38 are removed by a chemical mechanical polishing method. The second layer wiring 40 is electrically connected to the first layer wiring 26 through the via hole 37.

Next, as shown in FIG. 15, the insulating film 32 is removed by etching using a reducing plasma such as ammonia plasma or N ₂ / H ₂ plasma. By removing the insulating film 32 by reducing plasma treatment, Cu oxide (CuO, CuO ₂ ) generated on the surface of the second layer wiring 40 in the course of the chemical mechanical polishing treatment is reduced to Cu. A thin protective film made of CuN (copper nitride) can be formed on the surface of the two-layer wiring 40.

  Next, as shown in FIG. 16, a barrier insulating film 41 is deposited on the second layer wiring 40. The barrier insulating film 41 is an insulating film for preventing Cu in the second layer wiring 40 from diffusing into an interlayer insulating film (43) to be formed later. The barrier insulating film 41 is made of, for example, a silicon nitride film, a silicon oxynitride film, a silicon carbide film, or a silicon carbonitride film deposited by a plasma CVD method, like the barrier insulating film 27 that covers the first layer wiring 26. Further, the barrier insulating film 41 is formed in the same film formation conditions as the lower barrier insulating film 27, that is, the film is not conformally deposited along the side wall and the upper surface of the second layer wiring 40, and the upper side wall of the second layer wiring 40 is In the region where the pitch between adjacent second layer wirings 40 (the pitch between adjacent wirings) is the smallest among the plurality of second layer wirings 40 by depositing under film forming conditions that cause overhang in the vicinity. A space (air gap) 42 is formed in the space region of the two-layer wiring 40.

  This effectively reduces the dielectric constant of the barrier insulating film 41 interposed in the space region of the second layer wiring 40 in the region where the pitch between adjacent wirings is the smallest, that is, the region where the capacitance between wirings is the most problematic. Therefore, the inter-wiring capacity of the second layer wiring 40 can be reduced. Moreover, since a Cu ion leak path is not formed in the space region of the second layer wiring 40, it is possible to prevent the deterioration of the TDDB life.

  Next, as shown in FIG. 17, an interlayer insulating film 43 and a cap insulating film 44 are deposited on the barrier insulating film 41, and then a third layer wiring 45 is formed on the cap insulating film 44. A barrier insulating film 46 is deposited on the third layer wiring 45. The interlayer insulating film 43 is composed of a low dielectric constant insulating film such as SiOF or SiOC in order to reduce the inter-wiring capacitance, as with the lower interlayer insulating film 30, and the cap insulating film 44 is the lower cap insulating film 31. In the same manner as described above, the silicon oxide film is deposited by the CVD method. The third layer wiring 45 is composed of a TiN film (barrier film) and a Cu film like the second layer wiring 40 and is formed by the same method as the second layer wiring 40. The third layer wiring 45 is electrically connected to the second layer wiring 40 through the via hole 47.

  The barrier insulating film 46 is an insulating film for preventing Cu in the third-layer wiring 45 from diffusing into an interlayer insulating film (50) to be formed later. Like the barrier insulating films 27 and 41 in the lower layer, the barrier insulating film 46 is plasma. A silicon nitride film, a silicon oxynitride film, a silicon carbide film, or a silicon carbonitride film deposited by a CVD method is used. In addition, by depositing the barrier insulating film 46 under the same film formation conditions as the lower barrier insulating films 27 and 41, the pitch (adjacent wiring) between the adjacent third layer wirings 45 among the plurality of third layer wirings 45. In the region where the (interval pitch) is the smallest, a gap (air gap) 48 is formed in the space region of the third layer wiring 45.

  As a result, like the first layer wiring 26 and the second layer wiring 40, it is interposed in the space region of the third layer wiring 45 in the region where the pitch between adjacent wirings is the smallest, that is, the region where the capacitance between wirings is the most problematic. Since the dielectric constant of the barrier insulating film 41 can be effectively lowered, the inter-wiring capacitance of the third layer wiring 45 can be reduced. Further, since a Cu ion leak path is not formed in the space region of the third layer wiring 45, it is possible to prevent the deterioration of the TDDB life.

  Next, as shown in FIG. 18, an interlayer insulating film 50 and a cap insulating film 51 are deposited on the barrier insulating film 46, and then a fourth layer wiring 52 is formed inside the interlayer insulating film 50. A barrier insulating film 53 is deposited on the fourth layer wiring 52. The interlayer insulating film 50 is composed of a low dielectric constant insulating film such as SiOF or SiOC in order to reduce the inter-wiring capacitance, similarly to the lower interlayer insulating films 30 and 43, and the cap insulating film 44 is formed of the lower cap insulating film. Like the films 31 and 44, the film is formed of a silicon oxide film deposited by the CVD method.

  The fourth layer wiring 52 is composed of a TiN film (barrier film) and a Cu film like the first to third layer wirings 26, 40, and 45, but with another adjacent fourth layer wiring (not shown). Is assumed to be far enough that the capacitance between the wirings is not a problem. The same applies to the wiring (not shown) above the fourth layer wiring 52. In this case, the fourth layer wiring 52 and the upper layer wiring are formed by using a well-known dual damascene method without forming a gap in the space region between adjacent wirings. Thereby, it is possible to reduce the inter-wiring capacity of the first to third layer wirings 26, 40, 45 and prevent the deterioration of the TDDB life without reducing the mechanical strength of the entire wiring layer.

  In the first embodiment described above, a process and structure that does not use the insulating films 20, 31, 44, and 51 are possible.

  In this embodiment, the method of forming a gap in the space area of the wiring in the area where the pitch between adjacent wirings where the capacity between the wirings is a problem has been described. However, the area where the pitch between adjacent wirings is relatively wide. In FIG. 19A to FIG. 19D, when the air gap is to be formed in the wiring space area or the air gap is to be formed in an area other than the wiring space area, as shown in FIGS. The dummy wirings 39 may be disposed in the wirings, and the pitch between the wirings 26 and the dummy wirings 39 or the pitch between the dummy wirings 39 may be minimized. The dummy wiring 39 is a conductor pattern formed at the same time as the wiring 26, but is not required as an LSI electrical circuit, that is, a conductor pattern that does not function as the wiring 26.

(Embodiment 2)
In the process described in the first embodiment, when the via hole 37 that connects the second layer wiring 40 and the first layer wiring 26 is formed (see FIG. 11), A positional shift may occur between the first layer wiring 26 and the first layer wiring 26. Normally, when such a positional shift occurs, when the via hole 37 is formed by etching the insulating film above the first layer wiring 26, the insulating film in the space region of the first layer wiring 26 is also partially removed. However, in the region where the pitch between adjacent wirings is narrow, since the air gap 28 is formed in the space region of the first layer wiring 26, even the insulating film below the air gap 28 is cut away. There is a possibility that part of the bottom reaches the gate electrode 7 or the substrate 1. Such a problem also occurs when the via hole 47 that connects the third layer wiring 45 and the second layer wiring 40 is formed.

  As a countermeasure, in this embodiment, the via hole 37 is formed by the following method. Although explanation is omitted, the via hole 47 is also formed by the same method.

  First, as shown in FIG. 20, the silicon nitride film 15 and the silicon oxide film 16 formed on the n-channel MISFET (Qn) and the p-channel MISFET (Qp) are etched to form a contact hole 17. Subsequently, after a plug 18 is formed inside the contact hole 17, three layers of insulating films 20, 21, and 22 are deposited on the silicon oxide film 16.

  Next, as shown in FIG. 21, after the antireflection film 23 and the photoresist film 24 are formed on the insulating film 22, the antireflection film 23 and the insulating films 22, 21, A wiring trench 25 is formed by dry etching 20. The steps so far are the same as the steps shown in FIGS. 1 to 4 of the first embodiment. In FIG. 21 and the following FIGS. 22 to 29, illustration of the region below the insulating film 20 is omitted.

Next, as shown in FIG. 22, the photoresist film 24, the antireflection film 23, and the insulating film 22 are removed. FIG. 23 shows the planar shapes of the insulating film 21 and the wiring trench 25 in this state. The insulating film 21 is a material that can be etched by ammonia plasma processing or N ₂ / H ₂ plasma processing, for example, an organic polymer low dielectric constant insulating material such as SiLK described above. Note that the insulating film 22 may be left on the insulating film 21.

Next, as shown in FIG. 24, an electron beam (EB) is applied to the region where the via hole 37 for connecting the second layer wiring 40 and the first layer wiring 26 is formed in the subsequent process and the insulating film 21 around the region. Irradiate. As a result, the insulating film 21 in the region exposed to the electron beam (EB) changes in quality and becomes an insulating film 21a that is not etched by the ammonia plasma process or the N ₂ / H ₂ plasma process. FIG. 25 is a plan view showing the position of the via hole 37 and the irradiation region of the electron beam (EB). The position of the via hole 37 shown here is between the first-layer wiring 26 to be formed later. This is the position when no misalignment occurs (position when the misalignment of the photomask is 0). On the other hand, the irradiation region of the electron beam (EB) is a region where the above positional deviation is 0 to maximum.

Next, as shown in FIG. 26, the first layer wiring 26 is formed in the wiring groove 25 by the same method as in the first embodiment. The electron beam (EB) irradiation may be performed after the first layer wiring 26 is formed in the wiring groove 25. An energy beam other than an electron beam (EB) may be used as long as the insulating film 21 can be modified to an insulating film 21a that is not etched by ammonia plasma treatment or N ₂ / H ₂ plasma treatment.

Next, as shown in FIG. 27, when the insulating film 21 is removed by ammonia plasma processing or N ₂ / H ₂ plasma processing, the insulating film 21a remains only around the region where the via hole 37 is formed.

  Next, as shown in FIG. 28, when the barrier insulating film 27 is deposited on the first layer wiring 26 by the same method as in the first embodiment, the first layer is formed in the region where the pitch between adjacent wirings is minimum. A gap 28 is formed in the space area of the wiring 26. At this time, since the insulating film 21a remains around the region where the via hole 37 is formed, the air gap 28 is not formed. Therefore, although the capacitance formed in the space region of the first layer wiring 26 is larger than the other regions around the region where the via hole 37 is formed, the occupied area of the via hole 37 formed on the substrate 1 is as follows. Since the area occupied by the first layer wiring 26 is much smaller, the influence on the inter-wiring capacitance of the entire first layer wiring 26 is negligible.

  After that, as shown in FIG. 29, a via hole 37 is formed by etching the insulating film above the first layer wiring 26 by the same method as in the first embodiment. According to the present embodiment, at this time, even if a positional shift occurs between the via hole 37 and the first layer wiring 26 due to the misalignment of the photomask, the via hole in the region shifted from the first layer wiring 26 Since the insulating film 21a is formed under 37, there is no possibility that the insulating film under the first layer wiring 26 will be scraped. Here, the case where the via hole 37 for connecting the second layer wiring 40 and the first layer wiring 26 is formed has been described, but the case where the via hole 47 for connecting the third layer wiring 45 and the second layer wiring 40 is formed. Of course, the present invention can also be applied.

  Further, as a countermeasure against misalignment other than the method described above, as shown in FIG. 30, only in the region where the via hole 37 is formed, the width of the first layer wiring 26 is widened, and the via hole 37 is caused by misalignment of the photomask. The via hole 37 may be disposed on the first layer wiring 26 even when a positional deviation occurs between the first layer wiring 26 and the first layer wiring 26. This method is simpler than the method of modifying a part of the insulating film 21 by irradiation with an electron beam (EB). However, since the pitch between adjacent wirings becomes wide, when applied to a region where the wiring density is high. , Chip size will increase.

(Embodiment 3)
In this embodiment, a method for further reducing the capacitance between wirings will be described. First, as shown in FIG. 31, the silicon nitride film 15 and the silicon oxide film 16 formed on the n-channel MISFET (Qn) and the p-channel MISFET (Qp) are etched to form contact holes 17. Subsequently, after a plug 18 is formed inside the contact hole 17, three layers of insulating films 20, 21, 22 are deposited on the silicon oxide film 16, and an antireflection film 23 and a photoresist film are formed on the insulating film 22. 24. The steps so far are the same as the steps shown in FIGS. 1 to 3 of the first embodiment.

  Next, as shown in FIG. 32, the antireflection film 23 and the insulating films 22, 21, and 20 are dry-etched using the photoresist film 24 as a mask to form a wiring groove 25. Next, as shown in FIG. At this time, in this embodiment, a forward taper is provided on the sidewall of the wiring trench 25 by controlling the etching conditions of the insulating films 22, 21, and 20. That is, the area of the opening of the wiring groove 25 is made smaller than the area of the bottom. In order to provide the forward taper on the side wall of the wiring groove 25, the forward groove may be provided on the side wall of the wiring groove 25 by wet etching after the wiring groove 25 is formed under the same dry etching conditions as in the first embodiment. In FIG. 32 and the following FIGS. 33 to 36, the region below the insulating film 20 is not shown.

Next, after removing the photoresist film 24 and the antireflection film 23, as shown in FIG. 33, a first layer wiring 26 is formed in the wiring groove 25 by the same method as in the first embodiment, and then Then, as shown in FIG. 34, the insulating film 21 is removed by ammonia plasma treatment or N ₂ / H ₂ plasma treatment. The cross-sectional shape of the first layer wiring 26 thus obtained has an inverse taper in which the width of the upper end is wider than the width of the bottom.

Next, as shown in FIG. 35, a metal cap film 29 is formed on the upper surface of the first layer wiring 26. The metal cap film 29 is a barrier film for preventing Cu in the first layer wiring 26 from diffusing into an interlayer insulating film 30 to be formed later, and is made of, for example, W (tungsten). The metal cap film 29 made of W is selectively formed on the surface of the Cu film constituting the first layer wiring 26 by selective tungsten CVD using tungsten hexafluoride (WF ₆ ) and hydrogen (H ₂ ) gas. can do. In addition to W, the metal cap film 29 may be made of another metal or metal nitride having a barrier function for preventing diffusion of Cu, for example, Ti, CoWP, CoWB, Ta, TiN, or TaN.

  Next, as shown in FIG. 36, after depositing an interlayer insulating film 30 and a cap insulating film 31 on the first layer wiring 26, the surface of the cap insulating film 31 is planarized by a chemical mechanical polishing method. That is, in the present embodiment, the interlayer insulating film 30 is formed without forming the barrier insulating film 27 on the first layer wiring 26, but the metal cap film 29 is formed on the surface of the first layer wiring 26. Even if the barrier insulating film 27 is not formed, Cu in the first layer wiring 26 does not diffuse into the interlayer insulating film 30.

  In the present embodiment, the cross-sectional shape of the first layer wiring 26 is inverted. For this reason, when the interlayer insulating film 30 is formed on the first layer wiring 26, in a region where the pitch between adjacent wirings is the minimum, before the interlayer insulating film 30 is completely embedded in the space region of the first layer wiring 26. In addition, the interlayer insulating films 30 are in contact with each other in the vicinity of the upper portion of the side wall of the first layer wiring 26, and a gap 28 is formed in the space region of the first layer wiring 26.

  As described above, the interlayer insulating film 30 is composed of a low dielectric constant insulating film such as SiOF or SiOC. Therefore, according to the present embodiment in which the upper and side walls of the first layer wiring 26 are covered with the interlayer insulating film 30 and the air gap 28 is formed in the space region of the first layer wiring 26, The capacity can be further reduced. In addition, according to this structure, unlike the ordinary damascene structure, a Cu ion leak path is not formed in the space region of the first layer wiring 26, so that it is possible to prevent the deterioration of the TDDB life.

  Further, by applying the structure of the present embodiment described above to the second layer wiring 40 and the third layer wiring 45, the inter-wiring capacitance of the second layer wiring 40 and the third layer wiring 45 can be further reduced. .

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is useful for promoting high speed and low power consumption of an LSI having a damascene Cu wiring and a low dielectric constant insulating film.

It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor device which is one embodiment of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 1. FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 4; FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 5; FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 7; FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 8; FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 9; FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 12; FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 13; FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 15; FIG. 17 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 17; (A)-(d) is a top view which shows the layout of the wiring and dummy wiring in the manufacturing method of the semiconductor device which is other Embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 20; FIG. 22 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 21; FIG. 22 is a fragmentary plan view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 21; FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 22; FIG. 23 is a plan view of relevant parts of a semiconductor substrate, illustrating a method for manufacturing a semiconductor device following FIG. 22; FIG. 25 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 24; FIG. 27 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 26; FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 27; FIG. 29 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 28; It is a top view which shows the shape of the wiring in the manufacturing method of the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. FIG. 32 is a main-portion cross-sectional view of the semiconductor substrate, which illustrates the manufacturing method of the semiconductor device following FIG. 31; FIG. 33 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 32; FIG. 34 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 33; FIG. 35 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 34; FIG. 36 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 35;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation groove 3 Silicon oxide film 4 P-type well 5 N-type well 6 Gate insulating film 7 Gate electrode 10 Side wall spacer 11 N-type semiconductor region (source, drain)
12 p-type semiconductor region (source, drain)
13 Co silicide film 15 Silicon nitride film 16 Silicon oxide film 17 Contact hole 18 Plugs 20, 21, 21a, 22 Insulating film 23 Antireflection film 24 Photoresist film 25 Wiring groove 26 First layer wiring 27 Barrier insulating film 28 Air gap (air gap)
29 Metal cap film 30 Interlayer insulating film 31 Cap insulating films 32 and 33 Insulating film 34 Alumina mask 35 Antireflection film 36 Photoresist film 37 Via hole 38 Wiring groove 39 Dummy wiring 40 Second layer wiring 41 Barrier insulating film 42 Air gap (air gap) )
43 Interlayer insulating film 44 Cap insulating film 45 Third layer wiring 46 Barrier insulating film 47 Via hole 48 Air gap (air gap)
50 Interlayer insulating film 51 Cap insulating film 52 Fourth layer wiring 53 Barrier insulating film EB: Electron beam Qn: n-channel type MISFET
Qp: p-channel type MISFET

Claims (20)

Manufacturing method of semiconductor device having the following steps:
(A) forming a plurality of first wiring grooves in the first insulating film on the semiconductor substrate;
(B) forming a first conductive film mainly composed of copper on the first insulating film including the inside of each of the plurality of first wiring grooves;
(C) removing the first conductive film outside the plurality of first wiring grooves by a chemical mechanical polishing method, thereby forming a first conductive film formed of the first conductive film inside each of the plurality of first wiring grooves. Forming one wiring;
(D) After the step (c), forming the first wirings separated on the semiconductor substrate by removing the first insulating film,
(E) After the step (d), a second insulating film having a function of suppressing or preventing diffusion of copper contained in the first wiring is formed on the upper and side portions of the first wiring. Forming with a film thickness such that the space region of the first wiring is not filled with an insulating film;
(F) forming a first interlayer insulating film including a third insulating film and a fourth insulating film above the third insulating film on the second insulating film;
(G) forming a void in the space region of the first wiring in the step (e) or the step (f);
(H) forming a via hole penetrating the third insulating film and the fourth insulating film above the first wiring;
(I) Before or after the step (h), using the alumina film formed on the fourth insulating film as a mask, etching the fourth insulating film in a region including the via hole forming region, thereby 4 forming a plurality of second wiring grooves in the insulating film;
(J) after removing the alumina film, forming a second conductive film containing copper as a main component on the fourth insulating film including the insides of the plurality of second wiring grooves and the via holes;
(K) The second conductive film outside the plurality of second wiring grooves is removed by a chemical mechanical polishing method, so that the second conductive film is formed inside each of the plurality of second wiring grooves and the via holes. Forming a second wiring comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is removed by etching using reducing plasma.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the gap is formed in a region where the pitch of the first wiring is minimum.   2. The method of manufacturing a semiconductor device according to claim 1, wherein an upper end of the gap is located above an upper surface of the first wiring.   2. The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film is formed in the vicinity of an upper portion of a side wall of the first wiring before the second insulating film is filled in a space region of the first wiring. A method for manufacturing a semiconductor device, characterized in that the semiconductor device is formed by contacting each other.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the fourth insulating film is etched by reducing plasma.   7. The method of manufacturing a semiconductor device according to claim 6, wherein a fifth insulating film having a function of suppressing or preventing oxidation of the fourth insulating film is provided between the fourth insulating film and the alumina film. A method of manufacturing a semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, wherein a width of the first wiring in a region where the via hole exposes the first wiring is made wider than a width in another region. Method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein when forming the first wiring in the step (c), the first conductive film is formed in a part of the plurality of first wiring trenches as wiring. A method for manufacturing a semiconductor device, comprising: forming a dummy wiring having no function. 2. The method of manufacturing a semiconductor device according to claim 1, wherein after the step (k),
(L) removing the fourth insulating film;
(M) After the step (l), a sixth insulating film having a function of suppressing or preventing diffusion of copper contained in the second wiring is formed so that a space region of the second wiring is formed by the sixth insulating film. A process of forming a film thickness not to be filled,
(N) forming a second interlayer insulating film on the sixth insulating film;
(O) forming a void in a space region of the second wiring in the step (m) or the step (n),
A method for manufacturing a semiconductor device, further comprising:   11. The method of manufacturing a semiconductor device according to claim 10, further comprising a step of forming a plurality of wirings in a plurality of wiring layers above the second wiring after the step (o), respectively. A manufacturing method of a semiconductor device, wherein the gap is not formed in a space region of the plurality of wirings formed in at least a part of the wiring layer among the layers. Manufacturing method of semiconductor device having the following steps:
(A) forming a plurality of first wiring grooves in the first insulating film on the semiconductor substrate;
(B) forming a first conductive film mainly composed of copper on the first insulating film including the inside of each of the plurality of first wiring grooves;
(C) removing the first conductive film outside the plurality of first wiring grooves by a chemical mechanical polishing method, thereby forming a first conductive film formed of the first conductive film inside each of the plurality of first wiring grooves. Forming one wiring;
(D) Between the step (a) and the step (b), or after the step (c), a lower region of a via hole that connects the first wiring and the second wiring formed in the subsequent step; Irradiating the first insulating film in the peripheral region with an energy beam to alter the first insulating film in the region irradiated with the energy beam;
(E) After the step (d), removing the first insulating film in a region other than the region irradiated with the energy beam, and leaving the altered first insulating film;
(F) After the step (e), a second insulating film having a function of suppressing or preventing diffusion of copper contained in the first wiring is formed on the upper and side portions of the first wiring. Forming with a film thickness such that the space region of the first wiring is not filled with an insulating film;
(G) forming a first interlayer insulating film including a third insulating film and a fourth insulating film above the third insulating film on the second insulating film;
(H) forming a void in the space region of the first wiring in the step (f) or the step (g);
(I) forming the via hole penetrating the third insulating film and the fourth insulating film above the first wiring;
(J) Before or after the step (i), using the alumina film formed on the fourth insulating film as a mask, etching the fourth insulating film in a region including the via hole forming region, thereby 4 forming a plurality of second wiring grooves in the insulating film;
(K) After removing the alumina film, forming a second conductive film mainly composed of copper on the fourth insulating film including each of the plurality of second wiring grooves and the via holes;
(L) The second conductive film outside the plurality of second wiring grooves is removed by a chemical mechanical polishing method, whereby the second conductive film is formed inside each of the plurality of second wiring grooves and the via holes. Forming a second wiring comprising:   13. The method of manufacturing a semiconductor device according to claim 12, wherein the energy beam is an electron beam.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the first insulating film and the fourth insulating film are removed by etching using reducing plasma.   15. The method of manufacturing a semiconductor device according to claim 14, wherein a fifth insulating film having a function of suppressing or preventing oxidation of the fourth insulating film is provided between the fourth insulating film and the alumina film. A method of manufacturing a semiconductor device. Manufacturing method of semiconductor device having the following steps:
(A) forming a plurality of first wiring grooves in the first insulating film on the semiconductor substrate;
(B) forming a first conductive film mainly composed of copper on the first insulating film including the inside of each of the plurality of first wiring grooves;
(C) removing the first conductive film outside the plurality of first wiring grooves by a chemical mechanical polishing method, thereby forming a first conductive film formed of the first conductive film inside each of the plurality of first wiring grooves. Forming one wiring;
(D) a step of removing the first insulating film after the step (c);
(E) After the step (d), forming a second conductive film having a function of suppressing or preventing diffusion of copper contained in the first wiring on the upper surface and the side portion of the first wiring;
(F) forming a first interlayer insulating film including a third insulating film and a fourth insulating film above the third insulating film on the first wiring, and forming a void in a space region of the first wiring; Forming step,
(G) forming a via hole penetrating the third insulating film and the fourth insulating film above the first wiring;
(H) Before or after the step (g), using the alumina film formed on the fourth insulating film as a mask, etching the fourth insulating film in a region including the via hole forming region, thereby 4 forming a plurality of second wiring grooves in the insulating film;
(I) after removing the alumina film, forming a second conductive film containing copper as a main component on the fourth insulating film including each of the plurality of second wiring grooves and the via holes;
(J) The second conductive film outside the plurality of second wiring grooves is removed by a chemical mechanical polishing method, whereby the second conductive film is formed inside each of the plurality of second wiring grooves and the via holes. Forming a second wiring comprising:   17. The method of manufacturing a semiconductor device according to claim 16, wherein the cross-sectional shape of the first wiring is an inverse taper in which the width of the upper end is wider than the width of the bottom.   17. The method of manufacturing a semiconductor device according to claim 16, wherein the second conductive film is a W film formed by a selective tungsten CVD method.   17. The method of manufacturing a semiconductor device according to claim 16, wherein the first insulating film and the fourth insulating film are removed by etching using reducing plasma.   20. The method of manufacturing a semiconductor device according to claim 19, wherein a fifth insulating film having a function of suppressing or preventing oxidation of the fourth insulating film is provided between the fourth insulating film and the alumina film. A method of manufacturing a semiconductor device.

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