JP2005122578A - Logic synthesis constraint generating device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To extract information related to timing constraints from design data in preparing synthetic constraints, in a semiconductor integrated circuit design environment where data are hierarchically divided so as to be sysnthesized for each hierarchy, and to realize error checking of the established constraints or the preparation and/or correction of the constraints by using the extracted information. <P>SOLUTION: This logic synthesis constraint generating device is provided with a circuit information input means 103, which inputs circuit information including logical design data 101 and synthetic hierarchy information 102 of an integrated circuit, a constraint input means 105 which inputs constraint conditions 104 for logic synthesis, a circuit information database 106 which stores the circuit information and the constraint conditions, a relevant clock-extracting means 108 which extracts the relevant clock of a block port from the information on the circuit information database 106 and registers it in the circuit information database 106, and a circuit information display means 107 which displays the information of the circuit information database 106 on a display device 112. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a logic synthesis constraint generation device, and in particular, when designing a logic circuit of a semiconductor integrated circuit device, by detecting an error in a constraint condition of each synthesis unit before executing logic synthesis, The present invention relates to a logic synthesis constraint generation device for suppressing the necessity of re-execution of logic synthesis.

  Conventionally, in the logic circuit design, the logic circuit is divided into blocks of a certain circuit scale, and the logic circuit design is performed in parallel for each block in response to the problem of increase in the design man-hour accompanying the development of large-scale LSI To reduce the design time. In this way, when designing in units of blocks, delay information outside the block is given to the block port that becomes the boundary of the block for the path connected to the outside of each block, and this is used as a constraint for each block. A method is used in which logic synthesis is executed and finally all blocks are assembled into one LSI.

  In addition, due to advances in semiconductor miniaturization technology, functions that were previously configured with multiple LSIs can now be built on a single LSI called a system LSI. For the purpose of setting an optimum operation speed in units of functions, a plurality of types of clocks are supplied on one LSI.

  When multiple types of clocks are supplied in this way, the timing target is set when the chip is assembled after logic synthesis unless the external delay of each block port is correctly set for which clock. It becomes impossible to achieve. Therefore, when an error is mixed in the timing constraint for the block port, the error must be corrected and logic synthesis must be re-executed.

In order to prevent such re-execution of logic synthesis, a method for preventing an error from being mixed by automation has been proposed.
As an example of an automated means, by automatically creating constraints for block ports from the clock constraints and design data given to the top layer in consideration of the layout, it is possible to prevent the introduction of manual errors and to optimize There is one that creates a timing constraint (see, for example, Patent Document 1).

  In addition, when design data and timing constraints are input, if a design change or timing constraint changes, a script that re-synthesizes only the minimum range covered by the change is generated, thereby shortening the time for re-synthesis. (For example, refer to Patent Document 2).

  However, the one described in Patent Document 1 is based on the premise that the clock constraint given to the top layer is correct, and even if there is a missing clock constraint, the missing clock cannot be detected. Timing constraints are created in the absence of clock constraints. The timing constraint error due to this clock constraint omission becomes clear after the logic synthesis and after the analysis of the verification result, the logic synthesis must be re-executed.

In addition, the method described in Patent Document 2 aims to perform re-synthesis by modification with the minimum necessary execution time, and if an error is detected in the timing constraint after synthesis, an error is detected in the shortest time. Although it is possible to obtain a composite result after correction, it is not possible to prevent the error itself.
Japanese Patent Laid-Open No. 11-8309 JP 2000-172730 A

  An object of the present invention is to extract information on timing constraints from design data when creating a synthesis constraint in order to avoid re-execution of logic synthesis caused by an error in the logic synthesis constraint, and use the extracted information to The purpose is to make it possible to check for errors in constraints or to create and modify constraints.

  In order to solve the above-mentioned problem, the present invention according to claim 1, in a semiconductor integrated circuit design environment in which data is divided into hierarchies and synthesis is performed for each hierarchy, logic design data of the integrated circuit and synthesis hierarchy information are combined. Circuit information input means for inputting circuit information including, constraint input means for inputting constraint conditions for logic synthesis, circuit information input by the circuit information input means, and constraint conditions input by the constraint input means Circuit information database to be held, related clock extraction means for extracting a clock related to a block port from the information in the circuit information database and registering it in the circuit information database, and circuit information for displaying the information in the circuit information database on a display device Display means.

As a result, confirmation of the related clock information of the block port is facilitated by the logic design data, and it is possible to avoid creating timing constraints due to erroneous information.
According to a second aspect of the present invention, in the above circuit, the circuit information input means reads the logic design data and the synthesis hierarchy information and extracts the partial circuit information necessary for setting the constraint, thereby holding the circuit on the device It is configured so that the data amount of information can be reduced.

  As a result, the amount of data in the circuit information database can be reduced, the handling of a large-scale circuit can be performed, and the size of the circuit information database can be reduced. This has the effect of increasing the processing speed.

  According to the third aspect of the present invention, in the above description, the information on the circuit information and the constraint condition is used to check whether there is an error in the timing constraint of each block port or the setting is missing, and the result is registered in the circuit information database. Timing constraint check means is provided.

  As a result, the related clock information extracted by the related clock extracting unit and the timing constraint information input by the constraint input unit can be compared to confirm whether there is a setting error or missing setting. An error of an existing constraint can be easily confirmed before the execution of logic synthesis, and the number of steps for returning after synthesis can be reduced.

  According to a fourth aspect of the present invention, in the above, the information displayed by the circuit information display means is interactively set on the display device using an input device such as a keyboard or a mouse, and the setting contents are set in the circuit information. A timing constraint setting means for registering in the database is provided.

This makes it easy to set timing constraints using design data information, and can reduce the number of man-hours for creating constraints.
According to a fifth aspect of the present invention, in the apparatus according to the first or second aspect, the timing constraint checking means according to the third aspect and the timing constraint setting means according to the fourth aspect are provided. is there.

  This makes it easy to check and modify existing constraints, or to check constraints created interactively, prevent constraint errors and omissions, and reduce the number of man-hours for creating constraints and the amount of time required to go back after synthesis. it can.

The present invention according to claim 6 includes means for outputting the information displayed on the circuit information display means to a file.
This makes it possible to output the block port related clock information extracted from the design data or the check result of the existing constraints to a file, so that multiple people can check the information in parallel and analyze the constraint check results. Etc. can be shortened.

  According to the logic synthesis constraint generation apparatus of the present invention, in a logic design environment in which logic synthesis is executed in units of blocks and an LSI chip is assembled, the related clock of the block port can be extracted from the design data. It is possible to detect setting errors of related clocks due to errors, and it is possible to detect block ports for which timing constraints are not set. This can be avoided and has the effect of reducing the number of man-hours for backtracking.

  Further, according to the present invention, since there are an interactive constraint setting function and a function for displaying and outputting a constraint error check result, it is possible to easily modify and set the constraint and shorten the constraint creation time.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a configuration diagram of a logic synthesis constraint generation apparatus according to an embodiment of the present invention, and FIG. 2 is a process flow diagram for explaining the operation of the constraint generation apparatus of FIG. Note that the numbers given to the respective processes in FIG. 2 correspond to the numbers given to the respective components in FIG. 3 is a diagram for explaining the processing in the block of the related clock extracting means 108 in FIGS. 1 and 2, and FIG. 4 is a diagram for explaining the processing between the blocks in the related clock extracting means 108. FIG. 5 is a circuit information display example when the circuit information display means 107 of FIGS. 1 and 2 is displayed as a block diagram, and FIG. 6 is a circuit information display example when displayed as text.

  This constraint generation apparatus includes an RTL description circuit 101 as design data described in RTL that expresses a function at a register transfer level using HDL, a hierarchy designation file 102 describing a hierarchy as a synthesis unit, and this hierarchy A circuit information input unit 103 that extracts information of blocks as synthesis units from the RTL description circuit 101 by using data of the designated file 102, a constraint file 104 that describes timing constraints to be applied to clock constraints and block boundaries, The constraint input means 105 for inputting information from the constraint file 104, the circuit information database 106 for holding the information input by the circuit information input means 103 and the constraint input means 105, and the information of the circuit information database 106 are displayed on the display device. Circuit information display means 107 for displaying, and circuit information data Related clock extraction means 108 that automatically extracts a clock signal from information in the base 106 and registers it in the circuit information database 106 in association with each block port, and the block port obtained from the circuit information database 106 by this related clock extraction means 108 Constraint check means 109 for performing a matching check between the related clock information of the block and the related clock information of the block port set by the timing constraint input by the constraint input means 105 and registering the check result in the circuit information database 106, circuit information The constraint setting means 110 for directly editing the constraints on the display device using the information displayed on the display device 107 by the display means 107 and registering them in the circuit information database 106, and the constraint information set in the circuit information database 106 Extract and logical combination A constraint output unit 111 that outputs a file in a format that can be input by the system to the edited constraint file 114, and a display information output unit 112 that outputs the circuit information displayed on the display device by the circuit information display unit 107 to the circuit information file 113. It comprises.

  Next, the processing operation based on the above configuration will be described with reference to FIGS. First, the design data of the RTL description circuit 101 and the data of the hierarchy designation file 102 are input to the circuit information input means 103. The circuit information input means 103 reads data from the RTL description circuit 101 and the hierarchy designation file 102 and extracts partial circuit information related to timing constraints. The extracted circuit information is registered in the circuit information database 106.

  When extracting the partial circuit information, in order to reduce the amount of data on the circuit information database 106, a block and a block port are extracted from the synthesis hierarchy designated by the hierarchy designation file 102, and a signal connected to the block port is obtained. The first stage register counting from the block port is extracted. Also, the connection relationship between the extracted register and block port, the connection relationship between each block port, and the clock signal of each register are extracted and registered in the circuit information database 106 as the minimum necessary circuit information for setting a constraint. To do.

  As a method for determining a clock signal, for example, Verilog-RTL, it can be determined as a clock signal by recognizing a signal included in a sensitivity list of an always block. Specifically, when it is described as always (positioned sigA) {...}, sigA is recognized as a clock signal.

  Next, the data of the constraint file 104 is input by the constraint input means 105. The constraint input means 105 reads the constraint file 104 for logic synthesis, searches the circuit information database 106 for block ports for which constraints are set, and registers the constraint conditions in the circuit information database 106 as block port attributes.

  Here, the circuit information database 106 holds the circuit information extracted by the circuit information input means 103. The information to be held includes the block, the block port that becomes the boundary of each block, the first register counted from the block port, the clock signal of each register, the block port-register, and the block port-block port Connection information, a clock constraint input by the constraint input means 105, and a timing constraint for each block port.

  Next, related clock information of each block port is extracted by the related clock extracting means 108 and registered in the circuit information database 106. The related clock extraction means 108 first performs processing within a block, and then performs processing between blocks. The processing in the block will be described with reference to FIG. 3, and the description between the blocks will be described with reference to FIG.

  In the processing in the block, first, all registers on the circuit information database 106 are searched, and clock information is propagated to the block port for each register. Referring to FIG. 3, information on the clock signal ClockA 304 connected to the register RegA 303 is picked up from the circuit information database 106. Next, InputA301 and InputB302 which are block ports connected to RegA301 are found from the register-blockport connection information in the circuit information database 106, and ClockA304 is registered in the circuit information database 106 as internal clock information of these InputA301 and InputB302. This process is performed for all registers in all blocks. Reference numeral 305 denotes a register RegB, and reference numeral 306 denotes a block port OutputA.

  Next, in the process between blocks, the internal clock information is propagated to the connection destination block port using the connection information between the block port and the block port on the circuit information database 106 for all the block ports, and the related clock information. Register as The process will be described with reference to FIG. 4. As a connection destination of the block port Output A 401 of BLOCK 1, the block port Input A 402 of BLOCK 3 is searched using the connection information between block ports in the circuit information database 106, and the output A 401 's related clock information is output as the related clock information of Input A 402. Register internal clock information. This process is performed for all block ports. Similarly, the block port InputB404 of BLOCK3 is searched for as the connection destination of the block port OutputB402 of BLOCK2, and the internal clock information of OutputB403 is registered as related clock information of InputB404.

  Next, the constraint checking unit 109 in FIGS. 2 and 1 checks whether there is an error between the existing constraint and the related clock information of the block port extracted by the related clock extracting unit 108, and the result is obtained from the circuit information database 106. Register with. That is, the constraint check unit 109 compares the related clock information of the timing constraint of each block port input from the constraint input unit 105 to the circuit information database 106 and the related clock information extracted by the related clock extraction unit 108, and compares the related clock information. If a timing constraint is set with a clock other than the related clock extracted by the extraction means 108 as a related clock, the constraint is registered in the circuit information database 106 as an error. Further, when the restriction on the related clock extracted by the related clock extracting means 108 is not set, it is registered in the circuit information database 106 as a missing setting.

  Next, the timing constraint check result in the circuit information database 106 is displayed by the circuit information display means 107. That is, the circuit information display means 107 displays information registered in the circuit information database 106 on a display device, and a person using the device can interactively change the display method and display range. As a display method of the circuit information in the circuit information database 106, for example, a block port-block port or a block port-register connection relation is displayed by a block diagram as shown in FIG. It is possible to display connection relations. It is also possible to pay attention to a specific block and display related clock information of a block port of the block and preset timing constraints.

  Next, the circuit information displayed on the display device by the circuit information display means 107 is output to a file by the display information output means 112, and the timing constraint check result is confirmed by a plurality of persons.

  The display information output means 112 can also output the screen displayed on the display device by the circuit information display means 107, and outputs to the circuit information file 113 even a portion outside the display screen due to the display size. It is possible. In addition, when the displayed information is information in text format, it is possible to output in text format in addition to outputting the display screen.

  Next, a timing constraint is set by the constraint setting unit 110 for a block port in which the timing constraint found by the constraint check unit 109 is incorrect or missing. In other words, the constraint setting means 110 can interactively set constraints by using an input device such as a keyboard or a mouse on the display device. As a technique, the constraint setting means 110 manually inputs the related clocks of the respective block ports. And a method of calling and setting the related clock information extracted by the related clock extracting means 108. The set constraints are registered in the circuit information database 106, whereby the constraint check means 109 can reconfirm whether or not the set constraints are correct.

  Finally, the constraint information registered in the circuit information database 106 is output to the edited constraint file 114 by the constraint output unit 111, thereby completing the process.

  The logic synthesis constraint generation apparatus according to the present invention facilitates confirmation of related clock information of a block port from design data, can avoid creation of timing constraints due to erroneous information, and can be used for logic circuit design of a semiconductor integrated circuit device. In this case, a logic synthesis constraint generating device for detecting an error in a constraint condition of each synthesis unit before executing a logic synthesis, thereby preventing a forced re-execution of the logic synthesis due to an error in the constraint It is useful as such.

Configuration diagram of logic synthesis constraint generation apparatus according to an embodiment of the present invention FIG. 1 is a processing flowchart for explaining the operation of the logic synthesis constraint generation apparatus of FIG. The figure for demonstrating the process in the block of the related clock extraction means in FIG. 1 and FIG. The figure for demonstrating the process between the blocks of the related clock extraction means in FIG. 1 and FIG. The figure which shows the example of a circuit information display at the time of displaying with a block diagram in the circuit information display means of FIG. 1 and FIG. The figure which shows the example of a circuit information display at the time of displaying with a text in the circuit information display means of FIG. 1 and FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 RTL description circuit 102 Hierarchy designation file 103 Circuit information input means 104 Constraint file 105 Constraint file input means 106 Circuit information database 107 Circuit information display means 108 Related clock extraction means 109 Constraint check means 110 Constraint setting means

Claims (6)

In a semiconductor integrated circuit design environment in which data is divided into hierarchies and synthesized for each hierarchy, circuit information input means for inputting circuit information including logic design data of the integrated circuit and synthesis hierarchy information, and constraints for logic synthesis Constraint input means for inputting conditions, circuit information database for holding circuit information input by the circuit information input means and constraint conditions input by the constraint input means, and information on the block port from the information of this circuit information database A logic synthesis constraint generating apparatus comprising: a related clock extracting unit that extracts a related clock and registers it in the circuit information database; and a circuit information display unit that displays information of the circuit information database on a display device. The circuit information input means is configured to be able to reduce the data amount of the circuit information held on the device by reading the logic design data and the synthesis hierarchy information and extracting the partial circuit information necessary for setting the constraints. The logic synthesis constraint generating device according to claim 1. A timing constraint check means is provided for checking whether there is an error in a timing constraint of each block port or setting omission using circuit information and constraint condition information, and registering the result in a circuit information database. Item 3. The logic synthesis constraint generation device according to Item 1 or 2. Timing constraint setting means for interactively setting constraints on the display device using an input device such as a keyboard and a mouse for the information displayed by the circuit information display means and registering the setting contents in the circuit information database. 3. The logic synthesis constraint generation apparatus according to claim 1 or 2, characterized in that: A timing constraint check unit according to claim 3 and a timing constraint setting unit and a constraint output unit according to claim 4, wherein the timing constraint is interactively set using information obtained from the previously set constraint and circuit information. 3. The logic synthesis constraint generation apparatus according to claim 1, wherein the constraint is configured so that the constraint can be corrected. 6. The logic synthesis constraint generation apparatus according to claim 1, further comprising means for outputting the information displayed on the circuit information display means to a file.

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