JP2005122033A - Current generating circuit, electrooptical device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a current generating circuit which can generate an analog current of nonlinear characteristics to gradation data instructed by a linear shape with a small number of circuit elements and with a simple circuit configuration, and to provide an electrooptical device and an electronic apparatus using the current generating circuit. <P>SOLUTION: A digital-to-analog conversion circuit 25 is equipped with a first digital-to-analog conversion circuit section 26 which converts image digital data D 1 to D 4 (DD 1 to DD 4) to the output current (data signal) IDm of the linear characteristics which is an analog signal and a second digital-to-analog conversion circuit section 27. The first digital-to-analog conversion circuit section 26 and the second digital-to-analog conversion circuit section 27 are cascade connected and the output current of the first digital-to-analog conversion circuit section 26 is inputted as the reference current of the second digital-to-analog conversion circuit section 27. As a result, the nonlinear analog current can be inputted to the inputted image digital data D 1 to D 4 (DD 1 to DD 4). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a current generation circuit, an electro-optical device, and an electronic apparatus.

  A digital-analog converter circuit (DAC) that converts a digital signal into an analog signal is widely used in various electronic devices. For example, a DAC used in an electro-optical display device such as an organic electroluminescence display device uses a current DAC that converts a digital signal (gradation data) into an analog current value and supplies the analog current value to a pixel circuit. This type of current DAC forms a current mirror in which the β (gain coefficient) ratio of each transistor with a common gate connected is binary weighted, and the current flowing through each transistor is added to the analog signal with respect to the digital signal. A signal (analog current) was obtained.

  By the way, there is a case where a non-linear analog signal (current) is required for a digital signal depending on the application. For example, the electro-optical device has signal processing called γ (gamma) correction. This γ correction is performed for linearly-designated gradation data (digital signal) so that the luminance emitted at that gradation looks natural to human eyes. Signal processing for outputting an analog current having a non-linear characteristic (for example, exponential or logarithmic).

  However, the current DAC is a linear DAC, and an analog current having a non-linear characteristic cannot be generated with respect to grayscale data instructed linearly. Therefore, a signal processing circuit for γ correction has been used in order to generate an analog current having non-linear characteristics for the gradation data. This signal processing circuit is a complicated circuit with many circuit elements, and the circuit scale has been increased. As a result, it has been a serious problem in electro-optical devices that are required to be reduced in size and cost.

  The present invention has been made to solve the above-described problems, and its object is to provide a simple circuit configuration with a small number of circuit elements and an analog current having a non-linear characteristic with respect to linearly designated gradation data. It is an object of the present invention to provide a current generation circuit that can be generated by the above, an electro-optical device and an electronic apparatus using the current generation circuit.

  In order to solve the above problem, the current generation circuit of the present invention generates a plurality of first subcurrents based on a reference signal, and based on a first control signal from the first subcurrents. A first current adding circuit that adds the selected first subcurrents and outputs the first output current, and a plurality of second subcurrents are generated based on the first output current; And a second current adding circuit that adds the second subcurrent selected from the subcurrents based on the second control signal and outputs the second subcurrent as a second output current.

  According to the present invention, the first current adding circuit outputs a first output current proportional to the input first control signal, and the second current adding circuit is based on the first output current. In addition, a second output current proportional to the input second control signal is output. Therefore, an analog current output having non-linearity with respect to a digital input signal can be obtained with a simple circuit configuration with a small number of circuit elements without providing a complicated signal processing circuit. Therefore, the entire circuit can be reduced in size and the cost can be reduced.

In the current generation circuit of the present invention, the plurality of first subcurrents include those in which the respective current values are in a binary weighted relationship.
According to the present invention, the first subcurrent is weighted corresponding to each bit of the first control signal, so that the first current adding circuit has a linear characteristic with a small number of circuit elements and a simple circuit configuration. An analog current output having can be obtained. Therefore, the entire circuit can be reduced in size and the cost can be reduced.

In the current generation circuit of the present invention, the plurality of second subcurrents include those in which the respective current values are in a binary weighted relationship.
According to the present invention, the second sub-current is weighted corresponding to each bit of the second control signal, so that the second current adding circuit has a linear characteristic with a small number of circuit elements and a simple circuit configuration. An analog current output having can be obtained. Therefore, the entire circuit can be reduced in size and the cost can be reduced.

In the current generation circuit of the present invention, the first control signal and the second control signal are the same or have a corresponding relationship.
According to the present invention, it is possible to obtain the output of the same current generation circuit regardless of whether the first control signal and the second control signal are the same or in a corresponding relationship.

  The current generation circuit of the present invention further includes means for generating a third subcurrent having a predetermined ratio with respect to the first output current, and the third subcurrent with respect to the second output current. Is provided.

  According to the present invention, a third subcurrent having a predetermined ratio with respect to the first output current is generated, and the third subcurrent is added to the output of the second current adding circuit. Thus, the current generation circuit can obtain an analog current output having a wide range of nonlinearity. Therefore, an analog current output having a wide range of non-linearity with respect to a digital input signal can be obtained with a small number of circuit elements and a simple circuit configuration without providing a complicated signal processing circuit. Therefore, the entire circuit can be reduced in size and the cost can be reduced.

  The current generation circuit of the present invention includes a first reference voltage, a plurality of first transistors to which the first reference voltage is commonly applied to the gates, and a current output from the plurality of first transistors. A first combination circuit that generates a first output current by selectively adding based on a control signal of the first, and a second current based on the first output current. A reference circuit for generating a reference voltage, a plurality of second transistors to which the second reference voltage is commonly applied to the gates, and a current output from the plurality of second transistors as the second control signal. And a second combining means for generating a second output current by selectively adding based on the second current adding circuit.

  According to the present invention, the first current adding circuit selectively adds the currents output from the plurality of first transistors to which the first reference voltage is commonly applied to the gates based on the first control signal. Thus, the first output current is generated. The second current adder circuit generates a second reference voltage by the conversion circuit based on the first output current, and a plurality of second transistors to which the second reference voltage is commonly applied to the gates Is selectively added based on the second control signal to generate a second output current. Therefore, an analog current output having linear characteristics can be obtained with a simple configuration. Therefore, the entire circuit can be reduced in size and the cost can be reduced.

In the current generation circuit of the present invention, the conversion circuit includes a transistor whose gate and drain are electrically connected.
According to the present invention, the conversion circuit includes a transistor whose gate and drain are electrically connected. Therefore, current can be converted into voltage with a simple configuration.

In the current generating circuit of the present invention, the gain ratios of the plurality of first transistors are set to binary weighted values.
According to the present invention, by weighting the gain coefficient of the plurality of first transistors corresponding to each bit of the first control signal, the current generation circuit is linear with a small number of circuit elements and a simple circuit configuration. An analog current output having characteristics can be obtained. Therefore, the entire circuit can be reduced in size and the cost can be reduced.

In the current generation circuit of the present invention, the gain ratios of the plurality of second transistors are set to binary weighted values.
According to the present invention, by weighting the gain coefficients of the plurality of second transistors corresponding to the respective bits of the second control signal, the current generation circuit is linear with a small number of circuit elements and a simple circuit configuration. An analog current output having characteristics can be obtained. Therefore, the entire circuit can be reduced in size and the cost can be reduced.

In the current generation circuit of the present invention, the first transistor or the second transistor includes a parallel connection configuration of transistors having a predetermined gain.
According to the present invention, the first transistor or the second transistor is connected in parallel with a transistor having a predetermined gain, so that the current generation circuit has a small number of circuit elements and a simple circuit configuration. An analog current output having a linear characteristic can be obtained with high accuracy.

In the current generation circuit of the present invention, the first transistor or the second transistor includes a serial connection configuration of transistors having a predetermined gain.
According to this invention, the first transistor or the second transistor is connected in series with a transistor having a predetermined gain, so that the current generation circuit has a small number of circuit elements and a simple circuit configuration. An analog current output having a linear characteristic can be obtained with high accuracy.

In the current generation circuit of the present invention, the first control signal and the second control signal are the same or have a corresponding relationship.
According to the present invention, it is possible to obtain the output of the same current generation circuit regardless of whether the first control signal and the second control signal are the same or in a corresponding relationship.

  The current generation circuit of the present invention further includes a third transistor to which the second reference voltage is applied to the gate, and adds the current output from the third transistor to the second output current. Means.

  According to the present invention, by adding the current output from the third transistor to which the second reference voltage is applied to the gate to the second output current, the current generation circuit has a wide range of nonlinearity. An analog current output can be obtained. Therefore, an analog current output having a wide range of non-linearity with respect to a digital input signal can be obtained with a small number of circuit elements and a simple circuit configuration without providing a complicated signal processing circuit. Therefore, the entire apparatus can be reduced in size and the cost can be reduced.

  The current generation circuit according to the present invention includes a control unit that changes a value of the first output current, a current output from the plurality of second transistors, or a current output from the third transistor. Prepare.

  According to this invention, the control means changes the value of the first output current, the current output from the plurality of second transistors, or the current output from the third transistor. Therefore, an analog current output having a wider range of non-linearity with respect to a digital input signal can be obtained with a simple circuit configuration with a small number of circuit elements without providing a complicated signal processing circuit. Therefore, the entire apparatus can be reduced in size and the cost can be reduced.

The current generation circuit of the present invention further includes an adjusting unit for adjusting the amount of current change by the control unit.
According to this invention, the amount of current change by the control means is adjusted by the adjusting means. Therefore, an analog current output having a wider range of non-linearity with respect to a digital input signal can be obtained with a simple circuit configuration with a small number of circuit elements without providing a complicated signal processing circuit. Therefore, the entire apparatus can be reduced in size and the cost can be reduced.

  The electro-optical device of the present invention includes a plurality of scanning lines, a plurality of data lines, and a pixel having an electro-optical element provided corresponding to each intersection of the plurality of scanning lines and the plurality of data lines. A scanning line driving circuit for scanning the plurality of scanning lines, and a data line driving circuit for supplying an analog current to the corresponding pixel portion via the plurality of data lines, The drive circuit generates a plurality of first subcurrents based on a reference signal, adds a first subcurrent selected from the first subcurrents based on a first control signal, and adds a first subcurrent. And a plurality of second subcurrents are generated based on the first output current, and a second control signal is selected from the second subcurrents based on the second control signal. The second sub current selected in this step is added to produce the second output current. And a second current summing circuit.

  According to the present invention, the first current adding circuit outputs a first output current proportional to the input first control signal, and the second current adding circuit is based on the first output current. In addition, a second output current proportional to the input second control signal is output. Therefore, an analog current output having non-linearity with respect to a digital input signal can be obtained with a simple circuit configuration with a small number of circuit elements without providing a complicated signal processing circuit. Therefore, the entire circuit can be reduced in size and the cost can be reduced.

In the electro-optical device according to the aspect of the invention, the plurality of first subcurrents include those in which the respective current values are in a binary weighted relationship.
According to the present invention, the first subcurrent is weighted corresponding to each bit of the first control signal, so that the first current adding circuit has a linear characteristic with a small number of circuit elements and a simple circuit configuration. An analog current output having can be obtained. Therefore, the entire circuit can be reduced in size and the cost can be reduced.

In the electro-optical device according to the aspect of the invention, the plurality of second subcurrents include those in which each current value has a binary weighted relationship.
According to the present invention, the second sub-current is weighted corresponding to each bit of the second control signal, so that the second current adding circuit has a linear characteristic with a small number of circuit elements and a simple circuit configuration. An analog current output having can be obtained. Therefore, the entire circuit can be reduced in size and the cost can be reduced.

In the electro-optical device according to the aspect of the invention, the first control signal and the second control signal are the same or have a corresponding relationship.
According to the present invention, it is possible to obtain the output of the same current generation circuit regardless of whether the first control signal and the second control signal are the same or in a corresponding relationship.

  The electro-optical device of the present invention further includes means for generating a third subcurrent having a predetermined ratio with respect to the first output current, and the third subcurrent with respect to the second output current. Is provided.

  According to the present invention, a third subcurrent having a predetermined ratio with respect to the first output current is generated, and the third subcurrent is added to the output of the second current adding circuit. Thus, the current generation circuit can obtain an analog current output having a wide range of nonlinearity. Therefore, an analog current output having a wide range of non-linearity with respect to a digital input signal can be obtained with a small number of circuit elements and a simple circuit configuration without providing a complicated signal processing circuit. Therefore, the entire circuit can be reduced in size and the cost can be reduced.

  The electro-optical device of the present invention includes a plurality of scanning lines, a plurality of data lines, and a pixel having an electro-optical element provided corresponding to each intersection of the plurality of scanning lines and the plurality of data lines. A scanning line driving circuit for scanning the plurality of scanning lines, and a data line driving circuit for supplying an analog current to the corresponding pixel portion via the plurality of data lines, The driving circuit includes: a first reference voltage; a plurality of first transistors to which the first reference voltage is commonly applied to gates; and a current output from the plurality of first transistors as the first control signal. A first combining circuit that generates a first output current by selectively adding based on the first output current, and a second reference voltage based on the first output current. A conversion circuit to be generated, and the second reference A second output current is obtained by selectively adding a plurality of second transistors whose voltages are commonly applied to the gates and a current output from the plurality of second transistors based on the second control signal. A second current adding circuit including a second synthesizing unit.

  According to the present invention, the first current adding circuit selectively adds the currents output from the plurality of first transistors to which the first reference voltage is commonly applied to the gates based on the first control signal. Thus, the first output current is generated. The second current adder circuit generates a second reference voltage by the conversion circuit based on the first output current, and a plurality of second transistors to which the second reference voltage is commonly applied to the gates Is selectively added based on the second control signal to generate a second output current. Therefore, an analog current output having linear characteristics can be obtained with a simple configuration. Therefore, the entire circuit can be reduced in size and the cost can be reduced.

In the electro-optical device according to the aspect of the invention, the conversion circuit includes a transistor in which a gate and a drain are electrically connected.
According to the present invention, the conversion circuit includes a transistor whose gate and drain are electrically connected. Therefore, current can be converted into voltage with a simple configuration.

In the electro-optical device according to the aspect of the invention, the gain ratio of each of the plurality of first transistors is set to a binary weighted value.
According to the present invention, by weighting the gain coefficient of the plurality of first transistors corresponding to each bit of the first control signal, the current generation circuit is linear with a small number of circuit elements and a simple circuit configuration. An analog current output having characteristics can be obtained. Therefore, the entire circuit can be reduced in size and the cost can be reduced.

In the electro-optical device according to the aspect of the invention, the gain ratio of each of the plurality of second transistors is set to a binary weighted value.
According to the present invention, by weighting the gain coefficients of the plurality of second transistors corresponding to the respective bits of the second control signal, the current generation circuit is linear with a small number of circuit elements and a simple circuit configuration. An analog current output having characteristics can be obtained. Therefore, the entire circuit can be reduced in size and the cost can be reduced.

In the electro-optical device according to the aspect of the invention, the first transistor or the second transistor includes a parallel connection configuration of transistors having a predetermined gain.
According to the present invention, the first transistor or the second transistor is connected in parallel with a transistor having a predetermined gain, so that the current generation circuit has a small number of circuit elements and a simple circuit configuration. An analog current output having a linear characteristic can be obtained with high accuracy.

In the electro-optical device according to the aspect of the invention, the first transistor or the second transistor includes a serial connection configuration of transistors having a predetermined gain.
According to this invention, the first transistor or the second transistor is connected in series with a transistor having a predetermined gain, so that the current generation circuit has a small number of circuit elements and a simple circuit configuration. An analog current output having a linear characteristic can be obtained with high accuracy.

In the electro-optical device according to the aspect of the invention, the first control signal and the second control signal are the same or have a corresponding relationship.
According to the present invention, it is possible to obtain the output of the same current generation circuit regardless of whether the first control signal and the second control signal are the same or in a corresponding relationship.

  The electro-optical device of the present invention further includes a third transistor to which the second reference voltage is applied to a gate, and adds the current output from the third transistor to the second output current. Means.

  According to the present invention, by adding the current output from the third transistor to which the second reference voltage is applied to the gate to the second output current, the current generation circuit has a wide range of nonlinearity. An analog current output can be obtained. Therefore, an analog current output having a wide range of non-linearity with respect to a digital input signal can be obtained with a small number of circuit elements and a simple circuit configuration without providing a complicated signal processing circuit. Therefore, the entire apparatus can be reduced in size and the cost can be reduced.

  The electro-optical device according to the aspect of the invention includes a control unit that changes a value of the first output current, a current output from the plurality of second transistors, or a current output from the third transistor. Prepare.

  According to this invention, the control means changes the value of the first output current, the current output from the plurality of second transistors, or the current output from the third transistor. Therefore, an analog current output having a wider range of non-linearity with respect to a digital input signal can be obtained with a simple circuit configuration with a small number of circuit elements without providing a complicated signal processing circuit. Therefore, the entire apparatus can be reduced in size and the cost can be reduced.

The electro-optical device of the present invention further includes an adjusting unit for adjusting the amount of current change by the control unit.
According to this invention, the amount of current change by the control means is adjusted by the adjusting means. Therefore, an analog current output having a wider range of non-linearity with respect to a digital input signal can be obtained with a simple circuit configuration with a small number of circuit elements without providing a complicated signal processing circuit. Therefore, the entire apparatus can be reduced in size and the cost can be reduced.

In the electro-optical device according to the aspect of the invention, the electro-optical element is an organic electroluminescence element.
According to the present invention, an electro-optical device in which an electro-optical element is an organic electroluminescence element does not include a complicated signal processing circuit, and has a small number of circuit elements and a simple circuit configuration. An analog current output having nonlinearity can be obtained.

The gist of an electronic apparatus of the present invention is that it includes the above-described current generation circuit.
According to the present invention, an analog current output having non-linearity with respect to a digital input signal can be obtained with a small number of circuit elements and a simple circuit configuration without providing a complicated signal processing circuit.

The gist of an electronic apparatus of the present invention is to include the electro-optical device described above.
According to the present invention, an analog current output having non-linearity with respect to a digital input signal can be obtained with a small number of circuit elements and a simple circuit configuration without providing a complicated signal processing circuit.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block circuit diagram showing an electrical configuration of an organic electroluminescence display device using an organic electroluminescence element as an electro-optical device. FIG. 2 is a block circuit diagram showing a circuit configuration of the display panel unit 12. FIG. 3 is a circuit diagram showing an internal configuration of the pixel circuit 20.

  In FIG. 1, the organic electroluminescence display device 10 includes a signal generation circuit 11, a display panel unit 12, a scanning line driving circuit 13, and a data line driving circuit 14. The organic electroluminescence display device 10 in this embodiment is an active matrix driving method.

  The signal generation circuit 11, the scanning line driving circuit 13, and the data line driving circuit 14 of the organic electroluminescence display device 10 may be configured by independent electronic components. For example, each of the signal generation circuit 11, the scanning line driving circuit 13, and the data line driving circuit 14 may be configured by a one-chip semiconductor integrated circuit device. Further, all or part of the signal generation circuit 11, the scanning line driving circuit 13, and the data line driving circuit 14 may be configured by a programmable IC chip, and the function may be realized by software by a program written in the IC chip. Good.

  The signal generation circuit 11 receives a clock pulse CP and 4-bit image digital data D from an external device (not shown). The signal generation circuit 11 generates a vertical synchronization signal VSYNC for determining the timing for sequentially selecting the scanning lines Y1 to Yn (see FIG. 2) based on the clock pulse CP. Further, the signal generation circuit 11 generates a horizontal synchronization signal HSYNC for determining the timing of outputting the data signals ID1 to IDm to the corresponding data lines X1 to Xm (see FIG. 2) based on the clock pulse CP.

Then, the signal generation circuit 11 outputs the vertical synchronization signal VSYNC to the scanning line driving circuit 13 in synchronization with the image digital data D, and outputs the horizontal synchronization signal HSYNC to the data line driving circuit 14. Further, the signal generation circuit 11 outputs the image digital data D to the data line driving circuit 14.

  As shown in FIG. 2, the display panel unit 12 includes m data lines X1 to Xm (m is a natural number) extending along the column direction. The display panel unit 12 includes n scanning lines Y1 to Yn (n is a natural number) extending along the row direction. Here, it is assumed that the m data lines X1 to Xm are formed from left to right in FIG. 2 in the described order. Similarly, the n scanning lines Y1 to Yn are formed from top to bottom in FIG. 2 in the described order.

  The display panel unit 12 is provided with pixel circuits 20 as pixel units at positions corresponding to intersections of the data lines X1 to Xm and the scanning lines Y1 to Yn. Each of the pixel circuits 20 is connected to the data line driving circuit 14 via the corresponding data lines X1 to Xm. Each pixel circuit 20 is connected to the scanning line driving circuit 13 via the corresponding scanning lines Y1 to Yn. Each pixel circuit 20 is connected to m power supply lines Lm (m is a natural number) extending in the column direction. Accordingly, each pixel circuit 20 is supplied with the drive voltage Vdd via the corresponding power supply lines L1 to Lm.

  FIG. 3 is a circuit diagram showing an internal configuration of the pixel circuit 20 arranged corresponding to each intersection of the mth data line Xm and the nth scanning line Yn. The pixel circuit 20 includes four transistors, one capacitive element, and an organic electroluminescence element as one electro-optical element. More specifically, the pixel circuit 20 includes a drive transistor Qd, a first switching transistor Qsw1, a second switching transistor Qsw2, a third switching transistor Qsw3, a holding capacitor Co, and an organic electroluminescence element OLED. The drive transistor Qd is a P-type TFT, and the first, second, and third switching transistors Qsw1, Qsw2, and Qsw3 are N-type TFTs. An organic electroluminescence element (hereinafter referred to as an organic EL element) OLED as an electro-optical element is a light emitting element that emits light when its light emitting layer is made of an organic material and is supplied with a driving current Ioel.

  The source of the drive transistor Qd is connected to the mth power supply line Lm that supplies the drive voltage Vdd. The drain of the driving transistor Qd is connected to the drain of the first switching transistor Qsw1 and the source of the second switching transistor Qsw2.

  Further, the first electrode D01 of the holding capacitor Co is connected to the gate of the driving transistor Qd. The second electrode D02 of the holding capacitor Co is connected to the power supply line Lm. A second switching transistor Qsw2 is connected between the gate and drain of the driving transistor Qd.

  The source of the first switching transistor Qsw1 is connected to the data line Xm. The gate of the first switching transistor Qsw1 is connected to the first sub-scanning line Yn1 constituting the scanning line Yn together with the gate of the second switching transistor Qsw2. The drain of the first switching transistor Qsw1 is connected to the drain of the third switching transistor Qsw3 together with the source of the second switching transistor Qsw2. The source of the third switching transistor Qsw3 is connected to the anode E1 of the organic EL element OLED. The cathode E2 of the organic EL element OLED is grounded. The gate of the third switching transistor Qsw3 is connected to the second sub-scanning line Yn2 that constitutes the scanning line Yn. That is, in the present embodiment, the scanning line Yn is composed of the first sub-scanning line Yn1 and the second sub-scanning line Yn2.

  In the present embodiment, the pixel circuit 20 includes the driving transistor Qd, the first switching transistor Qsw1, the second switching transistor Qsw2, the third switching transistor Qsw3, the holding capacitor Co, and the organic EL element. However, the present invention is not limited to this and may be changed as appropriate. Further, the channel type of the drive transistor Qd, the first switching transistor Qsw1, the second switching transistor Qsw2, and the third switching transistor Qsw3 is not limited to this, and a P or N channel type is appropriately selected. It is possible to select.

  The scanning line driving circuit 13 selects one scanning line among the n scanning lines Yn provided in the display panel unit 12 based on the vertical synchronization signal VSYNC from the signal generation circuit 11, and Scan signals SC1 to SCn (n is a natural number) corresponding to the selected scan line are output. More specifically, the scanning line driving circuit 13 includes first and second switching transistors connected to the first sub-scanning line Yn1 via the first sub-scanning line Yn1 based on the vertical synchronization signal VSYNC. First sub-scan signals SC11, SC21, SC31,..., SCn1 for controlling the on / off states of Qsw1 and Qsw2 are generated. The scanning line driving circuit 13 turns on / off each third switching transistor Qsw3 connected to the second sub-scanning line Yn2 via the second sub-scanning line Yn2 based on the vertical synchronization signal VSYNC. Second sub-scan signals SC12, SC22, SC32,..., SCn2 for controlling the off state are generated. When the first sub-scanning signals SC11 to SCn1 are at the H level, the second sub-scanning signals SC12 to SCn2 are at the L level, and the second after the first sub-scanning signals SC11 to SCn1 are at the L level. The sub-scan signals SC12 to SCn2 are at the H level. Then, after the second sub-scanning signals SC12 to SCn2 become L level again, the first sub-scanning signals SC11 to SCn1 become H level.

  The first sub-scan signals SC11 to SCn1 and the second sub-scan signals SC12 to SCn2 constitute scan signals SC1 to SCn. With these scanning signals SC1 to SCn, the timing of writing charges corresponding to the analog current signal (data signal) output from the data line driving circuit 14 to the holding capacitor Co of the pixel circuit 20 on the selected scanning line and the organic EL The timing at which the element OLED emits light is controlled.

  The image line data D and the horizontal synchronization signal HSYNC are input from the signal generation circuit 11 to the data line driving circuit 14. The data line driving circuit 14 includes a plurality of digital / analog conversion circuits 25 as shown in FIG. Each of the plurality of digital / analog conversion circuits 25 is connected to a corresponding data line X1, X2,. Each digital / analog conversion circuit 25 receives 4-bit image digital data D output from the signal generation circuit 11. Each digital / analog conversion circuit 25 creates data signals ID1, ID2,..., IDm, which are analog current signals of a level corresponding to the magnitude of the input image digital data D. Then, the digital / analog conversion circuit 25 corresponds to the data lines X1, X2,..., Xm corresponding to the data signals ID1, ID2,..., IDm according to the horizontal synchronization signal HSYNC output from the signal generation circuit 11. Are simultaneously output to the respective pixel circuits 20 via.

In each pixel circuit 20 on the first sub-scanning lines Y11 to Yn1 selected by the first sub-scanning signals SC11 to SCn1 sequentially output from the scanning line driving circuit 13, the first switching is performed. The transistor Qsw1 and the second switching transistor Qsw2 are each set to an on state. The drive transistor Qd functions as a diode whose gate and drain are connected to each other. As a result, the data signals ID1 to IDm based on the respective digital / analog conversion circuits 25 flow through the paths of the drive transistor Qd, the first switching transistor Qsw1, and the data lines X1 to Xm, respectively, and at that time, the drive transistor Qd The electric charge corresponding to the potential of the gate is accumulated in the holding capacitor Co.

  When the selected first sub-scanning lines Y11 to Yn1 are not selected, the first switching transistor Qsw1 and the second switching transistor Qsw2 are set to the off state, but the charge in the storage capacitor Co Therefore, the gate potential of the drive transistor Qd is held at the voltage when the data signal IDm flows. When the first sub-scanning lines Y11 to Yn1 are not selected, the second sub-scanning lines Y12 to Yn2 corresponding to the non-selected first sub-scanning lines Y11 to Yn1 are the second sub-scanning. It is selected by signals SC12 to SCn2. For this reason, the third switching transistor Qsw3 is set to an on state, and a drive current Ioel having a magnitude corresponding to the gate voltage flows between the source and drain of the drive transistor Qd. Specifically, the drive current Ioel flows through a path of the power supply lines L1 to Lm, the drive transistor Qd, the third switching transistor Qsw3, and the organic EL element OLED. Thus, the organic EL element OLED emits light with a luminance gradation corresponding to the drive current Ioel (data signal value). Thereafter, the scanning lines Y1, Y2,..., Yn are sequentially selected to supply the data signals ID1, ID2,..., IDm to the pixel circuits 20, and the organic EL elements OLED drive current Ioel. It emits light with a brightness corresponding to the current level. In this way, an image corresponding to the image digital data D is displayed on the display panel unit 12.

FIG. 4 is a diagram for explaining the internal configuration of the digital-analog conversion circuit 25 in the present embodiment.
The digital / analog conversion circuit 25 includes a first digital / analog conversion circuit unit 26 and a second digital / analog conversion circuit unit 27. In this embodiment, the first digital / analog conversion circuit unit 26 and the second digital / analog conversion circuit unit 27 convert 4-bit image digital data D (D1 to D4) into an analog current having a linear characteristic. This is a current output type digital-analog conversion circuit. The first digital / analog conversion circuit unit 26 and the second digital / analog conversion circuit unit 27 include a reference current generation unit and a conversion unit, respectively, and output current of the first digital / analog conversion circuit unit 26. Is input to the reference current generation unit of the second digital / analog conversion circuit unit 27.

  Specifically, the first digital / analog conversion circuit unit 26 includes a reference current generation unit 26a and a conversion unit 26b. The reference current generation unit 26a includes a conversion transistor Qc1 and a reference current source IR. The conversion unit 26b includes first to fourth switching transistors Qsw11 to Qsw14 and first to fourth driving transistors Qd11 to Qd14. The conversion unit 26b includes first to fourth current lines La11 to La14 and first to fourth digital signal lines Ld11 to Ld14.

  The first to fourth switching transistors Qsw11 to Qsw14 are transistors that function as switching elements that are on / off controlled in accordance with 4-bit image digital data D1 to D4.

The source of the conversion transistor Qc1 is connected to the drive voltage Vdd. The drain of the conversion transistor Qc1 is connected to the reference current source IR. The conversion transistor Qc1 is diode-connected, and the gate of the conversion transistor Qc1 is connected to the common gate line GL1. The common gate line GL1 is connected to the gates of the first to fourth drive transistors Qd11 to Qd14. That is, the conversion transistor Qc1 and each of the first to fourth drive transistors Qd11 to Qd14 form a current mirror circuit. The sources of the first to fourth drive transistors Qd11 to Qd14 are connected to the power supply line VL1 for supplying the drive voltage Vdd, and the drains of the first to fourth drive transistors Qd11 to Qd14 are connected to the first to fourth current lines La11 to Lad arranged in parallel. Each is connected to La14. The first to fourth current lines La11 to La14 are connected to the drains of the corresponding first to fourth switching transistors Qsw11 to Qsw14, respectively.

  The first to fourth switching transistors Qsw11 to Qsw14 have their gates connected to the corresponding first to fourth digital signal lines Ld11 to Ld14, respectively. The first to fourth digital signal lines Ld11 to Ld14 correspond to the respective bits of the image digital data D1 to D4 input from the signal generation circuit 11. The sources of the first to fourth switching transistors Qsw11 to Qsw14 are connected to the output current line Lo1.

  In the example of FIG. 4, the conversion transistor Qc1, the first to fourth drive transistors Qd11 to Qd14 are P-channel transistors, and the first to fourth switching transistors Qsw11 to Qsw14 are N-channel transistors.

  Here, the ratio of the gain coefficient β of the first to fourth drive transistors Qd11 to Qd14 is set to 1: 2: 4: 8. Further, the gain coefficient β of the conversion transistor Qc1 is set equal to that of the first drive transistor Qd11. Here, the gain coefficient β is defined by β = M × β0 = (μ × C × W / L), where M is a relative value, β0 is a predetermined constant, μ is carrier mobility, C is gate capacitance, W is the channel width and L is the channel length. The gain coefficients β of the first to fourth drive transistors Qd11 to Qd14 are respectively set to values associated with the weights of the respective bits of the image digital data D1 to D4. For example, the least significant bit D1 of the image digital data is supplied to the first switching transistor Qsw11 connected to the first driving transistor Qd11 having the smallest gain coefficient β. The most significant bit D4 of the image digital data is supplied to the fourth switching transistor Qsw14 connected to the fourth drive transistor Qd14 having the largest gain coefficient β.

  Further, since the current drive capability of the transistor is proportional to the gain coefficient β, the ratio of the current drive capabilities of the conversion transistor Qc1 and the first to fourth drive transistors Qd11 to Qd14 is 1: 1: 2: 4: 8. . Therefore, the current level ratio of the first to fourth analog currents I11, I12, I13, and I14 flowing through the first to fourth current lines La11, La12, La13, and La14 is 1: 2: 4: 8. Further, the current level ratio between the first reference current Iref and the first analog current I11 flowing through the first current line La11 is 1: 1.

  When the first reference current Iref is input to the first digital / analog conversion circuit unit 26, the first reference current Iref flows through the conversion transistor Qc1. When the 4-bit image digital data D is input from the signal generation circuit 11, the first to fourth switching transistors Qsw11 to Qsw14 are turned on based on the image digital data D. The first to fourth current lines La11 to La14 connected to the first to fourth switching transistors Qsw11 to Qsw14 correspond to the current driving capability of the first to fourth driving transistors Qd11 to Qd14, that is, A binary weighted current flows. The total sum of the currents flowing through the current lines is proportional to the input image digital data D1 to D4, and the output current line Lo1 has an output current Iout1 binary-weighted with respect to the first reference current Iref. And output to the reference current generation unit of the second digital / analog conversion circuit unit 27. The output current Iout1 has the following relationship.

Iout1 = (1 × D1 + 2 × D2 + 4 × D3 + 8 × D4) × Iref
In the second digital / analog conversion circuit unit 27, the reference current generation unit 27a includes a conversion transistor Qc2. The converter 27b includes first to fourth switching transistors Qsw21 to Qsw24 and first to fourth driving transistors Qd21 to Qd.
24. The second digital / analog conversion circuit unit 27 includes first to fourth current lines La21 to La24 and first to fourth digital signal lines Ld21 to Ld24.

  The first to fourth switching transistors Qsw21 to Qsw24 are transistors that function as switching elements that are ON / OFF controlled according to 4-bit image digital data D (DD1 to DD4). Here, the image digital data DD1 to DD4 are the same signals as the image digital data D1 to D4 in the present embodiment, and are input through a buffer (not shown) provided in the data line driving circuit 14, for example. For example, the image digital data D1 to D4 are held by holding means such as a latch circuit (not shown) provided in the data line driving circuit 14, and the image digital data DD1 to DD4 are different in timing from the image digital data D1 to D4. May be input to the second digital / analog conversion circuit unit 27.

  The drain of the conversion transistor Qc2 is connected to the output current line Lo1 that is the output of the first digital / analog conversion circuit section 26, and the source thereof is grounded. The conversion transistor Qc2 is diode-connected, and the gate of the conversion transistor Qc2 is connected to the common gate line GL2. The common gate line GL2 is connected to the gates of the first to fourth drive transistors Qd21 to Qd24. That is, the conversion transistor Qc2 and each of the first to fourth driving transistors Qd21 to Qd24 form a current mirror circuit. The sources of the first to fourth drive transistors Qd21 to Qd24 are grounded, and the drains thereof are connected to first to fourth current lines La21 to La24 arranged in parallel, respectively. The first to fourth current lines La21 to La24 are connected to the sources of the corresponding first to fourth switching transistors Qsw21 to Qsw24, respectively.

  The first to fourth switching transistors Qsw21 to Qsw24 have their gates connected to the corresponding first to fourth digital signal lines Ld21 to Ld24, respectively. The first to fourth digital signal lines Ld21 to Ld24 correspond to each bit of the image digital data DD1 to DD4 input from the signal generation circuit 11. The drains of the first to fourth switching transistors Qsw21 to Qsw24 are connected to the output line Xm. The first to fourth switching transistors Qsw21 to Qsw24 are transistors that function as switching elements that are ON / OFF controlled according to the image digital data DD1 to DD4.

  In the example of FIG. 4, the conversion transistor Qc2, the first to fourth drive transistors Qd21 to Qd24, and the first to fourth switching transistors Qsw21 to Qsw24 are N-channel type.

  Here, the ratio of the gain coefficient β of the first to fourth drive transistors Qd21 to Qd24 is the same as the gain coefficient β of the first to fourth drive transistors Qd21 to Qd24 of the first digital-analog converter circuit unit 26. And 1: 2: 4: 8. That is, the gain coefficient β of the first to fourth drive transistors Qd21 to Qd24 is set to a value associated with the weight of each bit of the image digital data DD1 to DD4. Further, the gain coefficient β of the conversion transistor Qc2 is set equal to that of the first drive transistor Qd21. Therefore, the ratio of the current drive capabilities of the conversion transistor Qc2 and the first to fourth drive transistors Qd21 to Qd24 is 1: 1: 2: 4: 8.

Next, the first to fourth analog currents I21 flowing in the first to fourth current lines La21, La22, La23, La24 of the second digital / analog conversion circuit unit 27, respectively.
, I22, I23, I24 are proportional to the respective gain coefficients β. Therefore, the current level ratio of the first to fourth analog currents I21, I22, I23, and I24 flowing through the first to fourth current lines La21, La22, La23, and La24 is 1: 2: 4: 8. Further, the current level ratio between the second reference current and the first analog current I21 flowing through the first current line La21 is 1: 1.

  When the output current Iout1 is input as the second reference current to the second digital / analog conversion circuit unit 27, the output current Iout1 flows through the conversion transistor Qc2. When 4-bit image digital data DD is input from the signal generation circuit 11, the first to fourth drive transistors Qd21 to Qd21 are connected to the current lines of the switching transistors that are turned on based on the image digital data DD. A current corresponding to the driving capability of Qd24, that is, a binary weighted current flows. The total sum of the currents flowing through the current lines is proportional to the input image digital data DD1 to DD4, and the second reference current, that is, the output current Iout1 of the first digital / analog conversion circuit unit 26 is further increased to 2. The progressively weighted output current is output as the data signal IDm. In the present embodiment, since the image digital data DD1 to DD4 are the same signals as the image digital data D1 to D4, if the image digital data DD1 to DD4 are the image digital data D1 to D4, the output current (data signal) IDm is as follows. It becomes the relationship. Note that the output current (data signal) IDm is proportional to only the size of the image digital data D1 to D4 (DD1 to DD4) and does not depend on the timing thereof, so the image digital data DD1 to DD4 and the image digital data D1 to D4 Even when the timings are different, the following relationship holds.

IDm = (1 × D1 + 2 × D2 + 4 × D3 + 8 × D4) × Iout1
= (1 × D1 + 2 × D2 + 4 × D3 + 8 × D4) ² × Iref
That is, an output current (data signal) IDm that is a square analog current output is obtained with respect to the input image digital data D1 to D4 (DD1 to DD4). Therefore, γ correction in the display panel unit 12 can be approximately realized.

  Note that the reference signal described in the claims corresponds to, for example, the first reference current Iref in the present embodiment. The first subcurrent described in the claims corresponds to, for example, the first to fourth analog currents I11, I12, I13, and I14 in the present embodiment. The first control signal described in the claims corresponds to, for example, 4-bit image digital data D (D1 to D4) in the present embodiment. Further, the first current adding circuit described in the claims corresponds to, for example, the first digital / analog conversion circuit unit 26 in the present embodiment. Further, the first output current described in the claims corresponds to, for example, Iout1 in the present embodiment. Also, the second subcurrent described in the claims corresponds to, for example, the first to fourth analog currents I21, I22, I23, and I24 in the present embodiment. The second control signal described in the claims corresponds to, for example, 4-bit image digital data DD (DD1 to DD4) in the present embodiment. Furthermore, the second current adding circuit described in the claims corresponds to, for example, the second digital / analog conversion circuit unit 27 in the present embodiment. Further, the second output current described in the claims corresponds to, for example, IDm in the present embodiment.

  Further, the first reference voltage described in the claims corresponds to, for example, the gate voltage of the conversion transistor Qc1 in the present embodiment. Further, the first transistor described in the claims corresponds to, for example, the first to fourth drive transistors Qd11 to Qd14 in the present embodiment. Moreover, the 1st synthetic | combination means described in a claim respond | corresponds to the output current line Lo1 in this embodiment, for example.

  Further, the second reference voltage described in the claims corresponds to, for example, the gate voltage of the conversion transistor Qc2 in the present embodiment. The conversion circuit described in the claims corresponds to, for example, the conversion transistor Qc2 in the present embodiment. The second transistor described in the claims corresponds to, for example, the first to fourth drive transistors Qd21 to Qd24 in the present embodiment. Further, the second synthesizing means described in the claims corresponds to, for example, the output line Xm in the present embodiment.

  Further, the current generation circuit described in the claims corresponds to, for example, the digital / analog conversion circuit 25 in the present embodiment. Furthermore, the electro-optical device described in the claims corresponds to, for example, the organic electroluminescence display device 10 in the present embodiment.

According to the above embodiment, the following effects can be obtained.
(1) In the embodiment described above, the current output type digital-analog conversion circuit 25 provided in the data line driving circuit 14 includes the first digital-analog conversion circuit unit 26 having linear characteristics and the second digital having linear characteristics. An analog conversion circuit unit 27 is provided. The output current of the first digital / analog conversion circuit unit 26 is input to the reference current generation unit of the second digital / analog conversion circuit unit 27.

  As a result, an output current Iout1 obtained by binary weighting the first reference current Iref by the first digital / analog conversion circuit unit 26 is used as the second reference current, and the second reference current is converted into the second digital / analog conversion. An analog current further weighted in binary by the circuit unit 27 is output as an output current (data signal) IDm. Therefore, a square analog current output can be obtained for the input image digital data D1 to D4 (DD1 to DD4).

(2) In the above embodiment, the input digital image data D1 can be obtained simply by connecting the first digital / analog conversion circuit section 26 having linear characteristics and the second digital / analog conversion circuit section 27 having linear characteristics in series. Analog current output having a square characteristic with respect to ˜D4 (DD1 to DD4) was obtained. Therefore, an analog current having non-linear characteristics can be generated with a small number of circuit elements and a simple circuit configuration with respect to gradation data that is linearly designated without a special signal processing circuit. Therefore, the entire apparatus can be reduced in size and the cost can be reduced.
(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. In this embodiment, adjustment means 28 is added to the digital / analog converter circuit 25 described in the first embodiment, and fixed resistors R1 to R5, a variable resistor R6, a second resistor are added to the second digital / analog converter circuit unit 27. The difference from the first embodiment is that five drive transistors Qd25 and a fifth current line La25 are added. In the following embodiments, the same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 5, the digital / analog conversion circuit 25 includes an adjusting unit 28. The adjusting means 28 is a means for adjusting the resistance value of the variable resistor R6, and its output is connected to the variable resistor R6. The second digital / analog conversion circuit unit 27 includes fixed resistors R1 to R5, a variable resistor R6, a conversion transistor Qc2, first to fourth switching transistors Qsw21 to Qsw24, and first to fifth drive transistors Qd21 to Qd25. It has. The second digital / analog conversion circuit unit 27 includes first to fifth current lines La21 to La25 and first to fourth digital signal lines Ld21 to Ld24.

The fixed resistor R1 is connected between the output current line Lo1 of the first digital / analog conversion circuit section 26 and the drain of the conversion transistor Qc2. The source of the conversion transistor Qc2 is grounded. The conversion transistor Qc2 is diode-connected, and the gate of the conversion transistor Qc2 is connected to the common gate line GL2. The common gate line GL2 is connected to the gates of the first to fifth drive transistors Qd21 to Qd25. That is, the conversion transistor Qc2 and each of the first to fifth driving transistors Qd21 to Qd25 constitute a current mirror circuit. The sources of the first to fifth drive transistors Qd21 to Qd25 are grounded, and the drains are connected to the first to fifth current lines La21 to La25 arranged in parallel, respectively. The first to fourth current lines La21 to La24 are connected to the sources of the corresponding first to fourth switching transistors Qsw21 to Qsw24, respectively. Fixed resistors R <b> 2 to R <b> 5 are connected between the drains of the first to fourth switching transistors Qsw <b> 21 to Qsw <b> 24 and the output line Xm of the second digital / analog conversion circuit unit 27. A variable resistor R6 is connected between the drain of the fifth drive transistor Qd25 and the output line Xm. In the present embodiment, the variable resistor R6 is set to have a resistance value regardless of the image digital data DD in the present embodiment. Set the resistance value to.

  Here, the ratio of the gain coefficient β of the fifth drive transistor Qd25 is set to the same value as the gain coefficient β of the first drive transistor Qd21, and the current drive capability of the conversion transistor Qc2 and the fifth drive transistor Qd25. The ratio is 1: 1. That is, when the resistance value of the fixed resistor R1 and the resistance value of the variable resistor R6 are equal, the output current Iout1 that flows as the second reference current and the fifth analog current I25 that flows in the fifth current line La25 have the same value. The fifth analog current I25 flowing through the fifth current line La25 has the following relationship.

I25 = (R1 / R6) × Iout1
That is, the fifth analog current I25 flowing through the fifth current line La25 increases as the variable resistance R6 is decreased with respect to the fixed resistance R1. If the fixed resistors R2 to R5 have negligible resistance values with respect to the on-resistances of the first to fourth drive transistors Qd21 to Qd24, the fixed resistors R2 to R5 are the first to fourth drive transistors. The current value flowing through Qd21 to Qd24 is not limited. The sum of the currents flowing through the first to fourth current lines La21 to La24 is (1 × D1 + 2 × D2 + 4 × D3 + 8 × D4) when the image digital data DD is the image digital data D as in the first embodiment. × Iout1.

  Accordingly, the output current (data signal) IDm of the second digital / analog conversion circuit unit 27 has the following relationship when the image digital data DD is the image digital data D as in the first embodiment.

IDm = (1 × D1 + 2 × D2 + 4 × D3 + 8 × D4) × Iout1 + I25
= {(1 × D1 + 2 × D2 + 4 × D3 + 8 × D4) ² + (R1 / R6)
× (1 × D1 + 2 × D2 + 4 × D3 + 8 × D4)} × Iref
That is, non-linear analog current output is possible for the input image digital data D1 to D4 (DD1 to DD4). Furthermore, the slope of the characteristic of the output current (data signal) IDm can be changed by changing the resistance value of the variable resistor R6. In other words, when the variable resistor R6 is decreased with respect to the fixed resistor R1, the fifth analog current I25 flowing through the fifth current line La25 increases, and thereby the slope of the output current (data signal) IDm is suddenly increased. can do. When the variable resistor R6 is increased with respect to the fixed resistor R1, the fifth analog current I25 flowing through the fifth current line La25 decreases, and thereby the inclination of the output current (data signal) IDm is relaxed. be able to. Therefore, it is possible to obtain not only the square of the image digital data D1 to D4 (DD1 to DD4) but also an output having a wider range of nonlinearity, and approximately realizes γ correction in the display panel unit 12. can do.

  Note that the third subcurrent described in the claims corresponds to, for example, the fifth analog current I25 in the present embodiment. The third transistor recited in the claims corresponds to, for example, the fifth drive transistor Qd25 in the present embodiment. The control means described in the claims corresponds to, for example, the variable resistor R6 in the present embodiment. Furthermore, the adjusting means described in the claims corresponds to the adjusting means 28 in the present embodiment, for example.

According to the above embodiment, the following effects can be obtained.
(1) In the above embodiment, the adjustment means 28 is added to the digital / analog conversion circuit 25, the fixed resistors R1 to R5, the variable resistor R6, and the fifth drive transistor Qd25 are added to the second digital / analog conversion circuit unit 27. A fifth current line La25 was added. And the value of the current flowing through the fifth current line La25 can be varied by changing the value of the variable resistor R6. Thereby, it is possible to obtain an analog current having not only a square nonlinear characteristic but also a wider range of nonlinearity without providing a special signal processing circuit.

(2) In the above embodiment, the first digital / analog conversion circuit unit 26 having linear characteristics and the second digital / analog conversion circuit unit 27 having linear characteristics are connected in series. Then, the input digital image data D1 to D4 (DD1 to DD4) is squared by simply changing the value of the variable resistor R6 provided in the second digital / analog conversion circuit unit 27 by the adjusting means 28. In addition to nonlinear characteristics, analog currents of a wider range of nonlinear characteristics can be generated with a small number of circuit elements and with a simple circuit configuration. Therefore, the entire apparatus can be reduced in size and the cost can be reduced.
(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIG. This embodiment is different from the first embodiment in that an adjusting unit 28 is added to the digital-analog converter circuit 25 described in the first embodiment. In the present embodiment, the second digital-analog conversion circuit unit 27 described in the first embodiment includes fifth to seventh drive transistors Qda, Qdb, Qdc, and fifth to seventh current lines Laa, Lab. , Lac, and fifth to seventh switching transistors Qswa, Qswb, and Qswc are different from the first embodiment. In the following embodiments, the same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 6, the digital / analog conversion circuit 25 includes an adjusting unit 28. The adjusting means 28 is means for selectively turning on the fifth to seventh switching transistors Qswa, Qswb and Qswc, and the output thereof is the gates of the fifth to seventh switching transistors Qswa, Qswb and Qswc. It is connected to the. The second digital / analog conversion circuit unit 27 includes a conversion transistor Qc2, first to seventh switching transistors Qsw21 to Qsw24, Qswa, Qswb, Qswc and first to seventh drive transistors Qd21 to Qd24, Qda, Qdb, Qdc. The second digital / analog conversion circuit unit 27 includes first to seventh current lines La21 to La24, Laa, Lab, and Lac and first to fourth digital signal lines Ld21 to Ld24.

The gates of the fifth to seventh drive transistors Qda, Qdb, Qdc are connected to the common gate line GL2, and the sources thereof are grounded. The drains of the fifth to seventh drive transistors Qda, Qdb, and Qdc are connected to the fifth to seventh current lines Laa, Lab, and Lac, respectively. The fifth to seventh current lines Laa, Lab, and Lac are connected to the sources of the fifth to seventh switching transistors Qswa, Qswb, and Qswc, respectively. The fifth to seventh switching transistors Qswa, Qswb,
The drain of Qswc is connected to the output line Xm, and digital signals Da, Db, Dc are input from the adjusting means 28 to the gates, respectively. In this embodiment, the digital signals Da, Db, and Dc selectively turn on any one of the fifth to seventh switching transistors Qswa, Qswb, and Qswc regardless of the image digital data D (DD). It is a signal to make. For example, when the digital signal Da is at H level, the fifth switching transistor Qswa is turned on. On the other hand, the digital signals Da and Db become L level, and the sixth and seventh switching transistors Qswb and Qswc are turned off.

  Here, the ratios of the gain coefficients β of the first drive transistor Qd21 and the fifth to seventh drive transistors Qda, Qdb, and Qdc are different from each other, and are set to 1: a: b: c. Therefore, the ratio of the current drive capabilities of the conversion transistor Qc2 and the fifth to seventh drive transistors Qda, Qdb, Qdc is 1: a: b: c. The fifth to seventh switching transistors Qswa, Qswb, and Qswc receive any one of the fifth to seventh analog currents Ia, Ib, and Ic that flow through the fifth to seventh current lines Laa, Lab, and Lac. In order to selectively turn on, if the selected one current is Ik and the current drive capability ratio is K times, Ik has the following relationship.

Ik = K × Iout1 (K is one of a, b, and c)
Further, the sum of the currents flowing through the first to fourth current lines La21 to La24 is (1 × D1 + 2 × D2 + 4 × D3 + 8 × D4) × Iout1 as in the first embodiment.

Accordingly, the output current (data signal) IDm of the second digital / analog conversion circuit unit 27 has the following relationship when the image digital data DD is the image digital data D as in the first embodiment.
IDm = (1 × D1 + 2 × D2 + 4 × D3 + 8 × D4) × Iout1 + K × Iout1
= {(1 × D1 + 2 × D2 + 4 × D3 + 8 × D4) ²
+ K × (1 × D1 + 2 × D2 + 4 × D3 + 8 × D4)} × Iref
That is, non-linear analog current output is possible for the input image digital data D1 to D4 (DD1 to DD4). Further, by selecting any one of the fifth to seventh drive transistors Qda, Qdb, and Qdc, the slope of the analog current output characteristic can be changed. For example, if the ratio of the gain coefficient β is a <b <c, the slope of the output current (data signal) IDm can be made steep in the order of the fifth to seventh drive transistors Qda, Qdb, Qdc. . Therefore, an output having a wider range of nonlinearity can be obtained, and γ correction in the display panel unit 12 can be approximately realized.

  The third subcurrent described in the claims corresponds to, for example, the fifth to seventh analog currents Ia, Ib, and Ic in the present embodiment. Further, the third transistor described in the claims corresponds to, for example, the fifth to seventh drive transistors Qda, Qdb, and Qdc in the present embodiment. The control means described in the claims corresponds to, for example, the fifth to seventh switching transistors Qswa, Qswb, and Qswc in the present embodiment.

According to the above embodiment, the following effects can be obtained.
(1) In the above embodiment, the adjustment means 28 is added to the digital / analog conversion circuit 25, and the fifth to seventh drive transistors Qda, Qdb, Qdc and the fifth to fifth drive transistors are added to the second digital / analog conversion circuit section 27. Seven current lines Laa, Lab, Lac and fifth to seventh switching transistors Qswa, Qswb, Qswc were added. Then, by selecting any one of the fifth to seventh drive transistors Qda, Qdb, and Qdc, the value of the current flowing through the fifth to seventh current lines La25 to La27 was changed. Thereby, it is possible to obtain an analog current having not only a square nonlinear characteristic but also a wider range of nonlinearity without providing a special signal processing circuit.

(2) In the above embodiment, the first digital / analog conversion circuit unit 26 having linear characteristics and the second digital / analog conversion circuit unit 27 having linear characteristics are connected in series. Then, only by selecting one of the fifth to seventh drive transistors Qda, Qdb, Qdc provided in the second digital / analog conversion circuit unit 27, the input image digital data D1-D4 (DD1 ˜DD4) can generate an analog current with a square non-linear characteristic. Further, not only the square nonlinear characteristic but also an analog current having a wider range of nonlinear characteristic can be generated with a small number of circuit elements and a simple circuit configuration. Therefore, the entire apparatus can be reduced in size and the cost can be reduced.
(Fourth embodiment)
Next, application of the organic electroluminescence display device 10 using the organic EL element as the electro-optical device described in the first to third embodiments to an electronic apparatus will be described with reference to FIG. The organic electroluminescence display device 10 can be applied to various electronic devices such as mobile personal computers, mobile phones, viewers, game machines and other portable information terminals, electronic books, and electronic paper. The organic electroluminescence display device 10 can be applied to various electronic devices such as a video camera, a digital still camera, a car navigation system, a car stereo, a driving operation panel, a personal computer, a printer, a scanner, a television, and a video player.

  FIG. 7 is a perspective view showing the configuration of the mobile personal computer. In FIG. 7, the mobile personal computer 100 includes a main body 102 including a keyboard 101 and a display unit 103 using the organic electroluminescence display device 10. Also in this case, the display unit 103 using the organic electroluminescence display device 10 exhibits the same effect as the first to third embodiments. As a result, the mobile personal computer 100 can realize display with excellent display quality.

In addition, you may change each said embodiment as follows.
In the second embodiment, the resistance value of the variable resistor R6 is individually fixed in accordance with the characteristics of the organic electroluminescence display device 10 in the inspection process at the time of factory shipment. For example, the variable resistor R6 is composed of a resistor element and an analog switch, the analog switch is selected by a program in which the function of adjusting the resistance value is written in the IC chip, and the resistance value of the variable resistor R6 is set according to the display image. It may be varied in real time.

  In the third embodiment, three types of fifth to seventh drive transistors Qda, Qdb, Qdc and fifth to seventh switching transistors Qswa, Qswb, Qswc having different gain coefficients β are used. The slope of the nonlinear characteristic was changed by selectively turning it on. Alternatively, two or more of the three types of fifth to seventh switching transistors Qswa, Qswb, and Qswc may be combined and turned on to change the slope of the nonlinear characteristic.

In the third embodiment, nonlinear characteristics are obtained by using three types of fifth to seventh drive transistors Qda, Qdb, Qdc and fifth to seventh switching transistors Qswa, Qswb, Qswc having different gain coefficients β. The inclination of was changed. Alternatively, the slope of the nonlinear characteristic may be changed by selectively turning on a drive transistor having two or four or more types of gain coefficients β and a corresponding switching transistor. In addition, two or more of these two types or four or more types of switching transistors may be combined and turned on to change the slope of the nonlinear characteristic. In addition, the function of selectively turning on these switching transistors may be selected in real time according to the display image by a program written in the IC chip to change the slope of the nonlinear characteristic.

  In the above embodiment, a suitable result was obtained by applying to the organic electroluminescence display device 10, but the present invention may be applied to a non-linear DAC used for an audio compression device other than the organic electroluminescence display device.

  In the above embodiment, the 4-bit image digital data D is applied to the digital / analog conversion circuit 25 for converting the analog digital current into an analog current. The present invention may be applied to the digital / analog conversion circuit 25.

  In the above embodiment, the first to fourth drive transistors Qd11 to Qd14 and Qd21 to Qd24 are transistors having different gain coefficients β. By connecting a plurality of transistors having the same gain coefficient β in parallel or in series, and changing the number of transistors connected in parallel or in series, the first to fourth drive transistors Qd11 to Qd14, Qd21 to Qd24 are respectively changed. Equivalently different gain coefficients β may be used.

  In the above embodiment, the pixel circuit 20 is embodied and a suitable effect is obtained. However, the pixel circuit 20 is embodied in a unit circuit that drives a current driving element such as a light emitting element such as an LED or FED other than the organic EL element OLED. Also good. The present invention may be embodied in a storage device such as a RAM (particularly MRAM).

  In the above embodiment, the organic EL element OLED is embodied as the current driving element, but may be embodied in an inorganic electroluminescence element. That is, you may apply to the inorganic electroluminescent display apparatus which consists of an inorganic electroluminescent element.

  In the above embodiment, the case where an organic EL element is used has been described as an example. However, the present invention is not limited to this, and a liquid crystal element, a digital micromirror device (DMD), an FED (Field Emission Display), The present invention is also applicable to SED (Surface-Condition Electron-Emitter Display).

The block circuit diagram which shows the electric constitution of the organic electroluminescent display apparatus of 1st Embodiment. Similarly, the block circuit diagram which shows the circuit structure of a display panel part. Similarly, a circuit diagram of a pixel circuit. Similarly, the block circuit diagram which shows the structure of a digital-analog converting circuit. The block circuit diagram which shows the structure of the digital-analog converting circuit of 2nd Embodiment. The block circuit diagram which shows the structure of the digital-analog converting circuit of 3rd Embodiment. The perspective view which shows the structure of the mobile type personal computer for describing 4th Embodiment.

Explanation of symbols

Co ... holding capacitor, Xm ... data line, Yn ... scanning line, OLED ... organic EL element, Qc1, Qc2 ... conversion transistor, Qd11-Qd14, Qd21-Qd25, Qda, Qdb, Qdc ... first to seventh drive transistors , Qsw11 to Qsw14, Qsw21 to Qsw25, Qswa, Qswb, Qswc ... 1st to 7th switching transistor, 10 ... Organic electroluminescence display device, 11 ... Signal generation circuit, 12 ... Display panel section, 13 ... Scanning line drive circuit , 14 Data line drive circuit, 20 Pixel circuit, 25 Digital / analog conversion circuit, 26 First digital / analog conversion circuit, 27 Second digital / analog conversion circuit, 28 Adjusting means, 100: Mobile personal computer.

Claims (33)

A plurality of first sub-currents are generated based on the reference signal, and the first sub-current selected from the first sub-currents based on the first control signal is added to obtain a first output current. A first current adding circuit for outputting;
A plurality of second sub-currents are generated based on the first output current, and a second sub-current selected from the second sub-currents based on a second control signal is added to add a second sub-current. And a second current adding circuit that outputs the output current as a current output circuit. The current generation circuit according to claim 1,
The plurality of first sub-currents include those in which each current value has a binary weighted relationship. The current generation circuit according to claim 1 or 2,
The plurality of second sub-currents include those in which the respective current values are in a binary weighted relationship. The current generation circuit according to any one of claims 1 to 3,
The current generation circuit, wherein the first control signal and the second control signal are the same or have a corresponding relationship. The current generation circuit according to any one of claims 1 to 4,
Means for generating a third subcurrent in a predetermined ratio with respect to the first output current, and means for adding the third subcurrent to the second output current. A characteristic current generation circuit. A first reference voltage, a plurality of first transistors to which the first reference voltage is commonly applied to the gates, and a current output from the plurality of first transistors are selectively selected based on a first control signal. A first combining circuit for generating a first output current by adding to the first current adding circuit,
A conversion circuit for generating a second reference voltage based on the first output current; a plurality of second transistors to which the second reference voltage is commonly applied to a gate; and the plurality of second transistors. A second synthesizing unit that generates a second output current by selectively adding the output current based on the second control signal; and
A current generation circuit comprising: The current generating circuit according to claim 6,
The conversion circuit includes a transistor whose gate and drain are electrically connected to each other. The current generation circuit according to claim 6 or 7,
Each of the plurality of first transistors has a gain ratio set to a binary weighted value. The current generation circuit according to any one of claims 6 to 8,
Each of the plurality of second transistors has a gain ratio set to a binary weighted value. The current generation circuit according to claim 8 or 9,
The current generation circuit according to claim 1, wherein the first transistor or the second transistor includes a parallel connection configuration of transistors having a predetermined gain. The current generation circuit according to any one of claims 8 to 10,
The current generation circuit according to claim 1, wherein the first transistor or the second transistor includes a serial connection configuration of transistors having a predetermined gain. The current generation circuit according to any one of claims 6 to 11,
The current generation circuit, wherein the first control signal and the second control signal are the same or have a corresponding relationship. The current generation circuit according to any one of claims 6 to 12,
The apparatus further comprises a third transistor to which the second reference voltage is applied to a gate, and further includes means for adding a current output from the third transistor to the second output current. Current generation circuit. The current generation circuit according to any one of claims 6 to 13,
Current generation comprising control means for changing the value of the first output current, the current output from the plurality of second transistors, or the current output from the third transistor circuit. The current generation circuit according to claim 14, wherein
The current generating circuit further comprising adjusting means for adjusting the amount of current change by the control means. In an electro-optical device,
A plurality of scanning lines; a plurality of data lines; a pixel portion having an electro-optic element provided corresponding to an intersection of the plurality of scanning lines and the plurality of data lines; and the plurality of scanning lines. A scanning line driving circuit for scanning the data, and a data line driving circuit for supplying an analog current to the corresponding pixel portion via the plurality of data lines,
The data line driving circuit includes:
A plurality of first sub-currents are generated based on the reference signal, and the first sub-current selected from the first sub-currents based on the first control signal is added to obtain a first output current. A first current adding circuit for outputting;
A plurality of second sub-currents are generated based on the first output current, and a second sub-current selected from the second sub-currents based on a second control signal is added to add a second sub-current. An electro-optical device comprising: a second current adding circuit that outputs the output current of the second current adding circuit. The electro-optical device according to claim 16,
The electro-optical device, wherein the plurality of first sub-currents include ones whose current values are in a binary weighted relationship. The electro-optical device according to claim 16 or 17,
The electro-optical device, wherein the plurality of second sub-currents include those in which current values are in a binary weighted relationship. The electro-optical device according to any one of claims 16 to 18,
The electro-optical device, wherein the first control signal and the second control signal are the same or have a corresponding relationship. The electro-optical device according to any one of claims 16 to 19,
Means for generating a third subcurrent in a predetermined ratio with respect to the first output current, and means for adding the third subcurrent to the second output current. Electro-optical device characterized. In an electro-optical device,
A plurality of scanning lines; a plurality of data lines; a pixel portion having an electro-optic element provided corresponding to an intersection of the plurality of scanning lines and the plurality of data lines; and the plurality of scanning lines. A scanning line driving circuit for scanning the data, and a data line driving circuit for supplying an analog current to the corresponding pixel portion via the plurality of data lines,
The data line driving circuit includes:
A first reference voltage, a plurality of first transistors to which the first reference voltage is commonly applied to the gates, and a current output from the plurality of first transistors are selectively selected based on a first control signal. A first combining circuit for generating a first output current by adding to the first current adding circuit,
A conversion circuit for generating a second reference voltage based on the first output current; a plurality of second transistors to which the second reference voltage is commonly applied to a gate; and the plurality of second transistors. A second synthesizing unit that generates a second output current by selectively adding the output current based on the second control signal; and
An electro-optical device comprising: The electro-optical device according to claim 21,
The electro-optical device, wherein the conversion circuit includes a transistor whose gate and drain are electrically connected. The electro-optical device according to claim 21 or 22,
The electro-optical device, wherein each of the plurality of first transistors has a gain ratio set to a binary weighted value. The electro-optical device according to any one of claims 21 to 23,
The electro-optical device, wherein each of the plurality of second transistors is set to a binary weighted value. The electro-optical device according to claim 23 or 24,
The electro-optical device, wherein the first transistor or the second transistor includes a parallel connection configuration of transistors having a predetermined gain. The electro-optical device according to any one of claims 23 to 25,
The electro-optical device, wherein the first transistor or the second transistor includes a serial connection configuration of transistors having a predetermined gain. The electro-optical device according to any one of claims 21 to 26,
The electro-optical device, wherein the first control signal and the second control signal are the same or have a corresponding relationship. The electro-optical device according to any one of claims 21 to 27,
The apparatus further comprises a third transistor to which the second reference voltage is applied to a gate, and further includes means for adding a current output from the third transistor to the second output current. Electro-optic device. The electro-optical device according to any one of claims 21 to 28,
An electro-optical device comprising: control means for changing a value of the first output current, the current output from the plurality of second transistors, or the current output from the third transistor. apparatus. 30. The electro-optical device according to claim 29,
An electro-optical device further comprising adjusting means for adjusting the amount of current change by the control means. The electro-optical device according to any one of claims 16 to 30,
The electro-optic device is an organic electroluminescence device. An electronic apparatus comprising the current generation circuit according to claim 1. An electronic apparatus comprising the electro-optical device according to any one of claims 16 to 31.

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