JP2005116838A - Thin film transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor (TFT) capable of adjusting the concentration of impurity or the concentration of carrier in an overlap area and an offset area in the TFT having GOLD structure. <P>SOLUTION: The thin film transistor (TFT) is provided with a semiconductor layer 2 including a channel area 4, a pair of first low concentration impurity areas 6, 7 formed so as to put the channel area 4 between them, a pair of second low concentration impurity areas 9, 10 formed so as to put the first low concentration impurity areas 6, 7 between them and having carrier concentration different from that of the first low concentration impurity areas 6, 7, and a pair of high concentration impurity areas 11, 12 formed so as to put the second low concentration impurity areas 9, 10; a gate insulating film 3 formed so as to cover the semiconductor layer 2; and a gate electrode 8 formed on the gate insulating film 3 so as to be located on the upper parts of the channel area 4 and the first low concentration impurity areas 6, 7, and so as not to be located on the upper parts of the second low concentration impurity areas 9, 10. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device that is used in an active matrix display device or the like and includes a thin film transistor (hereinafter abbreviated as TFT) and a method for manufacturing the same.

  In recent years, a driver monolithic panel in which a display unit including a plurality of pixels and a drive circuit for driving display are provided on a transparent insulating substrate such as glass has been developed. In particular, there is a growing need for high-definition and small-sized liquid crystal panels for projectors, such as data projectors used for presentations and liquid crystal rear projectors compatible with high-definition broadcast standards. Along with this, one of the important issues is to increase the definition of an image while reducing the size of the panel.

  In such a panel, pixel TFTs and drive circuit TFTs are formed on a transparent insulating substrate using polycrystalline silicon having a relatively high mobility. To reduce the panel size, the TFT size is reduced. There is a need. However, when the TFT is miniaturized, there is a problem in reliability that the withstand voltage between the source and the drain decreases, or the electric field applied to the vicinity of the drain becomes very large and the deterioration of TFT characteristics due to hot carriers becomes more remarkable. .

  As one of means for solving these reliability problems, a TFT having a GOLD (Gate-Overlapped LDD) structure is generally known. The TFT includes a channel region provided in the semiconductor layer, a pair of low-concentration impurity regions provided so as to sandwich the channel region, and a high-concentration impurity region provided so as to sandwich the pair of low-concentration impurity regions. In a TFT having an LDD (Lightly Doped Drain) structure including a certain source / drain region, a gate electrode is provided so as to cover all or part of the channel region and the low concentration impurity region. With such a structure, the concentration of the electric field in the vicinity of the drain region can be reduced as compared with the LDD structure, and hot carriers can be prevented from being injected into the drain region. For this reason, it is effective in preventing deterioration of TFT characteristics.

  A GOLD structure having a low concentration impurity region (hereinafter referred to as an overlap region) covered with a gate electrode and a low concentration impurity region (hereinafter referred to as an offset region) not covered with a gate electrode is also known. . According to this structure, since the offset region functions as a resistance, an effect of reducing off-leakage current can be obtained in addition to an improvement in resistance to hot carriers.

  Patent Document 1 discloses a TFT having such a GOLD structure. As shown in FIG. 11, the TFT 500 includes a semiconductor layer 502 formed on an insulating substrate 501. The semiconductor layer 502 includes a channel region 513, low-concentration impurity regions 511 and 512 that sandwich the channel region 513, and source / drain regions 509 and 510 that sandwich the low-concentration impurity regions 511 and 512. The low-concentration impurity regions 511 and 512 include overlap regions 511a and 512a that are covered with the first gate electrode 508c and offset regions 511b and 512b that are not covered with the first gate electrode 508c. The first gate electrode 508c and the second gate electrode 507b form a hat-shaped gate electrode.

  According to Patent Document 1, the TFT 500 is manufactured by the following method. As illustrated in FIG. 12A, the semiconductor layer 502 is formed over the insulating substrate 501, and the gate insulating film 503 is formed over the semiconductor layer 502. A first conductive film 504 made of TaN having a thickness of about 30 nm and a second conductive film 505 made of W having a thickness of about 370 nm are formed on the gate insulating film 503. In order to obtain a hat-shaped gate electrode, the first conductive film 504 cannot be made too thick.

  As shown in FIG. 12B, after the photoresist mask 506 is formed, the second conductive film 505 is etched using an ICP (Inductivity Coupled Plasma) etching apparatus to taper the end. A second gate electrode 507a having a shape is formed. Next, as shown in FIG. 12C, using the resist mask 506 as it is, the first gate electrode 504 is etched by an ICP etching apparatus to form a first gate electrode 508a having a width W1. Thereafter, as shown in FIG. 12D, the resist mask 506 is used as it is, and the second gate electrode 507a and the first gate electrode 508a are etched by an ICP etching apparatus, so that the width W2 and the taper angle are about 70, respectively. A second gate electrode 507b having a degree and a first gate electrode 508b having a width W1 and a taper angle of about several degrees to 15 degrees are formed.

  Subsequently, as shown in FIG. 12E, ion implantation is performed using the first gate electrode 508b as a mask to form high-concentration impurity regions 509 and 510 in the semiconductor layer 502 (first doping step). . 13A, ion implantation is performed using the resist mask 506 and the second gate electrode 507b as masks to form low-concentration impurity regions 511 and 512 in the semiconductor layer 502 (second region). Doping process). By the resist mask 506 and the second gate electrode 507b, the region of the semiconductor layer 502 into which the impurity is not implanted in the first doping step or the second doping step becomes a channel region 513.

  Next, as shown in FIG. 13B, a part of the taper portion of the first gate electrode is removed by anisotropic etching using an RIE etching apparatus or an ICP etching apparatus with the resist mask 506 left. The first gate electrode 508c having a width W3 and a taper angle of about several degrees to 15 degrees is formed by removing the first gate electrode 508c. Thereby, overlap regions 511a and 512a covered with the first gate electrode 508c and offset regions 511b and 512b not covered with the first gate electrode 508c are formed.

  After that, as shown in FIG. 11, after removing the resist mask 506, an interlayer insulating film 514 is formed by depositing an insulating film on the entire surface, and then contact holes for extracting electrodes on the source region 509 and the drain region 510 are formed. Form. A film made of a metal material such as Al is formed on the interlayer insulating film 514 and in the contact hole, and is patterned into a predetermined shape, whereby the source electrode 515 and the drain electrode 516 are formed. Thereby, the TFT 500 shown in FIG. 11 is completed.

  Patent Document 1 describes that the number of steps can be reduced by the above-described method, and the manufacturing cost can be reduced and the yield can be improved. Further, it is described that in the TFT 500, the widths of the overlap regions 511a and 512a and the widths of the offset regions 511b and 512b can be freely adjusted.

  However, Patent Document 1 intends to make the impurity concentration of the overlap regions 511a and 512a equal to the impurity concentration of the offset regions 511b and 512b. For this reason, the TFT of Patent Document 1 or the method described in Patent Document 1 cannot independently adjust the impurity concentration or the carrier concentration of the overlap regions 511a and 512a and the offset regions 511b and 512b. Since the thickness and taper angle of the first gate electrode 508c are small, it is difficult to give a concentration difference to impurities implanted into the semiconductor layer through the first gate electrode 508c.

In the above-described method, as shown in FIG. 14, since the thickness of the tapered portion of the first gate electrode 508c is small and the taper angle is gentle, variations in the thickness and the taper angle are different. Due to the etching variation in the isotropic etching, the lateral length of the first gate electrode 508b remaining after the etching is likely to vary. For this reason, the position 530 of the boundary between the overlap regions 511a and 512a and the offset regions 511b and 512b is likely to vary, causing a problem that the characteristic variation of the TFT 500 increases.
JP 2002-57165 A

  An object of the present invention is to solve the above-described problems of the prior art and provide a TFT having a GOLD structure capable of adjusting the impurity concentration or the carrier concentration in the overlap region and the offset region. It is another object of the present invention to provide a GOLD structure TFT with small variation in characteristics.

  The thin film transistor of the present invention is provided so as to sandwich a channel region, a pair of first low-concentration impurity regions provided so as to sandwich the channel region, and the pair of first low-concentration impurity regions. A semiconductor layer including a pair of second low-concentration impurity regions having a carrier concentration different from that of the first low-concentration impurity region and a pair of high-concentration impurity regions provided so as to sandwich the pair of second low-concentration impurity regions A gate insulating film provided so as to cover the semiconductor layer, and provided on the gate insulating film, located above the channel region and the pair of first low-concentration impurity regions, and And a gate electrode not located above the pair of second low-concentration impurity regions.

  The thin film transistor of the present invention includes a channel region, a pair of first low-concentration impurity regions provided to sandwich the channel region, and a pair of first low-concentration impurity regions provided to sandwich the pair of first low-concentration impurity regions. A semiconductor layer including a pair of high-concentration impurity regions provided so as to sandwich the second low-concentration impurity region and the pair of second low-concentration impurity regions; and a gate insulating film provided so as to cover the semiconductor layer And over the channel region and the pair of first low-concentration impurity regions, and over the pair of second low-concentration impurity regions. And a pair of insulating sidewalls provided on the sides of the gate electrode, and the pair of second low-concentration impurity regions are respectively provided below the pair of insulating sidewalls. It is located.

  In a preferred embodiment, the insulating sidewalls and the second low-concentration impurity regions have the same length in the channel length direction.

In a preferred embodiment, when the carrier concentrations of the first low concentration impurity region, the second low concentration impurity region, and the high concentration impurity region are C _L1 C _L2 and C _H , respectively, C _L1 C _L2 and C _H However, the relationship of C _L1 <C _L2 <C _H is satisfied.

In a preferred embodiment, when the carrier concentrations of the first low concentration impurity region, the second low concentration impurity region, and the high concentration impurity region are C _L1 C _L2 and C _H , respectively, C _L1 C _L2 and C _H However, the relationship of C _L2 <C _L1 <C _H is satisfied.

In a preferred embodiment, when the carrier concentrations of the first low concentration impurity region, the second low concentration impurity region, and the high concentration impurity region are C _L1 C _L2 and C _H , respectively, C _L1 C _L2 and C _H However, the relationship of C _L2 = C _L1 <C _H is satisfied.

  An active matrix liquid crystal display device according to the present invention includes any one of the above thin film transistors, a signal wiring electrically connected to one of the high concentration impurity regions of the thin film transistor, a gate wiring electrically connected to the gate electrode, and A substrate on which a pixel electrode electrically connected to the other of the high-concentration impurity regions of the thin film transistor is formed; and a liquid crystal layer that changes an optical state in accordance with a potential of the pixel electrode.

Further, the active matrix type liquid crystal display device of the present invention, C _L2 <C _L1 <the TFT satisfies the relationship C _H, one electrically connected to the signal wiring of high concentration impurity regions of the thin film transistor, said gate electrode And a pixel portion including a pixel electrode electrically connected to the other of the high concentration impurity regions of the thin film transistor and the thin film transistor satisfying a relationship of C _L1 <C _L2 <C _H A substrate configured to drive the pixel unit; and a liquid crystal layer that changes an optical state in accordance with a potential of the pixel electrode.

  The method for manufacturing a thin film transistor of the present invention includes a step (A) of forming a semiconductor layer on an insulating substrate, a step (B) of forming a gate insulating film covering the semiconductor layer, a channel region in the semiconductor layer, A step (C) of adding a first conductivity type impurity to a portion other than the portion to define a channel region in the semiconductor layer, the channel region and the semiconductor layer adjacent to each other with the channel region interposed therebetween, A step (D) of forming a gate electrode so as to cover a pair of first low-concentration impurity regions and defining a first low-concentration impurity region overlapping the gate electrode in the semiconductor layer; A step (E) of forming a mask adjacent to the pair of first low-concentration impurity regions in the layer and covering at least a portion to be the pair of second low-concentration impurity regions; and using the mask Adding a first conductivity type impurity, forming a high concentration impurity region in the semiconductor layer, and defining a second low concentration impurity region in a portion covered with the mask (F). .

  In a preferred embodiment, the mask used in the step (E) is a resist mask that covers the gate electrode and the pair of second low-concentration impurity regions.

  In a preferred embodiment, the mask used in the step (E) is an insulating sidewall provided adjacent to the gate electrode.

  In a preferred embodiment, the insulating sidewall includes a step (e1) of forming an insulating film so as to cover the gate electrode in the step (E), and the insulating film is perpendicular to the substrate. And selectively etching (e2).

  In a preferred embodiment, the first low-concentration impurity region and the second low-concentration impurity region have substantially the same impurity concentration.

  In a preferred embodiment, the method of manufacturing a thin film transistor further includes a step (G) of adding a first conductivity type impurity to the semiconductor layer using the gate electrode as a mask after the step (D).

In a preferred embodiment, when the carrier concentrations of the first low concentration impurity region, the second low concentration impurity region, and the high concentration impurity region are C _L1 C _L2 and C _H , respectively, C _L1 C _L2 and C _H However, the relationship of C _L1 <C _L2 <C _H is satisfied.

  In a preferred embodiment, the method of manufacturing a thin film transistor further includes a step (G) of adding a second conductivity type impurity to the semiconductor layer using the gate electrode as a mask after the step (D).

In a preferred embodiment, when the carrier concentrations of the first low concentration impurity region, the second low concentration impurity region, and the high concentration impurity region are C _L1 C _L2 and C _H , respectively, C _L1 C _L2 and C _H but satisfies the relationship of _{C L2 <C L1 <C H} .

  According to the present invention, the first low-concentration impurity region sandwiched between the channel region and the high-concentration impurity region and overlapping the gate electrode, and the second low-concentration impurity region not overlapping the gate electrode are provided. A TFT having a GOLD structure capable of independently adjusting the carrier concentration of the low concentration impurity region and the second low concentration impurity region is obtained.

  In addition, since the length of the second low-concentration impurity region in the channel direction is determined by the sidewall and variation in the length is small, a small and highly reliable TFT can be obtained.

(First embodiment)
FIG. 1 is a cross-sectional view showing a first embodiment of a TFT according to the present invention. Although the TFT 100 shown in FIG. 1 is an n-channel type (n-type), the present invention is not limited to this and may be a p-channel type (p-type). In addition, although the first conductivity type and the second conductivity type of the semiconductor will be described as n-type and p-type, the first conductivity type and the second conductivity type may be p-type and n-type.

  The TFT 100 includes a semiconductor layer 2 provided on an insulating substrate 1 such as a quartz substrate, a gate insulating film 3 provided on the semiconductor layer 2, and a gate electrode 8 provided on the gate insulating film 3. .

  The semiconductor layer 2 is made of, for example, amorphous silicon, polycrystalline silicon, single crystal silicon, or the like. The semiconductor layer 2 includes a channel region 4, first low-concentration impurity regions 6 and 7, second low-concentration impurity regions 9 and 10, and high-concentration impurity regions 11 and 12.

  When the channel region 4 is made of amorphous silicon, it may be made of intrinsic Si to which no impurity is added, and when it is made of polycrystalline silicon, the p-type impurity is added at a low concentration. It may be formed from type Si.

  The first low-concentration impurity regions 6 and 7 are provided so as to sandwich the channel region 4, and are preferably adjacent to the channel region 4. The second low-concentration impurity regions 9 and 10 are provided outside the first low-concentration impurity regions 6 and 7 so as to sandwich the first low-concentration impurity regions 6 and 7. The high-concentration impurity regions 11 and 12 are provided outside the second low-concentration impurity regions 9 and 10 so as to sandwich the second low-concentration impurity regions 9 and 10 and function as source / drain regions. The first low-concentration impurity regions 6 and 7, the second low-concentration impurity regions 9, 10 and the high-concentration impurity regions 11 and 12 all have the same conductivity type. In this embodiment, it is n-type. The impurity concentration of the first low-concentration impurity regions 6 and 7 and the second low-concentration impurity regions 9 and 10 is lower than the impurity concentration of the high-concentration impurity regions 11 and 12, and accordingly, the first low-concentration impurity regions 6 and 7 and the second low-concentration impurity regions 6 and 7 The carrier concentration of the low concentration impurity regions 9 and 10 is lower than the carrier concentration of the high concentration impurity regions 11 and 12.

  A gate electrode 8 is provided on the semiconductor layer 2 via a gate insulating film 3. The gate electrode 8 is provided only above the channel region 4 and the first low concentration impurity regions 6 and 7, and the gate electrode 8 is not located above the second low concentration impurity regions 9 and 10. Therefore, the TFT 100 includes an overlap region in which the gate electrode 8 is provided on the first low concentration impurity regions 6 and 7 and an offset region in which the gate electrode 8 is not provided above the second low concentration impurity regions 9 and 10. A GOLD structure including

  Therefore, the voltage applied by the gate electrode 8 generates an electric field in the first low-concentration impurity region 7 toward the inside of the TFT element, thereby preventing hot carriers from moving from the channel region 4 to the drain region 12. As a result, the semiconductor layer can be prevented from being deteriorated at the end of the drain region 12 due to the inflow of hot carriers, and the reliability can be improved. Further, the off-leakage current can be reduced by the second low-concentration impurity regions 9 and 10 provided between the channel region 4 and the high-concentration impurity regions 11 and 12 and not overlapping the gate electrode 8.

  The maximum width of the gate electrode 8 in the channel length direction, which is a direction perpendicular to the direction in which the gate electrode 8 extends, is L, the boundary b1 between the first low-concentration impurity region 6 and the second low-concentration impurity region 9, and the first low-concentration impurity region 9. This coincides with the distance of the boundary b2 between the concentration impurity region 7 and the second low concentration impurity region 10. When the side surfaces 8a and 8b of the gate electrode 8 are formed substantially perpendicular to the insulating substrate 1, the positions of the boundaries b1 and b2 coincide with the positions of the side surfaces 8a and 8b, respectively. The gate electrode 8 may be formed of a single layer metal film or conductive silicon film, or may be laminated. However, it is preferable that the gate electrode 8 has a sufficient thickness over the whole so that it can be used as a mask when impurities are added to the second low-concentration impurity regions 9 and 10.

The first low-concentration impurity regions 6 and 7, the second low-concentration impurity regions 9, 10 and the high-concentration impurity regions 11 and 12 are doped with n-type impurities and are n-type semiconductors. One of the features of the present invention is that the carrier concentrations of the first low-concentration impurity regions 6 and 7 and the second low-concentration impurity regions 9 and 10 can be freely adjusted independently. For this reason, it is preferable that the first low concentration impurity regions 6, 7 and the second low concentration impurity regions 9, 10 have different carrier concentrations, and the first low concentration impurity regions 6, 7 and the second low concentration impurity regions 9 are different. The carrier concentration of 10 is preferably lower than the carrier concentration of the high concentration impurity region. That is, when the carrier concentrations of the first low-concentration impurity regions 6 and 7, the second low-concentration impurity regions 9 and 10, and the high-concentration impurity regions 11 and 12 are C _L1 C _L2 and C _H , C _L1 <C _H , C _L2 <C _H and C _L1 ≠ C _L2 .

  In the present embodiment, as long as these relationships are satisfied, the carrier concentration of the first low-concentration impurity regions 6 and 7 and the second low-concentration impurity regions 9 and 10 can be arbitrarily set. By adjusting, it is possible to realize TFTs having different characteristics according to the application while taking advantage of the GOLD structure. However, in the TFT of the present invention, the first low-concentration impurity regions 6 and 7 and the second low-concentration impurity regions 9 and 10 can have the same carrier concentration.

For example, when the carrier concentration of the second low-concentration impurity regions 9 and 10 is made higher than that of the first low-concentration impurity regions 6 and 7, that is, when C _L1 <C _L2 <C _H is satisfied, the second resistance region is formed. The carrier concentration in the low-concentration impurity region becomes high and the resistance becomes low. For this reason, the on-current of the TFT 100 can be increased. Such a TFT is suitable for a driver circuit.
Further, when the carrier concentration of the second low-concentration impurity regions 9 and 10 is made lower than that of the first low-concentration impurity regions 6 and 7, that is, when C _L2 <C _L1 <C _H is satisfied, a second resistance region is formed. The carrier concentration in the low-concentration impurity region is lowered and the resistance is increased. For this reason, the off-current of the TFT 100 can be reduced. Such a TFT is suitable for a pixel switch element.

  As described above, according to the TFT of the present embodiment, the improvement of the reliability and the improvement of the TFT characteristics by the GOLD structure are achieved at the same time, and the first low concentration impurity regions 6 and 7 and the second low concentration impurity region 9 are achieved. By adjusting the carrier concentration of 10, it is possible to realize TFT characteristics more suitable for the application.

  Hereinafter, the manufacturing method of the TFT 100 according to the present embodiment will be described.

  First, as shown in FIG. 2A, a semiconductor layer 2 is formed on a transparent insulating substrate 1 such as quartz. The semiconductor layer 2 is made of, for example, amorphous silicon, polycrystalline silicon, single crystal silicon, or the like. When the semiconductor layer 2 is formed of polycrystalline silicon, an amorphous silicon thin film having a thickness of about 50 to 150 nm is deposited on the transparent insulating substrate 1 by a low pressure CVD (Low Power Chemical Vapor Deposition, hereinafter referred to as LPCVD) method. After that, high temperature heat treatment or laser annealing is performed to polycrystallize amorphous silicon. Thereafter, patterning is performed by a photolithography process and an etching process to form a semiconductor layer 2 having a predetermined shape. Thereafter, a p-type impurity for controlling the threshold value of the transistor may be added by implantation or the like, if necessary.

  Next, as shown in FIG. 2B, a gate insulating film 3 having a thickness of about 100 nm is formed on the semiconductor layer 2. The gate insulating film can be deposited by, for example, a CVD (Chemical Vapor Deposition) method. The gate insulating film 3 may be formed by oxidizing the surface of the formed semiconductor layer 2.

As shown in FIG. 2C, a region to be the channel region 4 in the semiconductor layer 2 is covered with a resist 5, and a p-type impurity element is added to the semiconductor layer 2 by ion implantation (first impurity addition step). As a result, regions 6 ′ and 7 ′ having the same impurity concentration as the first low-concentration impurity regions 6 and 7 are formed in the semiconductor layer 2. In the first impurity addition step, for example, n-type impurities such as phosphorus and arsenic are performed at a dose of 5 × 10 ¹² to 1 × 10 ¹⁴ / cm ² . A region where impurities are not implanted by the resist 5 becomes a channel region 4. This step defines the channel region 4.

As shown in FIG. 2D, after the resist 5 is peeled off, a gate electrode 8 is formed on the gate insulating film 3. The gate electrode 8 is formed by depositing a film made of WSi or the like having a thickness of about 300 nm using, for example, sputtering or LPCVD, and then patterning so as to cover the channel region 4 and part of the regions 6 ′ and 7 ′. Is obtained. Regions 6 ′ and 7 ′ covered with the gate electrode 8 are defined in the semiconductor layer 2 as first low-concentration impurity regions 6 and 7. The gate electrode 8 may be phosphorus-doped polycrystalline silicon (N ⁺ poly-Si), or may have a structure in which WSi or the like is further laminated thereon.

  As shown in FIG. 2E, using the gate electrode 8 as a mask, an impurity element is added to the semiconductor layer 2 by ion implantation (second impurity addition step) to form regions 9 'and 10'. The impurity concentration of the regions 9 ′ and 10 ′ is equal to that of the second low concentration impurity region. The region where the impurity element is not implanted by the gate electrode 8 becomes the first low-concentration impurity regions 6 and 7 and functions as an overlap region of the GOLD structure.

  Depending on the conductivity type of the impurity element added in the second impurity addition step, the carrier concentration of the second low-concentration impurity region can be made higher or lower than that of the first low-concentration impurity regions 6 and 7.

When the carrier concentration of the second low-concentration impurity region is higher than that of the first low-concentration impurity regions 6 and 7, an impurity element having the same conductivity type as that of the impurity used in the first impurity addition step is used. Specifically, n-type impurities such as phosphorus and arsenic are implanted into the semiconductor layer 2 at a dose of 5 × 10 ¹² to 1 × 10 ¹⁴ / cm ² .

When the carrier concentration of the second low-concentration impurity region is lower than that of the first low-concentration impurity regions 6 and 7, an impurity element having a conductivity type opposite to that of the impurity used in the first impurity addition step is used. Specifically, p-type impurities such as boron are implanted into the semiconductor layer 2 at a dose of 1 × 10 ¹² to 1 × 10 ¹⁴ / cm ² . Due to the counter-doping, the carriers generated by the impurities implanted in the first impurity addition step are canceled by the carriers generated by the impurities implanted in the second impurity addition step, and the carrier concentration of the second low-concentration impurity region is the first concentration. It becomes lower than the carrier concentration of the low concentration impurity region.

  Note that when the carrier concentration of the second low-concentration impurity region is equal to the carrier concentration of the first low-concentration impurity regions 6 and 7, the second impurity addition step is not performed.

As shown in FIG. 3, a resist 5 'is formed so that the regions on both sides of the gate electrode 8 are left as the second low-concentration impurity regions 9, 10, and an n-type impurity element is ion-implanted using this resist as a mask. Is added (third impurity addition step) to form and define the source region 11 and the drain region 12 in the semiconductor layer 2. Of the regions where the impurity ions are not implanted by the resist 5, regions that do not overlap the gate electrode 8 are defined as second low-concentration impurity regions 9 and 10. Since the second low-concentration impurity regions 9 and 10 do not overlap the gate electrode 8, they become offset regions of the GOLD structure. The third impurity addition step is performed with an n-type impurity such as phosphorus or arsenic at a dose of 1 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² . Thereafter, the resist 5 is peeled off and annealing for activating impurity ions is performed.

  As shown in FIG. 1, after an insulating film is deposited on the entire surface and an interlayer insulating film 13 is formed, contact holes are formed on the source region 11 and the drain region 12 for electrode extraction. A source electrode 14 and a drain electrode 15 are formed by depositing a metal material such as Al in the interlayer insulating film 13 and the contact hole, and patterning it into a predetermined shape.

(Second Embodiment)
FIG. 4 is a cross-sectional view showing a second embodiment of a TFT according to the present invention. The TFT 200 shown in FIG. 4 is also described as an n-type TFT, but may be a p-type TFT.

  The TFT 200 is different from the TFT 100 according to the first embodiment in that it further includes a pair of insulating sidewalls 17 provided on the side of the gate electrode 8.

  As shown in FIG. 4, the sidewall 17 is located above the second low-concentration impurity regions 9 and 10 and almost completely overlaps the second low-concentration impurity regions 9 and 10 via the gate insulating film 3. ing. Therefore, the lengths of the sidewalls 17 and the second low-concentration impurity regions 9 and 10 are equal in the channel length direction.

  The sidewall 17 functions as a mask for forming the second low-concentration impurity regions 9 and 10. The sidewall 17 is usually formed by anisotropic etching, and has small dimensional variations in the direction parallel to the substrate. For this reason, it is possible to reduce the variation in the length of the second low-concentration impurity regions 9 and 10 formed using the sidewalls 17 as a mask, in the channel length direction, thereby achieving the TFT effect of the first embodiment. In addition, a TFT with little characteristic variation can be manufactured. The reason for this will be described with reference to FIGS.

  As shown in FIG. 5A, the sidewall 17 is formed of an insulating film 16 such as silicon oxide. After the insulating film 16 is deposited so as to cover the gate electrode 8, the insulating film 16 is etched by anisotropic etching such as reactive ion etching (RIE) or ion milling. For example, as shown in FIG. 5A, the substrate 1 is introduced into a reactive ion etching apparatus, and an electric field perpendicular to the substrate 1 is applied, so that the reactive gas is indicated by an arrow as indicated by an arrow. When accelerated in a direction perpendicular to the etching, the etching proceeds only in a direction perpendicular to the substrate 1. For this reason, as shown in FIG. 5B, the thickness of the insulating film 16 decreases while maintaining the profile (uneven shape) of the surface of the insulating film 16 before etching. As shown in FIG. 5C, when all the flat portions of the insulating film 16 are etched, the sidewalls 17 remain on the sides of the gate electrode 8.

  As shown in FIG. 5C, the sidewall 17 has a convex curved surface 17 a, and the curved surface 17 e has a large angle with respect to the substrate 1 at the end portion 17 e of the sidewall 17 that is not in contact with the gate electrode 8. Standing up at. For this reason, the position of the end portion 17 e is less likely to vary in the side wall 17 forming process in which etching is performed only in a direction that is mainly perpendicular to the substrate 1. As shown in FIG. 5C, when the variation amount δ1 due to etching is set to a portion close to parallel to the substrate 1 and the variation amount δ2 due to etching at the end portion 17e is assumed, δ2 << δ1. The length of the sidewall 17 in the gate length direction can be adjusted by changing the height of the gate electrode 8, etching conditions, and the thickness of the insulating film 16 for forming the sidewall 17.

  This means that the variation in length in the channel length direction of the second low-concentration impurity region 10 formed using the sidewall 17 as a mask is reduced. That is, according to the present embodiment, in addition to the effects of the TFT of the first embodiment, a TFT having uniform characteristics with little variation in the length in the channel length direction of the second low-concentration impurity region that is the offset region of the GOLD structure can be obtained. can get. Therefore, it is not necessary to form a large element in order to ensure a margin of transistor characteristics such as reliability and breakdown voltage, and a fine TFT can be manufactured. Such a feature is particularly suitable for the TFT used in an active matrix substrate of a display device or the like that is required to form a large number of switching elements with uniform characteristics, and for the reason described above. Therefore, it is suitable for a display device having fine pixels or a display device having a large number of pixels.

  The method for manufacturing the TFT 200 according to the present embodiment will be described below.

  First, as shown in FIG. 6A, a semiconductor layer 2 is formed on a transparent insulating substrate 1 such as quartz. The semiconductor layer 2 is made of, for example, amorphous silicon, polycrystalline silicon, single crystal silicon, or the like. When the semiconductor layer 2 is formed of polycrystalline silicon, an amorphous silicon thin film having a thickness of about 50 to 150 nm is deposited on the transparent insulating substrate 1 by a low pressure CVD (Low Power Chemical Vapor Deposition, hereinafter referred to as LPCVD) method. After that, high temperature heat treatment or laser annealing is performed to polycrystallize amorphous silicon. Thereafter, patterning is performed by a photolithography process and an etching process to form a semiconductor layer 2 having a predetermined shape. Thereafter, a p-type impurity for controlling the threshold value of the transistor may be added by implantation or the like, if necessary.

  Next, as shown in FIG. 6B, a gate insulating film 3 having a thickness of about 100 nm is formed on the semiconductor layer 2. The gate insulating film can be deposited by, for example, a CVD (Chemical Vapor Deposition) method. The gate insulating film 3 may be formed by oxidizing the surface of the formed semiconductor layer 2.

As shown in FIG. 6C, a region to be the channel region 4 in the semiconductor layer 2 is covered with a resist 5, and a p-type impurity element is added to the semiconductor layer 2 by ion implantation (first impurity addition step). As a result, regions 6 ′ and 7 ′ having the same impurity concentration as the first low-concentration impurity regions 6 and 7 are formed in the semiconductor layer 2. In the first impurity addition step, for example, n-type impurities such as phosphorus and arsenic are performed at a dose of 5 × 10 ¹² to 1 × 10 ¹⁴ / cm ² . A region where impurities are not implanted by the resist 5 becomes a channel region 4. This step defines the channel region 4.

As shown in FIG. 6D, after the resist 5 is removed, a gate electrode 8 is formed on the gate insulating film 3. The gate electrode 8 is formed by depositing a film made of WSi or the like having a thickness of about 300 nm using, for example, sputtering or LPCVD, and then patterning so as to cover the channel region 4 and part of the regions 6 ′ and 7 ′. Is obtained. Regions 6 ′ and 7 ′ covered with the gate electrode 8 are defined in the semiconductor layer 2 as first low-concentration impurity regions 6 and 7. The gate electrode 8 may be phosphorus-doped polycrystalline silicon (N ⁺ poly-Si), or may have a structure in which WSi or the like is further laminated thereon.

  As shown in FIG. 6E, using the gate electrode 8 as a mask, an impurity element is added to the semiconductor layer 2 by ion implantation (second impurity addition step) to form regions 9 'and 10'. The impurity concentration of the regions 9 ′ and 10 ′ is equal to that of the second low concentration impurity region. The region where the impurity element is not implanted by the gate electrode 8 becomes the first low-concentration impurity regions 6 and 7 and functions as an overlap region of the GOLD structure.

  Depending on the conductivity type of the impurity element added in the second impurity addition step, the carrier concentration of the second low-concentration impurity region can be made higher or lower than that of the first low-concentration impurity regions 6 and 7.

When the carrier concentration of the second low-concentration impurity region is higher than that of the first low-concentration impurity regions 6 and 7, an impurity element having the same conductivity type as that of the impurity used in the first impurity addition step is used. Specifically, n-type impurities such as phosphorus and arsenic are implanted into the semiconductor layer 2 at a dose of 5 × 10 ¹² to 1 × 10 ¹⁴ / cm ² .

When the carrier concentration of the second low-concentration impurity region is lower than that of the first low-concentration impurity regions 6 and 7, an impurity element having a conductivity type opposite to that of the impurity used in the first impurity addition step is used. Specifically, p-type impurities such as boron are implanted into the semiconductor layer 2 at a dose of 1 × 10 ¹² to 1 × 10 ¹⁴ / cm ² . Due to the counter-doping, the carriers generated by the impurities implanted in the first impurity addition step are canceled by the carriers generated by the impurities implanted in the second impurity addition step, and the carrier concentration of the second low-concentration impurity region is the first concentration. It becomes lower than the carrier concentration of the low concentration impurity region.

  When the carrier concentration of the second low concentration impurity region is made equal to that of the first low concentration impurity regions 6 and 7, this second impurity addition step is omitted.

  Next, as shown in FIG. 7A, an insulating film 16 is formed so as to cover the gate electrode 8 and the gate insulating film 3. As the insulating film 16, a silicon oxide film or a high temperature oxide film (HTO) formed by sputtering or the like can be used. The thickness of the insulating film 16 is determined in the range of about 100 to 500 nm depending on the height of the gate electrode 8, the width of the sidewall to be formed, and the etching conditions. In this embodiment, the insulating film 16 made of 300 nm HTO having the same thickness as the gate electrode 8 is formed.

  As shown in FIG. 7B, the insulating film 16 is removed by anisotropic etching, and insulating sidewalls 17 are formed on the sides of the gate electrode 8. For anisotropic etching, an etching method such as RIE or ion milling is used. In this embodiment, etching is performed by RIE.

As shown in FIG. 7C, an n-type impurity element is added to the semiconductor layer 2 by ion implantation using the sidewall 17 as a mask (third impurity addition step), and the source region 11 and the drain region 12 are formed in the semiconductor layer. Formed in 2 and defined. Regions where impurity ions are not implanted by the sidewalls 17 are defined as second low-concentration impurity regions 9 and 10. Since the second low-concentration impurity regions 9 and 10 do not overlap the gate electrode 8, they become offset regions of the GOLD structure. The third impurity addition step is performed with an n-type impurity such as phosphorus or arsenic at a dose of 1 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² . Thereafter, annealing for activating impurity ions is performed.

  As shown in FIG. 4, after an insulating film is deposited on the entire surface and an interlayer insulating film 13 is formed, contact holes are formed on the source region 11 and the drain region 12 for electrode extraction. A source electrode 14 and a drain electrode 15 are formed by depositing a metal material such as Al in the interlayer insulating film 13 and the contact hole, and patterning it into a predetermined shape.

(Third embodiment)
The TFT of the present invention can be preferably used for an active matrix liquid crystal display device.
FIG. 8 shows a portion corresponding to one pixel region of the TFT substrate (active matrix substrate) of the projector active matrix liquid crystal display device to which the TFT 200 of the second embodiment is applied. The TFT 100 of the first embodiment may be used in place of the TFT 200. The pixel region is surrounded by a signal wiring 102 for supplying a signal voltage to the pixel electrode 106 and a gate wiring 104 for supplying a scanning signal to the gate electrode 8.

  A TFT 200 formed as a switching element for driving a pixel is provided in the vicinity of the intersection between the signal wiring 102 and the gate wiring 104. The source region 11 of the TFT 200 is electrically connected to the source electrode 14 constituting a part of the signal wiring 102, and the drain region 12 is electrically connected to the drain electrode 15 connected to the pixel electrode 106. In the form shown in FIG. 8, an auxiliary capacitance is not shown between the TFT 200 and the pixel electrode 106, but an auxiliary capacitance may be provided using an auxiliary capacitance wiring or the like.

  FIG. 9 schematically shows a pixel portion 112 provided with a plurality of pixel regions shown in FIG. 8 and an active matrix substrate 110 in which drive circuits 113 and 114 are provided on an insulating substrate 111 for driving the pixel portion 112. ing. The pixel unit 112 uses the TFT 200 of the second embodiment. Further, the TFTs 200 are also used for the drive circuits 113 and 114. As described in the first embodiment, in the TFT 200 of the pixel portion 112, the carrier concentration of the second low-concentration impurity region is set lower than that of the first low-concentration impurity region to reduce the OFF current. Further, in the TFT 200 of the drive circuits 113 and 114, the carrier concentration of the second low concentration impurity region is higher than that of the first low concentration impurity region to increase the ON current.

  FIG. 10 schematically shows an active matrix liquid crystal display device (LCD) 125 for a projector configured using the TFT substrate 110. The LCD 125 includes a TFT substrate 110, a counter substrate 121, and a liquid crystal layer 122 sandwiched between the TFT substrate 110 and the counter substrate 121. Note that the counter substrate 121 includes an insulating substrate and a counter electrode (common electrode) formed on the insulating substrate.

  In the case of a general TN mode liquid crystal display device, an alignment film (not shown) is provided on the surface of the TFT substrate 110 and the counter substrate 121 on the liquid crystal layer 122 side, and polarization is applied to the outside of the TFT substrate 110 and the counter substrate 121, respectively. A plate (not shown) is provided. Depending on the display mode, the alignment film and the polarizing plate can be omitted. In order to perform color display, a color filter (not shown) may be provided on the counter substrate 121.

  According to the LCD 125, the TFT of the pixel portion has a GOLD structure, and the OFF current is reduced by lowering the carrier concentration of the second low-concentration impurity region. For this reason, even a projector LCD that receives strong light from a light source can reduce light leakage current. Therefore, by using the LCD 125, a projector capable of displaying a high-quality image can be realized.

  In addition, since the second low-concentration impurity region is determined by a sidewall having small dimensional variations, it is possible to realize a projector LCD having a small pixel portion and a drive circuit while maintaining excellent switching characteristics. .

  According to the present invention, a TFT having a GOLD structure can be obtained in which the carrier concentration of the low concentration impurity region overlapping with the gate electrode and the low concentration impurity region not overlapping with the gate electrode can be independently adjusted. . In addition, since the low-concentration impurity region that does not overlap with the gate electrode can be defined by the sidewall, variation in element characteristics is small, and the outer shape of the TFT can be reduced. For this reason, it can be suitably used for various semiconductor devices using TFTs. In particular, by adjusting the carrier concentration of the two low-concentration impurity regions, a pixel unit in which a TFT with a small OFF current is used as a switching element and a driving unit in which a TFT with a large ON current is used are provided. A display device with a small structure can be realized.

It is sectional drawing which shows 1st Embodiment of the thin-film transistor of this invention. (A) to (e) are cross-sectional views showing one step in the method of manufacturing the thin film transistor shown in FIG. These are sectional drawings which show one process in the manufacturing method of the thin-film transistor shown in FIG. It is sectional drawing which shows 2nd Embodiment of the thin-film transistor of this invention. (A) to (c) is a cross-sectional view showing a manufacturing process of a sidewall used in the thin film transistor shown in FIG. (A) to (e) are cross-sectional views showing one step in the method of manufacturing the thin film transistor shown in FIG. (A) to (c) are cross-sectional views showing one step in the method of manufacturing the thin film transistor shown in FIG. It is a top view which shows the structure for one pixel area | region of the active matrix substrate of this invention. 1 is a schematic plan view showing a structure of an entire active matrix substrate of the present invention. It is a schematic diagram which shows the cross-section of the liquid crystal display device of this invention. It is sectional drawing which shows the conventional thin-film transistor. (A)-(e) is sectional drawing which shows 1 process in the manufacturing method of the conventional thin-film transistor shown in FIG. 11, respectively. (A) And (b) is sectional drawing which shows 1 process in the manufacturing method of the conventional thin-film transistor shown in FIG. 11, respectively. It is sectional drawing explaining that the position of the boundary of an overlap area | region and an offset area | region tends to fluctuate in the conventional thin-film transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Semiconductor layer 3 Gate insulating film 4 Channel region 5 Resist 6, 7 1st low concentration impurity region 8 Gate electrode 9, 10 2nd low concentration impurity region 11 Source region 12 Drain region 13 Interlayer insulating film 14 Source electrode 15 Drain electrode 16 Insulating film 17 Side wall 100, 200 TFT
102 signal wiring 104 gate wiring 106 pixel electrode 110 active matrix substrate (TFT substrate)
111 Insulating substrate 112 Pixel portion 113, 114 Drive circuit 121 Counter substrate 122 Liquid crystal layer 125 LCD
501 Transparent insulating substrate 502 Semiconductor layer 503 Gate insulating film 504 First conductive film 505 Second conductive film 506 Resist 507a, 507b Second gate electrode 508a, 508b, 508c First gate electrode 509 Source region 510 Drain region 511, 512 Low-concentration impurity region 511a, 512a Overlap region 511b, 512b Offset region 513 Channel region 514 Interlayer insulating film 515 Source electrode 516 Drain electrode

Claims (17)

A channel region, a pair of first low-concentration impurity regions provided to sandwich the channel region, and a pair of first low-concentration impurity regions provided to sandwich the pair of first low-concentration impurity regions. A semiconductor layer including a pair of second low-concentration impurity regions having a carrier concentration different from that of the region, and a pair of high-concentration impurity regions provided so as to sandwich the pair of second low-concentration impurity regions;
A gate insulating film provided to cover the semiconductor layer;
A gate provided on the gate insulating film, located above the channel region and the pair of first low-concentration impurity regions, and not located above the pair of second low-concentration impurity regions Electrodes,
A thin film transistor comprising: A channel region, a pair of first low-concentration impurity regions provided so as to sandwich the channel region, and a pair of second low-concentration impurity regions provided so as to sandwich the pair of first low-concentration impurity regions, A semiconductor layer including a pair of high-concentration impurity regions provided so as to sandwich the pair of second low-concentration impurity regions;
A gate insulating film provided to cover the semiconductor layer;
A gate provided on the gate insulating film, located above the channel region and the pair of first low-concentration impurity regions, and not located above the pair of second low-concentration impurity regions Electrodes,
A pair of insulating sidewalls provided on the sides of the gate electrode;
And the pair of second low-concentration impurity regions are respectively located below the pair of insulating sidewalls.   3. The thin film transistor according to claim 2, wherein in the channel length direction, the insulating sidewall and the second low-concentration impurity region have the same length. When the carrier concentrations of the first low-concentration impurity region, the second low-concentration impurity region, and the high-concentration impurity region are C _L1 C _L2 and C _H , respectively, C _L1 C _L2 and C _H are
C _L1 <C _L2 <C _H
The thin film transistor according to claim 1, wherein the relationship is satisfied. When the carrier concentrations of the first low-concentration impurity region, the second low-concentration impurity region, and the high-concentration impurity region are C _L1 C _L2 and C _H , respectively, C _L1 C _L2 and C _H are
C _L2 <C _L1 <C _H
The thin film transistor according to claim 1, wherein the relationship is satisfied. When the carrier concentrations of the first low-concentration impurity region, the second low-concentration impurity region, and the high-concentration impurity region are C _L1 C _L2 and C _H , respectively, C _L1 C _L2 and C _H are
C _L2 = C _L1 <C _H
The thin film transistor according to claim 2 or 3 satisfying the relationship: A thin film transistor defined in any one of claims 1 to 6, a signal wiring electrically connected to one of the high concentration impurity regions of the thin film transistor, a gate wiring electrically connected to the gate electrode, and the thin film transistor A substrate on which a pixel electrode electrically connected to the other of the high-concentration impurity regions is formed;
A liquid crystal layer that changes an optical state in accordance with a potential of the pixel electrode;
An active matrix liquid crystal display device. 6. A thin film transistor as defined in claim 5, a signal wiring electrically connected to one of the high concentration impurity regions of the thin film transistor, a gate wiring electrically connected to the gate electrode, and a high concentration impurity region of the thin film transistor A substrate including a pixel portion including a pixel electrode electrically connected to the other, and a driving unit configured to be driven by the thin film transistor defined in claim 4 and driving the pixel unit;
A liquid crystal layer that changes an optical state in accordance with a potential of the pixel electrode;
An active matrix liquid crystal display device. Forming a semiconductor layer on the insulating substrate (A);
Forming a gate insulating film covering the semiconductor layer (B);
(C) adding an impurity of a first conductivity type in a portion other than a portion to be a channel region in the semiconductor layer, and defining a channel region in the semiconductor layer;
A gate electrode is formed so as to cover the channel region and a portion of the semiconductor layer that is adjacent to the channel region and becomes a pair of first low-concentration impurity regions, and the first overlapped with the gate electrode Defining a low concentration impurity region in the semiconductor layer (D);
Forming a mask (E) adjacent to the semiconductor layer so as to sandwich the pair of first low-concentration impurity regions and covering at least a portion to be the pair of second low-concentration impurity regions;
Adding a first conductivity type impurity using the mask, forming a high concentration impurity region in the semiconductor layer, and defining a second low concentration impurity region in a portion covered by the mask ( F) and
A method of manufacturing a thin film transistor including   10. The method of manufacturing a thin film transistor according to claim 9, wherein the mask used in the step (E) is a resist mask that covers a portion to be the gate electrode and the pair of second low-concentration impurity regions.   The method of manufacturing a thin film transistor according to claim 9, wherein the mask used in the step (E) is an insulating sidewall provided adjacent to the gate electrode. In the step (E), the insulating sidewall is
Forming an insulating film so as to cover the gate electrode (e1);
A step (e2) of selectively etching the insulating film in a direction perpendicular to the substrate;
The manufacturing method of the thin-film transistor of Claim 11 formed by performing.   The method for manufacturing a thin film transistor according to claim 9, wherein impurity concentrations of the first low-concentration impurity region and the second low-concentration impurity region are substantially equal.   12. The method of manufacturing a thin film transistor according to claim 8, further comprising a step (G) of adding a first conductivity type impurity to the semiconductor layer using the gate electrode as a mask after the step (D). . When the carrier concentrations of the first low-concentration impurity region, the second low-concentration impurity region, and the high-concentration impurity region are C _L1 C _L2 and C _H , respectively, C _L1 C _L2 and C _H are
C _L1 <C _L2 <C _H
The manufacturing method of the thin-film transistor of Claim 14 which satisfy | fills these relationships.   13. The method of manufacturing a thin film transistor according to claim 9, further comprising a step (G) of adding a second conductivity type impurity to the semiconductor layer using the gate electrode as a mask after the step (D). . When the carrier concentrations of the first low-concentration impurity region, the second low-concentration impurity region, and the high-concentration impurity region are C _L1 C _L2 and C _H , respectively, C _L1 C _L2 and C _H are
C _L2 <C _L1 <C _H
The manufacturing method of the thin-film transistor of Claim 16 which satisfy | fills the relationship of these.

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