JP2005197495A - Electrostatic protection element and its fabrication process, and semiconductor device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrostatic protection element exhibiting excellent electrostatic breakdown voltage in which rising voltage is designed freely while reducing the size, and also to provide a semiconductor device in which the electrostatic protection element and an active element, e.g. an HEMT, are provided on the same substrate. <P>SOLUTION: A first active layer containing first conductivity type impurities is formed on a semiconductor substrate, a first electrode is provided on the first active layer, a second active layer containing second conductivity type impurities is formed on a partial region of the first active layer, a third active layer containing first conductivity type impurities is formed on the second active layer, and a second electrode is formed on the third active layer. An electrostatic protection element of such an arrangement and a high electron mobility transistor are provided on the same substrate on which the active layer is formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an electrostatic protection element and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof.

  Conventionally, an electrostatic protection element has been provided in a semiconductor device in order to prevent the semiconductor device from being destroyed when a surge current due to static electricity flows through the input terminal of the semiconductor device. Further, when manufacturing a semiconductor device including such an electrostatic protection element, a method of simultaneously forming an electrostatic protection element and an active element such as a field effect transistor provided in an internal circuit including a logic circuit or the like is known.

  As an example of the active element, a high electron mobility transistor (HEMT) is known. Among field effect transistors using compound semiconductors, the high electron mobility transistor using an epitaxial substrate (hereinafter referred to as “HEMT”) has high electron mobility and excellent high frequency characteristics. Widely used in the field of high frequency regions such as circuits.

  However, the HEMT has a low strength against electrostatic breakdown due to its structure. In particular, as described above, the bias adjustment circuit and the antenna switch logic in the power amplifier used in the RF transmission / reception circuit of the cellular phone are used. A HEMT having a small gate width, for example, 10 to 20 μm, incorporated in a circuit has only a very low electrostatic withstand voltage and is prone to electrostatic breakdown. Therefore, it is essential to provide an electrostatic protection element. A semiconductor device having a configuration has been proposed (see, for example, Patent Document 1).

  Here, an example of a semiconductor device including a conventional electrostatic protection element and a HEMT is shown in FIGS. FIG. 9 is an explanatory view of the semiconductor device in a sectional view, and FIG.

  In FIG. 9, reference numeral 100 denotes a GaAs semi-insulating substrate, on which a GaAs buffer layer 110, an InGaAs channel layer 120, an AlGaAs spacer layer 130, an AlGaAs doping layer 140, an AlGaAs barrier layer 150, and a GaAs cap layer 160 are sequentially formed. It is epitaxially grown. Reference numeral 170 denotes an insulating film made of, for example, silicon nitride (SiN) formed on the GaAs cap layer 160. Reference numeral 180 denotes an element isolation region, which performs element isolation by etching. Reference numeral 191 denotes a HEMT gate electrode, and reference numerals 192 and 193 denote two electrodes of the electrostatic protection element, each of which is a Schottky electrode. Reference numerals 194 and 195 denote ohmic electrodes serving as the source and drain of the HEMT.

As described above, the electrostatic protection element in the IC using the HEMT is formed by the GaAs cap layer 160 serving as an active layer and the two Schottky electrodes 192 and 193 bonded thereto.
JP 2002-9253 A

  However, the GaAs cap layer 160 serving as an active layer of the electrostatic protection element is originally an epitaxial layer for reducing the contact resistance of the source electrode and the drain electrode of the HEMT, and generally has a thickness of about 50 nm. Only it is.

  For this reason, the electrostatic protection element provided with the GaAs cap layer 160 as an active layer has to have a large device width D as shown in FIG. 10 so that a large current caused by a surge can flow.

  As described above, since the electrostatic protection element that has to widen the device width D so as to obtain a sufficient electrostatic withstand voltage has a large area on the semiconductor device, This is a factor that prevents further miniaturization.

  An object of the present invention is to provide an electrostatic protection element and a manufacturing method thereof, a semiconductor device and a manufacturing method thereof that can solve the above-described problems.

  According to the first aspect of the present invention, a first active layer containing a first conductivity type impurity is formed on a semiconductor substrate, and a first electrode is provided on the first active layer. Forming a second active layer containing a second conductivity type impurity on a partial region of the active layer, and a third active layer containing the first conductivity type impurity on the second active layer; An electrostatic protection element in which a layer was formed and a second electrode was formed on the third active layer was obtained.

  According to a second aspect of the present invention, there is provided a semiconductor device in which a high electron mobility transistor and an electrostatic element are provided on the same substrate on which an active layer is formed. The first electrode is provided in the first active layer containing the type impurity, and the second active layer containing the second conductivity type impurity is formed on a partial region of the first active layer. A third active layer containing a first conductivity type impurity was formed on the second active layer, and a second electrode was formed on the third active layer.

  According to a third aspect of the present invention, a first active layer containing a first conductivity type impurity is formed on a semiconductor substrate, and a first electrode is provided on the first active layer, while the first electrode Forming a second active layer containing a second conductivity type impurity on a partial region of the active layer, and a third active layer containing the first conductivity type impurity on the second active layer; A method for manufacturing an electrostatic protection element is provided in which a layer is formed and a second electrode is formed on the third active layer.

  According to a fourth aspect of the present invention, there is provided a semiconductor device manufacturing method in which a high electron mobility transistor and an electrostatic element are provided on the same substrate on which an active layer is formed. A first electrode is provided on a first active layer containing one conductivity type impurity, and a second active layer containing a second conductivity type impurity is provided on a partial region of the first active layer. In addition, a third active layer containing a first conductivity type impurity is formed on the second active layer, and a second electrode is formed on the third active layer.

  (1) In the first aspect of the present invention, a first active layer containing a first conductivity type impurity is formed on a semiconductor substrate, and a first electrode is provided on the first active layer, A second active layer containing a second conductivity type impurity is formed on a partial region of the first active layer, and a second conductivity layer containing the first conductivity type impurity is formed on the second active layer. 3 active layers were formed, and a second electrode was formed on the third active layer. Therefore, the stacked first to third active layers can provide an electrostatic protection element having a structure equivalent to a structure in which two pn-junction diodes are arranged vertically, and a current caused by a surge or the like can flow in the vertical direction. Therefore, the device width can be made smaller than the conventional electrostatic element in which two electrodes are Schottky-bonded to one active layer, and the electrostatic protection element can be miniaturized.

  (2) A second aspect of the present invention provides a semiconductor device in which a high electron mobility transistor and an electrostatic element are provided on the same substrate on which an active layer is formed. A first electrode is provided on a first active layer containing one conductivity type impurity, and a second active layer containing a second conductivity type impurity is provided on a partial region of the first active layer. At the same time, a third active layer containing a first conductivity type impurity was formed on the second active layer, and a second electrode was formed on the third active layer. Therefore, the stacked first to third active layers can provide a semiconductor device including an electrostatic protection element having a structure equivalent to a structure in which two pn-junction diodes are vertically arranged. In this case, current due to surge or the like can flow in the vertical direction, so that the device width can be made smaller than a conventional electrostatic element in which two electrodes are Schottky bonded to one active layer, which contributes to miniaturization of a semiconductor device. it can.

  (3) In the present invention according to claim 3, a first active layer containing a first conductivity type impurity is formed on a semiconductor substrate, and a first electrode is provided on the first active layer, A second active layer containing a second conductivity type impurity is formed on a partial region of the first active layer, and a second conductivity layer containing the first conductivity type impurity is formed on the second active layer. 3 active layers were formed, and a second electrode was formed on the third active layer. Therefore, the stacked first to third active layers can provide an electrostatic protection element having a structure equivalent to a structure in which two pn-junction diodes are arranged vertically, and a current caused by a surge or the like can flow in the vertical direction. Therefore, it is possible to provide a small electrostatic protection element having a device width smaller than that of a conventional electrostatic element in which two electrodes are Schottky bonded to one active layer.

  (4) The present invention according to claim 4 is a method of manufacturing a semiconductor device in which a high electron mobility transistor and an electrostatic element are provided on the same substrate on which an active layer is formed, wherein the electrostatic protection element Provides a first electrode on a first active layer containing a first conductivity type impurity, while a second electrode containing a second conductivity type impurity on a partial region of the first active layer. An active layer is formed, and a third active layer containing a first conductivity type impurity is formed on the second active layer, and a second electrode is formed on the third active layer. . Therefore, the stacked first to third active layers can provide a semiconductor device including an electrostatic protection element having a structure equivalent to a structure in which two pn-junction diodes are vertically arranged. Then, since a current caused by a surge or the like can flow in the vertical direction, it is possible to provide a small semiconductor device having a device width smaller than that of a conventional electrostatic element in which two electrodes are Schottky bonded to one active layer. Become.

  In the present invention, a first active layer containing a first conductivity type impurity is formed on a semiconductor substrate, and a first electrode is provided on the first active layer, while one of the first active layers is provided. Forming a second active layer containing a second conductivity type impurity on the partial region, and forming a third active layer containing the first conductivity type impurity on the second active layer; A second electrode is formed on the third active layer.

  That is, in the electrostatic element according to the present embodiment, when the first conductivity type is n-type and the second conductivity type is p-type, the n-type doping layer and the p-type doping layer that are epitaxially grown on the semiconductor substrate are The n-type doping layer is used, and the electrodes of the electrostatic protection element are formed on the two n-type doping layers to form a diode structure.

  As described above, the electrostatic protection element according to the present embodiment has a structure equivalent to a structure in which two pn junction diodes are vertically arranged by the first to third active layers stacked on the semiconductor substrate. It is an electrostatic protection element, and can cause a current due to a surge or the like to flow in the vertical direction. Therefore, the device width can be made smaller than that of a conventional electrostatic element in which two electrodes are Schottky bonded to one active layer, and the electrostatic protection element can be reduced in size.

  This electrostatic protection element is suitable when provided on the same substrate as a high electron mobility transistor (hereinafter referred to as “HEMT: High Electron Mobility Transistor”) having a conductive impurity-containing layer as an active layer.

  That is, a semiconductor device in which an electrostatic protection element is provided on a part of or on a HEMT structure, and a high electron mobility transistor and an electrostatic element are provided on the same substrate on which an active layer is formed. In the electrostatic protection element, the first electrode is provided in the first active layer containing the first conductivity type impurity, and the second conductivity type impurity is provided on a partial region of the first active layer. And a second active layer containing a first conductivity type impurity is formed on the second active layer, and a second electrode is formed on the third active layer. Can be formed.

  Even in such a semiconductor device, the stacked first to third active layers can be a semiconductor device including an electrostatic protection element having a structure equivalent to a structure in which two pn junction diodes are vertically arranged. In the electrostatic protection element, current due to surge or the like can flow in the vertical direction, so that the device width can be made smaller than the conventional electrostatic element in which two electrodes are Schottky bonded to one active layer, thereby reducing the size of the semiconductor device. Can contribute.

  As described above, by using the electrostatic protection element according to the present embodiment and the manufacturing method thereof, the rising voltage of the electrostatic protection element in the IC using HEMT can be freely designed, and the electrostatic withstand voltage is excellent. It is possible to manufacture a small semiconductor device.

  Hereinafter, embodiments of the present invention will be described more specifically with reference to the drawings. FIG. 1 is a cross-sectional view illustrating a semiconductor device according to the present embodiment in which a HEMT and an electrostatic protection element are provided on the same substrate.

  As shown in FIG. 1, the semiconductor device according to the present embodiment has a GaAs buffer layer 32, an InGaAs channel layer 33, an AlGaAs spacer layer 34, an AlGaAs on a GaAs semi-insulating substrate 31 as in the conventional structure. A doping layer 35, an AlGaAs barrier layer 36, and a first GaAs cap layer 37 serving as a first active layer of the electrostatic protection element are stacked, and an electrostatic protection element for forming the electrostatic protection element In the formation region 10, a p-AlGaAs layer 38 and a second GaAs cap layer 39 serving as a second active layer are epitaxially grown sequentially.

  The p-AlGaAs layer 38 is doped with a p-type impurity made of, for example, Zn.

  The second GaAs cap layer 39 is doped with the same n-type impurity as that of the first GaAs cap layer 37, that is, Si in the present embodiment.

  A part of the p-AlGaAs layer 38 and the second GaAs cap layer 39 are removed by etching.

  A first electrode 11 is formed on the first GaAs cap layer 37, and a second electrode 12 is formed on the second GaAs cap layer 39, each forming an ohmic electrode. .

  On the other hand, the p-AlGaAs layer 38 and the second GaAs cap layer 39 other than the electrostatic protection element formation region 10 are etched away as described above, and the first GaAs cap layer 37 is also separated from the electrostatic protection element formation region 10. The portions other than the HEMT source electrode forming portion 21 and the drain electrode forming portion 22 are removed by etching. In FIG. 1, 21a is a HEMT source electrode made of an ohmic electrode, 22a is a HEMT drain electrode also made of an ohmic electrode, 23 is a HEMT gate electrode made of a Schottky electrode, and 40 is an insulating film made of SiN. .

  In addition, the element separation in the present embodiment is performed by removing the epitaxial layer by etching, but the element separation can also be performed by ion implantation with boron, for example.

  With the above configuration, the electrostatic protection element according to the present embodiment has a diode structure including the first electrode 11 and the second electrode 12, and the rising voltage is the p-type impurity concentration of the p-AlGaAs layer 38, the film It can be freely controlled by the thickness and the Al composition ratio.

  Thus, according to the present embodiment, a current due to a surge or the like flows in the longitudinal direction of the epitaxial structure constituted by the first GaAs cap layer 37, the p-AlGaAs layer 38, and the second GaAs cap layer 39. Thus, it is possible to reduce the size as compared with a structure in which two electrodes are Schottky bonded to one active layer as in a conventional electrostatic element.

  Here, a procedure for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 2, on a GaAs semi-insulating substrate 31, a GaAs buffer layer 32, an InGaAs channel layer 33, an AlGaAs spacer layer 34, an AlGaAs doping layer 35 necessary for forming a HEMT, An AlGaAs barrier layer 36, a first GaAs cap layer 37, a p-AlGaAs layer 38, and a second GaAs cap layer 39 are sequentially epitaxially grown.

  Here, the p-AlGaAs layer 38 is doped with a p-type impurity made of, for example, Zn, and its concentration is determined by the value of the rising voltage required for the electrostatic protection element. Further, the Al composition ratio and the film pressure are also determined by the rising voltage value in the same manner as the doping concentration.

  Further, as described above, the second GaAs cap layer 39 is doped with the same n-type impurity (Si) as the first GaAs cap layer 37 at the same concentration.

  Next, as shown in FIG. 3, a device formed by an epitaxial layer, that is, an epitaxial layer other than the HEMT forming region 20 for forming the HEMT and the electrostatic element forming region 10 for forming the electrostatic protection element in the present embodiment. The layer is etched away with, for example, an etchant composed of a mixture of phosphoric acid, hydrogen peroxide, and water.

  Next, as shown in FIG. 4, except for a part of the electrostatic protection element formation region 10, the p-AlGaAs layer 38 and the second GaAs cap layer 39 are removed by etching with the same etching solution.

  Thereafter, as shown in FIG. 5, the first GaAs cap layer 37 is formed, for example, by leaving a part of the electrostatic protection element forming region 10 and the source electrode forming portion 21 and the drain electrode forming portion 22 in the HEMT forming region 20. Etch away using a mixture of acid and hydrogen peroxide.

  Next, as shown in FIG. 6, after depositing an insulating film 40 made of, for example, SiN, a part of the electrostatic protection element forming region 10 is opened at two places simultaneously, and the first opening 40 a and the second opening 40 b are formed. Provide. At this time, the first opening 40 a is formed on the first GaAs cap layer 37 and the second opening 40 b is formed on the second GaAs cap layer 39.

  Next, the same material as that of the source electrode 21a and the drain electrode 22a (see FIG. 1) of the HEMT, that is, a multilayer film of AuGe, Ni, and Au is deposited on the first opening 40a and the second opening 40b. The first electrode 11 and the second electrode 12 are formed by depositing and patterning by sputtering, as shown in FIG.

  Thereafter, the contact resistances of the HEMT source electrode 21a and drain electrode 22a, the first electrode 11 and the first GaAs cap layer 37, and the second electrode 12 and the second GaAs cap layer 39 are reduced. Perform alloy processing.

  Finally, the HEMT gate electrode 23 is formed, and the electrodes of the respective elements are connected by wiring, whereby the semiconductor device in which the HEMT and the electrostatic element shown in FIG. 1 are provided on the same substrate is completed. Become.

  The electrostatic protection element in the semiconductor device manufactured by the above-described procedure includes the first GaAs cap layer 37 that is an n-type doping layer epitaxially grown on the GaAs semi-insulating substrate 31 and the p-type doping layer p. It is formed by the AlGaAs layer 38 and the second GaAs cap layer 39 which is an n-type doping layer. Since the first electrode 11 and the second electrode 12 of the electrostatic protection element are respectively formed in two n-type doping layers to form a diode structure, a wide pn junction surface can be taken. The current due to surge or the like can flow in the vertical direction, and the device width can be reduced and the device can be downsized.

It is explanatory drawing by the cross sectional view which shows the semiconductor device which concerns on this Embodiment. FIG. 27 is an explanatory diagram showing a manufacturing process of the semiconductor device. FIG. 27 is an explanatory diagram showing a manufacturing process of the semiconductor device. FIG. 27 is an explanatory diagram showing a manufacturing process of the semiconductor device. FIG. 27 is an explanatory diagram showing a manufacturing process of the semiconductor device. FIG. 27 is an explanatory diagram showing a manufacturing process of the semiconductor device. FIG. 27 is an explanatory diagram showing a manufacturing process of the semiconductor device. It is explanatory drawing by the cross sectional view of the conventional semiconductor device. It is explanatory drawing by the planar view which shows the electrostatic protection element part of the semiconductor device.

Explanation of symbols

31 GaAs semi-insulating substrate 32 GaAs buffer layer 33 InGaAs channel layer 34 AlGaAs spacer layer 35 AlGaAs doping layer 36 AlGaAs barrier layer 37 first GaAs cap layer 38 p-AlGaAs layer 39 second GaAs cap layer

Claims (4)

  A first active layer containing a first conductivity type impurity is formed on a semiconductor substrate, and a first electrode is provided on the first active layer, while a first electrode is provided on a partial region of the first active layer. , Forming a second active layer containing a second conductivity type impurity and forming a third active layer containing a first conductivity type impurity on the second active layer, An electrostatic protection element, wherein a second electrode is formed on an active layer. A semiconductor device in which a high electron mobility transistor and an electrostatic element are provided on the same substrate on which an active layer is formed,
The electrostatic protection element is
A first active layer containing a first conductivity type impurity is provided with a first electrode, and a second active layer containing a second conductivity type impurity is formed on a partial region of the first active layer. And a third active layer containing a first conductivity type impurity is formed on the second active layer, and a second electrode is formed on the third active layer. Semiconductor device.   A first active layer containing a first conductivity type impurity is formed on a semiconductor substrate, and a first electrode is provided on the first active layer, while a first electrode is provided on a partial region of the first active layer. , Forming a second active layer containing a second conductivity type impurity and forming a third active layer containing a first conductivity type impurity on the second active layer, A method of manufacturing an electrostatic protection element, wherein a second electrode is formed on an active layer. A method of manufacturing a semiconductor device in which a high electron mobility transistor and an electrostatic element are provided on the same substrate on which an active layer is formed,
The electrostatic protection element is
A first active layer containing a first conductivity type impurity is provided with a first electrode, and a second active layer containing a second conductivity type impurity is formed on a partial region of the first active layer. And a third active layer containing a first conductivity type impurity is formed on the second active layer, and a second electrode is formed on the third active layer. A method for manufacturing a semiconductor device.

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