JP2005196802A - Design supporting method for lsi - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate efficient countermeasures by specifying an EMI generation part for an analysis-processed LSI. <P>SOLUTION: This LSI design supporting method comprises: an unnecessary radiation analyzing process for analyzing the unnecessary radiation quantity of an LSI by the execution of simulation; a process for selecting an instance whose noise quantity is large in the unnecessary radiation analyzing process; and a process for adjusting the driving capability of an instance to drop to such extent that any delay is not generated in the signal timing of the selected instance. At the time of optimizing the analyzed unnecessary radiation, the part whose optimization is necessary is extracted, and measures to the necessary part is taken only by the necessary quantity by, for example, taking measures to increase the creation area of a decoupling capacitance. Also, the aspect ratio of the block is changed, the block position is changed, and a cell line is changed, so that the decoupling capacitance can be easily created at the most effective insertion position. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an LSI design support method, and in particular, performs a high-speed and high-precision simulation for a large-scale and high-speed driving LSI (large-scale semiconductor integrated circuit) and performs unnecessary radiation (EMI: Electromagnetic) by electromagnetic radiation. The present invention relates to a method for supporting LSI design so as to optimize the interference.

  LSIs are used not only for computers but also for communication devices such as mobile phones, general household products, toys, and automobiles. However, on the other hand, unnecessary radiation generated from these products has become a problem as a cause of radio interference of receivers such as televisions and radios and malfunctions of other systems. Countermeasures for the entire product, such as filtering and shielding, have been taken to deal with these problems, but noise suppression as an LSI package is strong from the viewpoint of increasing the number of parts, increasing costs, and difficulty in taking countermeasures on products. It has been requested.

  Under such circumstances, the LSI is positioned as a key device in each product, and it is required to increase the scale and speed of the LSI in order to ensure the competitiveness of the product. As product cycles become shorter, it is essential to automate LSI design in order to meet these requirements, and there is an increasing need to adopt synchronous design as a condition for the introduction of current design automation technology. In the case of a large-scale and high-speed driving LSI, all the circuits operate in synchronization with the reference clock, and the instantaneous current becomes very large, which causes an increase in unnecessary radiation.

The present invention relates to a simulation method capable of performing EMI evaluation, which is indispensable for reducing unnecessary radiation while maintaining large scale and high speed of LSI.
There are two types of noise that causes damage to LSI: radiation noise and conduction noise. There is noise radiated from the internal wiring of the LSI as direct radiation noise from the LSI, but the internal wiring is not large as an antenna. Of course, it is considered that noise directly radiated from the LSI will become a problem in the future as the operating frequency of the LSI is improved, but at present, the radiated noise inside the LSI is not at a problem level.

  In contrast, conduction noise affects other devices on the printed circuit board through direct connections such as wires, lead frames, packages and wiring on the printed circuit board in LSIs, and the source of these connection paths. That is, noise is radiated as an antenna. The antenna formed by this connection path is much larger than the wiring inside the LSI, and is a dominant element in considering unnecessary radiation.

There are a power source and a signal as a path of conduction noise from the LSI, but when considering a nearby electromagnetic field, it is considered that a change in the current of the power source is dominated by noise radiated from the power source line as an antenna. In addition to this power source, the package or measurement system often becomes a problem.
For example, EMI noise in LSIs has become an important issue in recent years, and the IEC (International Electrotechnical Commission) is trying to standardize the measurement method for LSI EMI noise. Analysis methods such as the magnetic probe method and VDE method Has been proposed.
As a result, LSI vendors can get on the same ground and appeal to customers the EMI noise performance of their LSIs, and customers can also compare absolute LSIs in terms of EMI noise. In addition, if this standard measurement method becomes widespread, it is likely that the LSI EMI noise standards will be established.
However, since the measurement system (measurement apparatus and printed circuit board for measurement) has not been considered in the past, it has not been possible to determine whether or not the above-mentioned criteria are satisfied at the LSI development stage.
Further, in the signal, ringing and overshoot that occur when the signal changes may be a problem, but it is often a problem that the fluctuation of the LSI internal power level is conducted as a signal waveform. The noise radiated through both the power supply and signal paths is considered to be strongly correlated with changes in the power supply current.

  The power supply current of the CMOS circuit will be described using a simple inverter circuit. When the input voltage to the inverter circuit changes, load capacitance charge / discharge current, which is the main power supply current of the CMOS circuit, flows. In addition to this, a through current is added and flows. In designing such a CMOS circuit, synchronization is made due to restrictions in using an automatic design tool. However, since the entire LSI circuit operates simultaneously due to the synchronization, the power supply peak is synchronized with the reference clock. A current is generated. Moreover, in order to increase the speed, that is, to shorten the cycle, the transistor is enlarged so that it can be charged and discharged in a short time. As a result, the peak current increases. Naturally, the power supply current of the entire LSI increases as the LSI becomes larger. In this way, the peak current of the power supply increases, and the power supply current changes abruptly. However, this abrupt change increases the harmonic component, leading to an increase in unnecessary radiation. Yes.

It is considered effective to evaluate the unnecessary radiation in the LSI by performing a highly accurate simulation on the change of the power supply current, which can be said to be a main factor of the unnecessary radiation.
Conventionally, as shown below, a current simulation method for performing current analysis at the transistor level has been used.

  FIG. 47 is a block diagram showing a processing flow of a conventional EMI analysis method using a transistor level current analysis method. In this method, layout parameter extraction (hereinafter referred to as LPE) processing 4703 is performed from the layout information of the LSI to be analyzed, and circuit simulation 4706, current source modeling processing 4708, power supply wiring LPE processing 4710 for the switch level netlist, Each step of the transient analysis simulation 4712 and the FFT processing 4714 is performed.

Hereinafter, each step will be described with reference to FIG.
In step 4703, the layout data 4701 of the semiconductor integrated circuit to be analyzed by EMI, transistor elements, various wiring parasitic elements (resistance, capacitance, etc.), parameter values of each element, and LPE rule 4702 defining the output format of the extraction results are defined. Is input, the parameters of each element in the layout data 4701 are calculated based on the LPE rule 4702, and a netlist 4704 is generated. In this step, the parasitic elements of the power supply (and ground) wiring are not extracted.

  In step 4706, the net list 4704 generated in step 4703 and a test pattern 4705 for reproducing a desired logical operation in the analysis target circuit are input, and the load capacitance is charged / discharged according to the operation state of the internal circuit. A charge / discharge current, a through current, and the like are calculated, and current waveform information 4707 for each transistor is generated. In the first process of this step, the process is performed assuming that the power supply (and ground) potential is an ideal potential without fluctuation.

  In step 4708, the current waveform information 4707 for each transistor generated in step 4706 is input, and each is modeled into a format applicable in the subsequent step 4712, and current source element model information 4709 is generated. In order to reduce the processing load in the subsequent step 4712, a method of modeling as a current source element for each functional circuit block composed of a plurality of transistors is generally used.

  Step 4710 differs from Step 4703 only in that the extraction target is replaced with the parasitic elements (resistance, decoupling capacitance, etc.) of the power supply and the ground wiring from the transistor elements and various wiring parasitic elements to be subjected to EMI analysis. Therefore, explanation is omitted. In this step, a power supply (and ground) wiring net list 4711 is generated.

  In step 4712, the current source element model information 4709 generated in step 4708, the power (and ground) wiring netlist 4711 generated in step 4710, and the impedance (resistance, capacitance, inductance) 4716 of the wire or lead frame are input. Then, an analysis using a transient analysis simulator typified by SPICE generates a power supply voltage drop result 4717 in which the power supply voltage fluctuation of the analysis target circuit is calculated.

  Thereafter, the reprocessing of Step 4706 is performed. At this time, in the first processing of step 4706, the power supply (and ground) potential is assumed to be an ideal potential without fluctuation, whereas here, the power supply voltage drop result 4717 generated from step 4712 is input, The current waveform information 4707 for each transistor taking into account the power supply voltage variation is generated again. Similarly, the reprocessing of steps 4708 and 4712 is performed.

  By repeating the loop processing of steps 4706, 4708, and 4712 a plurality of times, a current waveform result 4713 that reproduces the power supply voltage fluctuation with higher accuracy is generated. In step 4714, the current waveform result 4713 generated in step 4712 is input, and by performing fast Fourier transform (hereinafter referred to as FFT), it becomes possible to perform frequency spectrum analysis and obtain an EMI analysis result 4715. I can do it.

  In this conventional example, although the verification accuracy largely depends on the LPE processing 4703, the power supply wiring LPE processing 4710, and the current source modeling processing 4708, a certain level of analysis accuracy can be expected. However, since a transient analysis simulator typified by SPICE is used for such transistor level current analysis, the circuit scale subject to EMI analysis is limited and the processing time is long. With the increase in scale of semiconductor integrated circuits, in recent years, establishment of an EMI analysis method that has a higher level of abstraction than the transistor level and enables high-speed analysis is desired.

  In addition, the power line network has been enlarged due to the increase in the size of the chip and the increase in the number of elements, and the increase in the processing time is becoming a major obstacle in the unnecessary radiation analysis. In order to shorten the processing time, reduction means for the resistance / capacitance of these power supply lines have also been proposed, but they are limited to gate arrays in which the power supply lines have a lattice structure.

  Even if the EMI analysis is performed by performing FFT on the power supply current value, the designer finally determines the FFT characteristics. This means that it takes a very long time or is impossible to identify the cause, and there is also a problem that it is not sufficient as analysis information to directly reflect it in correction.

  The measurement system also has a problem that the processing time increases depending on the scale and elements of the measurement system itself, and cannot be ignored in unnecessary radiation analysis.

  As described above, the conventional unnecessary radiation analysis method for LSI is based on the fact that the power supply and ground, and thus the measurement system, take into account the decoupling due to resistance, capacitance, and inductance and the high-speed processing, and the unnecessary radiation analysis result is quickly reflected in the design. It was not enough from the viewpoint.

  Thus, in recent years when semiconductor integrated circuits are becoming larger in scale, it is desired to establish an EMI analysis method using a gate level current analysis method that has a higher abstraction level than a transistor level and enables high-speed analysis. Various proposals have been made. Under such circumstances, a sufficient technique has not been established as an optimization measure according to the analyzed unnecessary radiation information, and various studies have been repeated.

  Further, even if EMI analysis is performed, it is unclear which circuit is the main cause, and there is a problem that it is not known which circuit is effective for improving EMI.

  Therefore, by reflecting the influence of decoupling due to the resistance, capacitance, and inductance of the power supply and ground in the power supply current calculation while performing high-speed analysis, the unnecessary radiation of the LSI can be evaluated in a realistic time on the simulation. In order to provide an unnecessary radiation analysis method and apparatus, the present inventors assign a FFT analysis discrete width for each frequency band and model the current change information calculated by the modeling process using fast Fourier transform. An unnecessary radiation analysis method including a conversion process is proposed (Japanese Patent No. 2000-63783). In this method, the influence of the decoupling capacitance on the FFT result cannot be expressed, and if it is expressed, it is only possible to widen the bottom of the triangle. There was a problem that could not.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to make it possible to specify an EMI occurrence location for an LSI that has been subjected to analysis processing and to take an efficient countermeasure.

  Therefore, in the present invention, an analysis step of analyzing the waveform of the power supply current of the LSI by executing a simulation, a step of extracting a block or instance having a large amount of noise in the analysis step, and the extracted block or instance Depending on the design stage, the power noise reduction processing, the analysis is performed again, the analysis step until the noise amount becomes smaller than a predetermined value, the instance extraction step, and the power noise reduction processing are performed. It is characterized in that the steps to be performed are repeated.

  In the present invention, the step of performing power supply noise processing according to the design stage includes the first step of performing layout data change processing in the floor plan stage.

  In the present invention, the step of performing the power supply noise reduction process according to the design stage includes a second process of performing layout data change processing in the layout stage.

  In the present invention, the first step includes a step of calculating a necessary amount of decoupling capacity from the peak current information of the target block extracted in the extracting step, and a decoupling capacity calculated in the calculating step. Including a step of calculating a shortage amount of the power source area from the above and a step of changing layout data based on the shortage amount.

  In the present invention, the second step includes a step of calculating a necessary amount of decoupling capacity from the peak current information of the target block extracted in the extracting step, and a decoupling capacity calculated in the calculating step. Including a step of calculating a shortage amount of the power source area from the above and a step of changing layout data based on the shortage amount.

  In the present invention, the first step includes a step of calculating a necessary amount of decoupling capacity from the peak current information of the target block extracted in the extracting step, and a decoupling capacity calculated in the calculating step. Including a step of calculating a shortage amount of the power source area from the above and a step of changing layout data for a necessary block based on the shortage amount.

  In the present invention, the step of changing the layout data includes a step of changing an aspect ratio of the target block, that is, an aspect ratio, and substantially changing a wiring area of the power supply current path.

  In the present invention, the step of changing the layout data includes a step of changing a wiring area of a power supply current path by changing a block position of the target block and changing a power supply current path connected to the target block. Including what is.

  In the present invention, the second step inverts one direction of the cell lines arranged in common with the ground line or the power supply line so as to have a desired decoupling capacitance, and This includes a configuration in which a predetermined interval is provided between the ground line.

  In the present invention, the second step includes an auxiliary line connected to a potential between the power supply line and the ground line in an upper layer or a lower layer of a layer where the power supply line and the ground line adjacent to each other are formed. And adjusting the combined capacitance between the power line and the ground line, the ground line and the auxiliary line, and the auxiliary line and the power line so as to have a desired decoupling capacity. Including things.

  In the present invention, there is a delay in the unnecessary radiation analysis step of analyzing the amount of unnecessary radiation of the LSI by executing simulation, the step of selecting an instance having a large amount of noise in the unnecessary radiation analysis step, and the signal timing of the selected instance. Adjusting the drive capacity of the instance so as not to occur.

  According to such a configuration, if an instance having a large amount of noise is selected and the driving capability is lowered to such an extent that the signal timing is not delayed, the unnecessary radiation is easily optimized with good workability. It becomes possible. Here, reducing the drive capability to such an extent that no delay occurs means, for example, reducing the drive capability while maintaining a state in which an error can not occur in the output of the LSI, that is, the circuit operation can be normally performed.

  In the present invention, in the above method, the adjusting step further includes a second instance having the instance as the first instance and having an output signal wiring parallel to and adjacent to the output signal wiring of the first instance. When crosstalk occurs here, considering the slopes of the output signal waveforms of both instances, the first instance only or the first and second instances (so as not to increase the mutual drive capability ratio). The method includes a step of adjusting so as to lower the driving ability.

  In the present invention, in the above method, an unnecessary radiation analysis step of analyzing the amount of unnecessary radiation of the LSI by executing a simulation, a step of selecting an instance having a large amount of noise in the unnecessary radiation analysis step, and a signal of the selected instance And correcting so as to add the inductance of the local power supply wiring supplied to the instance to the extent that no delay occurs in timing.

  According to the present invention, in the above method, the correcting step includes a step of increasing a wiring resistance.

  In the present invention, an unnecessary radiation analysis step of analyzing the amount of unnecessary radiation of the LSI by executing a simulation, a step of selecting a crosstalk aggressor instance based on the data obtained in the unnecessary radiation analysis step, and the selected Adjusting the drive performance of the aggressor instance so as not to cause a delay in the signal timing of the instance.

  The present invention is characterized in that the above method further includes a step of increasing the drive capability of the victim instance to such an extent that the EMI noise of the victim instance does not become a problem.

  The present invention is characterized in that, in the above method, when the drive capacities of both the aggressor instance and the victim instance are lowered, the respective drive capacities are set so as not to increase the drive capability ratio.

  In the present invention, an unnecessary radiation analysis step of analyzing the amount of unnecessary radiation of the LSI by executing a simulation, a step of extracting a block or instance with a large amount of noise in the unnecessary radiation analysis step, and the extracted block or instance On the other hand, according to the design stage, the process of performing unnecessary radiation reduction processing from both the floor plan stage and layout stage, and unnecessary radiation analysis is performed again, and a series of processing is performed until the amount of unnecessary radiation becomes smaller than a predetermined value. It is characterized by being repeated.

  According to such a configuration, for example, measures for increasing the generation area of the chip decoupling capacitance (such as a countermeasure method for increasing the power source area) have a demerit that causes an increase in the chip area. Therefore, an excessive increase in area can be suppressed.

  Further, when trying to use a measure for changing the aspect ratio or a measure for changing the block position, it is extremely effective because it is an EMI measure that does not increase the chip area. This method has good work efficiency because it can take early measures with a floor plan.

  Furthermore, the countermeasure by changing the cell line is effective because the position coupling capacitance closest to the instance is easily generated, that is, the most effective insertion position. In this way, it is possible to take measures against EMI while minimizing the increase in chip area.

  According to the present invention, in the above method, the step of performing unnecessary radiation reduction processing according to the design stage includes a first step of performing layout data change processing at the floor plan stage.

  According to the present invention, in the above method, the step of performing unnecessary radiation reduction processing according to the design stage includes a second step of performing layout data change processing at the layout stage.

  In the present invention, in the above method, the first step is calculated by calculating the required amount of decoupling capacity from the peak current information of the target block extracted in the extracting step and the calculating step. The method includes a step of calculating a shortage amount of the power source area from the decoupling capacitance, and a step of changing layout data based on the shortage amount.

  In the present invention, in the above method, the second step is calculated by calculating the required amount of decoupling capacity from the peak current information of the target block extracted in the extracting step and the calculating step. The method includes a step of calculating a shortage amount of the power source area from the decoupling capacitance, and a step of changing layout data based on the shortage amount.

  In the present invention, in the above method, the first step is calculated by calculating the required amount of decoupling capacity from the peak current information of the target block extracted in the extracting step and the calculating step. The method includes a step of calculating a shortage amount of the power source area from the decoupling capacitance, and a step of changing layout data for a necessary block based on the shortage amount.

  According to the present invention, in the above method, the step of changing the layout data is a step of changing an aspect ratio of the target block, that is, an aspect ratio, and substantially changing a wiring area of a power supply current path. .

  According to the present invention, in the above method, the step of changing the layout data is a step of changing a block position of a target block and substantially changing a wiring area of a power supply current path.

  In the present invention, in the above method, the second step inverts one direction of the cell lines arranged in common with the ground line or the power supply line so as to have a desired decoupling capacitance, and is adjacent to each other. A predetermined interval is provided between the power supply line and the ground line.

  In the present invention, in the above method, the second step is connected to a potential between the power supply line and the ground line in an upper layer or a lower layer of a layer where the power supply line and the ground line adjacent to each other are formed. And adjusting the combined capacity between the power line and the ground line, the ground line and the auxiliary line, and the combined capacity between the auxiliary line and the power line to have a desired decoupling capacity. Is further included.

  In the present invention, the simulation is executed at the time of occurrence of a signal change, and the target is considered in consideration of each event information including the instance name, the signal name, the generation time, and the transition information of each cell of the LSI chip that is the generation target. A step of calculating an instantaneous current amount for the block, extracting a block or instance having a noise level that is high enough to take measures against unnecessary radiation, and a display step of sorting and displaying the block or instance according to the magnitude of the noise level It is characterized by including.

  According to such a configuration, by sorting and displaying according to the level of the noise level, it is possible to easily detect an inappropriate place, and thus it is possible to work with good workability.

  In the present invention, the simulation is executed at the time of occurrence of a signal change, and the target is considered in consideration of each event information including the instance name, the signal name, the generation time, and the transition information of each cell of the LSI chip that is the generation target. A step of calculating an instantaneous current amount for the block, a step of modeling the instantaneous current amount according to a predetermined rule, and a step of performing frequency analysis processing of current change information calculated by the modeling step In the unnecessary radiation analysis method, including a display step of displaying the frequency information obtained in the frequency analysis processing step.

  In the present invention, in the above method, a step of highlighting a block to be noted from the information displayed in the display step, unnecessary radiation optimization processing is performed on the block, and unnecessary radiation information after the optimization processing is performed. And an unnecessary radiation analysis step for analyzing the information, and a step for displaying the analyzed information.

  The present invention is characterized in that the above method includes a step of storing the optimization processing as processing history information and a step of displaying the processing history information as necessary. The simulation is performed, for example, by executing a logic simulation, and includes a step of assigning and modeling an FFT analysis discrete width for each frequency band, and a step of performing a fast Fourier transform process on the current change information calculated by the modeling step. Including.

The present invention includes a step of determining a portion where the unnecessary radiation noise is large based on a result of analyzing the unnecessary radiation noise of the LSI, and a step of displaying a portion where the unnecessary radiation noise is determined to be large in the determining step. And
According to such a configuration, an unsuitable part can be easily detected and can be visually observed, so that the workability for optimization is very good.

In the present invention, the displaying step includes a step of calculating and displaying a difference in a portion where the unnecessary radiation noise is large among the differences based on two or more FFT results.
According to such a configuration, the result is easy to understand, and the workability for optimization is improved.

In the present invention, the displaying step includes a step of displaying two FFT results, and displaying the difference between the designated arbitrary shape portions by color.
According to such a configuration, the result is easy to understand, and the workability for optimization is improved.

In the present invention, the step of determining includes a step of calculating based on information on the partial circuits sorted according to the magnitude of noise.
According to such a configuration, since the information is sorted according to the magnitude of noise, it is possible to easily perform calculations with good workability.

In the present invention, the displaying step includes a step of color-coding circuit diagram information or layout information or displaying character information.
With this configuration, the workability of the optimization process is extremely good.

The present invention includes an unnecessary radiation analysis step of performing unnecessary radiation optimization on the block and analyzing unnecessary radiation information of the optimized portion, and a display step of displaying the analyzed information. .
According to this configuration, when the optimized portion is further analyzed to determine whether it is satisfactory, workability is extremely good.

  The present invention performs unnecessary radiation analysis including analysis of changes in power supply current, which can be said to be the main cause of unwanted radiation, and optimizes the effect of decoupling due to resistance, capacitance, and inductance of the power supply and ground. Reflecting efficiently, it is possible to achieve both high speed and high accuracy and to evaluate unnecessary radiation of LSI in a realistic time on simulation. Furthermore, it is possible to efficiently take measures against EMI by supporting the identification of the location where EMI occurs.

  Furthermore, the present invention provides a step of calculating equivalent power supply current information flowing in the power supply current in the ideal power supply from the circuit information of the LSI chip in the analysis of the power supply current, which can be said to be a main factor of unnecessary radiation, and the equivalent power supply current information. Analysis control information includes at least one of power source information of a power source that supplies current to the LSI chip, package information of the package of the semiconductor chip, and measurement system information of a measurement system that measures the characteristics of the semiconductor chip. In consideration, an unnecessary radiation analysis including an estimation process for estimating, as an equivalent circuit, comprehensive information in which the analysis control information is reflected in the circuit information, and a simulation process for executing simulation according to the comprehensive information estimated in the estimation process Can be used to optimize the process more efficiently. .

  According to the above configuration, unnecessary radiation caused by the power supply, package, and measurement system can be analyzed with high accuracy at high speed and with a small amount of memory.

And, by reflecting the influence of decoupling due to the resistance, capacitance, and inductance of the power supply and ground, the hybrid analysis is reflected in the power supply current calculation to achieve both high speed and high accuracy, and the unnecessary radiation of LSI is realistic in the simulation. Allows evaluation in time. Furthermore, it is possible to efficiently take measures against EMI by supporting the identification of the location where EMI occurs.
In addition, since the present invention includes a display step for sorting and displaying blocks or instances according to the size of the noise level, analysis at higher speed and higher accuracy can be performed, and excellent optimization processing is possible. It becomes.

  Although it is practically impossible to optimize fully automatically, the best optimization method can be interactively performed with the user by using information specific to EMI indicating the amount of noise emitted from each instance with respect to the frequency. Effective optimization can be realized by selecting and deciding.

Hereinafter, embodiments of the method for optimizing unnecessary radiation according to the present invention will be described.
Embodiment 1
FIG. 1 is a conceptual diagram showing the entire configuration of an unwanted radiation analysis apparatus for carrying out the unwanted radiation optimization method according to the present invention.

  This unnecessary radiation analysis apparatus includes a measurement system for measuring circuit information 101 of the LSI chip, power supply information of a power source that supplies current to the LSI chip, package information of the package of the semiconductor chip, and characteristics of the semiconductor chip. Analysis control input unit 102 for adding at least one piece of information of measurement system information as analysis control information, and estimating total information obtained by adding the analysis control information to the circuit information as an equivalent circuit, and the analysis control input unit Obtained by the unnecessary radiation simulation unit 103 for executing the simulation, the analysis information display unit 104 for displaying the analysis information obtained by the unnecessary radiation simulation unit 103, and the unnecessary radiation simulation unit 103. Based on the analysis information obtained and the optimization criteria from the optimization control input unit 105. The unwanted radiation optimization unit 106 that optimizes the unnecessary radiation and have, on the basis of the information of the unnecessary radiation optimization unit 106, characterized by comprising the optimized information display unit 107 for displaying the optimization information.

  Here, as shown in the flowchart of FIG. 48, the unnecessary radiation optimization unit includes a step of adjusting the instance drive capability so as not to cause a signal timing delay. Assume that an instance having a large amount of noise is selected by a method described later, and a method of performing unnecessary radiation optimization countermeasures for this instance will be described.

  First, EMI analysis is performed by simulation, and an instance with a large amount of noise is selected (step 4801).

  Next, it is determined whether or not there is a margin in the signal timing of the selected instance (step 4802). If it is determined that there is a margin, the instance drive capability is lowered to the extent that no signal timing delay occurs (step 4803).

Embodiment 2
Next, a second embodiment of the present invention will be described. Here, as shown in the flow chart of FIG. 49, unnecessary radiation countermeasures are taken in consideration of crosstalk, and parallel to the output signal wiring of the instance determined to have a large amount of noise. When an instance having an output signal wiring to be present is present, when this instance is large, not only the instance but also the drive capability of this instance is lowered to such an extent that no signal timing delay occurs.

Here, it is assumed that an instance having a large amount of noise has been selected by a method described later, and a method for performing unnecessary radiation optimization countermeasures for this instance will be described.
First, EMI analysis is performed by simulation, and an instance with a large amount of noise is selected (step 4901).

  Next, it is determined whether or not there is a margin in the signal timing of the selected instance (step 4902). If it is determined that there is a margin, in the determination step 4903, the first instance A determined to have a large amount of noise. It is determined whether there is a second instance B having an output signal line parallel to and adjacent to the output signal line. If it is determined that the first instance A and the second instance B are compared, the magnitude of the output signal waveform is greater or similar in the first instance A. Not only the first instance but also the driving capability of the first instance is lowered to such an extent that no signal timing delay occurs and the driving capability ratio of the first and second instances is not increased, and the second instance B If the slope of the signal waveform is larger, the drive capability of only the first instance A is lowered to such an extent that no signal timing delay occurs (step 4904). Here, the drive capacity ratio of the first instance A and the second instance B is set so that the drive capacity ratio after the change does not become larger than the drive capacity ratio before the change. It is to lower. That is, the drive capacity of the first instance A and the second instance B is lowered under the condition of the drive capacity ratio before change> = drive capacity ratio after change.

  On the other hand, if it is determined that there is no second instance B that causes crosstalk, the drive capability of the first instance A is lowered to the extent that no signal timing delay occurs (step 4905).

Embodiment 3
Next, a third embodiment of the present invention will be described. Here, as shown in the flowchart of FIG. 50, the unnecessary radiation optimizing unit is configured to take measures against unnecessary radiation in consideration of IR drop. For an instance determined to have a large amount of noise, The method includes a step of increasing the resistance of the local power supply wiring supplied to the instance and adjusting the drive voltage to be lowered by reducing the applied voltage to the instance to such an extent that no timing delay occurs due to IR drop. And

Here, it is assumed that an instance having a large amount of noise has been selected by a method described later, and a method for performing unnecessary radiation optimization countermeasures for this instance will be described.
First, EMI analysis is performed by simulation, and an instance with a large amount of noise is selected (step 5001).

  Next, it is determined whether there is a margin in the signal timing of the selected instance (step 5002). If it is determined that there is a margin, the resistance of the local power supply wiring supplied to this instance is increased and IR drop is performed. The application voltage to the instance is lowered to such an extent that timing delay does not occur, and adjustment is made so as to lower the driving capability (step 5003).

Embodiment 4
Next, a fourth embodiment of the present invention will be described. Here, as shown in the flowchart of FIG. 51, the unnecessary radiation optimization unit selects an aggressor instance that is a perpetrator of crosstalk in the unnecessary radiation analysis step, and the signal timing of the selected aggressor instance is delayed. And a step of adjusting the drive capability of the aggressor instance so as not to occur.

Here, it is assumed that an instance having a large amount of noise has been selected by a method described later, and a method for performing unnecessary radiation optimization countermeasures for this instance will be described.
First, EMI analysis is performed by simulation to select an aggressor instance that is a perpetrator of noise (step 5101).

  Next, it is determined whether the noise amount of the selected aggressor instance is large (step 5102). If it is determined that the noise amount is large, it is determined whether the signal timing of the selected aggressor instance has a margin. (Step 5103) If it is determined that there is a margin, the drive capability of the aggressor instance is lowered to such an extent that no signal timing delay occurs (step 5104).

  If it is determined in decision step 5102 that the amount of noise is not large, or if it is determined in decision step 5103 that there is no room, the process shifts to the step shown in FIG.

  Here, it is determined whether or not the EMI noise of the victim side, that is, the victim instance is small (step 5201). If it is determined that the EMI noise amount is small, the driving ability of the victim instance is increased to such an extent that the amount of EMI noise does not become a problem ( Step 5202) On the other hand, if it is determined that the EMI noise on the victim side, that is, the victim instance is not small, the parallel signal wiring length is reduced or the wiring interval is increased (Step 5203). Thereby, crosstalk is reduced.

Embodiment 5
Next, a fifth embodiment of the present invention will be described. FIG. 53 shows the entire processing flow of measures against unwanted radiation by inserting a decoupling capacitor according to the fifth embodiment of the present invention. Here, as shown in the flowchart in FIG. 53, unnecessary radiation reduction processing is performed separately for floorplanning and layout, and then unnecessary radiation analysis is performed to determine whether or not unnecessary radiation is below a predetermined range. If not, it is characterized in that it returns to the design phase again. Further, the present invention is characterized by having a step of calculating an effective insertion position of the decoupling capacitance and a step of creating an insertion portion for a portion where the unnecessary radiation needs to be optimized.

  That is, unnecessary radiation analysis processing is performed in step 5301, the frequency spectrum of the FFT analysis result obtained here is extracted (step 5302), and a block or instance having a high noise level that requires countermeasures against unnecessary radiation is sorted (step 5303). . That is, for example, the frequency spectrum is stored in an external computer system, and the input / output calculation unit stores it as a program group having each step of each component, and sorting is performed in a desired order.

  On the other hand, the FFT result sorting means 7502 is stored as a program group having each step of each constituent element in the input / output arithmetic unit of the computer system.

  Thereafter, the design phase (step 5304) is entered, and the first unnecessary radiation reduction processing unit performs unnecessary radiation reduction processing during floorplanning (step 5305), while the second unnecessary radiation reduction processing unit performs cells during layout. Unnecessary radiation reduction processing is performed during the placement (step 5306).

Then, unnecessary radiation analysis is performed again (step 5307), and it is determined whether or not the amount of unnecessary radiation is smaller than a predetermined value (step 5308).
When it is determined that the amount of unnecessary radiation is sufficiently smaller than the reference value, the countermeasure for unnecessary radiation ends.

On the other hand, when it is determined that the amount of unnecessary radiation is not sufficiently smaller than the reference value, the process returns to the design phase again (step 5304), and the first and second unnecessary radiation reduction processing units again perform processing countermeasures.
Next, the unnecessary radiation optimization process in the floor plan will be described with reference to FIG.

  Here, first, peak current information is extracted from unnecessary radiation analysis result information of the target block obtained by sorting at the output unit of the computer system (step 5401). An example of unnecessary radiation analysis result information is shown in FIG. From FIG. 56, MH2 is sorted as a block with a large unnecessary radiation at a frequency component of 100 MHz. An example of the peak current information is shown in FIG. The peak current information is current information flowing through the power supply wiring at the block or instance entrance. In this embodiment, as an example, the peak current information is obtained by extracting the peak current value and the slope of the current waveform as information.

  As shown in FIG. 60, using the peak current-decoupling capacity database DB1 (5402) showing the relationship between the peak current and the decoupling capacity necessary for reducing the peak current, as shown in FIG. A necessary amount of decoupling capacity for reducing unnecessary radiation is calculated (step 5403).

  The decoupling capacitance required for the target block thus obtained and the relationship between the decoupling capacitance and the area of the power supply wiring where the decoupling capacitance is inserted as shown in FIG. 61 are shown. From the capacity-power supply area database DB2 (5404), the required power supply area is calculated as shown in FIG. 62 (step 5405). (In this description, the power supply area is defined as the area of the power supply wiring that can be the insertion point of the decoupling capacitor.)

  On the other hand, layout data is extracted from the database (step 5407). In this example, for example, as shown in FIG. 63, there is a target block B located between electrode pads P1 and P2 provided on opposite sides. 64, the current paths 1, 2, and 3 are determined in ascending order of resistance value as shown in FIG. 64 (step 5408), and the power source area of the first current path is calculated as indicated by hatching H in FIG. Step 5409).

  From the power source area of the first current path obtained in this way and the required amount of power source area obtained from the peak current information of the target block, the power source area that becomes the insertion location of the decoupling capacitor has reached the required amount. If the required amount is not reached, countermeasures are sequentially implemented for each route (step 5406). In addition, since the current path is defined by the resistance value, it is possible to calculate and use the peak current information for each current path in step 5401.

  The aspect ratio change processing unit changes the aspect ratio, that is, the aspect ratio of the block shape in order to increase the power supply area thus obtained (step 5410). For example, if the aspect ratio of the target block B is reversed as shown in FIG. 66, the electrode area H2 is increased.

Further, the block arrangement change processing unit changes the block arrangement position (step 5411). For example, as shown in FIG. 67, when the block position is separated from the second power supply pad P2 and the power supply wiring area of the first current path is increased, the electrode area is increased by H3.
Furthermore, the power supply wiring change processing unit changes the power supply wiring (step 5412). For example, as shown in FIG. 67, when the wiring width is partially doubled and the power supply wiring area of the first current path is increased, the electrode area is increased by H4.

In this way, in order to reduce unnecessary radiation, the power supply area of the first current path having the largest insertion effect of the decoupling capacitance is increased by the aspect ratio change process, the block arrangement change process, and the power supply wiring change process, and the power is supplied again. It is determined whether the required amount of area is satisfied (step 5413).
When it is determined that the necessary amount of the power source area is not satisfied, the process returns to step 5408 again to determine the current path again. As shown in an example in FIG. 69, when the first current path is changed because the position of the target block B has moved to the side closer to the first power supply pad P1 in the previous countermeasure process, The determined first current path is the target path. When the first current path is not changed by the countermeasure process, the second current path is the target path. Then, in order to reduce unnecessary radiation again for each path, the power supply area is increased by the aspect ratio change process, the block arrangement change process, and the power supply wiring change process, and it is determined again whether the required amount of the power supply area is satisfied ( Step 5413), repeat these steps until it is OK.

  In general, a measure for increasing the generation area of the chip decoupling capacitance is used as a technique for reducing unnecessary radiation, but has a demerit that increases the chip area. In the power supply wiring changing process according to the present embodiment, the locations where the processing is performed are limited based on the analysis results, and only the necessary amount of measures are taken at the required locations, so there is no risk of an increase in area due to excessive measures. Further, the aspect ratio changing process and the block arrangement changing process in the present embodiment are effective because it is possible to take EMI countermeasures without increasing the chip area.

  In the above-described embodiment, the power source area is defined as the area of the power supply wiring that can be an insertion point of the decoupling capacitance. However, by indicating which current path the decoupling capacitance belongs to, the power source area is decoupled. It can also be defined and handled as a capacity insertion area.

  In this way, unnecessary radiation reduction processing at the time of floor planning is performed. On the other hand, countermeasures in the unnecessary radiation reduction processing unit at the time of layout described in the overall processing flow of unnecessary radiation countermeasures in FIG.

This process is shown in FIG. FIG. 56 shows an example of result information (5501) obtained by sorting instances that need countermeasures. In FIG. 56, X102.XM123.MH2 and X178.XM123.MH2 are sorted as instances of unnecessary radiation with a frequency component of 100 MHz. By the way, when considering a block as shown in FIG. 70, each instance I has a power line and a ground line as shown in FIG. 71. As described above, each cell line often has a double back arrangement, that is, a cell arrangement in which the ground lines and the power supply lines are arranged on the same side. Therefore, a decoupling capacitance is generated between the adjacent power line Vcc and the ground line GND by inverting one cell line and arranging the power line and ground line of the adjacent cell line separated by a predetermined distance c. Is done.
In this way, a decoupling capacitor can be formed in a plane.

  Using this fact, the result information obtained by sorting the instances that need countermeasures is extracted (step 5501), and a double decoupling is canceled or inverted from this data to generate a planar decoupling capacity as described above. A line is determined (step 5502). FIG. 57 shows an explanatory diagram of the cell line inversion. When the hatched instance is an instance requiring countermeasures, the cell line to which the most instances requiring countermeasures belong is determined. The decoupling capacity can be increased by releasing the double back (step 5503).

  In the embodiment described above, unnecessary radiation is reduced by generating a planar decoupling capacitance by canceling double back, that is, by inverting the cell line. In addition to this, FIG. As shown in section -A, an additional wiring line Vs is disposed above and below the ground line and the power line via an insulating film, and an intermediate potential between the ground line and the power line is maintained, thereby adding the ground line and the power line. Three decoupling capacitances of a wiring line, a power supply line and an additional wiring line, and a power supply line and a ground line can be added, and a necessary decoupling capacitance can be easily formed with a small area. In addition, since the decoupling capacitance can be formed at a position closest to the target instance, it can be said that the decoupling capacitance is efficiently inserted at a position where the effect of the countermeasure is easily exhibited.

Also, it is possible to easily use the necessary amount of the power source area calculated in steps 5401 to 5405 in FIG. 54 when performing unnecessary radiation reduction processing at the time of layout, that is, at the time of cell placement. Since it becomes clear how much measures should be taken, an excessive increase in area can be suppressed.
The decoupling capacitance is determined according to the width of the power supply wiring of the target chip and the state of the peripheral circuit.

  This power supply wiring width information is estimated at the specification stage or determined at the floor plan, whether or not there is a ring power supply wiring around the chip and its width / expected at the specification stage, or determined at the floor plan The width of the main power supply wiring between each module is expected at the specification stage, or determined by the floor plan. The width of the strap power supply between each module is expected at the specification stage, or determined by the floor plan. Considering the presence or absence of a decoupling capacitor cell under the power supply wiring, it is desirable to input such a value as data. However, it is not necessary that all these components are input.

Embodiment 6
Next, a user interface for improving the efficiency of such an optimization process will be described.
In the conventional EMI analysis means in LSI, a method of reporting only the FFT result has been common. This method has a problem that it takes a very long time to determine the cause.
Therefore, in this embodiment, in order to solve this problem, a method of performing FFT on the current waveform for each instance and sorting the instance names in descending order of noise of each current frequency component is used as a user interface. This facilitates optimization processing.

FIG. 75 shows the configuration of the unwanted radiation analysis apparatus according to Embodiment 6 of the present invention. The unwanted radiation analysis apparatus shown in the figure includes an FFT result storage unit 7501, an FFT result sort unit 7502, and a sort result storage unit 7503.
Of these, the FFT result storage means 7501 and the sort result storage means 7503 are assigned to the external storage device of the computer system described above.

  On the other hand, the FFT result sorting means 7502 is stored as a program group having each step of each constituent element in the input / output arithmetic unit of the computer system.

  Next, each element constituting the unwanted radiation analysis apparatus of FIG. 75 will be described, and a procedure for analyzing unwanted radiation using the FFT result information shown in FIG. 76 will be explained.

The FFT result storage means 7501 is information about the FFT result, and stores FFT result information as shown in FIG. 76 in advance.
This FFT result information is composed of information on the frequency and current frequency component of the FFT result for each instance.
The sort result storage unit 7503 stores the sort result information calculated by the FFT result sort unit 7502 as shown in FIG.
This sort result information is composed of one or more FFT result information of the target circuit consisting of an instance name and a current frequency component value for each frequency.

  The FFT result sorting means 7802 performs analysis according to a flowchart as shown in FIG.

First, in step 7801, the FFT result information shown in FIG. 78 stored in the FFT result storage means 7501 is read.
In step 7802, frequency information in the FFT result information is read. In step 7803, the first frequency is selected.
Thereafter, in step 7804, all instances and current frequency components corresponding to the target frequency are selected, and the instances and current frequency components selected in step 7805 are sorted in descending order of current frequency components.

In step 7806, the target frequency, the sorted instance name, and the current frequency component are written in the sorting result storage information. At this time, the data may be displayed in the form shown in FIG. 56 or the data shown in FIG. 79 as necessary.
Steps 7804 to 7806 are repeated until all the frequency information described in the FFT result information has been processed. When the processing is completed, the FFT result sorting unit ends.

By the above method, the instance that affects the noise is identified as a user interface by performing FFT on the current waveform for each instance and sorting the instance names in descending order of the noise of each current frequency component. Is possible.
Further, when displaying the FFT result, as shown in FIGS. 79A to 79C, the frequency is displayed by performing simultaneous display before (a), after (b), and before and after (c). Each improvement display is easy to understand. Further, the difference is displayed in different colors, which makes it easier to display, and it is possible to quickly determine how effective the frequency component to be noticed is.

Embodiment 7
Furthermore, a user interface for improving the efficiency of such an optimization process will be described.
In the conventional EMI optimization process in an LSI, a method of reporting only the result is common. In this method, there is a problem that it takes a very long time to grasp the processing from various data including circuit data and a net list and determine the next step.

In order to solve this problem, the present embodiment is characterized in that a display process is provided for each step as a user interface so that the user can perform processing while making a determination. 79 to 83 are views showing display examples.
As an example, data change processing will be described.

  The display means for performing this display step is stored as a program group having each step of each constituent element in the input / output calculation unit of the computer system of each functional means, and can be displayed sequentially.

  As shown in FIG. 84, when the change step is started in the circuit data changing means (step 8401), the circuit data extraction step 8402 is followed by the circuit data location that needs to be changed as shown in FIG. A highlight is displayed (step 8403).

When a function selection such as data change or parameter change is made in the function selection input step (step 8404), the selection function is displayed in the selection function display step (step 8405).
Next, when a region corresponding to the designation information is displayed in the designated region display step (step 8406), the designated region is input in the designated region input step (step 8407).

  When data change is selected in the function selection, a determination is made based on the displayed information. When a change in circuit data is instructed in the designated area data temporary change process (step 8408), an unnecessary radiation simulation (step 8409) is performed accordingly. ) Is executed.

  Then, the circuit information is read again (step 8410), and the circuit data temporary change (step 8411) result in the designated area data change step (step 8408) and the parameter value obtained according to the circuit data are changed. Display is performed in the circuit data display step (step 8412).

  In this display data, as shown in FIG. 80 (b), when a portion to be selected is selected, a parameter value confirmation screen is displayed, and then a parameter is displayed. In addition, as shown in FIG. 80 (c), another part related to one part may be displayed.

  For example, in the function selection step (step 8405), when the function of widening the wiring width is selected, a function selection display is made on the screen as shown in FIG. 81 (a), and the wiring width is widened on the screen. As shown in FIG. 81 (b), the internally calculated parameter value is displayed, and a confirmation screen is displayed.

  It is also useful to be able to output a processing history report such as a problem solving technique. Furthermore, the processing result report can be output as a file. FIG. 83 is a diagram showing an example of a display screen, B1 shows a history display button, and B2 shows a report display button. Each of these is displayed by pressing these buttons.

  In this way, various displays are made, confirmation input after change (step 8413) is made, and if YES is selected in decision step 8414, the circuit data is changed (step 8415), and the circuit information 8416 is updated. .

  According to this method, since the optimization process can be performed while viewing the display, it is possible to perform the unnecessary radiation optimization process with high workability and high accuracy.

Embodiment 8
In the above-described embodiment, the method of performing the circuit data change process by temporarily changing the designated area data has been described. However, in the case of the process of changing the parameter value, the following display is performed. First, when a function is selected, a function selection display is made on the screen as shown in FIG. 82 (a). When a desired parameter value is input on the screen of FIG. 82 (b), the screen shown in FIG. 82 (c) is displayed. As shown, the circuit data is changed and a confirmation screen is displayed.

  FIG. 85 shows the flowchart.

  In this example, steps similar to the circuit data change processing step shown in FIG. 84 are used. In the seventh embodiment, after the designated area input step 8406, the designated area display step 8407 is followed by the unnecessary radiation simulation step 8408. Instead of the designated area display step 8407, FIG. And as shown to (b), the step (step 8507) which performs unnecessary radiation simulation in the changed state, the display step (step 8508) which displays this parameter value and the designated area, and the parameter value according to the display result This is characterized in that an unnecessary radiation simulation step 8510 (corresponding to the unnecessary radiation simulation step 8408 in FIG. 84) is executed through a change step (step 8509) for changing.

Embodiment 9-10
Further, although the circuit information change has been described in the above embodiment, the same applies to the netlist, and the netlist change flowchart is shown in FIGS. 86 and 87.

  In the above embodiment, the optimization after the unnecessary radiation analysis and the method for improving the efficiency have been described. However, these methods are effective in the unnecessary radiation analysis method shown below, and the following method is applied. As a result, the analysis can be performed at higher speed and with higher accuracy, and therefore, an excellent optimization process can be performed.

  Note that full-automatic optimization is practically impossible, and it is interactive with the user as described above using information specific to EMI (the amount of noise from each instance is known for a certain frequency). Therefore, it is necessary to select and determine the best optimization method, thereby realizing effective optimization.

Embodiment 11
Next, an unnecessary radiation analysis method used when executing this optimization process will be described. The following analysis method can be applied to any of Embodiments 1 to 10.
FIG. 1 is a conceptual diagram showing the overall configuration of an unwanted radiation analysis apparatus for carrying out the unwanted radiation analysis method according to the present invention.

  This unnecessary radiation analysis apparatus includes a measurement system for measuring circuit information 101 of the LSI chip, power supply information of a power source that supplies current to the LSI chip, package information of the package of the semiconductor chip, and characteristics of the semiconductor chip. At least one piece of measurement system information is added as analysis control information, and comprehensive information obtained by adding the analysis control information to the circuit information is roughly estimated as an equivalent circuit, and a simulation considering this is performed. It is characterized by this.

  Here, the estimated current waveform for each logic change in the digital simulation is expressed with a function of transition time and a side of the function as a function of decoupling capacitance, and simulation is performed. High accuracy and high reliability Unnecessary radiation analysis can be executed at high speed.

  This unnecessary radiation analysis apparatus includes a measurement system for measuring circuit information 101 of the LSI chip, power supply information of a power source that supplies current to the LSI chip, package information of the package of the semiconductor chip, and characteristics of the semiconductor chip. Analysis control input unit 102 for adding at least one piece of information of measurement system information as analysis control information, and estimating total information obtained by adding the analysis control information to the circuit information as an equivalent circuit, and the analysis control input unit Obtained by the unnecessary radiation simulation unit 103 for executing the simulation, the analysis information display unit 104 for displaying the analysis information obtained by the unnecessary radiation simulation unit 103, and the unnecessary radiation simulation unit 103. Based on the analysis information obtained and the optimization criteria from the optimization control input unit 105. The unwanted radiation optimization unit 106 that optimizes the unnecessary radiation and have, on the basis of the information of the unnecessary radiation optimization unit 106, characterized by comprising the optimized information display unit 107 for displaying the optimization information.

  Further, as shown in FIG. 2, the analysis control input unit 102 includes power supply information of a power source that supplies current to the LSI chip, package information of the package of the semiconductor chip, and a measurement system that measures characteristics of the semiconductor chip. Equivalent circuit estimation means 1021 for adding at least one piece of measurement system information as analysis control information and estimating the total information obtained by adding the analysis control information to the circuit information as an equivalent circuit; and the equivalent circuit estimation means 1021 Thus, the power supply / package / measurement system RLC information 1022 is obtained as equivalent circuit information of the comprehensive information resulting from the power supply / package / measurement system, and the netlist 1023 including the power supply / package / measurement system RLC information 1022 and circuit information And the current estimation model 1024 from the power supply / package / measurement system. A power source / package / measurement system-considered current FFT result estimating means 1025 for calculating an estimation result of the frequency spectrum of the EMI noise caused by the power source current, performing the FFT processing thereof, and the power source, package And a power source / package / measurement system consideration FFT result 1026 which is a frequency spectrum as an FFT result considering the measurement system.

  An example of this netlist is shown in FIG. This shows an inverter circuit, and this netlist information is composed of information on connection of one or more circuit elements, wirings and external terminals, and current information when each circuit element is driven. In this example, the buffers BUF1, BUF2, BUF3, BUF4, and BUF5 that flow 4 mA at the time of rising and 6 mA at the time of falling, and wirings that connect the external input terminal A and the external output terminals Y1, Y2, and Y3, respectively. FIG. 3 shows circuit information of the LSI chip when the power source used for calculating the power source / package / measurement system non-consideration current as shown in FIG. 10 is an ideal power source, and FIG. The result of modeling the circuit current and the power supply / package / measurement system RLC information as an equivalent impedance is shown as an equivalent power supply current.

  The equivalent circuit including the package and measurement system of the LSI device to be simulated here is composed of a package part P, a power supply circuit part S, and a measurement system M, as shown in FIG. In this equivalent circuit, the package portion, the power supply circuit portion, and the measurement system are formed independently, but the package portion, the power supply circuit portion, and the measurement system are not necessarily independent.

By modeling the measurement system in this way, it is possible to correlate with the measurement result of the LSI measurement system (measurement apparatus) that is about to be standardized.
FIG. 5 shows a frequency spectrum which is an FFT result finally obtained by the present invention. The vertical axis represents noise (dBmA), and the horizontal axis represents frequency (Hz).

  FIG. 7 shows the estimated current waveform for each logic change in the digital simulation as a shogi-shaped wave with a triangular shape as shown in FIGS. 7A to 7D. When the decoupling capacity is small, FIG. The estimated power supply current has an acute angle as shown in FIG. 7C, and the estimated power supply current when the decoupling capacity is large becomes an obtuse angle as shown in FIG. 7D.

  On the other hand, there is a method of expressing as a triangular wave as shown in FIGS. In this case, the amount of current is expressed as a function of the transition time at the base of the triangle, so the only way to consider the decoupling capacity is to adjust the base, but if the base is widened, it will be reduced by the decoupling capacity. As a result, not only noise in a high frequency region but also noise in a low frequency region is reduced, which means that it does not match actual measurement.

  On the other hand, FIG. 7 shows the optimum modeling when the power / package / measuring device non-consideration current estimation means is realized by using a logic simulator. By using this, the equivalent power supply current circuit is close to the actual one. Can be realized in the form.

  In this method, the bottom side can be expressed as a function of transition time, and the side surface can be expressed as a function of decoupling capacitance, and the influence of the decoupling capacitance on the frequency spectrum (FFT result) can be accurately expressed.

  FIG. 8 shows the current information not considering the power source / package / measuring device calculated by the power source / package / measuring device non-considering current estimation means using such a model. This current information includes information on each time and the power supply current value, and is information when the power supply current as shown in FIG. An example of a method for converting this power supply current information into an equivalent power supply current is shown in FIG. An equivalent power source current can be obtained by connecting a D / A converter 901 to a terminal of an LSI chip and connecting the power source / package / measuring device non-considering current estimating means to the D / A converter 901 as a digital current calculating circuit 901. it can. When information as shown in FIG. 8 is calculated by a digital current value calculation circuit (that is, a power estimation / package / measurement device non-consideration current estimation means configured by a logic simulator) and then converted into an equivalent power supply current, By using a D / A converter as shown in FIG. 9, the circuit shown in FIG. 9 can be smoothly simulated with a transistor level simulator.

In addition, if a transistor level simulation is performed by combining an equivalent power supply current circuit and an impedance circuit, the power supply current calculated by the power supply / package / measurement device non-consideration current estimation means is corrected, and the power supply / package / measurement device consideration current is corrected. Can be estimated, and a frequency spectrum as shown in FIG. 5 can be obtained by performing FFT.
Next, a case where the analysis control input unit 102 is implemented will be described using the equivalent circuit shown in FIG. 11 and the block diagram shown in FIG.

  Here, a step of calculating a current at a gate level as a power source / package / measurement system non-consideration current estimation unit and a step of calculating a transistor level as a power source / package / measurement system consideration FFT estimation unit reflecting the result Run in sync. In other words, while calculating the estimated current for the cell, block or LSI at the gate level and simulating this calculated value in combination with the power supply net in synchronization with the calculation, a current calculation result considering the influence of the power supply net is obtained. It is what I did.

As shown in an equivalent circuit in FIG. 11 and a block diagram in FIG. 12, the analysis control input unit 102 shown in FIG. Package / measurement system non-considered current result 1012, power supply information of the power source for supplying current to the LSI chip, package information of the package of the semiconductor chip, and measurement system of the measurement system for measuring the characteristics of the semiconductor chip Equivalent circuit estimation means 1021 for adding power / package / measurement system RLC information 1022 obtained by adding at least one of the information as analysis control information and adding the analysis control information to the circuit information as an equivalent circuit; Based on the equivalent circuit obtained by the circuit estimation means 1021, it is caused by the power source / package / measurement system. Power supply / package / measurement system consideration FFT estimation means 1025 for performing frequency analysis by a method such as FFT processing from the total impedance as the power supply / package / measurement system RLC information 1022 and the net list 1023 is provided. The FFT result 1026 in consideration of the power source, the package, and the measurement system is output.
Next, flowcharts showing the operations of the power source / package / measurement system non-consideration current estimation means and the power source / package / measurement system consideration current estimation means are shown in FIGS.

  First, as shown in FIG. 13, the current estimation in the power source / package / measurement system non-consideration current estimation means 1011 is performed by inputting a netlist 1023 and circuit input information 1010 1301 and reading the input information 1302. There is a step 1303 for fetching the read circuit input information line by line, a step 1304 for looking at the flag to determine whether or not a flag has been sent from the power source / package / measurement system consideration current estimation means, and a flag. In step 1305 for determining whether or not the flag has been sent or if the extracted circuit input information is the first row, the power supply current when the extracted circuit input information is given to the net list is determined. Completing the step 1306 for calculating and writing the file, all the circuits Determining whether or not the processing end about the power information (step 1307), if it is finished and ends.

  Here, the circuit input information is a time series of input values applied to the external input terminals of the netlist. The simulation time and the logical signal values applied to the external input terminals at that time are stored in one line. This is described until the simulation end time.

If all the rows of the circuit input information have not been processed in the decision step 1307, the process returns to the circuit input information extraction step 1303 and the same steps are repeated.
Furthermore, when the flag is not sent from the power source / package / measurement system consideration current estimation means, it is checked whether the flag is sent again.

  Further, as shown in FIG. 14, the current estimation in the power source / package / measurement system-considered current estimation means is performed by a step 1401 of monitoring information addition of the estimation result in the power source / package / measurement system non-consideration current estimation means, and a monitoring step In step 1402, it is determined whether or not information has been added (step 1402). If it is determined that information has been added, additional current information is read (step 1403).

  Then, a current simulation is performed from the RLC of the power source / package / measurement system to the simulation time of the additional current information of the circuit determined, the current of the additional current information is applied (step 1404), and the power source / package / measurement system current estimation A flag is sent to the means 1011 (step 1405).

Then, it is determined whether or not the sending of the flag has been completed (step 1406). If the flag has been transmitted, the current information is subjected to FFT processing (step 1407), and the output information is written (step 1408).
If the sending of the flag has not ended, the process returns to the monitoring step 1401 for monitoring the addition of information of the estimation result in the power source / package / measurement system non-consideration current estimation means, and the subsequent steps are repeated again.

Embodiment 12
Next, a twelfth embodiment of the present invention will be described.
Here, a method of reflecting a gate level current calculation result as a power source / package / measurement system non-considered current estimation means in a transistor level calculation by post-processing is adopted. In other words, after calculating the estimated current for a cell, block, or LSI at the gate level, the calculated value is combined with the power supply net to obtain a current calculation result considering the influence of the power supply net. is there.

  FIG. 15 illustrates an operation method for reflecting the gate level current calculation result in the transistor level calculation in post-processing. Here, the step of flag propagation from the power supply / package / measurement system consideration current estimation means to the power supply / package / measurement system non-consumption current estimation means, which is necessary for synchronization in the synchronous read operation described in FIG. 12, is eliminated. The other steps are the same as the steps in FIG.

  Here, the estimation operation of the power source / package / measurement system non-consideration current estimation means 1011 is shown in FIG. Here, the circuit input information 1010 is read as input information (step 1601), the corresponding circuit input information is taken out line by line (step 1602), the taken out circuit input information is added to the netlist 1023, and the power supply current at this time Is calculated and file writing is performed (step 1603). Then, it is determined whether or not the processing has been completed for all circuit input information (determination step 1604). When it is determined that the processing has been completed, the estimation operation is terminated.

  On the other hand, if it is determined in the determination step 1604 that the process has not been completed, the process returns to step 1602 where the circuit input information is fetched line by line, and the above operation is repeated again.

  Next, the estimation operation of the power source / package / measurement system consideration current estimation means 1025 is shown in FIG. First, the simulation time is initialized (step 1701), the circuit input information 1010 is read as input information (step 1702), and the current information is calculated by adding the corresponding circuit input information to the RLC information of the power supply / package / measurement system ( Step 1703), the current information is subjected to FFT processing (Step 1704). Then, the FFT result obtained in this way is written as output information (step 1705) and output to the display device.

  According to such a configuration, the influence on the FFT result of the power supply net can be accurately expressed in time series. Also, in the case of such asynchronous reading, since the flag is not sent compared to the synchronous reading, the process of sending the flag can be cut, thereby enabling high-speed processing.

Embodiment 13
Next, a thirteenth embodiment of the present invention will be described.
Here, a method of reflecting a gate level current calculation result as a power source / package / measurement system non-consideration current estimation means asynchronously in a transistor level calculation is adopted. In other words, signal changes related to cells, blocks or LSIs are stored, these signal changes are read at fixed intervals, the estimated current is represented as a current source by D / A conversion, etc., and simulation is performed in combination with the power supply net. The current calculation result considering the influence is obtained.

  FIG. 15 shows an asynchronous read operation for asynchronously reading the gate level current calculation result, which is exactly the same as the operation method reflected in the transistor level calculation in the post-processing described in the second embodiment.

  Further, the estimation operation of the power source / package / measurement system non-consideration current estimation means 1011 is exactly the same as the operation shown in FIG. 16 described in the second embodiment.

  Next, an estimation operation of the power source / package / measurement system consideration current estimation means 1025 is shown in FIG. First, the simulation time is initialized to 0 (step 1801), the circuit input information 1011 at the simulation time is read as input information (step 1802), and the corresponding circuit input information is added to the RLC information of the power supply / package / measurement system (step 1802). Step 1803).

Then, a current simulation is performed for a simulation unit time, and after obtaining a current value, the simulation time is advanced by 1 (step 1804).
It is determined whether or not the simulation target period has ended (step 1805). If the simulation target period has ended, the current information is subjected to FFT processing (step 1806). Then, the FFT result obtained in this way is written as output information (step 1807) and output to the display device.

  If not completed in the determination step 1805, the process returns to the current information reading step 1802 at the simulation time again, and the following flow is repeated again.

  According to such a configuration, it is possible to accurately represent the influence of the power supply net on the FFT result. In addition, by reading at the process interval in this way, the digital unit as the power source / package / measurement system non-consideration current estimation unit is not limited by the processing speed of the analog unit as the power source / package / measurement system consideration FFT estimation unit. It becomes possible to calculate.

Embodiment 14
Next, a fourteenth embodiment of the present invention will be described.
Here, a method is adopted in which the average or maximum current calculation result of the gate level is reflected in the calculation of the transistor level. In other words, as a current / package / measurement system non-consideration current estimation means, an estimated current related to a cell, block or LSI is calculated at the gate level, and this calculated value is averaged or calculated for each cycle as a current source. A current calculation result considering the influence of the power supply net is obtained by simulating in combination with the power supply net.

  FIG. 19 shows an operation method in which the current level calculation result of the power source / package / measurement system non-consideration current estimation means is reflected in the post-processing of the transistor level calculation as the power source / package / measurement system consideration FFT estimation means. Will be described. Here, it is the same as that described in FIG. 12 in the eleventh embodiment, but as shown in the block diagram of FIG. 19, the measurement obtained from the power / package / measurement system non-consideration current estimation means (not shown). The current value for each cycle of the system non-considered power supply current result 1902 is averaged or the maximum value calculated so as to be convoluted into one cycle is used as an equivalent current source, and current is supplied to the LSI chip as the circuit information. RLC information 1901 in which at least one information of power supply information of the power supply, package information of the package of the semiconductor chip and measurement system information of a measurement system for measuring the characteristics of the semiconductor chip is added as analysis control information is equivalent to And an information estimation means for performing an FFT process and calculating an estimation result, adding to the current source and performing simulation, Kkeji and is configured to output the FFT result 1904 in consideration of the measurement system.

Here, the estimation operation of the power source / package / measurement system consideration current estimation means 1903 is shown in FIG. Here, the power source / package / measurement system non-considered current result and the power source / package / measurement system RLC information are read as input information (step 2001), and this input current information is set to a predetermined time as shown in FIG. It divides | segments by an interval (step 2002), and calculates the average value or maximum value of all the division | segmentation current information with the relative time on the basis of the divided | segmented time (step 2003). FIG. 22 shows an averaged current obtained by averaging the current information shown in FIG. In FIG. 21 and FIG. 22, the vertical axis represents current value and the horizontal axis represents time. Then, the corrected current information in which the power / package / measurement system RLC information is reflected on the current information thus calculated is subjected to FFT processing (step 2004), and the calculated FFT result is written as output information (step 2004). Step 2005).
According to such a configuration, it is possible to accurately represent the influence of the power supply net on the FFT result. Further, by performing averaging or maximum value processing at regular intervals, it is possible to estimate the influence of noise at high speed.

Embodiment 15
Next, a fifteenth embodiment of the present invention will be described.
Here, a method of removing a change other than the target frequency band from the current calculation result of the gate level and reflecting it in the calculation of the transistor level is adopted. That is, as a power / package / measurement system non-consideration current estimation means, an estimated current related to a cell, block or LSI is calculated at the gate level, and the calculated value is subjected to FFT, and after excluding a non-target frequency band from the result, A current calculation result in consideration of the influence of the power supply net is obtained by simulating a combination of the inverse FFT and the power supply net as a current source.

  The present invention uses the same configuration as block diagram 19 of the fourteenth embodiment. FFT of the measurement system non-considered power supply current result 1902 obtained from the power supply / package / measurement system non-consideration current estimation means (not shown), after excluding the non-target frequency band from the result, As an equivalent current source, the circuit information includes power supply information of a power source that supplies current to the LSI chip, package information of the package of the semiconductor chip, and measurement system information of a measurement system that measures the characteristics of the semiconductor chip. RLC information 1901 added with at least one of them as analysis control information is added to the equivalent current source for simulation, and includes information estimation means for performing an FFT process to calculate an estimation result, including a power source, a package, and It is configured to output an FFT result 1904 considering the measurement system.

  Here, the estimation operation of the power source / package / measurement system consideration FFT current estimation means 1903 is shown in FIG. Here, an estimated current obtained from a power source / package / measurement system non-consideration current estimation means (not shown) is input and FFT processing is performed (step 2401), and a non-target frequency band is excluded from this input information ( Step 2402), processing for excluding frequency band components other than those in a predetermined time range is performed, this is subjected to inverse FFT processing, and a current waveform is calculated (step 2403).

  After that, the frequency response in the measuring device when a current having this current waveform is applied to the RLC circuit of the power supply / package / measurement system is calculated (step 2404), and the current value in consideration of the power supply, package, and measurement system is output information (Step 2405).

According to such a configuration, it is possible to accurately represent the influence of the power supply net on the FFT result. Further, by performing FFT and inverse FFT, it is possible to reduce the information on the current source and finish the transistor level simulation in a short time. It is also event-driven and effective. Furthermore, analysis from a block or a plurality of FFT results is also possible.
Note that step 2402 may be omitted, and even when omitted, the effect that the information of the estimated current can be compressed by inverse FFT remains.

Embodiment 16
Next, a sixteenth embodiment of the present invention will be described. In the eleventh to fifteenth embodiments, the equivalent power supply current information is obtained from the circuit information, and the simulation is performed in combination with the analysis control information and the total impedance of the circuit information. However, in this method, the power supply, the package, By calculating the total impedance from the equivalent circuit of the measurement system, obtaining a function for correcting the equivalent power supply current information by this total impedance, calculating and correcting the frequency spectrum of the equivalent power supply current information by this function, The present invention is characterized in that a frequency spectrum of power supply current information considering a package and a measurement system is obtained.

  Here, a method is employed in which a gate level FFT calculation result as power source / package / measurement system non-consideration current estimation means is calculated by a function obtained from power source / package / measurement system RLC information. That is, the estimated current for the cell, block or LSI is calculated at the gate level, the calculated value is FFTed, the frequency response in the measuring device of the power supply / package / measurement system is calculated, and the response result is returned to the non-power supply / package / measurement system. A current calculation result in consideration of the influence of the power supply net is obtained by multiplying the consideration current result.

  FIG. 23 describes an operation method for calculating a gate level FFT calculation result as a power source / package / measurement system non-consideration current estimation means using a function obtained from the power source / package / measurement system RLC information. Here, it is the same as that described with reference to FIG. 12 in the eleventh embodiment. However, as shown in the block diagram of FIG. 23, the power / package / measurement system non-consideration current FFT result 2302 indicates that the power / package / measurement system is not considered. A current obtained by subjecting an estimated current obtained from a consideration current estimating means (not shown) to FFT processing is prepared. And information on at least one of the power supply information of the power supply for supplying current to the LSI chip, the package information of the package of the semiconductor chip, and the measurement system information of the measurement system for measuring the characteristics of the semiconductor chip The power source / package / measurement system RLC information 2301 is configured to output an FFT result 2304 in consideration of the power source, package, and measurement system.

FIG. 26 shows an estimation operation of the power source / package / measurement system consideration FFT current estimation unit 2303. Here, the estimated current obtained from the power source / package / measurement system non-consideration current estimation means (not shown) and the power source / package / measurement system RLC information as input information (step 2601) are input. The frequency response in the power supply / package / measurement system part is calculated from the / package / measurement system RLC information (step 2602), and the FFT result of the power / package / measurement system non-considered current is multiplied by the frequency response result (step 2602). 2603), and outputs this current value as output information (step 2604).
FIG. 27 shows the frequency response result at this time.

  According to such a configuration, the influence of the power supply / package / measurement system can be reflected in the frequency spectrum, and high-speed and high-accuracy calculation is possible. In this way, the influence of the FFT power supply net on the FFT result can be accurately expressed. Further, since the response result for each frequency is multiplied, the processing can be performed at a higher speed and the memory capacity can be reduced.

Embodiment 17
This example shows a modification of the estimation operation of the power source / package / measurement system consideration FFT current estimation unit 2303 in the sixteenth embodiment.
In the sixteenth embodiment, the frequency response in the power supply / package / measurement system measurement device is calculated and the response result is multiplied by the power supply / package / measurement system non-considered current result. In this example, however, the power supply / package / measurement is multiplied. The frequency response of the power source / package / measurement system measurement device for each frequency is calculated for the FFT result of the system non-consideration current result, and the response results are cumulatively processed.

  FIG. 25 shows an estimation operation of the power source / package / measurement system consideration FFT current estimation unit 2303. Here, the FFT result obtained by performing FFT processing on the estimated current obtained from the power source / package / measurement system non-consideration current estimation means (not shown) and the power source / package / measurement system RLC information are input information (step 2501). A measuring device for selecting a current value (noise level) for each frequency from the FFT result (step 2502) and supplying a current having an amplitude of the current value having the frequency to the RLC circuit of the power supply / package / measurement system Frequency frequency response is calculated (step 2503), the response result is cumulatively processed (step 2504), and it is determined whether or not the processing is completed for all frequencies (step 2505). Outputs frequency spectrum that takes into account the power supply, package, and measurement system, which are cumulative results of frequency response, as output information. (Step 2506).

  According to such a configuration, it is possible to accurately represent the influence of the power supply net on the FFT result. In addition, since the response results for each frequency are cumulatively processed, it is possible to express with higher accuracy.

Embodiment 18
This example is characterized by an analysis processing method.
That is, the power supply waveform result is used as a library, and the FFT characteristic of the entire circuit is calculated.
This apparatus is characterized in that it includes an FFT library in which cell or block current analysis using parameters such as input / output conditions, frequency, wiring capacity, and slew in advance is stored.

  FIG. 28 shows an apparatus configuration used in the unwanted radiation analysis method according to the embodiment of the present invention. The unnecessary radiation analysis apparatus shown in the figure performs cell or block current analysis using input / output conditions, frequency, wiring capacity, slew, and the like as parameters, a current waveform library 2801 storing the results, a netlist 2802, It consists of circuit input information 2803 and current FFT estimation means 2804, and outputs an FFT result 2805.

The current FFT estimation means 2804 performs analysis according to a flowchart as shown in FIG.
First, in step 2901, the net list information stored in the net list 3002 and the circuit input information 3003 are read.

In step 2902, the circuit scale, load capacity, waveform rounding, and circuit input information are estimated from the library corresponding to each cell.
Further, in step 2903, each current waveform corresponding to the circuit scale, load capacity, waveform rounding, and circuit input information is called from the library corresponding to each cell, and these are added together to calculate the power source current result.
Thereafter, in step 2904, FFT is performed, and in step 2905, output information is written.

  In other words, in this example, when calculating the FFT analysis result of the entire LSI, the calculation amount is greatly increased by adding the current waveforms from the FFT library instead of calculating the FFT analysis result of all the elements. FFT results can be obtained while reducing.

With the above method, by extracting the corresponding power supply current waveform from the library and performing FFT estimation, current calculation and FFT can be omitted, and the speed can be increased.
By combining this method with the eleventh to seventeenth embodiments, it is possible to obtain the FFT result with a higher speed and a smaller memory, and to estimate the influence of the noise of the entire LSI at a higher speed.

Embodiment 19
In this example, the FFT result is stored in the library, and the FFT characteristic of the entire circuit is calculated.

  That is, the present invention is characterized in that an FFT library in which current analysis of cells or blocks using parameters such as input / output conditions, frequency, wiring capacity, and slew in advance is stored.

  FIG. 30 shows an apparatus configuration used in the unwanted radiation analysis method according to one embodiment of the present invention. The unnecessary radiation analysis apparatus shown in FIG. 1 performs an analysis of the current of a cell or block using parameters such as input / output conditions, frequency, wiring capacity, and slew, and stores the results, an FFT library 3001, a netlist 3002, and a circuit input. It comprises information 3003 and current FFT estimation means 3004, and outputs an FFT result 3005.

The current FFT estimation means 3004 performs analysis according to a flowchart as shown in FIG.
First, in step 3101, the net list information stored in the net list 3102 and the circuit input information 3103 are read.

In step 3102, the circuit scale, load capacity, waveform rounding, and circuit input information are estimated from the library corresponding to each cell.
In step 3103, the circuit scale, load capacity, waveform rounding, circuit input information and corresponding FFT results are calculated from the library corresponding to each cell and integrated.
Thereafter, in step 3104, output information is written.

  In other words, in this example, when calculating the FFT analysis result of the entire LSI, it is not necessary to calculate the FFT analysis result of all elements, but by adding the current components of each frequency from the FFT library, the calculation amount is reduced. The FFT result can be obtained while greatly reducing.

By taking out from the library and performing FFT estimation by the above method, current calculation and FFT can be omitted, and the speed can be increased.
By combining this method with the eleventh to seventeenth embodiments, it is possible to obtain the FFT result with a higher speed and a smaller memory, and to estimate the influence of the noise of the entire LSI at a higher speed.
In this method, the FFT analysis result of the cell or block whose parameters are input / output conditions, frequency, wiring capacity, slew, etc. is previously stored as a library. However, the FFT data is obtained by static analysis or dynamic analysis. You may make it create. (Japanese Patent Application No. 11-196190, Japanese Patent Application No. 11-200247) Further, it is possible to reduce the data amount by narrowing down to the FFT result in the range to be estimated.

Embodiment 20
This example relates to a function level analysis method.
In other words, the FFT analysis results of the clock buffer, memory, FF, and IO with parameters such as input / output conditions, frequency, wiring capacity, slew, and configuration as a library are preliminarily synthesized from the function description only for the main components, The FFT result is estimated.

  FIG. 32 shows an apparatus configuration used in this unwanted radiation analysis method. The unnecessary radiation analysis apparatus shown in the figure includes a function description library 3201 that stores FFT analysis results of a clock buffer, memory, FF, and IO using parameters such as input / output conditions, frequency, wiring capacity, slew, and configuration, and functions. The function description part having the description 3202, circuit input information 3203, and function description FFT estimation means 3204 is configured to output a function description FFT result 3205.

The function description FFT estimation means 3204 performs analysis according to the flowchart shown in FIG.
First, in step 3301, the function description 3202 stored in the function description section and the circuit input information 3203 are read.

Next, in step 3302, functional grouping such as a clock tree memory, flip-flop, and input / output buffer as shown in FIG. 34 is performed from the function description.
In step 3303, the circuit scale, load capacity, waveform rounding, and circuit input information are estimated from the library corresponding to each group.
Further, in step 3304, from the library corresponding to each group, the circuit scale, load capacity, waveform rounding, circuit input information, and corresponding FFT results are calculated and integrated.
Thereafter, in step 3305, output information is written.

  In other words, in this example, when calculating the FFT analysis result of the entire LSI, the FFT analysis result of all the elements is not calculated, but is grouped and estimated at the functional level, so that the entire LSI can be estimated at high speed. The influence of noise can be estimated.

Embodiment 21
This example relates to a hybrid analysis method using the advantages of dynamic analysis and static analysis.
That is, an estimation method is selected in advance, and an optimum FFT result is estimated.
FIG. 35 shows a device configuration used in this unwanted radiation analysis method. The unnecessary radiation analysis apparatus shown in the figure has an estimation method selection means 3502 for selecting an estimation method from the netlist 3501 according to input / output conditions, frequency, wiring capacity, slew, configuration, required accuracy, and the like. The power source current FFT result estimating means 3503 for estimating the FFT result is combined with the estimation method, and the FFT result 3504 is output.

The estimation method selection means 3502 performs analysis according to a flowchart as shown in FIG.
First, in step 3601, input information is read.

In step 3602, the power consumption of each instance is estimated.
In step 3603, the estimation method is selected by using the high-precision estimation method for the instance with high power consumption and applying the high-speed estimation method to the other instances.

  In this way, high-speed processing can be performed.

Embodiment 22
After performing the rough analysis in the first step, the influence of the noise of the entire LSI can be estimated at high speed by analyzing in detail the large peak portion using dynamic analysis. (Fig. 37)

The estimation method selection means 3502 performs analysis according to a flowchart as shown in FIG.
First, in step 3701, input information is read.

In step 3702, the peak current of each instance is estimated.
In step 3703, the high-precision estimation method is used for the instance having a high peak, and the high-speed estimation method is applied to the other instances, and the estimation method is selected.

  In this way, high-speed processing can be performed.

Embodiment 23
In the first step, an analysis method may be selected for each block from the power consumption and FF / CLK concentration. (Fig. 38)

The estimation method selection means 3502 performs analysis according to a flowchart as shown in FIG.
First, in step 3801, input information is read.

In step 3802, the power consumption of each instance is estimated.
Then, in step 3803, the total power consumption is calculated for each block group, and in step 3804, the high-precision estimation method is used for the group having a high peak, and the high-speed estimation method is applied to the other, and the estimation method is selected. .
In this way, high-speed processing can be performed.

Embodiment 24
Alternatively, the sum of peak currents for each group may be calculated, and a high-precision estimation method may be applied to a group with a high peak, and a high-speed estimation method may be applied to the other. (Fig. 39)

The estimation method selection means 3502 performs analysis according to a flowchart as shown in FIG.
First, in step 3901, input information is read.

Next, in step 3902, the peak current of each instance is estimated.
Then, in step 3903, the sum of peak currents is calculated for each group, and in step 3904, the high-precision estimation method is used for the group with a high peak, and the high-speed estimation method is applied to the other, and the estimation method is selected.

  In this way, high-speed processing can be performed.

Embodiment 25
The number of flip-flop clock buffers for each group may be calculated, and a high-precision estimation method may be applied to a large number of groups, and a high-speed estimation method may be applied to other groups.

The estimation method selection means 3502 performs analysis according to a flowchart as shown in FIG.
First, in step 4001, input information is read.

In step 4002, the number of flip-flop clock buffers for each group is calculated, and the power consumption of each instance is estimated.
In step 4003, the estimation method is selected by using the high-precision estimation method for a large number of groups and applying the high-speed estimation method to the other groups.

  In this way, high-speed processing can be performed.

Embodiment 26
This example also relates to a hybrid analysis method using the advantages of dynamic analysis and static analysis.
That is, by determining according to the analysis accuracy, an estimation method is selected in advance, and an optimal FFT result estimation is performed.
FIG. 41 shows a device configuration used in this unwanted radiation analysis method. The unnecessary radiation analysis apparatus shown in the figure is an estimation method selection means for selecting an estimation method from the netlist 4101 and circuit input information 4102 according to input / output conditions, frequency, wiring capacity, slew, configuration, required accuracy, and the like. 4103 and a power source current FFT result estimating means 4104 for estimating the FFT result by combining the selected estimation method, and the FFT result 4105 is output.

The estimation method selection means 4102 performs analysis according to a flowchart as shown in FIG.
First, in step 4201, input information is read.

Next, in step 4202, the power consumption or peak current of each instance is estimated.
In step 4203, the number of changes of each instance is estimated.
In step 4204, the estimation method is selected by integrating the power consumption or peak current and the number of changes, using the high-precision estimation method for an instance with a high integrated value, and applying the high-speed estimation method for the other instances.
In this way, high-speed processing can be performed.

Embodiment 27
Alternatively, the frequency spectrum may be calculated by a high-speed estimation method, and the high-precision estimation method may be re-applied to a portion having a high peak.
That is, as shown in the flowchart in FIG. 43, the estimation method selection means 4102 executes analysis.
First, in step 4301, input information is read.

Next, in step 4302, a frequency spectrum (FFT result) is calculated by a fast estimation method.
In step 4303, the high-precision estimation method is re-applied to a portion having a high peak, and the estimation method is selected.

  In this way, high-speed and high-precision processing can be performed.

Embodiment 28.
Next, an unnecessary radiation analysis method using increment calculation will be described.
There is a problem that recalculation is required at the time of correction, and it takes a very long time. In this embodiment, this is done to solve this problem, and only the difference is calculated to increase the speed. It is characterized by that.

  FIG. 44 shows a device configuration used in this unwanted radiation analysis method. The unnecessary radiation analysis apparatus shown in the figure includes the RLC information 4401 of the power supply / package / measurement system, the frequency spectrum 4405 obtained by the FFT not considering the power supply package, input / output conditions, frequency, wiring capacity, slew, configuration, and necessary According to the accuracy and the like, the net list 4402 and the change point information 4403 indicating the change point are estimated by the power source package-considered FFT re-estimation means 4404, and the FFT result 4406 is output. .

The re-estimation method selection unit 4404 performs analysis according to the flowchart shown in FIG.
First, in step 4501, input information is read.

Next, in step 4502, it is determined whether or not the changed portion is a power source. If the changed portion is a power source, a power-considered FFT analysis is executed (step 4504).
If it is not the power source, only the changed part is replaced by the power source non-considering FFT analysis (step 4503), and then the power source considering FFT analysis is executed (step 4504).

  In this way, high-speed processing can be performed.

  The present invention performs unnecessary radiation analysis including analysis of changes in power supply current, which can be said to be the main cause of unwanted radiation, and optimizes the effect of decoupling due to resistance, capacitance, and inductance of the power supply and ground. Reflecting efficiently, it is possible to achieve both high speed and high accuracy and to evaluate unnecessary radiation of LSI in a realistic time on simulation. Furthermore, it is effective for effective EMI countermeasures by supporting the specification of the location where EMI occurs.

  Also, unnecessary radiation caused by the power supply, package, and measurement system can be analyzed with high accuracy at high speed and with a small amount of memory.

The block diagram which shows the structure for implement | achieving the unwanted radiation analysis method in the 11th Embodiment of this invention The flowchart figure for implement | achieving the unnecessary radiation analysis method in the 11th Embodiment of this invention The figure which shows an example of the net list used with the unnecessary radiation analysis method in 11th Embodiment Equivalent circuit diagram showing power supply package measurement system RLC information used in the unwanted radiation analysis method in the eleventh embodiment An example of a frequency spectrum obtained by the unwanted radiation analysis method according to the eleventh embodiment Diagram showing waveform model of estimated power supply current model The figure which shows the optimal waveform model used when implement | achieving the power-source / package / measurement-device non-considering current estimation means of 11th Embodiment of this invention using a logic simulator. The figure which shows an example of the data used by the 11th Embodiment of this invention Explanatory drawing which shows the calculation method of an equivalent power supply current in 11th Embodiment of this invention The figure which shows an example of the frequency spectrum data corresponding to the data of 8 used in the 11th Embodiment of this invention Equivalent circuit diagram showing power supply package measurement system RLC information used in the unwanted radiation analysis method in the eleventh embodiment The figure which shows the example of data of the detailed frequency memory | storage means in the 11th Embodiment of this invention The flowchart figure which shows the estimation method of the power supply package measurement system non-consideration estimation means in the 11th Embodiment of this invention The flowchart figure which shows the estimation method of the power supply package measurement system consideration estimation means in the 11th Embodiment of this invention The flowchart figure which shows the synchronous read-out method in the 12th Embodiment of this invention The flowchart figure which shows the estimation method of the power supply package measurement system non-consideration estimation means in the 12th Embodiment of this invention The flowchart figure which shows the estimation method of the power supply package measurement system consideration estimation means in the 12th Embodiment of this invention The flowchart figure which shows the estimation method of the power supply package measurement system consideration estimation means in the 13th Embodiment of this invention The flowchart figure of the FFT analysis in the 14th Embodiment of this invention The flowchart figure which shows the estimation method of the power supply package measurement system consideration estimation means in the 14th Embodiment of this invention The figure which shows the current information in the 14th Embodiment of this invention The figure which shows the average current information in the 14th Embodiment of this invention The flowchart figure of the FFT analysis in the 15th Embodiment of this invention The flowchart figure which shows the estimation method of the power supply package measurement system consideration estimation means in the 17th Embodiment of this invention The flowchart figure which shows the operation | movement of the power supply / package / measurement system consideration FFT current estimation means in the 17th Embodiment of this invention. The flowchart figure which shows the estimation method of the power supply package measurement system consideration estimation means in the 16th Embodiment of this invention The figure which shows the frequency response result in the 16th Embodiment of this invention The block diagram which shows the structure for implement | achieving the unwanted radiation analysis method in the 18th Embodiment of this invention. The flowchart figure which shows the estimation method of the FFT estimation means in the 18th Embodiment of this invention The block diagram which shows the structure for implement | achieving the unnecessary radiation analysis method in the 19th Embodiment of this invention The flowchart figure which shows the estimation method of the FFT estimation means in the 19th Embodiment of this invention The block diagram which shows the structure for implement | achieving the unnecessary radiation analysis method in the 20th Embodiment of this invention. The flowchart figure which shows the estimation method of the FFT estimation means in the 20th Embodiment of this invention The figure which shows an example of the function description in the 10th Embodiment of this invention The block diagram which shows the estimation method using the hybrid analysis in the 21st Embodiment of this invention The flowchart figure which shows the estimation method using the hybrid analysis in the 21st Embodiment of this invention The flowchart figure which shows the estimation method using the hybrid analysis in the 22nd Embodiment of this invention The flowchart figure which shows the estimation method using the hybrid analysis in the 23rd Embodiment of this invention The flowchart figure which shows the estimation method using the hybrid analysis in 24th Embodiment of this invention The flowchart figure which shows the estimation method using the hybrid analysis in the 25th Embodiment of this invention Device block diagram for executing the estimation method using hybrid analysis in the twenty-sixth embodiment of the present invention The flowchart figure which shows the estimation method using the hybrid analysis in the 26th Embodiment of this invention The flowchart figure which shows the estimation method using the hybrid analysis in the 27th Embodiment of this invention A block diagram showing an apparatus for executing an estimation method using incremental analysis according to a twenty-eighth embodiment of the present invention. The flowchart figure which shows the estimation method using the incremental analysis in the 28th Embodiment of this invention. The block diagram which shows the conceptual structure for implement | achieving the unnecessary radiation analysis method of a prior art example The block diagram which shows the conceptual structure for implement | achieving the unnecessary radiation analysis method of the transistor level of a prior art example The flowchart figure which shows the unnecessary radiation optimization process of the 1st Embodiment of this invention The flowchart figure which shows the unnecessary radiation optimization process of the 2nd Embodiment of this invention The flowchart figure which shows the unnecessary radiation optimization process of the 3rd Embodiment of this invention. The flowchart figure which shows the unnecessary radiation optimization process of the 4th Embodiment of this invention The flowchart figure which shows the unnecessary radiation optimization process of the 4th Embodiment of this invention Overall processing flowchart showing an unnecessary radiation optimization process of the fifth embodiment of the present invention The flowchart figure which shows the process process at the time of the floor plan of the unnecessary radiation optimization process of the 5th Embodiment of this invention The flowchart figure which shows the process process at the time of the layout cell arrangement | positioning of the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The figure which shows the unnecessary radiation optimization process of the 6th Embodiment of this invention The block diagram which shows the structure for implement | achieving the unwanted radiation analysis method in the 7th Embodiment of this invention The figure which shows the example of data of the FFT result storage means in the 7th Embodiment of this invention The figure which shows the example of data of the sort result memory | storage means in the 7th Embodiment of this invention Flowchart of FFT sort means in the seventh embodiment of the present invention The figure which shows the display of the FFT result of embodiment of this invention The figure which shows the example of a display of the circuit data of embodiment of this invention The figure which shows the function display of embodiment of this invention The figure which shows the function display of embodiment of this invention The figure which shows the display of the report output of embodiment of this invention The flowchart figure which shows the change process process of the circuit data of the 7th Embodiment of this invention The flowchart figure which shows the change process process of the circuit data of the 8th Embodiment of this invention The flowchart figure which shows the change process process of the net list of the 9th Embodiment of this invention The flowchart figure which shows the change process process of the net list of the 10th Embodiment of this invention

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 Circuit information 102 Analysis control input part 103 Unnecessary radiation simulation part 104 Analysis information display part 105 Optimization control input part 106 Unnecessary radiation optimization part 107 Optimization information display part

Claims (10)

An analysis process for analyzing the waveform of the power supply current of the LSI by executing a simulation;
Extracting a block or instance having a large amount of noise in the analysis step;
A step of performing power supply noise reduction processing on the extracted block or instance according to a design stage;
The LSI design is characterized in that the analysis is performed again, and the analysis step, the instance extraction step, and the power supply noise reduction processing step are repeated until the noise amount becomes smaller than a predetermined value. Support method.   2. The LSI design support method according to claim 1, wherein the step of performing power supply noise processing in accordance with the design stage includes a first step of performing layout data change processing in a floor plan stage.   3. The LSI design support method according to claim 1, wherein the step of performing power supply noise reduction processing in accordance with the design stage includes a second step of performing layout data change processing in the layout stage. The first step is a step of calculating a necessary amount of decoupling capacity from the peak current information of the target block extracted in the step of extracting;
Calculating a deficiency of the power source area from the decoupling capacity calculated in the calculating step;
The LSI design support method according to claim 2, further comprising a step of changing layout data based on the shortage amount. The second step is a step of calculating a necessary amount of decoupling capacity from the peak current information of the target block extracted in the extracting step;
Calculating a deficiency of the power source area from the decoupling capacity calculated in the calculating step;
The LSI design support method according to claim 3, further comprising a step of changing layout data based on the shortage amount. The first step is a step of calculating a necessary amount of decoupling capacity from the peak current information of the target block extracted in the step of extracting;
Calculating a deficiency of the power source area from the decoupling capacity calculated in the calculating step;
The LSI design support method according to claim 2, further comprising a step of changing layout data for a necessary block based on the shortage amount.   5. The LSI according to claim 4, wherein the step of changing the layout data is a step of changing an aspect ratio of the target block, that is, an aspect ratio, and substantially changing a wiring area of a power supply current path. Design support method.   The step of changing the layout data is a step of changing a wiring area of a power supply current path by changing a block position of the target block and changing a power supply current path connected to the target block. The LSI design support method according to claim 4.   The second step inverts one direction of the ground lines or the cell lines arranged in common to the power supply lines so as to have a desired decoupling capacitance, and between the adjacent power supply lines and the ground lines. 4. The LSI design support method according to claim 3, wherein a predetermined interval is provided in the LSI.   In the second step, an auxiliary line connected to a potential between the power supply line and the ground line is disposed on an upper layer or a lower layer of a layer where the power supply line and the ground line adjacent to each other are formed, The method further includes a step of adjusting the combined capacitance between the power line and the ground line, the ground line and the auxiliary line, and the auxiliary line and the power line so as to have a desired decoupling capacity. The LSI design support method according to claim 3.

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