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JP2005175260A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP2005175260A
JP2005175260A JP2003414649A JP2003414649A JP2005175260A JP 2005175260 A JP2005175260 A JP 2005175260A JP 2003414649 A JP2003414649 A JP 2003414649A JP 2003414649 A JP2003414649 A JP 2003414649A JP 2005175260 A JP2005175260 A JP 2005175260A
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Prior art keywords
semiconductor
semiconductor chip
semiconductor device
chip
substrate
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JP2003414649A
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Japanese (ja)
Inventor
Koji Furusawa
宏治 古澤
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NEC Corp
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NEC Corp
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Priority to JP2003414649A priority Critical patent/JP2005175260A/en
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein the entire thickness cannot be thinned since a spacer or the like is required in a conventional configuration when composing a semiconductor device by laminating a plurality of semiconductor chips having an external electrode terminal arrangement with the same size or an identical external electrode terminal arrangement. <P>SOLUTION: An electrode pad is formed on the upper surface of the semiconductor chip, a conductor bump is formed on the lower surface, and the chips are laminated on the substrate. By performing second bonding of a wire to the electrode pad of the semiconductor chip, the same type of chip can be laminated and the entire thickness can be thinned. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体装置とその製造方法に関し、特に同一サイズの半導体装置を積層して形成するスタックＬＳＩに関する。   The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a stack LSI in which semiconductor devices of the same size are stacked.

半導体チップの実装効率を上げるため、複数の半導体チップを積層して一つのＬＳＩパッケージを構成するスタックＬＳＩ技術が普及している。通常、積層された各半導体チップと基板とはワイヤボンディング法によって接続される。ワイヤボン−ディングは通常半導体チップにファーストボンディングされるため、面積の大きい半導体チップ一番下に配置し順にピラミッド状に積層する方式が行われている。   In order to increase the mounting efficiency of a semiconductor chip, a stacked LSI technique in which a plurality of semiconductor chips are stacked to form a single LSI package has become widespread. Usually, each laminated semiconductor chip and the substrate are connected by a wire bonding method. Since wire bonding is usually first-bonded to a semiconductor chip, a method of placing the semiconductor chip at the bottom of a large-sized semiconductor chip and sequentially stacking it in a pyramid shape is used.

一方、同一サイズの半導体チップを積層する場合は、例えば図２に示されたような構成が知られている。まず、第１の半導体チップ１２０が導体バンプ１５０を介してフリップチップ接続でインタポーザ基板１１０に対して接続される。第１の半導体チップ１２０とインタポーザ基板１１０の間には接着剤１７０が形成されている。次に第１の半導体チップ１２０の上面に、第２の半導体チップ１３０を接着剤１７１で接着し、金ワイヤー１６０によるボールボンディング接続にてインタポーザ基板１１０と接続する。２枚の半導体チップは周囲を樹脂１８０で封止される。しかし、この技術で積層できる半導体チップは２枚までである。第３の半導体チップを積層する場合は第１、第２の半導体チップより小さいサイズの半導体チップを用いる必要がある。同一サイズの半導体チップを積層するならば、スペーサを介在させてその上に積層する必要がある。また、図２の構成では、フリップチップ接続が使用できるのは一番下段の半導体チップのみである。   On the other hand, when stacking semiconductor chips of the same size, for example, a configuration as shown in FIG. 2 is known. First, the first semiconductor chip 120 is connected to the interposer substrate 110 via the conductor bumps 150 by flip chip connection. An adhesive 170 is formed between the first semiconductor chip 120 and the interposer substrate 110. Next, the second semiconductor chip 130 is bonded to the upper surface of the first semiconductor chip 120 with an adhesive 171 and connected to the interposer substrate 110 by ball bonding connection using a gold wire 160. The periphery of the two semiconductor chips is sealed with resin 180. However, up to two semiconductor chips can be stacked with this technology. When the third semiconductor chip is stacked, it is necessary to use a semiconductor chip having a smaller size than the first and second semiconductor chips. If semiconductor chips of the same size are stacked, it is necessary to stack them on top of each other with a spacer interposed. In the configuration of FIG. 2, flip chip connection can be used only for the lowermost semiconductor chip.

さらに別の技術としては、同一サイズの２つの半導体チップであって互いに折り返し対照の位置に電気接続パッドを備えたチップを積層する技術が知られている。これら２つの半導体チップは該電気接続パッドとその間に配置される導体バンプを介して互いに対向して接続する。この半導体装置では、ボンディングワイヤは上記電気接続パッド上に配置された導体バンプにセカンドボンディングされ、基板に対してファーストボンディングされる。電力や信号が基板側からボンディングワイヤを介して両半導体チップに供給される（例えば、特許文献１参照）。   As yet another technique, a technique is known in which two semiconductor chips of the same size and stacked with chips each having an electrical connection pad at a position to be compared with each other are known. These two semiconductor chips are connected to face each other through the electrical connection pads and conductor bumps disposed therebetween. In this semiconductor device, the bonding wires are second-bonded to the conductor bumps disposed on the electrical connection pads and first bonded to the substrate. Electric power and signals are supplied to both semiconductor chips from the substrate side via bonding wires (see, for example, Patent Document 1).

特開２００２−３５９３４６号公報（第６−８頁、図１、図２）JP 2002-359346 A (page 6-8, FIGS. 1 and 2)

しかし、図２に記載の半導体装置では、同一サイズの半導体チップは２つしか積層できない。同一サイズのチップをさらに積層する場合はスペーサをチップ上に配置しなければならない。さらに、上側の半導体チップ上面にボンディングワイヤをファーストボンディングする構成なので、樹脂モールド後の半導体装置の厚みを薄くすることが困難である。   However, in the semiconductor device shown in FIG. 2, only two semiconductor chips of the same size can be stacked. When further stacking chips of the same size, spacers must be arranged on the chips. Furthermore, since the bonding wire is first bonded to the upper surface of the upper semiconductor chip, it is difficult to reduce the thickness of the semiconductor device after resin molding.

また、上記特許文献１記載の半導体装置では、原理的には同一サイズの半導体チップを３以上積層することが可能である。しかし、対向して接続される半導体チップは折り返し対照の配置で電気接続パッドを形成するため、同一構造の半導体チップを順次フリップチップ接続して積層することができない。   Further, in the semiconductor device described in Patent Document 1, it is possible in principle to stack three or more semiconductor chips of the same size. However, since the semiconductor chips connected to face each other form an electrical connection pad in a folded-back arrangement, semiconductor chips having the same structure cannot be sequentially stacked by flip-chip connection.

本発明は上記課題を解決するため、同一サイズで、同一の電極パッドの配置構造を有する複数の半導体チップを容易にフリップチップ接続により積層でき、かつ樹脂モールド後の厚みを薄くすることができる半導体装置とその製造方法を提供することを目的とする。   In order to solve the above problems, the present invention provides a semiconductor in which a plurality of semiconductor chips having the same size and the same electrode pad arrangement structure can be easily stacked by flip chip connection, and the thickness after resin molding can be reduced. An object is to provide an apparatus and a method for manufacturing the same.

本発明の半導体装置は、複数の半導体チップを基板上に積層して構成し、下面に導電体バンプを備え上面に導体部を備えた半導体チップをフリップチップ接続によって積層した構成を備え、前記導体部と基板部とを接続し該導体上に直接セカンドボンディングされたボンディングワイヤを備える。上記導体部は半導体チップに形成された回路部から独立して形成されることができる。導体部は前記半導体チップ上に絶縁層を介して形成することができる。上記半導体チップは、導体部から所定の距離だけ離れた領域に回路部を有することが望ましい。全体の厚みを薄くするため、最上部の半導体チップの導体部と基板部の間にはボンディングワイヤを配置しないことが望ましい。上記基板と半導体チップとの間、および各半導体チップ間には樹脂層を配置することが望ましい。また導体部は所定の電気回路を構成することができる。また上記半導体チップは同一サイズであることが可能である。   The semiconductor device of the present invention comprises a plurality of semiconductor chips stacked on a substrate, and a structure in which a semiconductor chip having a conductor bump on the lower surface and a conductor on the upper surface is stacked by flip chip connection, and the conductor A bonding wire that connects the board and the board and is second-bonded directly on the conductor. The conductor part can be formed independently of the circuit part formed on the semiconductor chip. The conductor portion can be formed on the semiconductor chip via an insulating layer. The semiconductor chip preferably has a circuit portion in a region separated from the conductor portion by a predetermined distance. In order to reduce the overall thickness, it is desirable not to arrange a bonding wire between the conductor portion of the uppermost semiconductor chip and the substrate portion. It is desirable to dispose a resin layer between the substrate and the semiconductor chip and between the semiconductor chips. The conductor portion can constitute a predetermined electric circuit. The semiconductor chips can be the same size.

本発明の半導体装置の製造方法は、所定の半導体チップの上面に導体部を形成し下面に導電体バンプを形成する工程と、基板上の導体部に半導体チップをフリップチップ接続する工程と、基板の導体部にファーストボンディングし半導体チップ上面の導体部にセカンドボンディングしてボンディングワイヤを形成する工程と、ワイヤボンディングされた半導体チップ上面に半導体チップをフリップチップ接続する工程とを備える。また、基板上の半導体チップ配置領域に接着樹脂層を形成する工程、および半導体チップ上に接着樹脂層を形成する工程、半導体ウェハ上に複数の半導体チップを形成しさらに各半導体チップ上に絶縁層と導体層を形成する工程、および上記基板上に積層された複数の半導体チップを樹脂モールドする工程を備えることができる。   A method of manufacturing a semiconductor device of the present invention includes a step of forming a conductor portion on an upper surface of a predetermined semiconductor chip and forming a conductor bump on the lower surface, a step of flip-chip connecting the semiconductor chip to the conductor portion on the substrate, Forming a bonding wire by first bonding to the conductor portion and second bonding to the conductor portion on the upper surface of the semiconductor chip, and flip-chip connecting the semiconductor chip to the upper surface of the wire-bonded semiconductor chip. Also, a step of forming an adhesive resin layer in a semiconductor chip arrangement region on the substrate, a step of forming an adhesive resin layer on the semiconductor chip, a plurality of semiconductor chips on the semiconductor wafer, and an insulating layer on each semiconductor chip And a step of forming a conductor layer and a step of resin molding a plurality of semiconductor chips stacked on the substrate.

本発明の半導体装置とその製造方法では、同一サイズで、同一の電極パッド配置構造を有する複数の半導体チップを容易にフリップチップ接続により積層でき、かつ樹脂モールド後の厚みを薄くすることができる。   In the semiconductor device of the present invention and the manufacturing method thereof, a plurality of semiconductor chips having the same size and the same electrode pad arrangement structure can be easily stacked by flip chip connection, and the thickness after resin molding can be reduced.

図１は、本発明の半導体装置の具体例を示す断面図である。インタポーザ基板１０上に、第１の半導体チップ２０と第２の半導体チップ３０の２枚の半導体チップが積層されている。インタポーザ基板１０下面の各電極パッドには、マザーボードとの接続に用いるハンダバンプ６０が形成されている。第１の半導体チップ２０は、その下面に電極パッドを備え、該電極パッド上に金バンプ２１を備える。この金バンプ２１により、第１の半導体チップ２０はインタポーザ基板１０上へフリップチップ接続される。第１の半導体チップ２０が配置されるインタポーザ基板１０の領域には、予め接着フィルム２２が形成されている。該接着フィルム２２は半導体チップ２０を固定し、また半導体チップ２０と基板１０との隙間を埋める。第１の半導体チップ２０の上面側には、まずポリイミド層（絶縁層）２３が形成され、この上に銅の導電層２４が積層されている。銅の導電層２４は第１の半導体チップ２０に形成される回路とは独立に配置されている。これら２つの層２３、２４は配線層２５を構成する。この配線層２５は、第２の半導体チップ３０の金バンプ３１によるフリップチップ接続と、ボンディングワイヤ２６によるボンディングを共に考慮した所定のパターンに形成される。配線層２５の電極パッド部とインタポーザ基板１０の電極部との間が金のボンディングワイヤ２６でボールボンディングされている。金のボンディングワイヤ２６は、インタポーザ基板１０にファーストボンディングされ、配線層２５の電極パッドに直接セカンドボンディングされている。上記配線層には簡単な抵抗やコイルを形成することも可能である。   FIG. 1 is a cross-sectional view showing a specific example of the semiconductor device of the present invention. Two semiconductor chips, a first semiconductor chip 20 and a second semiconductor chip 30, are stacked on the interposer substrate 10. Solder bumps 60 used for connection to the mother board are formed on each electrode pad on the lower surface of the interposer substrate 10. The first semiconductor chip 20 includes an electrode pad on its lower surface, and a gold bump 21 on the electrode pad. The first semiconductor chip 20 is flip-chip connected to the interposer substrate 10 by the gold bumps 21. An adhesive film 22 is formed in advance in the region of the interposer substrate 10 where the first semiconductor chip 20 is disposed. The adhesive film 22 fixes the semiconductor chip 20 and fills the gap between the semiconductor chip 20 and the substrate 10. A polyimide layer (insulating layer) 23 is first formed on the upper surface side of the first semiconductor chip 20, and a copper conductive layer 24 is laminated thereon. The copper conductive layer 24 is disposed independently of the circuit formed on the first semiconductor chip 20. These two layers 23 and 24 constitute a wiring layer 25. The wiring layer 25 is formed in a predetermined pattern considering both flip-chip connection by the gold bumps 31 of the second semiconductor chip 30 and bonding by the bonding wires 26. Ball bonding is performed between the electrode pad portion of the wiring layer 25 and the electrode portion of the interposer substrate 10 with a gold bonding wire 26. The gold bonding wire 26 is first bonded to the interposer substrate 10 and second bonded directly to the electrode pad of the wiring layer 25. A simple resistor or coil can be formed on the wiring layer.

半導体チップに形成される回路部は、上記セカンドボンディングの与える影響を少なくするため、このボンディングされる電極パッド部の直下には形成されず、また該電極パッド部から所定の距離だけ離れた領域に形成される。第１の半導体チップ２０上面の電極上には狭い間隔で第２の半導体チップ３０がフリップチップ接続される。なお第１の半導体チップ２０と第２の半導体チップ３０との間には接着フィルム３２が配置される。ワイヤ２６が配線層２５に直接セカンドボンディングされているので、次に積層される第２の半導体チップとの間隙を小さくすることができる。この構成において、第２の半導体チップは、第１の半導体チップとは独立にインタポーザ基板１０と接続しうる。第２の半導体チップは第１の半導体チップと同一サイズ、同一構造を有する。従って第２の半導体チップ３０の上面には上記と同様の配線層２５が形成されている。しかし、最上部の半導体チップ（図１の例では第２の半導体チップ）とインタポーザ基板１０との間にはボンディングワイヤが形成されない。図１には示されないが、さらに半導体チップを積層する場合、上述と同様の構造が繰り返される。積層される半導体チップは後述するように半導体ウェハから複数形成された同一サイズ、同一構造を有する場合が現実的である。しかし、異なる機能を有する半導体チップ同士の積層も可能であり、また積層に支障を生じなければ半導体チップの金バンプ形成位置、セカンドボンディング位置、または配線層２５の構成が半導体チップ間で相違していてもよい。   In order to reduce the influence of the second bonding, the circuit portion formed on the semiconductor chip is not formed immediately below the electrode pad portion to be bonded, and in a region separated from the electrode pad portion by a predetermined distance. It is formed. The second semiconductor chip 30 is flip-chip connected to the electrodes on the upper surface of the first semiconductor chip 20 at a narrow interval. An adhesive film 32 is disposed between the first semiconductor chip 20 and the second semiconductor chip 30. Since the wire 26 is directly second bonded to the wiring layer 25, the gap with the second semiconductor chip to be stacked next can be reduced. In this configuration, the second semiconductor chip can be connected to the interposer substrate 10 independently of the first semiconductor chip. The second semiconductor chip has the same size and the same structure as the first semiconductor chip. Accordingly, a wiring layer 25 similar to the above is formed on the upper surface of the second semiconductor chip 30. However, no bonding wire is formed between the uppermost semiconductor chip (the second semiconductor chip in the example of FIG. 1) and the interposer substrate 10. Although not shown in FIG. 1, when further stacking semiconductor chips, the same structure as described above is repeated. As will be described later, it is practical that a plurality of stacked semiconductor chips have the same size and the same structure formed from a semiconductor wafer. However, it is possible to stack semiconductor chips having different functions, and if there is no problem with the stacking, the position of the gold bump formation, the second bonding position, or the wiring layer 25 of the semiconductor chip differs between the semiconductor chips. May be.

次に上記半導体装置の製造方法について説明する。公知の半導体製造技術によって、半導体ウェハに複数の半導体チップに対応する電気回路を形成する。このウェハを各半導体チップごとに切断する前に、ウェハのままでポリイミド層２３を形成し、この上の配線層不要部分にレジストをパターニングする。次に所定形状の銅パターンをメッキ形成する。レジストを除去して銅パターンを形成する。表面絶縁層としてポリイミドをパターニング塗布する。またウェハ下面に電極パッドを形成する。この後、各半導体チップに切断する。切断された各チップの下面に金バンプを形成する。次に、予め用意したインタポーザ基板１０上で上記半導体チップが設置される領域に接着フィルム２２を形成する。接着フィルム２２は例えばスクリーン印刷によって形成することができ、あるいは所定形状のフィルムを貼り付けることができる。この接着フィルム２２上に第１の半導体チップ２０をフリップチップ接続する。   Next, a method for manufacturing the semiconductor device will be described. Electric circuits corresponding to a plurality of semiconductor chips are formed on a semiconductor wafer by a known semiconductor manufacturing technique. Before the wafer is cut for each semiconductor chip, the polyimide layer 23 is formed as it is, and a resist is patterned on the wiring layer unnecessary portion. Next, a copper pattern having a predetermined shape is formed by plating. The resist is removed to form a copper pattern. Polyimide is applied by patterning as a surface insulating layer. An electrode pad is formed on the lower surface of the wafer. Thereafter, the semiconductor chip is cut. Gold bumps are formed on the lower surface of each cut chip. Next, an adhesive film 22 is formed in a region where the semiconductor chip is placed on the interposer substrate 10 prepared in advance. The adhesive film 22 can be formed by, for example, screen printing, or a film having a predetermined shape can be attached. The first semiconductor chip 20 is flip-chip connected on the adhesive film 22.

次に第１の半導体チップ２０の上面には接着フィルム３２を上記方法によって形成する。その後のボンディングワイヤ２６を配置する工程では、まず金ワイヤをインタポーザ基板の所定の電極パッドにファーストボンディングし、続けて半導体チップ２０上面の銅パターンの所定位置にセカンドボンディングする。次に上記ワイヤがセカンドボンディングされた第１の半導体チップ２０の電極パッド上に第２の半導体チップをフリップチップボンディングする。第２の半導体チップの金バンプはセカンドボンディングされたワイヤ上に接続される場合と、セカンドボンディングされる銅パターン上に接続される場合がある。さらに３以上の半導体チップを積層するときは、同様の工程を繰り返す。所望の数の半導体チップの積層とワイヤの形成が完了したのち、インタポーザ基板１０を樹脂５０で封止する。   Next, the adhesive film 32 is formed on the upper surface of the first semiconductor chip 20 by the above method. In the subsequent step of disposing the bonding wire 26, first, a gold wire is first bonded to a predetermined electrode pad of the interposer substrate, and then second bonded to a predetermined position of the copper pattern on the upper surface of the semiconductor chip 20. Next, a second semiconductor chip is flip-chip bonded onto the electrode pad of the first semiconductor chip 20 to which the wire is second bonded. The gold bumps of the second semiconductor chip may be connected on a second bonded wire or on a second bonded copper pattern. Further, when three or more semiconductor chips are stacked, the same process is repeated. After the desired number of semiconductor chips are stacked and the wires are formed, the interposer substrate 10 is sealed with the resin 50.

本発明の半導体装置の構成例を示す断面図。FIG. 10 is a cross-sectional view illustrating a structure example of a semiconductor device of the invention. 従来の半導体装置の構成例を示す断面図。Sectional drawing which shows the structural example of the conventional semiconductor device.

符号の説明Explanation of symbols

１０ インタポーザ基板
２０ 第１の半導体チップ
２２、３２ 接着フィルム
２６ ボンディングワイヤ
３０ 第２の半導体チップ
DESCRIPTION OF SYMBOLS 10 Interposer board | substrate 20 1st semiconductor chip 22, 32 Adhesive film 26 Bonding wire 30 2nd semiconductor chip

Claims (14)

複数の半導体チップを基板上に積層して構成した半導体装置において、下面に導電体バンプを備え上面に導体部を備えた半導体チップをフリップチップ接続によって積層した構成を備え、前記導体部と基板とを接続し該導体上に直接セカンドボンディングされたボンディングワイヤを備えることを特徴とする半導体装置。 A semiconductor device configured by laminating a plurality of semiconductor chips on a substrate, comprising a configuration in which a semiconductor chip having conductor bumps on the lower surface and a conductor portion on the upper surface is laminated by flip chip connection, the conductor portion and the substrate, And a bonding wire that is directly second bonded on the conductor. 前記導体部は半導体チップに形成された回路部から独立して形成されている請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the conductor portion is formed independently of a circuit portion formed in the semiconductor chip. 前記半導体チップは、該導体部から所定の距離だけ離れた領域に回路部を有する請求項１または２記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the semiconductor chip has a circuit portion in a region separated from the conductor portion by a predetermined distance. 最上部の半導体チップの導体部と基板部の間にはボンディングワイヤが配置されない請求項１、２または３のいずれか１つに記載の半導体装置。 4. The semiconductor device according to claim 1, wherein a bonding wire is not disposed between the conductor portion of the uppermost semiconductor chip and the substrate portion. 前記基板と半導体チップとの間、および各半導体チップ間には樹脂層が配置されている請求項１、２、３または４のいずれか１つに記載の半導体装置。 The semiconductor device according to claim 1, wherein a resin layer is disposed between the substrate and the semiconductor chip and between the semiconductor chips. 前記導体部は前記半導体チップ上に絶縁層を介して形成される請求項２記載の半導体装置。 The semiconductor device according to claim 2, wherein the conductor portion is formed on the semiconductor chip via an insulating layer. 前記導体部は所定の電気回路を構成している請求項６記載の半導体装置。 The semiconductor device according to claim 6, wherein the conductor portion constitutes a predetermined electric circuit. 前記半導体チップは同一サイズである請求項１、２、３、４、５、６、または７のいずれか１つに記載の半導体装置 The semiconductor device according to claim 1, wherein the semiconductor chips have the same size. 前記半導体チップは半導体メモリである請求項１ないし８のうちいずれか１つに記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor chip is a semiconductor memory. 前記基板下面には導電体バンプが形成されている請求項１ないし９のうちいずれか１つに記載の半導体装置。 The semiconductor device according to claim 1, wherein a conductor bump is formed on the lower surface of the substrate. 半導体装置の製造方法であって、
所定の半導体チップの上面に導体部を形成し下面に導電体バンプを形成する工程と、
基板上の導体部に前記半導体チップをフリップチップ接続する工程と、
前記基板の導体部にファーストボンディングし前記半導体チップ上面の導体部にセカンドボンディングしてボンディングワイヤを形成する工程と、
前記ワイヤボンディングされた半導体チップ上面に前記半導体チップをフリップチップ接続する工程と、
を備えることを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device, comprising:
Forming a conductor portion on the upper surface of a predetermined semiconductor chip and forming a conductor bump on the lower surface;
Flip chip connecting the semiconductor chip to a conductor on a substrate;
Forming a bonding wire by first bonding to the conductor portion of the substrate and second bonding to the conductor portion of the upper surface of the semiconductor chip;
Flip chip connecting the semiconductor chip to the upper surface of the wire bonded semiconductor chip;
A method for manufacturing a semiconductor device, comprising: 基板上の半導体チップ配置領域に接着樹脂層を形成する工程、および半導体チップ上に接着樹脂層を形成する工程を備える請求項１１記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 11, comprising a step of forming an adhesive resin layer in a semiconductor chip arrangement region on the substrate and a step of forming an adhesive resin layer on the semiconductor chip. 半導体ウェハ上に複数の半導体チップを形成し、さらに各半導体チップ上に絶縁層と導体層を形成する工程を備える請求項１１記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 11, further comprising forming a plurality of semiconductor chips on the semiconductor wafer and further forming an insulating layer and a conductor layer on each semiconductor chip. 前記基板上に積層された複数の半導体チップを樹脂モールドする工程を備える請求項１１記載の半導体の製造方法。
The semiconductor manufacturing method according to claim 11, further comprising resin-molding a plurality of semiconductor chips stacked on the substrate.
JP2003414649A 2003-12-12 2003-12-12 Semiconductor device and manufacturing method thereof Pending JP2005175260A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011129272A1 (en) * 2010-04-13 2011-10-20 積水化学工業株式会社 Attachment material for semiconductor chip bonding, attachment film for semiconductor chip bonding, semiconductor device manufacturing method, and semiconductor device
US8384200B2 (en) 2006-02-20 2013-02-26 Micron Technology, Inc. Semiconductor device assemblies including face-to-face semiconductor dice and systems including such assemblies

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8384200B2 (en) 2006-02-20 2013-02-26 Micron Technology, Inc. Semiconductor device assemblies including face-to-face semiconductor dice and systems including such assemblies
US8927332B2 (en) 2006-02-20 2015-01-06 Micron Technology, Inc. Methods of manufacturing semiconductor device assemblies including face-to-face semiconductor dice
US9269695B2 (en) 2006-02-20 2016-02-23 Micron Technology, Inc. Semiconductor device assemblies including face-to-face semiconductor dice and related methods
WO2011129272A1 (en) * 2010-04-13 2011-10-20 積水化学工業株式会社 Attachment material for semiconductor chip bonding, attachment film for semiconductor chip bonding, semiconductor device manufacturing method, and semiconductor device
JP4922474B2 (en) * 2010-04-13 2012-04-25 積水化学工業株式会社 Semiconductor device
CN102834907A (en) * 2010-04-13 2012-12-19 积水化学工业株式会社 Attachment material for semiconductor chip bonding, attachment film for semiconductor chip bonding, semiconductor device manufacturing method, and semiconductor device

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