JP2005174548A - Information recording device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information recording device capable of employing a recording form to a recording medium capable of smoothly performing continuous reproducing of already written data and following additionally written data. <P>SOLUTION: A clock signal WCK for writing synchronized with a wobble signal is generated by a PLL circuit 70. A synchronisation signal SY recorded in each sync frame is generated by counting a clock signal WCK in a sync adding circuit 85 as using the detection signal SD of a sync frame synchronisation signal output from CPU9 as a trigger. Before writing, a triangle wave is generated by a triangle wave generation circuit 81 based on the synchronisation signal SY and sample-holds the triangle wave by a sample-hold circuit 82 with a prepit signal. A hold output is supplied to a varicap of a phase shift circuit 75 in a PLL circuit 70 through LPF 83. The phase of a clock signal WCK for writing is adjusted so that a prepit signal can be positioned in the center of a pulse in the synchronisation signal SY. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention belongs to the technical field of information recording devices, and in particular, a write once (WO) type in which information can be written only once in the same location, and a rewritable (RW: Rewritable) in which information can be rewritten many times in the same location. This belongs to the technical field of an information recording apparatus for recording information on an additional recordable recording medium such as an optical disc).

In this type of information recording apparatus, when writing information data to an additionally recordable disc, a write clock signal for writing the information data is generated while synchronizing the information data to be written. In other words, the information data is usually written to the disk while synchronizing (for example, so-called bit synchronization) with the generated writing clock signal having a stable desired frequency. This write clock signal is generally generated from a reference clock generator such as a crystal oscillator that can oscillate and output independently.

However, if additional writing or additional recording is performed on a disc on which information data has already been partially or partially written, new information data is written subsequent to the written information data, the written information There may be a phase difference between the write clock signal used for data and the write clock signal used for new information data.

In this case, in the operation of reading the disc obtained after recording the new data and continuously reproducing the preceding and following information data, the synchronizing clock signal of the read data of the disc is reproduced in the vicinity of the connecting portion of the preceding and following information data. Can often be difficult.

In particular, when a disc on which information data has been written by one information recording device is additionally written by another information recording device, even if these information recording devices are of the same type, they are separated. The write clock signal is generated at the time of each recording from the generation source of the data, and the preceding information data and the subsequent information data are written by the writing clock signals having different frequencies as well as the phase. I can't deny it.

A PLL (Phase Locked Loop) circuit using the read signal as an input is used for reproducing the read data synchronization clock signal. The preceding and succeeding information data is written by the write clock signal having a large difference in phase and frequency. Is greatly disturbed in the synchronization operation of the PLL circuit in the vicinity of the connecting portion between the preceding data and the succeeding data. As a result, the decoder that decodes the read data based on the read data synchronization clock signal may erroneously detect various data in the read data.

In addition to the bit synchronization as described above, the data written to the disk adopts a format in which a specific synchronization signal is arranged for each data block carrying a predetermined amount of information, and is synchronized with respect to the data block at the time of reproduction. However, even if such a specific synchronization signal is used, it is arranged in the data based on the write clock signal. Accordingly, the write clock signal having a large difference in phase and frequency generated as described above causes the interval between the specific synchronization signal disposed last in the preceding information data and the specific synchronization signal first disposed in the subsequent information data to be different. Therefore, the interval before and after that is greatly different, and the specific synchronization signal cannot be detected or erroneously detected during reproduction. In particular, this is a serious problem for a player having a low ability to detect the specific synchronization signal.

The present invention has been made in view of such problems, and smoothly reproduces written data and subsequently added data without disturbing the synchronization operation of the read data during information reproduction. It is an object of the present invention to provide an information recording apparatus capable of adopting a recording form on a recording medium that can be performed.

In order to solve the above-described problem, the information recording apparatus according to claim 1 adds recording information to a recording medium on which prepits are formed at an interval that is an integral multiple of the unit block interval while adding synchronization pulses at the unit block interval. An information recording apparatus capable of recording and additionally recording new recording information continuing to the already recorded recording information, and generating a recording clock signal based on a reference signal obtained from the rotating recording medium A clock signal generating means for generating a pre-pit detecting means for detecting the pre-pit and generating a detection pulse, a synchronizing pulse generating means for generating a synchronizing pulse based on the clock signal, and a phase difference between the detecting pulse and the synchronizing pulse. Phase difference detecting means for detecting, and adjusting the phase of the clock signal so that the detected phase difference becomes a predetermined reference value Characterized in that it comprises a phase adjustment means.

According to the information recording apparatus of the first aspect, the reference signal is obtained by rotating the recording medium and reading the information recorded on the recording medium. In addition, the clock signal generation means generates a recording clock signal based on the reference signal. Therefore, by controlling the rotation of the recording medium so that the reference signal always has a constant characteristic, for example, a recording clock signal having a constant frequency is generated. As a result, the recording information before the addition and the recording information after the addition are recorded by the same recording clock signal, and continuous reproduction is performed before and after the addition. However, there may be a phase difference between the recording clock signal used before the addition and the recording clock signal used at the time of addition. Therefore, the phase difference between the pre-pit detection pulse generated by the pre-pit detection means and the synchronization pulse based on the clock signal generated by the synchronization pulse generation means is detected by the phase difference detection means, and the detected phase difference is a predetermined value. The phase of the clock signal is adjusted by the phase difference adjusting means so that it becomes the reference value. Therefore, the synchronization pulse added at the unit block interval is always provided at a fixed position with respect to the pre-pit, and the synchronization pulse interval in the recording information before the addition and the synchronization pulse in the recording information after the addition are added. The interval and the interval of the synchronization pulse at the connection part before and after the addition are equal, and the reproduction performed while detecting the synchronization pulse is smoothly performed from the recording information before the addition to the recording information after the addition. It will be. In addition, since the synchronization pulse is generated based on the recording clock signal, the phase difference between the synchronization pulse and the detection pulse is kept at a predetermined reference value, so that the phase of the recording clock signal is different from that before recording. It will be aligned in the record after addition. Therefore, both before and after the addition, recording is performed with recording clock signals having the same frequency and the same phase, and good recording information is read without erroneous detection from before the addition to after the addition. Is done.

In order to solve the above problem, the information recording apparatus according to claim 2 is the information recording apparatus according to claim 1, wherein the reference signal and the recording clock signal are synchronized with each other, and Feedback control means for making the phase difference variable is provided, and the phase adjustment means is means for adjusting a control amount for the phase difference of the feedback control means in accordance with the phase difference between the detection pulse and the synchronization pulse. And

According to the information recording apparatus of the second aspect, the recording clock signal is synchronized with the reference signal by the feedback control means. The phase adjustment unit adjusts the control amount for the phase difference of the feedback unit so that the phase difference between the detection pulse and the synchronization pulse becomes a predetermined reference value, so that the recording clock signal is synchronized with the reference signal. In addition, the phase with respect to the reference signal is aligned. Therefore, recording is always performed with a recording clock signal having a constant phase at a constant frequency. As a result, at the time of reproduction, smooth reproduction is performed without misdetection and from the recorded information before the addition to the recorded information after the addition, with continuity maintained.

According to a third aspect of the present invention, there is provided an information recording apparatus according to the first aspect, wherein the phase difference between the reference signal and the detection pulse is a predetermined reference value. An error removing unit that adjusts the phase of the reference signal and removes a reading error of the reference signal is further included. The phase adjusting unit adjusts the phase adjustment amount of the error removing unit between the detection pulse and the synchronization pulse. It is a means for adjusting according to the phase difference.

According to the information recording apparatus of claim 3, the phase of the reference signal is adjusted by the error removing unit so that the phase difference between the reference signal and the detection pulse becomes a predetermined reference value, and the reference signal Reading errors are eliminated. That is, the reference signal is always a signal having a uniform phase with reference to the pre-pit. The phase adjusting unit adjusts the phase adjustment amount of the error removing unit so that the phase difference between the detection pulse and the synchronization pulse becomes a predetermined reference value. Therefore, the reference signal is not related to before and after the additional recording. The signal is always in phase with respect to the pre-pits, and the recording clock signal generated based on such a reference signal is always a recording signal in phase with a constant frequency. As a result, at the time of reproduction, smooth reproduction is performed without misdetection and from the recorded information before the addition to the recorded information after the addition, with continuity maintained.

According to the information recording apparatus of the present invention, the recording that can smoothly and continuously reproduce the written data and the data added after that without disturbing the synchronization operation of the read data during information reproduction. A recording form on a medium can be taken.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, a general physical format for writing information to a DVD-R (Digital Video Disk-Recordable) as one of additional recording media that can be recorded will be described with reference to FIGS.

Error correction processing performed on the DVD-R is performed using an ECC (Error Correction Code) block as its error unit. Such an ECC block is formed based on the data sector shown in FIG.

The original information recorded on the DVD-R has a physical structure including a plurality of data sectors 20 as shown in FIG. One data sector 20 has, from its head, ID information 21 indicating the start position of the data sector 20, an ID information error detection code (IED) 22 for correcting an error in the ID information 21, and Preliminary data 23, data 24 carrying main information to be recorded on the disc such as video, audio or computer data, and an error detection code (EDC) 25 for detecting an error in the data 24 Are constituted by block data arranged in order. In the DVD-R, original information to be recorded is constituted by a plurality of continuous data sectors 20.

Such a data sector 20 is used to construct an ECC block as shown in FIG.

First, as shown in FIG. 2A, one data sector 20 is divided every 172 bytes, and the divided data (hereinafter referred to as data block 33) are arranged in the vertical direction. Then, 12 rows of data blocks 33 are arranged in the vertical direction.

Next, as shown in FIG. 2B, an ECC code (PI (Pality In) code) 31 of 10 bytes is assigned to each data block 33. The ECC code 31 is added to the end of the data block 33 to constitute one correction block 34. At this stage, 12 rows of correction blocks 34 including the ECC code 31 are arranged in the vertical direction. Such an addition process of the intra-ECC code 31 is repeated for 16 data sectors 20. As a result, a correction block 34 of 192 rows is obtained.

In FIG. 2B, the block data formed by arranging the correction blocks 34 of 192 rows in the vertical direction as described above is divided into one byte each in the vertical direction. 16 ECC outer codes (PO: (Pality Out) codes) 32 are added. The ECC outer code 32 is also added to the portion of the ECC code 31 in the correction block 34.

Thus, one ECC block 30 including 16 data sectors 20 is formed. As can be seen from the above description, the total amount of information carried by one ECC block 30 is
(172 + 10) bytes × (192 + 16) rows = 37856 bytes, of which the information data 24 is
It becomes 2048 bytes × 16 = 32768 bytes.

In FIG. 2B, the number “# D. *” is assigned to each 1-byte data constituting the ECC block 30. For example, “D1.0” indicates 1-byte data arranged in the first row and 0th column, and “D190.170” indicates 1-byte data arranged in the 190th row and 170th column. Show. Therefore, the ECC inner code 31 is arranged in the 172nd to 181st columns, and the ECC outer code 32 is arranged in the 192nd to 207th rows.

Further, since one correction block 34 is continuously recorded on the DVD-R, an error of the entire block may occur. However, as shown in FIG. 2B, the ECC blocks 30 are configured to include both the intra-ECC code 31 and the outer ECC code 32, and are thus arranged in the horizontal direction in FIG. Data correction can be performed with the ECC inner code 31, and correction of data arranged in the vertical direction in FIG. 2B can be performed with the ECC outer code 32. Accordingly, double error correction in the horizontal and vertical directions can be performed in the ECC block 30 shown in FIG. 2B, and error correction processing used in a conventional CD (Compact Disk) or the like is possible. Compared with, error correction can be performed more powerfully.

More specifically, for example, one correction block 34 (including a total of 182 bytes of data including the ECC code 31 for one row, as described above, is continuously recorded on the DVD-R. )), Even if all of them are destroyed due to a DVD-R injury or the like, when viewed from the vertical direction, only one byte of data is destroyed for one ECC outer code 32. Therefore, if error correction is performed using the ECC outer code 32 corresponding to each column, even if all of one correction block 34 is destroyed, error correction can be performed and reproduction can be performed accurately.

A specific recording form of the ECC block 30 on the DVD-R is shown in FIG. In FIG. 3, the 1-byte data numbered with “D #. *” Is the same as that numbered in FIG.

First, as shown in the uppermost stage of FIG. 3, the ECC blocks 30 are arranged in a line in the horizontal direction for each correction block 34 and interleaved. Thereby, as shown in 2 cross sections of FIG. 3, it is converted into 16 recording sectors 40. In such conversion, one recording sector 40 includes 2366 bytes (37856 bytes ÷ 16) of information, and in this, the data sector 20, the ECC inner code 31 or the ECC outer code 32 are mixed. . However, ID information 21 (see FIG. 1) in the data sector 20 is arranged at the head of each recording sector 40.

As shown in the third row of FIG. 3, this one recording sector 40 is divided into data 41 for every 91 bytes, and a header H is added to each. Thereafter, the recording sector 40 with the header added is subjected to 8-16 modulation, and converted into a sync frame 42 for each data 41 and its header, as shown at the bottom of FIG. After the conversion, one sync frame 42 is composed of a header H ′ and data 43. The information amount of one sync frame 42 is
91 bytes × 8 × (16/8) = 1456 channel bits (1488 channel bits if sync information is included)
Thus, the sync frames 42 are written on the DVD-R in a continuous form. At this time, one recording sector 40 includes 26 sync frames 42.

By recording information on a DVD-R in accordance with the physical format described above, if the information is reproduced and 8-16 demodulation and deinterleaving are performed (see FIG. 3), the original ECC block 30 is restored. It is possible to accurately reproduce information by performing the powerful error correction as described above.

Thus, information is recorded on the DVD-R in the form of a sync frame sequence as shown at the bottom of FIG. 3, but the recording is performed on a predetermined track in the DVD-R.

FIG. 4 shows the structure of a recording layer of a DVD-R including a track that bears the recording location of such information.

In FIG. 4, a DVD-R 1 has a dye film 5 formed thereon and a groove track 2 on which the information of the sync frame series can be written, and reading light or writing (recording) on the groove track 2 adjacent to the groove track 2. A land track 3 for guiding a laser beam B as light is formed. The groove track 2 has a concave shape when viewed from the generation source side of the laser beam B, and the land track 3 has a convex shape when viewed from the guide generation side, and a gold vapor deposition surface as a light reflecting surface for reflecting the beam B 6 is formed.

The groove track 2 is so-called wobbling that undulates at a predetermined frequency (for example, a frequency corresponding to an appropriate rotational speed of the disk) in a direction parallel to the flat surface of the disk. By using such wobbling, it is possible to control the rotation of the disk when reading information.

The land track 3 is formed with pre-pits 4 for carrying recording control information corresponding to address information indicating the recording position of the DVD-R 1 and timing control information for controlling recording timing.

The wobbling and pre-pit 4 as well as the groove track 2 and the land track 3 are formed in advance when the DVD-R 1 is manufactured. In other words, the wobbling and the pre-pit 4 carry pre-formed record information that has already been formed (recorded) before writing the first information.

When recording information on a DVD-R1 having such a structure, the light beam B is irradiated onto the DVD-R1 so that the center of the light beam B coincides with the center of the groove track 2, and the groove track 2 corresponds to the sync frame sequence. A pit is formed. At this time, the size of the spot SP of the light beam B is set so that a part of the spot is also irradiated onto the land track 3, as shown in FIG. Further, the pre-pit 4 is detected by the push-pull method using a part of the reflected light of the light spot SP irradiated on the land track 3, and the pre-recorded information unique to the disc indicated by the pre-pit is acquired. Further, the wobble signal corresponding to the wobbling of the groove track 2 is detected using the reflected light of the light spot SP irradiated on the groove track 2, and the rotation control of the DVD-R 1 is performed based on the wobble signal.

The groove track 2 and the sync frame sequence data written thereon and the pre-pits (hereinafter referred to as LPP (Land Pre Pit)) 4 formed on the land track 3 have a correspondence as shown in FIG.

As shown in FIG. 5, the groove track 2 records thin frame series data as recording information along the center line. In such recording, control is performed so that one sync frame is recorded for every eight wobbling periods exhibited by the groove track 2. The wobbling frequency is constant at 140 kHz (appropriate reading rate converted value) over all sync frames.

As described with reference to FIG. 3, the header H 'is arranged at the head of the sync frame, and the synchronization signal SY is assigned to the head of the header. The synchronization signal SY is provided to synchronize the sync frame and has the same waveform symbol having a length of 14T. Here, T corresponds to the pit interval in the data series before 8-16 modulation as shown in the third row of FIG. The sync frame has a length of 1488T.

On the other hand, the LPP 4 is formed at a position corresponding to the upward arrow in FIG. In other words, in FIG. 5, the land track 2 is formed at a position corresponding to one of the peak and trough of the wave presented by the wobbling of the groove track 2 and adjacent to the three positions in the sync frame. I try to do it. However, in one recording sector (see FIG. 3), LPP4 is formed only in even-numbered sync frames (EVEN frames) or only in odd-numbered sync frames (ODD frames). FIG. 5 shows a case where the LPP 4 is formed only in the EVEN frame, and the LPP 4 is not formed at the position corresponding to the upward dotted arrow. The LPP 4 arranged closest to the head of the sync frame is provided for synchronization, and is always arranged corresponding to a predetermined even or odd numbered frame. The synchronization LPP 4 bears address information on the recording surface of the DVD-R, and the address information is identified for each recording sector.

In the present embodiment, the write clock phase adjusting circuit described later is configured so that the recording position of the synchronization signal SY in the sync frame data written to the groove track 2 is always constant with respect to the LPP4 formation position. Has been.

The information recording apparatus according to the present embodiment can handle a DVD-R in which pre-recorded information is formed in the above-described form and sync frame sequence data is written, and the details thereof will be described below.

FIG. 6 is a diagram showing a schematic configuration of such an information recording apparatus.

In FIG. 6, a DVD-R1 (hereinafter simply referred to as a disk) is rotated by a spindle motor 50 while being picked up by a pickup 60 as an optical head capable of outputting laser light at both a reading light level and a writing light level. Laser light is irradiated. The laser light incident on the disk reaches the reflection surface (see FIG. 4) of the disk and is guided to the pickup 60 as reflected light in a state corresponding to the recording information.

The pickup 60 has a built-in photoelectric conversion circuit including a light receiving element, receives light reflected from the disk, and performs photoelectric conversion according to the light reception level and state. The photoelectric conversion output is supplied to the regenerative amplifier 61 as a read signal.

The regenerative amplifier 61 amplifies the supplied read signal, and supplies the amplified read signal to a wobble detection circuit 63 and an LPP (prepit) detection circuit 64 via a band pass filter (BPF) 62.

The wobble detection circuit 63 detects or extracts a wobble signal as a reference signal corresponding to the wobbling from the read signal, and extracts this from the crosstalk removal circuit 6.
5 to one input.

An LPP detection circuit 64 serving as a prepit detection unit detects the prepit 4 from the read signal and generates a prepit signal corresponding to the detection result. The prepit signal is supplied to the other input of the crosstalk removing circuit 65 and also supplied to the prepit (LPP) decoder 66.

The crosstalk removing circuit 64 as an error removing unit has a function of removing a jitter component caused by crosstalk included in the wobble signal based on the pre-pit signal, and the wobble signal after the removal is converted into a PLL for generating a wobble synchronization clock. Supply to circuit 70. The obtained wobble signal has an accuracy depending on the detection accuracy of the pre-pit signal based on the residual error that cannot be removed by the time axis servo such as the spindle servo on the time axis. In other words, the obtained wobble signal includes a prepit signal error (about ± 5T) due to a residual error.

The PLL circuit 70 has a wobble signal from which crosstalk has been removed as one input, compares the phase of the wobble signal with another input signal, and outputs an error signal corresponding to the phase difference between them, and a low error signal. A low-pass filter (LPF) 72 that passes the frequency component and a varicap are included, and the DC component of the phase difference is converted into a varicap based on a phase adjustment signal from a write clock phase adjustment circuit 80 described later. The phase shift circuit (PS) 75 as phase adjusting means for changing the capacitance of the varicap and shifting the phase to the lag side or the advance side by applying, and the low voltage supplied via the phase shift circuit 75 The VCO 73 that changes the oscillation frequency according to the output of the band-pass filter 72 and the oscillation output clock signal of the VCO 73 are frequency-divided to receive a signal having the same frequency as the wobble signal. It generates constituted by a frequency divider 74 supplied to the other input of the phase comparator circuit 71. The output clock signal of the VCO 73 is used as the write clock signal WCK. Therefore, the write clock signal WCK is phase-synchronized with the wobble signal by the PLL circuit 70 and is supplied to an encoder 91 and a sync adding circuit 84 to be described later. The PLL circuit 70 corresponds to clock signal generation means.

The amplified read signal from the reproduction amplifier 61 is also supplied to the main data decoder 67, the pit clock reproduction circuit 68, and the sync detection circuit 69.

The main data decoder 67 performs processing for restoring the data 24 while performing error correction processing from the ECC block, including 8-16 demodulation and deinterleaving data processing for the read signal (see FIGS. 1 to 3). ) The restored data is transferred to the CPU 9. The CPU 9 sends the transferred restoration data to a reproduction data processing system (not shown) for actual sound output, video output or data output. On the other hand, the LPP decoder 66 detects address information and sync frame synchronization information indicating the recording position on the recording surface of the disc from the detected pre-pit signal, and sends them to the CPU 9. The CPU 9 performs various processes using the address and sync frame synchronization information based on the pre-pit signal.

The clock recovery circuit 68 recovers a bit synchronization clock (having a period T) of data carried by the read signal, and is performed by detecting a synchronization signal SY (see FIG. 5) included in the read signal. The output of the clock recovery circuit 68 is supplied to the CPU 9 as a recovery clock RCK.

The sync detection circuit 69 detects the synchronization signal SY included in the read signal, and generates, for example, a pulsed sync detection signal SY 'in response to the detection. The sync detection signal SY ′ is supplied to the CPU 9.

The ECC addition circuit 84 forms the ECC block 30 by adding the above-described ECC code 31 and ECC outer code 32 to the original signal of the data to be written, and performs processing for interleaving the ECC block 30. An original signal of data to be written is temporarily stored in a built-in memory 9m of the CPU 9 from a write data supply system (not shown), sequentially read at a predetermined timing determined by the CPU 9, and transferred to the ECC adding circuit 84.

The sync adding circuit 85 as a sync pulse generating means counts in synchronization with the write clock signal, and starts operation with the detected sync frame signal SD output from the CPU 9 based on the output from the LPP decoder 66 as a trigger. This counter is a circuit that generates a synchronization signal SY for writing having a length corresponding to 14T for every predetermined period and outputs it to the encoder 91. The sync adding circuit 85 is provided with a buffer. The interleaved data output from the ECC adding circuit 84 is temporarily stored in the buffer, and is synchronized with the write clock signal WCK. Forwarded to Since the data in the buffer is transferred after the output of the synchronization signal SY for writing, the data supplied to the encoder 91 is a synchronization signal as a header H as shown in the third stage of FIG. The data is 91-byte data with SY added. Further, the sync adding circuit 85 is provided with an output path of a synchronization signal SY to a triangular wave generating circuit 81 of the phase adjusting circuit 80 described later, and from this output path, after the trigger of the detected sync frame signal SD is input. The synchronization signal SY is output regardless of whether or not the writing operation is being performed. When the write start pulse signal SP indicating the start of the write operation is output from the CPU 9, the write synchronization signal SY and the data for every 91 bytes are encoded by using the write start pulse signal SP as a trigger. To 91.

The encoder 91 performs final stage encoding of data to be written to the disk output from the sync adding circuit 85. Here, code conversion for 8-16 modulation as referred to in FIG. 3 is performed. The data finally encoded by the encoder 91 is sent to the power control circuit 92.

In the writing mode, the power control circuit 92 generates a control signal for designating the laser power according to the encoded data sent from the encoder 91, and the laser driving circuit 93 performs an actual operation according to the control signal. A drive signal of a level corresponding to the pickup light source laser is emitted. As a result, the intensity of the recording (writing) laser light irradiated on the disk by the pickup 60 is changed in accordance with the encoded data. On the other hand, in the reading mode, the power control circuit 92 does not respond to the encoded data sent from the encoder 91 and generates a control signal for designating a low level and substantially constant laser power for reading, The laser drive circuit 93 emits a drive signal at a level corresponding to the actual pickup light source laser corresponding to the control signal. As a result, the disc is read by a constant low-level reading laser beam irradiated by the pickup 60.

As described above, the output wobble signal of the wobble detection circuit 63 is also used for controlling the rotation of the disk. Specifically, a wobble signal can be supplied to the other input of the phase comparator 51 that receives a reference clock signal supplied from a local oscillator (not shown) as one input. The phase comparator 51 obtains the frequency error and phase error of the two inputs, and supplies a spindle control signal corresponding to the frequency error to the driver circuit 52. The driver circuit 52 outputs the drive signal of the motor 50 corresponding to the spindle control signal. Occur. As a result, the rotation of the motor 50 is controlled so that the frequency of the wobble signal detected from the read signal matches the frequency of the reference clock signal.

The phase adjustment circuit 80 serving as a phase difference detection means includes a triangular wave generation circuit 81 that generates a triangular wave from the falling edge of the write synchronization signal SY output from the sync adding circuit 85, and the output timing of the LPP signal. A sample-hold (S / H) circuit 82 that samples and holds the signal and a low-pass that outputs the DC component to the varicap of the phase shift circuit 75 of the PLL circuit described above after making the output of the sample-and-hold circuit 82 a DC component. A filter (LPF) 83 is used. If the phase of the synchronization signal SY for writing generated in synchronization with the clock signal WCK for writing is out of phase with the LPP signal and the center of the synchronization signal SY does not coincide with the output timing of the LPP signal, this phase difference is added. The corresponding voltage is supplied to the varicap of the phase shift circuit 75 of the PLL circuit 70, and the phase of the write clock signal WCK is adjusted so that the center of the synchronization signal SY coincides with the output timing of the LPP signal.

Next, the operation of this information recording apparatus will be described.

FIG. 7 shows a series of written data (hereinafter referred to as old data) already written on the disc of the information recording apparatus shown in FIG. It is a time chart which shows each part operation waveform and operation form in the additional recording mode which writes after adding and writing.

In this embodiment, as shown in FIG. 7A, at the end of writing of old data, in the first recording sector 40T of the ECC block 30T to be placed next to the last ECC block 30E of the old data. Dummy data (hereinafter referred to as old dummy data) 44 corresponding to all data portions of the first sync frame 42F and the second sync frame 42S is recorded following the old data together with the synchronization information SY and the corresponding ID information 21. .

When an additional recording start command is issued from command means (not shown) to the old data-written disc in such a form, the CPU 9 performs additional recording processing as shown in FIGS. Execute.

That is, in response to the additional recording start command, the CPU 9 first starts the reading mode (step S1). In this process, the CPU 9 does not respond to the urinary force data from the encoder 91, and the read light is a relatively low constant reading light that does not cause the writing operation of the recording surface of the pickup 60. The power control circuit 92 is controlled to reach the level.

Next, in order to search the head side ID information 21 of the recording sector 40E in which the last old data is recorded among the old data, the CPU 9 searches for the N address which is the address corresponding to the ID information 21 (step). S2). This process is executed based on the output signal of the decoder 67.

Here, of the old data, it is assumed that the address indicated by the ID information 21 arranged on the head side of the data of the last recording sector 40E in the last ECC block 30E is the N address, and subsequently the old dummy data 44 It is assumed that the address indicated by the ID information 21 arranged at the head of the recording sector 40T in which is recorded is (N + 1) address.

When the ID information 21 corresponding to the N address is detected (see time t1 in FIG. 7), the data recorded in the recording sector 40E following the ID information 21 corresponding to the N address and the subsequent recording sector 40T are recorded. Start reading data (step S)
3).

Then, the CPU 9 determines whether or not the ID information 21 corresponding to the address (N + 1) has been detected based on the demodulated output of the read data, that is, the output signal of the decoder 67 (step S4). In step S4, when the ID information 21 corresponding to the address (N + 1) is not detected, the data reading is continued until it is detected.

When the ID information 21 corresponding to the address (N + 1) is detected in step S4 (see time t2 in FIG. 7), the CPU 9 now sets the search target to the recording sector 40T corresponding to the ID information 21 at the address (N + 1). A search is performed based on the read data obtained by further proceeding as the second sync frame 42S at (step S5). More specifically, the CPU 9 receives the detection signal SY ′ of the synchronization signal at the head of the second sync frame 42S after the detection of the ID information 21 at the address (N + 1) from the sync detection circuit 69, and the second sync frame with the reception timing. The arrival of 42S is detected.

When the second sync frame 42S is thus detected (see time t3 in FIG. 7), the CPU 9 starts counting the reproduction clock RCK from the clock reproduction circuit 68 (step S6).

Then, it is determined whether or not the count value has reached 1488T corresponding to one sync frame (step S7), and when it reaches 1488T, a write start pulse SP is output to the sync adding circuit 85. At the same time (see time t4 in FIG. 7), the control mode is switched to the writing mode (step S8). In this process, the CPU 9 applies the pickup 60 to the disk 1 between a writing light level that can cause a writing action on the disk recording surface and a reading light level that does not, in accordance with input data from the encoder 91. The power control circuit 92 is controlled to a recording mode in which the intensity of irradiation light is changed.

As a result, of the output data of the encoder 91, data after the third sync frame as indicated by the solid line in the (E) stage of FIG. 7 is taken into the power control circuit 92 and recorded on the disk 1. The output data of the encoder 91 indicated by the dotted line in FIG. 7E is transferred to the power control circuit 92 but is not reflected in the output of the power control circuit 92 because the reading mode is set. Show. The reason why the irradiation light of the pickup 60 is continuously set to the reproduction power even when data is not written is that the reflected light for tracking servo control is required to track the information recording track (groove track) on the disk. is there.

When the write start pulse SP is output to the sync adding circuit 85, the sync adding circuit 85 sends the write synchronization signal SY and data for every 91 bytes to the encoder 91 in synchronization with the write clock signal WCK. In the encoder 91, the 8-16 modulation and the data after the modulation are transferred to the power control circuit 92 in synchronization with the write clock signal WCK. The write clock signal WCK is a signal synchronized by the PLL circuit 70 with respect to the wobble signal from which the crosstalk has been removed by the crosstalk removal circuit 65, and further, by the phase adjustment circuit 80. The phase is such that the center of the synchronization signal SY (position T / 2 when the pulse width is T) coincides with the center of the LPP signal (position T ′ / 2 when the pulse width is T ′). Since it is an adjusted signal, the synchronization signal SY of the new data is accurately recorded at the additional recording position (position indicated by the timing at time t4 shown in FIG. 7).

Here, the operation of the circuit for adjusting the phase of the write clock signal WCK in this way will be described in detail based on the block diagram of FIG. 6 and the timing chart of FIG.

First, a wobble signal which is a reference signal for the write clock signal WCK is detected by a wobble detection circuit 63 as shown in FIG. However, the wobble signal detected by the wobble detection circuit 63 is a signal having jitter due to crosstalk, as shown in FIG. Therefore, in the present embodiment, such crosstalk is removed by the crosstalk removal circuit 65. As shown in FIG. 11, the crosstalk removing circuit 65 includes a frequency divider 100 that divides a wobble signal having jitter, and a phase comparison unit 101 that compares phases of the divided wobble signal and the LPP signal. The equalizer 102 that smoothes the output signal of the phase comparator 101 and the phase shifter 103 that shifts the phase of the wobble signal divided in accordance with the output of the equalizer 102. When a wobble signal having jitter as shown in FIG. 9A is frequency-divided by the frequency divider 100, the wobble signal is shaped into a pulse waveform and input to the phase comparator 101. In the phase comparison unit 101, the phases of the pulsed wobble signal and the LPP signal are compared, and when these phase relationships maintain the phase relationship between the groove track 2 and LPP4 shown in FIG. 5, that is, the pulsed wobble signal When the LPP signal is located at the center position of the High period, the output voltage value is not changed, and when the wobble signal is not at such an appropriate position with respect to the LPP signal, the pulse-shaped wobble signal The output voltage value is changed so that the phase is a leading phase or a lagging phase with respect to the LPP signal. This change in output voltage value is smoothed by the equalizer 102 and supplied to the phase shifter 103. The phase shifter 103 changes the phase of the pulse-like wobble signal in accordance with the output voltage of the equalizer 102. As a result, the pulse-like wobble signal has a high period of the wobble signal as shown in FIG. 9C. Are aligned to such a phase that the LPP signal is located at the center position of the signal and output from the crosstalk removing circuit 65.

The PLL circuit 70 receives a wobble signal in which jitter due to crosstalk is removed in this way and whose phase is aligned with the LPP signal. In the PLL circuit 70, such a wobble signal and a signal obtained by dividing the output from the write clock generation circuit (VCO) 73 by N by the frequency divider 74 are phase-shifted by the phase comparison circuit (PC) 71. Compare. FIG. 9E shows an example of the output signal of the frequency divider 74, and FIG. 9F shows an example of the output signal of the phase comparison circuit 71. The output of the phase comparison circuit 71 is extracted as a DC component by the LPG 72 as shown in FIG. 9G, and this DC component is supplied to the write clock generation circuit 73 via the phase shift circuit 75. The phase difference between the wobble signal and the N-divided write clock signal is adjusted to a predetermined reference value. The write clock signal WCK output from the write clock signal generation circuit 73 by such a PLL circuit 70 corresponds to the wobble signal from which jitter due to crosstalk has been removed as shown in FIG. The signal is synchronized and supplied to the sync adding circuit 85 or the encoder 91. Therefore, regardless of whether old data is written or new data is written, writing can always be performed with a write clock signal WCK having a constant frequency.

In the present embodiment, a phase shift circuit 75 is provided in the PLL circuit 70 in order to make the interval between the write synchronization signal SY synchronized with the write clock signal WCK and the LPP signal substantially constant. The phase shift circuit 75 is controlled by the adjustment circuit 80.

In the phase adjustment circuit 80, the write synchronization signal SY output from the sync adding circuit 85 is supplied to the triangular wave generation circuit 81 as shown in FIG. In the triangular wave generation circuit 81, a triangular wave as shown in FIG. 9H is output in synchronization with the falling edge of the synchronization signal SY. The three image waves are supplied to the sample-and-hold circuit 82 and sampled in a period corresponding to the pulse width of the LPP signal output from the LPP detection circuit 64 as shown in FIG. Is held. Then, the held voltage is converted into a DC component by the LPF 83 as shown in FIG. 9 (J), and is applied to the varicap of the phase shift circuit 75 provided before the write clock signal generation circuit 73 of the PLL circuit 70. Supplied.

The synchronization signal SY is a signal that is output at predetermined intervals by the counter in the sync adding circuit 85, using the detected sync frame signal SD output from the CPU 9 as a trigger. The detected sync frame signal SD serving as a trigger is obtained by outputting sync frame synchronization information based on the LPP signal detected by the LPP decoder 66 from the CPU 9 as a pulse signal. That is, when the CPU 9 receives the sync frame synchronization information from the LPP decoder 66, the CPU 9 counts the write clock signal WCK using this as a trigger, and outputs the detected sync frame signal SD at a fixed period T1, and the sync adding circuit 85 Using the detected sync frame signal SD as a trigger, the write clock signal WCK is counted, and the synchronization signal SY is output at every fixed period T2. Therefore, there is a relationship as shown in FIG. 10 among the LPP 4, the detection sync signal SD, and the synchronization signal SY. In particular, the count value in the sync adding circuit 85 is set so that the LPP signal is located at the center of the pulse of the synchronization signal SY. Therefore, when there is no phase shift of the write clock signal, the LPP signal is positioned at the center of the synchronization signal SY, and the output of the sample hold circuit 82 takes an intermediate value with respect to the peak-to-peak voltage of the triangular wave. It will be. Therefore, in the present embodiment, when the intermediate value is used as a reference value and the output voltage of the LPF 83 corresponding to the reference value is supplied to the varicap in the phase shift circuit 75 of the PLL circuit 70, the write clock signal The phase of does not change. However, when the phase of the clock signal for writing advances for some reason, the output of the sample hold circuit 82 becomes smaller than the reference value, and a large voltage smaller than the reference voltage is applied to the varicap. As a result, the capacitance of the varicap increases, and the phase of the write clock signal WCK is delayed. Conversely, when the phase of the write clock signal is delayed, the output of the sample hold circuit 82 becomes larger than the reference value, and a voltage higher than the reference voltage is supplied to the varicap. The capacitance of the varicap increases, and the phase of the write clock signal WCK is advanced. In this way, since the synchronization signal SY is output from the sync adding circuit 85 so as to be always at a fixed position with respect to the LPP signal and written to the recording medium, the time shown in FIG. It is written accurately at the position indicated by t4. In addition, since the synchronization signal SY is written in the same manner not only for the new data but also for the old data, the synchronization signal interval between the sync frames is the same as the old data area, the new data area, the old data area, and the new data area. Even in a player having a low synchronization signal detection capability at a connection portion of the data area, reproduction can be performed satisfactorily without causing detection failure or erroneous detection.

Also, making the position of the synchronization signal SY constant with respect to the LPP signal corresponds to making the phase of the write clock signal relative to the LPP signal always constant, so that either the old data area or the new data area Also in this area, the write clock signal is a signal having the same phase and the same frequency by the PLL circuit 70 described above, and is used for reproducing the reproduction clock signal which is a clock signal for synchronizing read data. The PLL circuit to be operated does not malfunction.

In addition, the reproduction clock signal is reproduced based on the synchronization signal SY. However, since the interval between the synchronization signals SY in adjacent sync frames is always constant as described above, the reproduction clock signal as described above is used. It is possible to accurately calculate the additional recording position.

As described above, based on the writing clock signal always having the same phase and frequency, and after the writing of new data is started using the synchronization signal SY at a fixed position with respect to the LPP signal, The CPU 9 determines whether or not the original new data to be transferred to the encoder 91 has been completed (step S9). If not completed, the recording of new data is continued, and if completed, as the final process at the end of recording, the beginning of the ECC block 30 to be placed next to the last ECC block 30 of the data. Dummy data 44 corresponding to all data portions of the first sync frame and the second sync frame in the recording sector 40 is stored subsequently to the data together with the synchronization information SY and the corresponding ID information 21 (step S10). This mode is the same as the above-described processing at the end of recording the old data.

When writing related to all new data including additional recording at the end of recording is completed in step S13, the CPU 9 keeps the intensity of the irradiation light to the disk 1 of the pickup 60 constant without responding to the input data from the encoder 91. The power control circuit 92 is controlled so as to achieve the reading light level, and the reading mode is switched (step S11). Thus, the new data additional recording process is completed.

As described above, according to the present embodiment, written data and new data can be smoothly and continuously recorded, and writing can be performed without hindering reproduction of a read clock signal and detection of a synchronization signal. Data and new data can be reproduced smoothly and continuously.

In the above-described embodiment, the example in which the phase shift circuit 75 is provided in the PLL circuit 70 has been described. However, the present invention is not limited to this, and instead of providing the phase shift circuit 75, as shown in FIG. In addition, the output of the equalizer 102 of the crosstalk removing circuit 65 and the output of the LPF circuit 83 of the phase adjusting circuit 80 may be added by the adder 104 and supplied to the phase shifter 103. With this configuration, the phase of the wobble signal serving as the reference for the write clock signal can be adjusted based on the phase difference of the synchronization signal SY with respect to the LPP signal, so that the same effect as the above-described example can be achieved. In addition, the circuit configuration can be simplified.

The position of the synchronization signal SY relative to the LPP signal is ideally controlled so that the LPP signal comes to the center of the synchronization signal SY in consideration of the eccentric component of the disk, but the falling edge of the synchronization signal SY Even if control is performed so that the LPP signal comes to (the front edge of the synchronization signal pulse), substantially the same effect can be obtained.

In the above-described embodiment, it has been described that new data is stored in each sync frame of the first recording sector 40T to be additionally recorded. However, as disclosed in Japanese Patent Laid-Open No. 9-270171, a new data is stored. Dummy data may be stored instead of data.

In the above-described embodiment, the DVD-R is mainly described as the recording medium. However, the present invention can be applied to other additionally recordable recording media.

In the above-described embodiment, the sync frame synchronization signal SY is taken as an example of the sync pulse added at the unit block interval. However, other syncs are arranged for each predetermined data block having an information amount different from the sync frame. It is also possible to implement the present invention using a signal as a synchronization pulse.

It is a figure which shows the structure of the data sector which bears the original recording information of DVD-R. It is a figure which shows the structure of the ECC block constructed | assembled using the data sector of FIG. It is a figure which shows the physical format of the data recorded on DVD-R. It is a perspective view which shows the structure of the recording layer of DVD-R. FIG. 4 is a schematic diagram showing a correspondence relationship between a groove track in a DVD-R, sync frame series data written on the groove track, and prepits formed on a land track. 1 is a block diagram showing a schematic configuration of an information recording apparatus in an embodiment of the present invention. It is a time chart which shows the operation | movement waveform and operation | movement form of each part of the information recording device of FIG. It is a flowchart which shows the procedure of the additional recording process performed by CPU in the information recording device of FIG. 7 is a time chart showing operations of a PLL circuit and a phase adjustment circuit in the information recording apparatus of FIG. 6. It is a time chart which shows the relationship between the prepit of the recording medium used for the information recording device of FIG. 6, and the detection sync frame synchronizing signal and synchronizing signal produced | generated within an information recording device. It is a block diagram which shows other embodiment of the phase adjustment part in the information recording device of this invention.

Explanation of symbols

1 ... DVD-R
DESCRIPTION OF SYMBOLS 50 ... Spindle motor 51 ... Phase comparator 52 ... Motor driver 60 ... Pickup 61 ... Reproduction amplifier 62 ... Band pass filter 63 ... Wobble detection circuit 64 ... Prepit detection circuit 65 ... Crosstalk detection circuit 66 ... Prepit decoder 67 ... Main data Decoder 68 ... Clock recovery circuit 69 ... Sync detection circuit 70 ... Clock generation PLL circuit 71 for wobble synchronization original writing ... Phase comparison circuit 72 ... Low-pass filter 73 ... Voltage-controlled oscillator 74 ... Frequency divider 80 ... For writing Clock phase adjustment circuit 81 ... Triangular wave generation circuit 82 ... Sample and hold circuit 83 ... Low-pass filter 84 ... ECC addition circuit 85 ... Sink addition circuit 9 ... CPU
91 ... Encoder 92 ... Power control circuit 93 ... Laser drive circuit

Claims (3)

Recording information is recorded on a recording medium in which pre-pits are formed at an interval that is an integral multiple of the unit block interval while adding synchronization pulses at the unit block interval, and new recording information that continues to the already recorded recording information Is an information recording device capable of additionally recording,
Clock signal generating means for generating a recording clock signal based on a reference signal obtained from the rotating recording medium;
Prepit detection means for detecting the prepit and generating a detection pulse;
Synchronization pulse generating means for generating a synchronization pulse based on the clock signal;
Phase difference detection means for detecting a phase difference between the detection pulse and the synchronization pulse;
Phase adjusting means for adjusting the phase of the clock signal so that the detected phase difference becomes a predetermined reference value;
An information recording apparatus comprising: A feedback control means for synchronizing the reference signal and the recording clock signal and making the phase difference between the signals variable;
The phase adjusting means is means for adjusting a control amount for the phase difference of the feedback control means in accordance with the phase difference between the detection pulse and the synchronization pulse.
The information recording apparatus according to claim 1. The phase adjustment unit further includes an error removal unit that adjusts a phase of the reference signal so that a phase difference between the reference signal and the detection pulse becomes a predetermined reference value, and removes a reading error of the reference signal. , Means for adjusting the phase adjustment amount of the error removal means according to the phase difference between the detection pulse and the synchronization pulse,
The information recording apparatus according to claim 1.

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