JP2005159028A - Anneal wafer and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an anneal wafer excellent in the breakdown voltage characteristics of a device producing region or the surface layer of the wafer and having oxygen deposit uniformly existing in the surface with a high density, in a stage before applying device process on a wafer bulk unit while being provided with excellent IG capability; and to provide the manufacturing method of the anneal wafer. <P>SOLUTION: The anneal wafer is obtained by applying heat treatment on a silicon wafer produced from a silicon single crystal raised by Czochralski method and the whole surface of the wafer is an N region wherein there is no grown-in defect or OSF (offset field), while the conforming rate of oxide film breakdown voltage characteristics in a region from the surface of the wafer to the depth of at least 5 μm is not less than 95%. The density of oxygen deposit in the wafer is not less than 1×10<SP>9</SP>/cm<SP>3</SP>and the value of ratio of the maximum value to the minimum value (maximum value/minimum value) of the density of oxygen deposit in the surface of wafer is 1-10. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an annealed wafer having a wafer surface layer portion having excellent oxide film breakdown voltage characteristics and a wafer bulk portion having excellent gettering capability, and a method for manufacturing the annealed wafer.

  In recent years, with the progress of miniaturization of elements due to high integration of semiconductor circuits, quality requirements for silicon wafers manufactured using the Czochralski method (hereinafter abbreviated as CZ method) as a substrate have increased. ing. In particular, there are defects due to single crystal growth that deteriorate the oxide breakdown voltage characteristics and device characteristics called Grown-in defects such as FPD, LSTD, and COP, and reduction of the density and size is regarded as important. ing.

  In describing these defects, first, atomic vacancy point defects called vacancy (hereinafter sometimes abbreviated as V) incorporated into a silicon single crystal, interstitial-silicon (interstitial-Si, In the following, there will be explained what is generally known about a factor that determines the concentration of each interstitial silicon type point defect, which may be abbreviated as I).

  In a silicon single crystal, the V region is a vacancy, that is, a region in which there are many such as recesses and holes generated due to a shortage of silicon atoms, and the I region is a dislocation generated by the presence of extra silicon atoms. Or a region having a large amount of excess silicon atoms, and a neutral (Neutral, hereinafter abbreviated as N) region between the V region and the I region without any shortage or excess of atoms. Will exist. And the above-mentioned grow-in defects (FPD, LSTD, COP, etc.) occur only when V or I is in a supersaturated state, and even if there is some atomic bias, if it is below saturation, It has been found that there is no Groin In defect.

  It is known that the concentration of these two point defects is determined by the relationship between the crystal pulling rate F (growth rate) in the CZ method and the temperature gradient G in the vicinity of the solid-liquid interface in the crystal. Further, a defect called an OSF (Oxidation Induced Stacking Fault) (hereinafter sometimes referred to as an OSF ring) is present in the N region between the V region and the I region. It was confirmed that it was distributed in a ring shape.

  When these defects due to crystal growth are classified, for example, when the growth rate is relatively high, such as about 0.6 mm / min or more, FPD, LSTD, and COP that are attributed to voids in which vacancy-type point defects are gathered. Such a grown-in defect such as a V region exists in a high density throughout the crystal diameter direction.

  When the growth rate is about 0.6 mm / min or less, an OSF ring is generated from the periphery of the crystal as the growth rate is reduced, and L / D ( Large Dislocation (abbreviation for interstitial dislocation loop, LSEPD, LFPD, etc.) is an I region (sometimes referred to as an L / D region) in which defects exist at low density. Further, when the growth rate is reduced to about 0.4 mm / min or less, the OSF ring aggregates and disappears at the center of the wafer, and the entire surface of the wafer becomes the I region.

  Further, in the middle of the V region and the I region, there is a region called the N region, as described above, in which neither FPD, LSTD, COP due to vacancy nor LSEPD, LFPD due to dislocation loop exist. This N region is outside the OSF ring, and when oxygen precipitation heat treatment is performed and the contrast of precipitation is confirmed by X-ray observation or the like, there is almost no oxygen precipitation, and LSEPD and LFPD are formed. It has been reported that it is the non-rich I region side. Furthermore, in recent years, it has been confirmed that there is an N region inside the OSF ring that is free from defects due to vacancies and defects due to dislocation loops.

  In the normal method, these N regions exist obliquely with respect to the growth axis direction when a single crystal is grown at a lower growth rate, and therefore exist only in a part of the wafer plane. Also for this N region, the Boronkov theory (Non-patent Document 1) argues that the parameter F / G, which is the ratio of the pulling speed F and the temperature gradient G near the crystal solid-liquid interface, determines the total concentration of point defects. Yes. Considering this, since the pulling speed should be constant in the plane in the crystal diameter direction, G is distributed in the plane in the growth of a general single crystal. Only a single crystal that becomes the V region and the I region in the peripheral portion across the N region was obtained.

  Therefore, in recent years, when the in-plane G distribution has been improved, for example, when the single crystal is pulled up while gradually lowering the pulling rate F, the N region, which has existed only at an angle in the past, can be expanded in the radial direction. As a result, it has become possible to produce a single crystal whose entire radial direction is an N region at a certain pulling rate. Further, by growing the single crystal while maintaining the pulling speed when the N region spreads over the entire radial direction, the crystal of the entire N region can be expanded in the length direction. In particular, taking into account that G changes as the crystal grows, the pulling speed is corrected and adjusted so that F / G is constant, so that the crystal that forms the entire N region is greatly expanded in the crystal growth direction. It became possible (for example, patent document 1).

  Further, when the N region outside the OSF ring is further classified, the Nv region (region with many atomic vacancies) adjacent to the outside of the OSF ring, and the Ni region (region with many interstitial silicon) adjacent to the I region (For example, Patent Document 2).

Here, each term shown above will be explained.
1) FPD (Flow Pattern Defect) is a method in which a wafer is cut out from a grown silicon single crystal rod, a strained layer on the surface is removed by etching with a mixed solution of hydrofluoric acid and nitric acid, K ₂ Cr ₂ O ₇ and By etching the surface with a mixed solution of hydrofluoric acid and water (Secco etching), a pit and a ripple pattern (flow pattern) are generated. This flow pattern is referred to as FPD, and the higher the FPD density in the wafer surface, the higher the breakdown voltage of the oxide film (see Patent Document 3).

  2) With SEPD (Secco Etch Pit Defect), when the same Secco etching as FPD is performed, the one with a flow pattern is called FPD, and the one without the flow pattern is called SEPD. Among these, a large SEPD (LSEPD) of 10 μm or more is considered to be caused by a dislocation cluster, and when a dislocation cluster exists in the device, a current leaks through the dislocation and does not function as a PN junction.

  3) In LSTD (Laser Scattering Tomography Defect), a wafer is cut out from a grown silicon single crystal, a strained layer on the surface is removed by etching with a mixed solution of hydrofluoric acid and nitric acid, and then the wafer is cleaved. Infrared light is incident from this cleavage plane (or wafer surface), and light emitted from the wafer surface (or cleavage plane) is detected, so that scattered light due to defects present in the wafer can be detected. The scatterers observed here have already been reported by academic societies and the like, and are regarded as oxygen precipitates (see Non-Patent Document 2). In addition, recent studies have reported the result of octahedral voids.

4) COP (Crystal Originated Particle) and is a defect causing degradation of oxide dielectric breakdown voltage of the wafer, in the Secco etch defects become FPD, SC-1 cleaning _{(NH 4 OH: H 2 O} 2: H 2 Cleaning with a mixed solution of O = 1: 1: 10) acts as a selective etching solution and becomes a COP. The diameter of the pit is 1 μm or less and is examined by a light scattering method.

  5) L / D (Large Dislocation: abbreviation for interstitial dislocation loop) includes LSEPD, LFPD, and the like, which are defects that are considered to be caused by the dislocation loop. As described above, LSEPD refers to a large SEPD having a size of 10 μm or more. The LFPD refers to a large one having a tip pit size of 10 μm or more among the above FPDs.

On the other hand, the silicon single crystal grown by the CZ method contains interstitial oxygen as an impurity at a concentration of approximately 10 ¹⁸ atoms / cm ³ . This interstitial oxygen is in a supersaturated state in the heat history (hereinafter sometimes abbreviated as crystal heat history) until it is cooled to room temperature after solidification during the crystal growth process, and in the heat treatment process in the manufacturing process of the semiconductor element. Therefore, silicon oxide precipitates (hereinafter sometimes referred to as oxygen precipitates, BMD (Bulk Micro Defects), or simply precipitates) are formed.

  This oxygen precipitate works effectively as a gettering site for capturing heavy metal impurities mixed in the device process (Internal Gettering: IG), and can improve device characteristics and yield. However, since oxygen precipitates strongly depend on heat treatment conditions, it is extremely difficult to obtain appropriate oxygen precipitates in different device processes for each user, and control of oxygen precipitates is a very important issue.

  Furthermore, the wafer is not only subjected to a thermal history in the device process, but also originally receives a crystalline thermal history. Therefore, oxygen precipitate nuclei (grow-in precipitation nuclei) formed by the crystal thermal history are already present in the as-grown crystal, and the presence of this grow-in precipitation nuclei makes it more difficult to control the oxygen precipitates. doing.

  The process of oxygen precipitation consists of the formation of precipitation nuclei and their growth process. In the case of a normal as-grown wafer, nucleation progresses in the crystal thermal history, grows greatly due to the subsequent thermal history of the device process, etc., and is detected as oxygen precipitates. Therefore, the oxygen precipitates present on the wafer before the device process is charged are extremely small and do not have IG capability. However, through the device process, oxygen precipitates grow greatly and have IG capability.

  However, with the recent increase in the diameter of wafers used in device processes, temperature reduction and shortening have progressed. For example, in a series of device processes, all heat treatments are performed at a temperature of 1000 ° C. or less, RTP (Rapid Thermal Processing), which performs only a heat treatment time of about ten seconds, is frequently used. In such a device process, for example, even if the heat history of all heat treatments is totaled, it may only correspond to heat treatment at 1000 ° C. for about 2 hours. I cannot expect growth. For this reason, it is desirable that oxygen precipitates of a detectable size having an IG capability are formed at a high density for a device process whose temperature has been reduced and shortened for a short time. On the other hand, if oxygen precipitates are present in the device fabrication region near the wafer surface, the device characteristics are deteriorated. Therefore, it is desirable that no oxygen precipitates exist near the wafer surface.

  In general, when a single crystal is grown by the CZ method, the single crystal may be grown in the V region where the pulling rate can be increased for reasons such as improvement of productivity. In addition to the above-mentioned grown-in precipitation nuclei, the wafer includes a void (hole) type such as COP formed by agglomeration of atomic vacancies as described above, as grown-in defects introduced by the thermal history during crystal pulling. Flaws exist. It is known that when such a void type defect such as COP is present in the device fabrication region, the device characteristics, particularly the oxide film breakdown voltage characteristics, which are important characteristics, are deteriorated. Therefore, it is desirable that no void-type defects exist in the wafer surface layer portion (usually, a region of about several μm from the wafer surface), which is a device manufacturing region, like oxygen precipitates.

  Therefore, in order to eliminate such void-type defects existing in the surface layer portion of the wafer, for example, the wafer is subjected to high-temperature heat treatment at about 1200 ° C. in an inert atmosphere such as hydrogen or argon. Further, for example, a method of adding nitrogen at the time of crystal growth has been proposed in order to eliminate void type defects such as COP existing in the wafer surface layer portion and to form oxygen precipitates inside the wafer (bulk portion). (For example, Patent Documents 4, 5, and 6).

  When nitrogen is added in this way to grow a single crystal and a wafer is produced from the single crystal, the size of voids existing in the wafer is reduced, so that defects are easily lost by high-temperature heat treatment near the wafer surface. In addition, since the grown-in precipitation nuclei formed in the single crystal become larger due to the crystal thermal history, the precipitation nuclei grow in the wafer bulk part without disappearing even if high-temperature heat treatment is performed to form oxygen precipitates. IG capability can be added to the wafer. Furthermore, recently, a method for making the in-plane distribution of the density of oxygen precipitates uniform has also been proposed (Patent Document 7).

However, even when a wafer to which nitrogen is added is produced, a high-temperature heat treatment of about 1200 ° C. is necessary to eliminate void-type defects in the wafer surface layer portion. There is a risk that void-type defects that cannot be detected remain. In addition, the large-sized grown-in precipitation nuclei are thermally stable and are therefore difficult to disappear even in the wafer surface layer portion and may remain in the surface layer portion. If such void type defects and grown-in precipitation nuclei remain in the wafer surface layer, problems such as deterioration of device characteristics occur when a device is manufactured thereafter.
Furthermore, when nitrogen is added at the time of crystal growth as described above, there are problems that the crystal manufacturing process becomes complicated and that it takes time to manage the nitrogen concentration.

JP-A-8-330316 JP 2001-139396 A JP-A-4-192345 JP-A-11-322490 JP 11-322491 A JP 2000-211995 A JP 2002-57160 A International Publication No. WO 01/057293 Pamphlet International Publication No. WO 02/002852 Pamphlet JP 2002-226296 A V. V. Voronkov, Journal of Crystal Growth, vol. 59 (1982), pp. 625 to 643 Shinsuke Sadamitsu et al. Japan Journal of Applied Physics Vol. 32 (1993), p. 3679

  Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to have excellent oxide film breakdown voltage characteristics of a wafer surface layer portion which is a device manufacturing region, and a device process in a wafer bulk portion. An object of the present invention is to provide an annealed wafer in which the density of oxygen precipitates is uniformly high in the plane before the introduction and has an excellent IG capability, and a method of manufacturing the annealed wafer.

In order to achieve the above object, according to the present invention, there is provided an annealed wafer obtained by performing heat treatment on a silicon wafer produced from a silicon single crystal grown by the Czochralski method, and the entire surface of the wafer has grown-in defects and OSFs. The non-defective N region, the non-defective rate of the oxide film pressure resistance in the region from the wafer surface to at least 5 μm in depth is 95% or more, and the density of oxygen precipitates in the wafer is 1 × 10 ⁹ / cm ³ or more Thus, an annealed wafer is provided in which the ratio of the maximum value and the minimum value of the density of oxygen precipitates in the wafer surface (maximum value / minimum value) is 1 to 10. ).

In the annealed wafer of the present invention, the entire surface of the wafer is in the N region, the yield rate of the oxide film withstand voltage characteristic is 95% or more, and the density of oxygen precipitates in the wafer (bulk portion) is 1 × 10 ⁹ / cm ^3. As described above, since the (maximum value / minimum value) value of the oxygen precipitate density in the wafer surface is 1 to 10, the oxide film withstand voltage characteristic of the wafer surface layer portion which is a device manufacturing region is very excellent. In addition, the density of oxygen precipitates exists in the wafer bulk portion at a stage before the device process is introduced in a uniform and high density in the plane, and an annealed wafer having excellent IG capability can be obtained.

  The present invention also relates to an annealed wafer obtained by subjecting a silicon wafer produced from a silicon single crystal grown by the Czochralski method to a heat treatment, wherein the silicon wafer has no grown-in defects and no OSF. There is provided an annealed wafer characterized by being in the Nv region with a large amount of heat and being subjected to heat treatment on the silicon wafer (claim 2).

As described above, if the annealed wafer is formed by annealing the silicon wafer in the Nv region with many atomic vacancies where the entire surface of the wafer does not have any grown-in defects and OSF, not only the wafer surface but also a region from the wafer surface to 5 μm, for example. Since this becomes a defect-free layer (DZ layer), it is possible to obtain a wafer having excellent oxide film pressure resistance characteristics of the wafer surface layer portion, and oxygen precipitates are, for example, 1 × 10 ⁹ / cm ^{3 in the} wafer bulk portion. Since it becomes the above-mentioned high density and uniform in-plane formation, it can be set as the wafer which has the outstanding IG capability.

In this case, the diameter of the annealed wafer may be 200 mm or more.
In the annealed wafer of the present invention, as described above, the oxygen precipitates are formed in a high density and uniformly in the plane, and the oxygen precipitates generate slip dislocations due to, for example, thermal stress when the wafer is heat-treated. It is known to have an effect of suppressing the above. Therefore, if the annealed wafer of the present invention has a diameter of 200 mm or more that is likely to cause slip dislocation by heat treatment, for example, a large-diameter wafer that can suppress the occurrence of slip dislocation due to thermal stress during the device process. In particular, it becomes a very effective wafer in a wafer of 300 mm or more which will be the mainstream in the future.

Further, according to the present invention, in the method of manufacturing a silicon wafer from a silicon single crystal grown by the Czochralski method, and subjecting the manufactured silicon wafer to a heat treatment to manufacture an annealed wafer, as the silicon wafer, After producing a silicon wafer that is an Nv region with many atomic vacancies, with no grown-in defects and no OSF on the entire surface, the produced silicon wafer is subjected to a temperature T ₁₁ ° C. of at least 500 ° C. and 700 ° C. for a predetermined time t. ₁₁ and then heated to a temperature T ₁₂ ° C. of 1000 ° C. to 1230 ° C. at a temperature rising rate of 5 ° C./min or less, and then a heat treatment is performed for t ₁₂ at the temperature T ₁₂ ° C. for a predetermined time. A method for manufacturing an annealed wafer is provided (claim 4).

  In this way, a silicon wafer to be an Nv region having many atomic vacancies is manufactured, and the silicon wafer is held at a temperature of 500 ° C. or higher and 700 ° C. or lower for a predetermined time, so that grown-in precipitation nuclei in the wafer are grown. Can be made difficult to disappear, and new oxygen precipitation nuclei can be generated in the wafer, and then heated to a temperature of 1000 ° C. to 1230 ° C. at a temperature rising rate of 5 ° C./min. By efficiently growing the existing high-density grown-in precipitation nuclei without annihilation, and then maintaining the temperature at that temperature for a predetermined time, oxygen precipitates in the wafer bulk portion are further grown, and oxygen near the wafer surface is simultaneously increased. D is diffused outward to eliminate oxygen precipitation nuclei on the wafer surface layer, and neither oxygen precipitates nor grown-in precipitation nuclei exist on the wafer surface D It is possible to form the layer. As a result, the oxide film withstand voltage characteristic of the wafer surface layer portion, which is a device fabrication region, is extremely excellent, and oxygen precipitates exist in the wafer bulk portion at a high density uniformly in the plane before the device process is introduced. An annealed wafer having excellent IG capability can be easily manufactured.

In this case, it is preferable that the time _{t 11} for holding the silicon wafer at a temperature _{T 11} ° C. of 500 ° C. or higher 700 ° C. or less and 15 minutes or more (claim 5).
Thus, by setting the time t ₁₁ to hold the silicon wafer at a temperature of 500 ° C. or higher 700 ° C. or less 15 minutes or more, can be more difficult to eliminate the grown-in precipitation nuclei, a further new oxygen precipitation nuclei It can be effectively generated in the wafer, and oxygen precipitation nuclei can be formed at a higher density.

Further, it is preferable that the time _{t 12} for holding the silicon wafer at a temperature _{T 12} ° C. of 1000 ° C. or higher 1230 ° C. or less to 30 minutes or more (Claim 6).
Thus, by the time t ₁₂ to hold the silicon wafer at a temperature of 1230 ° C. 1000 ° C. or more and 30 minutes or more, it is possible to stably grow the oxygen precipitates to a size having a gettering capability, Further, the DZ layer can be formed with a sufficient width in the vicinity of the wafer surface.

Further, according to the present invention, in the method of manufacturing a silicon wafer from a silicon single crystal grown by the Czochralski method, and subjecting the manufactured silicon wafer to a heat treatment to manufacture an annealed wafer, the silicon wafer is used as the silicon wafer. After producing a silicon wafer that is an Nv region with many atomic vacancies, with no grown-in defects and no OSF on the entire surface, at least R ₁ ° C./min. From the temperature T ₂₁ ° C. to the temperature T ₂₂ ° C. is applied to the produced silicon wafer. The temperature rising step A ₁ for raising the temperature at a temperature rising rate of R ₂ ° C./min, which is different from the temperature rising rate of the temperature raising step A ₁ from the temperature T ₂₂ ° C to the temperature T ₂₃ ° C. And performing a heat treatment including a temperature raising step B ₁ for heating and a holding step C _{1 for} holding at a temperature T ₂₃ ° C for a predetermined time t _21. A method of manufacturing a wafer is provided (claim 7).

Thus, to prepare a silicon wafer to be a vacancy-rich Nv region, by applying a heated process A ₁ on the silicon wafer, to be grown without causing as much as possible eliminate the grown-in precipitation nuclei in the wafer Next, by performing a temperature rising step B ₁ having a temperature rising rate different from the temperature rising step A ₁ and raising the temperature to a high temperature in a short time, it is possible to suppress the growth of oxygen precipitates in the vicinity of the wafer surface, holding step can be further grow fine oxygen precipitates grown at a heating step a ₁ and heated step B ₁ sized to have the IG capability in wafer bulk portion by applying a C _1, the wafer surface near Then, oxygen precipitates can be eliminated to form a DZ layer. As a result, the oxide film withstand voltage characteristic of the wafer surface layer portion, which is a device fabrication region, is extremely excellent, and oxygen precipitates exist in the wafer bulk portion at a high density uniformly in the plane before the device process is introduced. An annealed wafer having excellent IG capability can be easily manufactured.

At this time, it is preferable that the temperature raising step A ₁ , the temperature raising step B ₁ , and the holding step C ₁ are continuously performed (Claim 8).
Thus, by continuously performing the three steps of the temperature raising step A ₁ , the temperature raising step B ₁ and the holding step C ₁ , the process time of the entire heat treatment step can be shortened, and the efficiency of the heat treatment step and the improvement of the productivity are achieved. Can be achieved.

Further, in the above heating step _{A 1,} the temperature _{T 21} 700 ° C. or less, the temperature _{T 22} of 800 ° C. or higher 1000 ° C. or less, the heating rate _{R 1} to preferably set to 3 ° C. / min or less (according Item 9).
By performing the heating step A ₁ in such a condition, it is possible to increase the density of efficiently grown oxygen precipitate without as much as possible eliminate the grown-in precipitation nuclei formed in the crystal growth step, further steps It leads to shortening of time.

In this case, before performing the heating step _{A 1,} it is preferable to keep the temperature _{T 21} in 30 minutes or more (claim 10).
As described above, by holding the silicon wafer at the temperature T ₂₁ for 30 minutes or more before performing the temperature raising step A ₁ , not only can the grown-in precipitation nuclei be made more difficult to disappear, but in addition to the grown-in precipitation nuclei, New oxygen precipitation nuclei can be effectively generated to form higher density oxygen precipitation nuclei on the silicon wafer.

Further, in the heating step _{B 1,} the temperature _{T 22} of 800 ° C. or higher 1000 ° C. or less, the temperature _{T 23} 1050 ° C. or higher 1230 ° C. or less, the heating rate _{R 2} be 5 ° C. / min or more Preferred (claim 11).
By performing the temperature raising step B ₁ under such conditions, the temperature can be raised in a short time to the holding temperature of the holding step C ₁ , thereby suppressing the growth of oxygen precipitates in the vicinity of the wafer surface, it can be in the subsequent holding step C ₁ easy to eliminate the oxygen precipitates near the surface.

Further, in the holding step _{C 1,} the temperature _{T 23} 1050 ° C. or higher 1230 ° C. or less, it is preferable that the holding time _{t 21} to 30 minutes or more (claim 12).
By performing the holding step C ₁ in such a condition, it is possible to stably grow the oxygen precipitates wafer bulk portion grown in the above heating step A ₁ and heated Step B _1, and simultaneously, the wafer A DZ layer having no oxygen precipitates in the vicinity of the surface can be stably formed with a sufficient width.

  In the method for producing an annealed wafer according to the present invention, it is preferable to use a silicon wafer produced from a silicon single crystal grown without adding nitrogen as the silicon wafer to be subjected to the heat treatment.

  As described above, by using a silicon wafer produced from a silicon single crystal grown without adding nitrogen, a thermally stable grown-in precipitation nucleus, for example, a precipitate having a diameter of 40 nm or more is applied to the silicon wafer to which heat treatment is applied. Since no nuclei exist, the grown-in precipitation nuclei can be easily eliminated from the vicinity of the wafer surface when heat treatment is performed, and a DZ layer can be formed. In addition, since it is not necessary to add nitrogen when growing a silicon single crystal, there is an advantage that the crystal growth process is not complicated and work and management are facilitated.

Furthermore, it is preferable that the oxygen concentration of the silicon wafer subjected to the heat treatment is 14 ppma or more.
If the oxygen concentration of the silicon wafer subjected to the heat treatment is 14 ppma or more, oxygen precipitates can be formed at a higher density in the wafer bulk portion by performing the heat treatment, and the annealed wafer has a more excellent IG capability. Can be added. Further, by increasing the oxygen concentration of the silicon wafer to 14 ppma or higher, the growth rate of oxygen precipitates is increased, so that the overall process time can be shortened.

In the present invention, the diameter of the manufactured annealed wafer can be 200 mm or more.
The method for producing an annealed wafer according to the present invention can be applied particularly suitably when producing an annealed wafer having a large diameter of 200 mm or more, which has been easy to generate slip dislocation by heat treatment. That is, according to the present invention, as described above, large-size oxygen precipitates can be uniformly formed at a high density in the wafer surface, so that the probability that the slip dislocation generated during the heat treatment is pinned is increased, and the occurrence of slip dislocation is prevented. Can be suppressed. Therefore, it is possible to stably manufacture a large-diameter annealed wafer in which slip dislocation does not occur.

  As described above, according to the present invention, an annealed wafer is manufactured by heat-treating a silicon wafer, which is an Nv region with many atomic vacancies, in which the entire surface of the wafer is free of grown-in defects and OSF, under predetermined conditions. In addition, the oxide film pressure resistance of the wafer surface layer, which is the device fabrication area, is extremely excellent, and the oxygen precipitates exist in the wafer bulk part at a stage before the device process is introduced, and the IG capability is excellent evenly in the surface. An annealed wafer having the following can be provided.

Hereinafter, although an embodiment is described about the present invention, the present invention is not limited to these.
In order to produce a wafer in which the oxide film pressure resistance characteristics of the wafer surface layer portion are extremely excellent and the oxygen precipitates are present in the wafer bulk portion at a stage before the device process is introduced, in a uniform and high density in the surface. In addition, earnest experiment and examination were repeated. As a result, for example, when oxygen precipitation heat treatment is performed at 800 ° C. for 4 hours + 1000 ° C. for 16 hours, the amount of oxygen precipitation (that is, the difference between the initial oxygen concentration before the oxygen precipitation heat treatment and the oxygen concentration after the oxygen precipitation heat treatment) ) Is 1 ppma (JEIDA: Japan Electronics Industry Promotion Association standard) or higher silicon wafers have moderately stable thermally grown grown-in precipitation nuclei, so by performing heat treatment on such silicon wafers It was found that the oxygen precipitates can be stably formed by growing the grown-in precipitation nuclei in the wafer bulk part without annihilating them.

  On the other hand, in order to improve the oxide film breakdown voltage characteristics of the wafer, a silicon wafer in which the entire surface of the wafer is an N region in which neither a grown-in defect nor an OSF exists is used, and further, oxygen precipitates are formed on the silicon wafer serving as the N region. When heat treatment is performed, a DZ layer can be formed in the vicinity of the wafer surface, and oxygen precipitates can be formed in the bulk portion of the wafer. However, as described above, the N region includes the Nv region and the Ni region, and the Ni region is a region in which oxygen precipitation is less likely to occur as compared with the Nv region. Therefore, the Ni region and the Nv region are mixed in the wafer surface. When such a silicon wafer is subjected to heat treatment, the density of oxygen precipitates becomes non-uniform in the wafer plane, and as a result, the gettering ability of the wafer becomes non-uniform in the plane. It was. Further, in this case, it has been found that the wafer may be warped due to in-plane variation in the density of oxygen precipitates.

  Therefore, as a result of further experiments and examinations, the present inventors have found that, in the Nv region of a silicon wafer, the oxygen precipitation amount becomes 1 ppma or more when the above oxygen precipitation heat treatment is performed, and this When an annealed wafer is manufactured by heat-treating a silicon wafer in which the Nv region extends over the entire surface of the wafer, the oxide film pressure resistance characteristics of the wafer surface layer portion are very excellent, and oxygen precipitates are uniformly distributed in the wafer bulk portion. The present invention was completed by conceiving that a high-quality annealed wafer that exists at a high density can be obtained.

  That is, the annealed wafer of the present invention is an annealed wafer obtained by performing a heat treatment on a silicon wafer produced from a silicon single crystal grown by the CZ method, and the entire surface of the silicon wafer is free from any grown-in defects or OSFs. The Nv region has many holes, and is characterized in that the silicon wafer is heat-treated.

In addition, the annealed wafer of the present invention is an N region where the entire surface of the wafer is free of grow-in defects and OSF, and the non-defective rate of the oxide film withstand voltage in the region at least 5 μm deep from the wafer surface is 95% or more. And the density of oxygen precipitates in the wafer is 1 × 10 ⁹ / cm ³ or more, and the ratio of the maximum value and the minimum value of the density of oxygen precipitates in the wafer plane (maximum value / minimum value) Can be characterized by being 1-10.

As described above, the annealed wafer of the present invention has a defect-free layer formed not only on the wafer surface but also in a region at least 5 μm deep from the wafer surface. For example, even when a device is manufactured up to a relatively deep region of the surface layer portion of the wafer, it is possible to obtain a wafer that does not deteriorate the device characteristics. Here, the oxide dielectric breakdown voltage characteristic in the present invention means that the TZDB (Time Zero Dielectric Breakdown) characteristic, the yield rate, for example, the determination current value as 1 mA / cm ^2, dielectric breakdown field 8 MV / The ratio of what becomes cm or more is shown.

  As a simple method for detecting defects on the surface layer of the wafer, for example, there are a particle counter and a selective etching method. However, even when defects are inspected using these methods, there are cases where defects having a size smaller than the detection lower limit exist and the oxide film breakdown voltage characteristic is deteriorated. Therefore, as described above, it is extremely important that the annealed wafer of the present invention has excellent oxide film breakdown voltage characteristics such that the yield rate is 95% or more, and further 100%.

Further, since the annealed wafer of the present invention, the density of oxygen precipitate above size having an IG capability is detected in the wafer interior (bulk portion) as described above it is 1 × 10 9 ^/ cm ³ or more, the device process Even in device processes that have excellent IG capability at the stage prior to the introduction and the recent trend toward lower temperatures and shorter times, oxygen precipitates in the wafer bulk part function as gettering sites from the initial stage of the device process. It is possible to obtain a wafer that can exhibit a sufficient gettering ability without additional heat treatment. At this time, considering the mechanical strength of the annealed wafer, the density of oxygen precipitates is preferably 1 × 10 ¹³ / cm ³ or less in order to prevent deterioration due to excessive precipitation.

  In the present invention, the size of the oxygen precipitate having the IG ability is based on the size of the oxygen precipitate that can be detected experimentally (for example, about 30 to 40 nm in diameter), and particularly has a gettering ability. The size of the oxygen precipitate is preferably about 40 nm or more in diameter. In general, oxygen precipitates of a size that cannot be detected experimentally are considered to have IG capability, and thus an oxygen precipitate having a size that can be detected experimentally, such as a diameter of 40 nm or more, is sufficient. Can be judged to have IG capability. Such oxygen precipitates can be detected by, for example, an infrared scattering tomography method which is one of light scattering methods.

  Further, in the conventional wafer, the ratio (maximum value / minimum value) between the maximum value and the minimum value of the density of oxygen precipitates in the wafer surface is 20 or more, or an order of magnitude numerical value. In this annealed wafer, the ratio (maximum value / minimum value) between the maximum value and the minimum value of the density of oxygen precipitates in the wafer surface is 1 to 10, and more preferably 1 to 5. The in-plane variation of the IG capability in the bulk portion can be remarkably reduced, and a wafer having a very excellent gettering capability uniformly over the entire surface of the wafer can be obtained. Further, in this case, problems such as wafer warpage caused by the in-plane variation in the density of oxygen precipitates in the conventional annealed wafer can be easily solved.

  Further, if the annealed wafer of the present invention is a wafer having a diameter of 200 mm or more that is likely to generate slip dislocation by heat treatment, oxygen precipitates having an effect of suppressing the occurrence of slip dislocation are uniformly and densely within the wafer surface. Therefore, it becomes a large-diameter wafer in which the occurrence of slip dislocation is suppressed in the device process, and it becomes a very effective wafer particularly in a wafer of 300 mm or more which will be the mainstream in the future.

Next, a method for producing the annealed wafer of the present invention as described above will be described with reference to the drawings, but the present invention is not limited to this.
First, a method for producing an annealed wafer according to the first aspect of the present invention is a method of producing an annealed wafer by producing a silicon wafer from a silicon single crystal grown by a CZ method, and subjecting the produced silicon wafer to a heat treatment. As the silicon wafer, a silicon wafer having an Nv region with many atomic vacancies in which the entire surface of the wafer does not have a grown-in defect and no OSF is manufactured, and then the silicon wafer is at least 500 ° C. to 700 ° C. predetermined time at a temperature _{T 11} ° C. _{t 11} holds, then 5 ° C. / min or less was raised to a temperature _{T 12} ° C. of 1000 ° C. or higher 1230 ° C. or less at a Atsushi Nobori rate, then, a predetermined time temperature _{T 12} ° C. those having features to performing heat treatment for t ₁₂ holds.

  Hereinafter, the manufacturing method of the annealed wafer according to the first aspect of the present invention will be described more specifically. Here, FIG. 1 is a flowchart showing an example of a method for manufacturing an annealed wafer according to the first aspect of the present invention, and FIG. 2 is a schematic diagram schematically showing a heat treatment pattern applied to a silicon wafer. is there.

  First, a silicon wafer as a raw material for the annealed wafer is produced from a silicon single crystal grown by the CZ method (step 101 in FIG. 1). At this time, if the silicon wafer to be manufactured becomes an Nv region with many atomic vacancies in which the entire surface of the wafer does not have any grown-in defects or OSFs, the manufacturing method is not particularly limited. As described in 8, 9, 10 and the like, the ratio F / G between the pulling rate F when growing a single crystal and the temperature gradient G in the vicinity of the solid-liquid interface in the pulling crystal is controlled to control the single crystal. Wafers can be manufactured using a pulling method. Here, an example of a method for producing a silicon wafer in the present invention will be specifically described.

  An example of a single crystal pulling apparatus for pulling a silicon single crystal is shown in FIG. As shown in FIG. 5, the single crystal pulling apparatus 20 includes a main crucible 5 having a quartz crucible 5 for containing a raw material melt 4 and a graphite crucible 6 for protecting the quartz crucible 5 in a crucible driving mechanism (not shown). The heater 7 and the heat insulating material 8 are disposed so as to surround the crucibles 5 and 6. A pulling chamber 2 for accommodating and taking out the grown single crystal 3 is connected to the upper portion of the main chamber 1, and a pulling mechanism for pulling up the single crystal 3 while rotating it with a wire 16 is connected to the upper portion of the pulling chamber 2. (Not shown) is provided.

  In addition, a gas rectifying cylinder 13 is provided inside the main chamber 1, and a heat shield member 14 is installed at the lower part of the gas rectifying cylinder 13 so as to face the raw material melt 4. The radiation from the surface of the material is cut and the surface of the raw material melt 4 is kept warm. At this time, the heat shielding member 14 is installed so that the space | interval of the lower end and the surface of the raw material melt 4 will be about 2-20 cm, for example. Furthermore, a cooling cylinder 11 is installed above the gas rectifying cylinder 13, and the single crystal 3 can be forcibly cooled by flowing a cooling medium from the refrigerant inlet 12.

  Further, an inert gas such as argon gas can be introduced from the gas inlet 10 provided in the upper part of the pulling chamber 2, and after passing between the single crystal 3 being pulled and the gas rectifying cylinder 13, The heat shielding member 14 and the melt surface of the raw material melt 4 can be passed between and discharged from the gas outlet 9.

  Further, a magnet (not shown) can be installed outside the main chamber 1 in the horizontal direction, thereby suppressing the convection of the raw material melt by applying a horizontal or vertical magnetic field to the raw material melt 4. In addition, a so-called MCZ method for achieving stable growth of a single crystal can be used.

  For example, when a silicon single crystal is grown by the CZ method using such a single crystal pulling apparatus 20, first, a high-purity polycrystalline material of silicon is heated to a melting point (about 1420 ° C.) or higher in a quartz crucible 5. Melt. Next, the seed crystal 17 fixed to the seed holder 18 is brought into contact with or immersed in the approximate center of the surface of the silicon melt 4 by unwinding the wire 16. Thereafter, the crucible holding shaft 19 is rotated in an appropriate direction, and the wire 16 is wound while being wound to pull up the seed crystal, thereby starting the growth of the single crystal. Thereafter, the substantially cylindrical silicon single crystal 3 can be grown by appropriately adjusting the pulling rate of the single crystal and the temperature of the silicon melt.

At this time, when the pulling rate when growing the single crystal straight body portion is F [mm / min], and the crystal temperature gradient in the pulling axis direction between the silicon melting point and 1400 ° C. is expressed by G [° C./mm] The silicon single crystal is grown by controlling the pulling rate F so that the value of F / G [mm ² / ° C./min] is in the Nv region. In this case, for example, by setting the distance between the lower end of the heat shield member 14 and the surface of the raw material melt 4 to about 2 to 20 cm as described above, the temperature gradient Gc at the crystal central portion and the temperature gradient Ge at the crystal peripheral portion The temperature inside the furnace can be controlled so that the temperature gradient around the crystal is lower than the crystal center, and the entire surface in the crystal diameter direction can be easily made into the Nv region. It becomes possible. Furthermore, for example, it becomes possible to rapidly cool a temperature zone (1,080 to 1150 ° C.) in which a void defect is formed by the cooling cylinder 11 installed above the gas rectifying cylinder 13 to expand the Nv region in the crystal growth axis direction. It is possible to easily grow a single crystal in which the entire straight body portion is an Nv region over the entire radial direction.

  The silicon wafer obtained by slicing the silicon single crystal thus obtained is a silicon wafer that is an Nv region with many atomic vacancies and does not have any grown-in defects or OSFs. Such a silicon wafer can be a wafer in which no grown-in defects or oxygen precipitates are present in the wafer surface layer portion when heat treatment is performed thereafter, and a high oxygen precipitation amount can be obtained in the wafer bulk portion.

  In this case, the silicon wafer is preferably produced from a silicon single crystal grown without adding nitrogen. In the case of a silicon wafer produced from a silicon single crystal grown without adding nitrogen as described above, there is no thermally stable grown-in precipitation nucleus, for example, a precipitation nucleus having a diameter of 40 nm or more on the wafer. When the heat treatment according to the present invention is performed, the grown-in precipitation nuclei are eliminated from the vicinity of the wafer surface, and the DZ layer can be formed stably. Further, since it is not necessary to add nitrogen when growing the silicon single crystal, the crystal growing process is not complicated, and there is an advantage that work and management are simplified.

  In the present invention, a method for producing a silicon wafer from a silicon single crystal is not particularly limited. For example, after slicing a silicon wafer from a silicon single crystal, chamfering, lapping, etching, mirror polishing, etc., which are conventionally performed. By sequentially performing these steps, a silicon wafer can be easily manufactured.

Next, after the silicon wafer manufactured as described above is put into a heat treatment furnace maintained at a temperature T ₁₁ ° C. of, for example, 500 ° C. or more and 700 ° C. or less (step 102 in FIG. 1), as shown in FIG. The temperature T ₁₁ ° C. is maintained for a predetermined time t ₁₁ (step 103 in FIG. 1). By maintaining the temperature T ₁₁ ° C for a predetermined time t _{11 in} this way, it is possible to grow the grown-in precipitation nuclei in the wafer formed by growing the single crystal and to make it difficult to eliminate the precipitation nuclei existing in the wafer bulk portion. In addition, new oxygen precipitation nuclei can be generated on the wafer.

In this case, the holding temperature T _11, if the temperature capable of growing grown-in precipitation nuclei, but can increase the density of oxygen precipitates in annealed wafer after the heat treatment as is at low temperatures, long process time because it and can lead to reduced productivity, the temperature T ₁₁ is preferably set to more than 500 ° C.. On the other hand, when the temperature T ₁₁ is the temperature in excess of 700 ° C., it may become impossible to sufficiently increase the density of oxygen precipitates.

Furthermore, in this case, it is preferable that a silicon wafer temperature T ₁₁ time t ₁₁ to hold the 15 minutes or more, thereby it is possible to more difficult to eliminate grown-in precipitation nuclei, the effect of a new oxygen precipitation nuclei Therefore, it is possible to form oxygen precipitate nuclei at a higher density by generating them on the wafer. Further, the overall process time is too much longer holding time t ₁₁ is long, since it is considered to affect the productivity, the holding time t ₁₁ is preferable to be less approximately 60 minutes. In addition, when the silicon wafer is held at the temperature T ₁₁ as described above, it is not limited to holding the silicon wafer at a constant temperature with high accuracy, and a slight temperature change (for example, an increase of about ± 100 ° C.) near the temperature T ₁₁ depending on conditions. Temperature, temperature drop, etc.). That is, the temperature T _11, since it is sufficient 500 ° C. or higher 700 ° C. or less, to retain the temperature may be maintained at this temperature range, not necessarily a constant temperature. That is, holding at a temperature T ₁₁ ° C. for a predetermined time in the present invention includes such a case where the temperature T ₁₁ is changed and maintained within a range of 500 to 700 ° C.

Next, as shown in FIG. 2, the silicon wafer held at a temperature T ₁₁ of 500 ° C. or higher and 700 ° C. or lower is raised to a temperature T ₁₂ ° C. of 1000 ° C. or higher and 1230 ° C. or lower at a temperature rising rate of 5 ° C./min or lower. Warm (step 104). In this way, by heating the silicon wafer at a rate of 5 ° C./min or less, it is possible to efficiently grow the high-density grown-in precipitation nuclei existing on the wafer without annihilation as much as possible. The lower the is, the higher the precipitate density can be. Therefore, by performing the temperature raising step in this way, the grown-in precipitation nuclei formed when growing the single crystal can be effectively grown. For example, for newly forming oxygen precipitation nuclei on the wafer Even if the heat treatment step is not performed separately, the precipitate density can be made sufficiently high, and the overall process time can be shortened. At this time, the speed of raising the temperature from the temperature T ₁₁ to a temperature T ₁₂ ° C. become faster as exceeding 5 ° C. / min, the higher the percentage of grown-in precipitation nuclei disappear unable growth of oxygen precipitates The density may not be sufficiently obtained. On the other hand, if the process speed is too low, the process time becomes longer than necessary, and therefore the rate of temperature rise is preferably about 1 ° C./min or more.

In the present invention, as the temperature _{T 11} is low, and as the holding time _{t 11} at the temperature _{T 11} is long, as further heating rate from the temperature _{T 11} to the temperature _{T 12} is slow, a new silicon wafer Oxygen precipitate nuclei can be easily formed, and the density of oxygen precipitates in the annealed wafer after heat treatment can be increased. From the temperature T ₁₁ , the holding time t ₁₁ , and the temperature T ₁₁ , depending on the desired quality of the anneal wafer. it is possible to set the heating rate to a temperature T ₁₂ as appropriate.

Then, as described above, the temperature of the silicon wafer is raised to a temperature T ₁₂ ° C. of 1000 ° C. or more and 1230 ° C. or less, and then held at the temperature T ₁₂ ° C. for a predetermined time t ₁₂ (step 105). By holding this way at a temperature T ₁₂ a predetermined time, and the oxygen at the same time the wafer surface near the larger to the size having a gettering capability further grow oxide precipitates in the wafer bulk is outward diffusion of oxygen precipitate nuclei And a DZ layer free from oxygen precipitates can be formed on the surface layer of the wafer.

In this case, the the temperature T ₁₂ is lower than 1000 ° C., the longer it takes to grow a large oxide precipitates wafer bulk portion, becomes longer overall process time. On the other hand, the oxygen precipitate the desired size the higher the temperature T _12, that is, the time to grow to a size having a gettering capability is reduced, it is possible to shorten the total process time, greater than about 1230 ° C. because at high temperatures there is a risk that the metal contamination from a heat treatment furnace occurs significantly, the temperature T ₁₂ is preferably set to 1230 ° C. or less. Furthermore, in order to suppress the generation of the slip dislocation occurring wafer during the heat treatment, the temperature _{T 12} is 1200 ° C. or less, further more preferably in the 1150 ° C. or less, thus 1200 ° C. or less, more 1150 ° C. By holding the silicon wafer at the following temperature, it is possible to grow the oxygen precipitates in the wafer bulk part and at the same time form a DZ layer on the wafer surface layer part. This is particularly effective when heat treating the wafer.

The time t ₁₂ to hold at this temperature T _12, because to reliably grow the grown-in precipitation nuclei of wafer bulk portion size with a gettering ability, also form the DZ layer having a sufficient width to wafer surface In order to do this, it is preferable to set it for 30 minutes or more. Retention time t ₁₂ in this manner for 30 minutes, or by lengthening more than that, by increasing the size of the oxygen precipitates in the bulk portion, a diameter of about 30 nm to 40 nm, as further has a size of more than about 50nm At the same time, a DZ width can be formed in the vicinity of the wafer surface to increase the width. However, there is a fear that the productivity is reduced and the time t ₁₂ becomes too long, the size of the time t ₁₂ is about 4 hours or less, more preferably to more than about 2 hours, the oxygen precipitates grown Is preferably 100 nm or less. On the other hand, the holding time t ₁₂ is shorter than 30 minutes, there may not be obtained oxygen precipitates and DZ width of the desired size by a slight variation in time.

Further, the step of maintaining the temperature T ₁₂ (step 105) is performed in the bulk grown in the steps (steps 102 to 104) from when the silicon wafer is put into the heat treatment furnace until the temperature is raised to the temperature T ₁₂ ° C. The purpose is to further grow the oxygen precipitate and to form a DZ layer near the surface. Therefore, if the object can be achieved, not limited to only retain a high accuracy at a constant temperature, a slight temperature change around the temperature T ₁₂ in accordance with the conditions (for example, about ± 100 ° C. Atsushi Nobori, cooling, etc.) Can also be accompanied. That is, the temperature T12 may be 1000 ° C. or higher and 1230 ° C. or lower. Therefore, when the temperature is held, the temperature T ₁₂ may be held within this temperature range, and does not necessarily need to be a constant temperature. In the present invention, holding at a temperature T ₁₂ ° C. for a predetermined time includes the case where the temperature T ₁₂ is changed and held in the range of 1000 to 1230 ° C. in this way. Furthermore, in the present invention by adjusting the temperature T ₁₂ and the holding time t ₁₂ to hold the silicon wafer at a high temperature, we are possible to easily control the size of the oxygen precipitate formed in the annealed wafer.

After the heat treatment as described above, as shown in FIG. 2, for example, after the temperature in the heat treatment furnace was lowered at a rate of approximately about 2 ° C. / minute from T ₁₂ ° C. to 700 ° C. (cooling step: step 106 ), The silicon wafer is taken out of the heat treatment furnace (step 107). The temperature lowering speed and the wafer take-out temperature after the temperature drop are not particularly limited. For example, it is desirable to set conditions such that slip dislocation due to thermal stress does not occur when the wafer is lowered or taken out.

  Furthermore, in the present invention, the heat treatment atmosphere when performing the heat treatment is not particularly limited. For example, the heat treatment can be performed in an oxygen atmosphere, a mixed atmosphere of oxygen and nitrogen, an argon atmosphere, a hydrogen atmosphere, or the like. In particular, in a non-oxidizing atmosphere of argon or hydrogen, since an oxide film is not formed on the wafer surface, the outward diffusion of oxygen is promoted compared to the oxidizing atmosphere, which may be more preferable.

As described above, after the silicon wafer to be the Nv region is manufactured, the manufactured silicon wafer is subjected to heat treatment under the above-described conditions, whereby the above-described annealed wafer of the present invention, that is, the entire wafer surface is grown-in defect. N region where neither OSF nor OSF exists, the non-defective rate of the oxide film breakdown voltage characteristic in the region from the wafer surface to a depth of at least 5 μm is 95% or more, and the density of oxygen precipitates inside the wafer is 1 × 10 ^9. / Cm ³ or higher, and easily and stably a high-quality annealed wafer having a ratio (maximum value / minimum value) between the maximum density value and the minimum density value of oxygen precipitates in the wafer plane of 1-10. Can be manufactured.

  In the present invention, the silicon wafer to be subjected to the above heat treatment is one having an oxygen concentration of 14 ppma or more, so that oxygen precipitates can be formed at a higher density in the wafer bulk portion. It is possible to add more excellent IG capability. In addition, if the oxygen concentration of the silicon wafer is increased to 14 ppma or more, the growth rate of oxygen precipitates can be increased, so that the overall process time can be shortened. Then, the oxygen concentration of the silicon wafer to be heat-treated is preferably 23 ppma or less, more preferably 17 ppma or less.

Next, a method for manufacturing an annealed wafer according to the second aspect of the present invention will be described.
The method for producing an annealed wafer according to the second aspect of the present invention is a method for producing an annealed wafer by producing a silicon wafer from a silicon single crystal grown by a CZ method and subjecting the produced silicon wafer to a heat treatment. As a silicon wafer, a silicon wafer having an Nv region with many atomic vacancies in which the entire surface of the wafer is free from grow-in defects and OSF is fabricated, and then the fabricated silicon wafer is subjected to at least a temperature T ₂₁ ° C to a temperature T ₂₂ ° C. until the heating step a ₁ for heating at a heating rate of R ₁ ° C. / min, wherein different from the temperature T from ₂₂ ° C. to a temperature T ₂₃ ° C. Atsushi Nobori rate of the heating step a ₁ R ₂ ° C. / min this performing the heating step B ₁ of raising the temperature at a heating rate, the heat treatment and a holding step C ₁ for a predetermined time t ₂₁ held at said temperature T ₂₃ ° C. And have the characteristics.

  Hereinafter, the manufacturing method of the annealed wafer according to the second aspect of the present invention will be described more specifically. Here, FIG. 3 is a flow chart showing a method for manufacturing an annealed wafer according to the second aspect of the present invention, and FIG. 4 is a schematic view schematically showing a heat treatment pattern applied to the silicon wafer.

  First, a silicon wafer as a raw material for the annealed wafer is produced from a silicon single crystal grown by the CZ method (step 201 in FIG. 3). The silicon wafer can be manufactured using a method similar to the method (step 101 in FIG. 1) in which the wafer is manufactured in the first embodiment described above.

Then, the prepared silicon wafer was placed in a heat treatment furnace which is maintained for example at a temperature T ₂₁ ° C. (Step 202 in FIG. 3), as shown in FIG. 4, the temperature T ₂₂ ° C. from the temperature T ₂₁ ° C. until the heating step _{a 1} for heating at a heating rate of _{R 1} ° C. / min (step 203 in FIG. 3). By thus performing the temperature increase step A _1, it is possible to increase the density of efficiently grown oxide precipitates without as much as possible eliminate the grown-in precipitation nuclei formed in the crystal growth step.

At this time, when the temperature T ₂₁ is a temperature exceeding 700 ° C., tends to grown-in precipitation nuclei disappear present in the wafer, the concentration of oxygen precipitates in annealed wafer after the heat treatment which may not be sufficiently obtained , the temperature _{T 21} is preferably set to 700 ° C. or less. Further, it is possible to further increase the density of oxygen precipitate the density of viable grown-in precipitation nuclei higher temperature T ₂₁ is lower becomes higher, the longer the process time required to grow the grown-in precipitation nuclei, there is a fear causing a decrease in productivity, the temperature T ₂₁ is preferably set to 500 ° C. or higher.

In addition, when the temperature rising rate R ₁ from the temperature T ₂₁ to the temperature T ₂₂ in the temperature increasing step A ₁ exceeds 3 ° C./min, the grown-in precipitation nuclei cannot be sufficiently grown, and the growth-in precipitation is performed in the subsequent steps. Since the nuclei may disappear, it is preferable to set the temperature rising rate R ₁ to 3 ° C./min or less. Further, it is desirable that the rate of temperature increase R ₁ is lower because the rate of growth without growth of grown-in precipitation nuclei is higher. However, if the rate is too low, the process time becomes longer and is not efficient. ₁ is preferably 0.5 ° C./min or more.

Furthermore, in this case, the temperature _{T 22} after heating preferably set to 800 ° C. or higher 1000 ° C. or less. The temperature T ₂₂ can not be grown-in precipitation nuclei are sufficiently grown in heating step A ₁ is less than 800 ° C., the rate increases to disappear in the subsequent heating step B1, is sufficiently density of oxygen precipitates It may not be obtained. On the other hand, if the temperature T ₂₂ is higher than 1000 ° C., the grown-in precipitation nuclei near the wafer surface also grow greatly, and oxygen precipitates are near the surface even after the subsequent temperature raising step B ₁ and holding step C _1. In other words, the DZ layer cannot be formed on the surface layer of the wafer, and the oxide film breakdown voltage characteristic may be deteriorated.

In the present invention, it is preferable to keep at a temperature T ₂₁ 30 minutes or more before performing the heating step A _1. In this way, by keeping the silicon wafer at temperature T ₂₁ for 30 minutes or more before the temperature raising step A ₁ , it is possible to make the grow-in precipitation nuclei more difficult to disappear, and in addition to the grow-in precipitation nuclei, new oxygen is added. Precipitation nuclei can be effectively generated to form higher density oxygen precipitation nuclei on the silicon wafer. At this time, since the process time is too long holding time at the temperature T ₂₁ is longer than necessary, it is preferably not more than about 4 hours. Note that when the silicon wafer is held at the temperature T ₂₁ as described above, it is not limited to holding the silicon wafer at a constant temperature with high accuracy, and a slight temperature change in the vicinity of the temperature T ₂₁ can be accompanied depending on conditions. That is, if the temperature T ₂₁ is 700 ° C. or lower, it is not necessarily required to be a constant temperature, and includes a case where the temperature T ₂₁ is changed and maintained within a range of 700 ° C. or lower.

After the heating step A _1, as shown in FIG. 4, the temperature of heating at a heating rate of fast R ₂ ° C. / min than the temperature T ₂₃ ° C. until heating step A ₁ from the temperature T ₂₂ ° C. the rise step _{B 1} (step 204 in FIG. 3). By performing the temperature raising step B ₁ in this manner, the growth of oxygen precipitates in the vicinity of the wafer surface can be suppressed, and the temperature can be raised to a high temperature T ₂₃ in a short time. and prevented from growing more than necessary, the subsequent holding step oxygen precipitates wafer surface near a C ₁ can be easily extinguished.

At this time, heating rate R ₂ from the temperature T ₂₂ to a temperature T ₂₃ is, 5 ° C. / oxygen precipitates near the surface is less than min will grow significantly, hardly disappear in the subsequent holding step C ₁ Therefore, it is preferable that the heating rate R ₂ in the heating step B ₁ is 5 ° C./min or more. On the other hand, if the heating rate R ₂ is too high, oxygen precipitates in the wafer bulk portion may also disappear in the holding step C ₁ , and the oxygen precipitate density may be reduced. ₂ is preferably 10 ° C./min or less.

Also in this heating step _{B 1,} the temperature _{T 23} after heating preferably set to 1050 ° C. or higher 1230 ° C. or less. If the temperature T ₂₃ is less than 1050 ° C., a long time to grow the oxygen precipitates in the bulk portion to a desired size by holding step C ₁ is required, there is a fear that the productivity is reduced, thus by the temperature T ₂₃ and 1050 ° C. or higher, with growing oxygen precipitates in the bulk portion in the holding step C ₁ to efficiently enough, the oxygen in the vicinity of the surface by outward diffusion in the vicinity of the surface oxygen Precipitation nuclei can be eliminated. Further, as the temperature T ₂₃ is increased increases oxygen precipitates in the bulk portion, but also although the DZ width increases, since at high temperatures exceeding 1230 ° C. may occur metal contamination from a heat treatment furnace, the temperature T ₂₃ is It is preferable to set it as 1230 degrees C or less. Furthermore, in order to suppress the generation of the slip dislocation occurring wafer during the heat treatment, the temperature T ₂₃ is 1200 ° C. or less, further more preferably set to 1150 ° C. or less.

Then, after the heating step _{B 1,} as shown in FIG. 4, for holding step _{C 1} for a predetermined time _{t 21} maintained at a temperature _{T 23} ° C. (Step 205 in FIG. 3). By thus performing the holding step C _1, sized to have an IG capability of the above fine oxygen precipitates grown in heating step A ₁ and heated Step B ₁ in the wafer bulk portion, a diameter of about 40nm As described above, it can be grown to a size of about 50 nm or more in diameter, and oxygen precipitates can be more completely eliminated in the vicinity of the wafer surface, so that an extremely high quality DZ layer can be efficiently formed. it can.

At this time, the holding time t ₂₁ the holding step C ₁ is shorter than 30 minutes, the oxygen precipitates and DZ width of the desired size by a slight variation in time could not be obtained, the retention time t ₂₁ is It is preferable to make it 30 minutes or more. The size of the oxygen precipitates in the bulk portion as the holding time t ₂₁ becomes longer increases, also it is preferred because the DZ width increases, in consideration of the productivity of the annealed wafer, the retention time t ₂₁ is less than or equal to about 4 hours Is desirable.

Further, in the holding step C _1, by adjusting the temperature T ₂₃ and the holding time t ₂₁ for holding the silicon wafer at high temperature, the size and the wafer surface of the oxygen precipitates formed in a bulk portion of the annealed wafer DZ The width can be easily controlled, and an annealed wafer having a desired quality can be obtained efficiently and stably. In the holding step C ₁ , as well as the method according to the first aspect of the present invention, the holding step C ₁ is not limited to high-precision holding at the constant temperature T ₂₃ , and a little in the vicinity of the temperature T ₂₃ depending on conditions. A temperature change (for example, temperature increase or decrease of about ± 100 ° C.) can also be accompanied. That is, the temperature T _23, since it is sufficient 1050 ° C. or higher 1230 ° C. or less, to retain the temperature may be maintained at this temperature range, not necessarily a constant temperature. In the present invention, holding at a temperature T ₂₃ ° C for a predetermined time includes the case where the temperature T ₂₃ is changed and held in the range of 1050 to 1230 ° C in this way.

After performing the heat treatment as described above, as shown in FIG. 4, for example, after the temperature is lowered at a rate of about 3 ° C./minute from a temperature T ₂₃ ° C. to 700 ° C. (temperature lowering step: step 206), the silicon wafer is It is taken out of the heat treatment furnace (step 207). The temperature lowering speed and the wafer take-out temperature after the temperature drop are not particularly limited. For example, it is desirable to set conditions such that slip dislocation due to thermal stress does not occur when the wafer is lowered or taken out. Further, in the present invention, the heat treatment atmosphere during the heat treatment is not particularly limited as in the first embodiment.

In the method for producing annealed wafer according to the second aspect of the present invention, such as the above-mentioned heating during step A ₁ and heated Step B _1, and the wafer during the elevated Step B ₁ and holding step C ₁ Can be taken out of the heat treatment furnace, and the temperature raising step A ₁ , the temperature raising step B ₁ and the holding step C ₁ can be individually performed. In the present invention, these temperature raising step A ₁ and temperature raising step B _{1 are performed.} , and it is preferable to perform the holding step C ₁ are continuously, thereby possible to shorten the process time of the entire heat treatment process, it is possible to improve the efficiency and productivity of the heat treatment process.

As described above, after producing a silicon wafer to be an Nv region, the produced silicon wafer is subjected to a heat treatment having at least a temperature raising step A ₁ , a temperature raising step B _1, and a holding step C _1. The annealed wafer of the present invention can be manufactured easily and stably.

  In this case, it is preferable to use a silicon wafer to be subjected to the heat treatment, the wafer having an oxygen concentration of 14 ppma or more, whereby oxygen precipitates can be formed at a higher density in the wafer bulk portion. An even better IG capability can be added to the annealed wafer. Furthermore, if the oxygen concentration of the silicon wafer is increased to 14 ppma or more, the growth rate of oxygen precipitates increases, so that the overall process time can be shortened. However, if the oxygen concentration of the silicon wafer is excessively high, oxygen precipitates near the wafer surface may become difficult to disappear at a high temperature when the silicon wafer is heat-treated, and the production of a silicon single crystal may be difficult. Since it may be difficult, the oxygen concentration of the silicon wafer to be heat-treated is preferably 23 ppma or less, particularly preferably 17 ppma or less.

  The method for manufacturing the annealed wafer according to the first and second aspects of the present invention is particularly suitable for manufacturing an annealed wafer having a large diameter of 200 mm or more, which has been conventionally susceptible to slip dislocation by heat treatment. It can be used suitably. That is, according to the present invention, as described above, large-size oxygen precipitates can be uniformly formed at a high density in the wafer surface, so that the probability that the slip dislocation generated during the heat treatment is pinned is increased, and the occurrence of slip dislocation is prevented. Can be suppressed. Therefore, it is effective in a large-diameter wafer where slip dislocation is likely to occur, and a large-diameter annealed wafer in which slip dislocation does not occur, in particular, an annealing wafer having a diameter of 200 mm, more than 300 mm, which will become a mainstream in the future, is And can be manufactured at a high yield.

EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.
(Example)
A cooling cylinder 11 for forcedly cooling the single crystal by flowing a cooling medium as shown in FIG. 5 and using a single crystal pulling apparatus 20 capable of applying a horizontal magnetic field to the raw material melt, 24 inch quartz The crucible is charged with 150 kg of silicon polycrystal, and a silicon single crystal with a diameter of 200 mm, an orientation <100>, and an oxygen concentration of about 15 ppma (JEIDA) is applied to the length of the straight body while applying a horizontal magnetic field with a central magnetic field strength of 4000 gauss. Was grown to about 130 cm.

  At this time, nitrogen is not added to the single crystal to be grown, and the difference in the crystal temperature gradient G in the single crystal plane (that is, the difference between the temperature gradient Gc at the crystal central portion and the temperature gradient Ge at the crystal peripheral portion) is kept small. As described above, the distance between the silicon melt surface and the heat shield member 14 was set to 60 mm, and the single crystal was grown by gradually reducing the crystal growth rate with respect to the crystal growth axis direction.

  Next, the grown silicon single crystal is vertically divided to prepare a sample, and the vertical sample is subjected to selective etching to confirm the occurrence of FPD and LEPD, and is subjected to thermal oxidation at 1150 ° C. for 100 minutes to generate OSF. Checked the situation. Then, precipitation heat treatment was performed at 800 ° C. for 4 hours and 1000 ° C. for 16 hours, and the crystal defect region of the silicon single crystal was identified from lifetime mapping and the like. The result is shown in FIG. As shown in FIG. 7, it can be seen that the defect-free region, particularly the Nv region, is greatly expanded due to the rapid cooling effect of the cooling cylinder 11.

  Further, for the vertically divided sample prepared above, the initial oxygen concentration before the precipitation heat treatment and the precipitated oxygen concentration after the precipitation heat treatment were measured in the growth axis direction, and the difference between the initial oxygen concentration and the precipitated oxygen concentration after the precipitation heat treatment was measured. The amount of precipitated oxygen was determined. FIG. 7 shows a graph showing the measured initial oxygen concentration and oxygen precipitation amount. As a result, it can be seen that the amount of precipitated oxygen is 1 ppma (JEIDA) or more in the Nv region, whereas almost no precipitation occurs in the Ni region.

  Next, based on the above results, the silicon single crystal was pulled at a growth rate such that a single crystal only in the Nv region was obtained. At this time, the production conditions were adjusted so that the initial oxygen concentration was 15 ppma as described above. Sample wafers were cut out at 20 cm intervals in the growth axis direction from the silicon single crystals thus obtained, and the initial oxygen concentration was measured at 10 mm intervals within the surface of the cut out sample wafers. Thereafter, a heat treatment was performed at 800 ° C. for 4 hours, followed by a precipitation heat treatment at 1000 ° C. for 16 hours. The oxide film resulting from the heat treatment was removed, and the oxygen concentration was measured in the same manner as before the heat treatment. As a result, the oxygen precipitation amount obtained by subtracting the oxygen concentration after the precipitation heat treatment from the initial oxygen concentration exceeded 1 ppma at all measurement points in the plane in all the cut sample wafers. From this, it is considered that the silicon single crystal grown this time was able to form the entire Nv region over the entire area of the single crystal straight body.

  Then, after slicing the wafer from the silicon single crystal having the Nv region, chamfering, lapping, etching, and mirror polishing are performed to produce a mirror-polished silicon wafer, and the wafer is subjected to the following heat treatment in an argon atmosphere. gave. That is, after putting the silicon wafer in a heat treatment furnace heated to 700 ° C. and holding it for 30 minutes, the temperature is raised to 900 ° C. at a rate of 3 ° C./min, and further raised to 1150 ° C. at a rate of 5 ° C./min. And held at 1150 ° C. for 2 hours. Thereafter, the temperature in the heat treatment furnace was lowered to 700 ° C. at a rate of 3 ° C./min, and then the wafer was taken out from the heat treatment furnace.

  For the annealed wafer subjected to the above heat treatment, the density of oxygen precipitates (BMD) inside the wafer was measured at 10 mm intervals by an infrared scattering tomography method, and the in-plane distribution was investigated. According to this infrared scattering tomography method, oxygen precipitates having a diameter of 40 nm or more can be detected. The result is shown in FIG.

As shown in FIG. 9, the density of oxygen precipitates is 1 × 10 ⁹ / cm ³ or more at all measurement points in the wafer plane, and the maximum density of oxygen precipitates in the wafer plane at this time The ratio (maximum value / minimum value) between the minimum value and the minimum value was 2.7, and it was found that oxygen precipitates were uniformly present in the wafer bulk portion at a high density.

Further, in order to investigate the oxide film breakdown voltage characteristics of the annealed wafer manufactured as described above, a thermal oxidation treatment is performed on the wafer in a dry atmosphere to form a 25 nm gate oxide film on which a phosphorous having an electrode area of 8 mm ² is formed. A polysilicon electrode doped with is formed. Then, a voltage was applied to the polysilicon electrode formed on the oxide film, and a TZDB evaluation was performed with a judgment current value of 1 mA / cm ² and a dielectric breakdown electric field of 8 MV / cm or more. As a result, it was found that the non-defective rate of the oxide film withstand voltage characteristic was 100%.
Further, another annealed wafer manufactured as described above was polished by 5 μm from the surface by mechanical chemical polishing, and then TZDB evaluation similar to the above was performed. As a result, the yield rate of the oxide film withstand voltage characteristic was 97%.

(Comparative example)
Next, the cooling cylinder 11 is removed from the single crystal pulling apparatus 20 shown in FIG. 5, and 150 kg of silicon polycrystal is charged in a 24-inch quartz crucible using the single crystal pulling apparatus not equipped with the cooling cylinder 11. Then, while applying a horizontal magnetic field with a central magnetic field strength of 4000 gauss, the crystal growth rate of a silicon single crystal having a diameter of 200 mm, an orientation <100>, and an oxygen concentration of about 15 ppma (JEIDA) is gradually reduced as in the above embodiment. I was brought up. Here, FIG. 6 shows the result of analyzing the temperature distribution of the single crystal pulling apparatus used in the examples and comparative examples. As shown in FIG. 6, it can be confirmed that the single crystal pulling apparatus of the comparative example has a low degree of rapid cooling as compared with the example having the cooling cylinder.

  Subsequently, as in the above example, a vertically divided sample was produced from the grown silicon single crystal, and a crystal defect region of the silicon single crystal was identified. The result is shown in FIG. As shown in FIG. 8, it can be seen that a defect-free region (N region) is very narrow compared to the above example, and it is almost impossible to grow a single crystal whose entire surface is an Nv region.

  Next, based on the above results, the silicon single crystal was pulled at a growth rate such that a single crystal having a defect-free region in which both the Nv region and the Ni region existed was obtained. At this time, the production conditions were adjusted so that the initial oxygen concentration was 15 ppma. A sample wafer was cut out from the silicon single crystal thus obtained in the growth axis direction at intervals of 20 cm, and the amount of precipitated oxygen was determined by the same method as in the above example.

  As a result, in any of the sample wafers cut out, the oxygen precipitation amount did not exceed 1 ppma at all measurement points in the surface, and there were portions where the oxygen precipitation amount was 1 ppma or more and portions where the oxygen precipitation amount was hardly precipitated. From this, it is considered that the Nv region and the Ni region coexist in the silicon single crystal grown this time over the entire crystal region.

  Then, a mirror-polished silicon wafer was produced from the silicon single crystal having the Nv region and the Ni region in the same manner as in the example and subjected to heat treatment under the same conditions as in the example. And about the annealed wafer which heat-processed, the density of the oxygen precipitate (BMD) inside a wafer was measured at an interval of 10 mm by the infrared scattering tomography method, and in-plane distribution was investigated. The results are shown in FIG.

As shown in FIG. 9, annealed wafer manufactured in Comparative Example, the oxygen precipitates in at all measuring points the surface density in not become 1 × 10 9 ^/ cm ³ or more, indicating a low density of oxygen precipitate There was a part. At this time, the ratio of the maximum value and the minimum value of the density of oxygen precipitates in the wafer surface (maximum value / minimum value) was 25, and the in-plane distribution of the oxygen precipitate density was uneven. .

  The present invention is not limited to the above embodiment. The above embodiment is merely an example, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same operational effects. It is included in the technical scope of the invention.

It is a flowchart which shows an example of the manufacturing method of the annealed wafer which concerns on the 1st aspect of this invention. It is a schematic diagram which shows typically the pattern of the heat processing performed to a silicon wafer in the 1st aspect of this invention. It is a flowchart which shows an example of the manufacturing method of the annealed wafer which concerns on the 2nd aspect of this invention. It is a schematic diagram which shows typically the pattern of the heat processing performed to a silicon wafer in the 2nd aspect of this invention. It is the structure schematic which shows an example of the single crystal pulling apparatus which can be used with the manufacturing method of the annealed wafer of this invention. It is a graph which shows the temperature distribution of the single crystal pulling apparatus used in the Example, and the single crystal pulling apparatus used by the comparative example. It is a figure which shows the result of having calculated | required the result of having identified the crystal defect area | region, the initial oxygen concentration, and the oxygen precipitation amount about the vertically divided sample of an Example. It is a figure which shows the result of having identified the crystal defect area | region about the vertically divided sample of a comparative example. It is a graph which shows the value of the density of oxygen precipitates (BMD) and the in-plane distribution in the annealing wafer manufactured by the Example and the comparative example.

Explanation of symbols

1 ... main chamber, 2 ... pulling chamber,
3 ... single crystal (silicon single crystal), 4 ... raw material melt (silicon melt),
5 ... quartz crucible, 6 ... graphite crucible,
7 ... Heater, 8 ... Insulation,
9 ... Gas outlet, 10 ... Gas inlet, 11 ... Cooling tube,
12 ... Refrigerant introduction port, 13 ... Gas rectifier, 14 ... Heat shield member,
16 ... wire, 17 ... seed crystal,
18 ... Seed holder, 19 ... Holding shaft, 20 ... Single crystal pulling device.

Claims (15)

An annealed wafer obtained by heat-treating a silicon wafer produced from a silicon single crystal grown by the Czochralski method, and the entire surface of the wafer is an N region in which neither a grown-in defect nor an OSF exists, and at least a depth of 5 μm from the wafer surface. The non-defective product rate of the oxide film withstand voltage characteristic in the above region is 95% or more, and the density of oxygen precipitates in the wafer is 1 × 10 ⁹ / cm ³ or more, and the maximum value of the density of oxygen precipitates in the wafer surface An annealed wafer characterized in that the ratio of the maximum value to the minimum value (maximum value / minimum value) is 1 to 10.   An annealed wafer obtained by heat-treating a silicon wafer produced from a silicon single crystal grown by the Czochralski method, wherein the entire surface of the silicon wafer is free from grown-in defects and OSF, and has an Nv region with many atomic vacancies An annealed wafer, wherein the silicon wafer is heat-treated.   The annealed wafer according to claim 1 or 2, wherein a diameter of the annealed wafer is 200 mm or more. In a method of manufacturing an annealed wafer by fabricating a silicon wafer from a silicon single crystal grown by the Czochralski method and subjecting the fabricated silicon wafer to heat treatment, the entire surface of the wafer has both grown-in defects and OSF. After manufacturing a silicon wafer to be an Nv region having many atomic vacancies, the silicon wafer is maintained at a temperature T ₁₁ ° C. of at least 500 ° C. to 700 ° C. for a predetermined time t ₁₁ , and then 5 ° C. / min or less at a Atsushi Nobori rate was raised to a temperature T ₁₂ ° C. of 1000 ° C. or higher 1230 ° C. or less, then production of annealed wafer and performing heat treatment for a predetermined time t ₁₂ held at this temperature T ₁₂ ° C. Method. Method for producing annealed wafer according to claim 4, characterized in that the time t ₁₁ to hold at least 15 minutes at a temperature T ₁₁ ° C. below 700 ° C. 500 ° C. or higher the silicon wafer. Method for producing annealed wafer according to claim 4 or claim 5, characterized in that said silicon wafer to 1000 ° C. or higher 1230 ° C. temperature below T ₁₂ ° C. at which time t ₁₂ to 30 minutes or longer. In a method of manufacturing an annealed wafer by fabricating a silicon wafer from a silicon single crystal grown by the Czochralski method and subjecting the fabricated silicon wafer to heat treatment, the entire surface of the wafer has both grown-in defects and OSF. After manufacturing a silicon wafer to be an Nv region with many atomic vacancies, the temperature of the manufactured silicon wafer is increased at least from a temperature T ₂₁ ° C to a temperature T ₂₂ ° C at a rate of R ₁ ° C / min. a heating step a _1, the heating rate of the temperature T ₂₂ ° C. temperature T ₂₃ ° C. the heating step a ₁ to and a heating step B ₁ of raising the temperature at a heating rate of different R ₂ ° C. / minute the method of annealed wafer, characterized in that performing a heat treatment and a holding step C ₁ for a predetermined time t ₂₁ held at said temperature T ₂₃ ° C.. The method for manufacturing an annealed wafer according to claim 7, wherein the temperature raising step A ₁ , the temperature raising step B ₁ , and the holding step C ₁ are continuously performed. In the heating step _{A 1,} the temperature _{T 21} 700 ° C. or less, claims wherein the temperature _{T 22} of 800 ° C. or higher 1000 ° C. or less, characterized in that the heating rate _{R 1} and the 3 ° C. / min or less The manufacturing method of the annealed wafer of Claim 7 or Claim 8. Before performing the heating step A _1, the manufacturing method of the annealed wafer according to any one of claims 7 to 9, characterized in that retaining the temperature T ₂₁ in 30 minutes or more. In the temperature raising step B ₁ , the temperature T _{22 is set} to 800 ° C. to 1000 ° C., the temperature T _{23 is set} to 1050 ° C. to 1230 ° C., and the temperature rising rate R _{2 is set} to 5 ° C./min or more. The method for manufacturing an annealed wafer according to any one of claims 7 to 10. In the holding step _{C 1,} the temperature _{T 23} to 1050 ° C. or higher 1230 ° C. or less, according to any one of claims 7 to 11, characterized in that said holding time _{t 21} to 30 minutes or more Annealed wafer manufacturing method.   The method for producing an annealed wafer according to any one of claims 4 to 12, wherein the silicon wafer subjected to the heat treatment is a silicon wafer produced from a silicon single crystal grown without adding nitrogen. .   The method for manufacturing an annealed wafer according to any one of claims 4 to 13, wherein an oxygen concentration of the silicon wafer subjected to the heat treatment is set to 14 ppma or more.   The method for manufacturing an annealed wafer according to any one of claims 4 to 14, wherein a diameter of the annealed wafer to be manufactured is 200 mm or more.

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