JP2005031850A - Power supply noise analysis method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply noise analysis method, capable of analyzing power supply noise inside a semiconductor circuit taking an influence of a printed board into consideration and analyzing power supply noise, which is generated from the semiconductor integrated circuit, on the printed board. <P>SOLUTION: The semiconductor integrated circuit is divided into a plurality of first unit areas. On each of the first unit areas, power source wiring and current consumption are represented by a simplified power source network and a current source, and a model of the whole of the semiconductor integrated circuit is found by assembling the power source networks and the current sources of the first unit areas. The printed board for mounting the semiconductor circuit is divided into a plurality of second unit areas, a power source layer is represented by a power source network in each of the second unit areas, and a model of the whole of the printed board is found by assembling the power source networks of a plurality of the second unit areas. A circuit equation is solved by binding the model for the whole of the semiconductor integrated circuit and the model of the whole of the printed board together. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to a power supply noise analysis method for a semiconductor integrated circuit, and more particularly to a power supply noise analysis method for obtaining power supply noise at a design stage.
[Prior art]
When a large number of logic cells are switched at the same time inside a semiconductor integrated circuit, or when a large number of I / O cells for input / output from / to the outside are simultaneously switched, a large current flows instantaneously and the power supply is generated by an inductance component on the power supply wiring. Noise is generated. This power supply noise causes a malfunction of a circuit inside the semiconductor device. Furthermore, this power supply noise propagates through the power supply pin to the power supply layer of the printed circuit board outside the semiconductor device, thereby causing malfunction of other circuits on the printed circuit board and EMI noise due to resonance of the power supply layer. EMI noise refers to a phenomenon in which power supply noise generated inside a semiconductor integrated circuit is radiated to space as an electromagnetic wave through a printed circuit board. As the speed of semiconductor integrated circuits increases, the number of pins increases, and the current consumption increases, the problem of power supply noise tends to become more apparent.
[0002]
If a circuit is designed without properly analyzing the influence of power supply noise, the power supply noise of the manufactured circuit may eventually be too great, and the design may have to be performed again. Therefore, it is necessary to perform an appropriate power supply noise analysis at the design stage and design a circuit that copes with the power supply noise.
[0003]
[Patent Document 1]
JP 2002-270695 A [0004]
[Patent Document 2]
JP-A-10-98104 [Problem to be Solved by the Invention]
Even if a technique for analyzing power supply noise inside a semiconductor integrated circuit is constructed, the influence of the printed circuit board cannot be considered unless the printed circuit board is modeled. For example, if the power supply plane on the printed circuit board is expressed as an ideal power supply without modeling, the power supply noise of the semiconductor integrated circuit cannot be analyzed with high accuracy. That is, even if other semiconductor integrated circuits on the printed circuit board generate power supply noise, the influence on the semiconductor integrated circuit to which attention is paid cannot be considered.
[0005]
Further, unless the printed circuit board is modeled, it is impossible to analyze the power supply noise generated from the semiconductor integrated circuit and propagating on the printed circuit board. Similarly, the influence on the printed circuit board cannot be analyzed for power supply noise generated from a plurality of semiconductor integrated circuits.
[0006]
In view of the above, according to the present invention, in a method for analyzing power supply noise in a design stage, power supply noise inside a semiconductor integrated circuit is analyzed in consideration of the influence of the printed circuit board, and on the printed circuit board generated from the semiconductor integrated circuit. An object of the present invention is to provide a power supply noise analysis method capable of analyzing power supply noise.
[Means for Solving the Problems]
A power supply noise analysis method according to the present invention divides a semiconductor integrated circuit into a plurality of first unit regions, and for each first unit region, a power supply wiring, a circuit, and a power supply network, capacitance, And a power source network, a capacity, and a current source are collected for the plurality of first unit regions to obtain an overall model of the semiconductor integrated circuit, and a printed circuit board on which the semiconductor integrated circuit is mounted is obtained. By dividing into a plurality of second unit areas, the power supply layer is represented by a power supply network and a capacity for each second unit area, and the power supply network is grouped for the plurality of second unit areas, so that the entire printed circuit board The method includes obtaining each model and combining the whole model of the semiconductor integrated circuit and the whole model of the printed circuit board to solve a circuit equation.
[0007]
According to the above power supply noise analysis method, a power supply analysis is performed by combining a power supply noise analysis model of a semiconductor integrated circuit and a power supply noise analysis model of a printed circuit board. The influence of the power supply noise generated by the other semiconductor integrated circuits can be taken into consideration, and the power supply noise generated from the semiconductor integrated circuit and propagated on the printed circuit board can be analyzed. Therefore, the accuracy of power source noise analysis inside the semiconductor integrated circuit is improved, and the influence of power source noise on the printed circuit board (such as EMI noise due to electromagnetic radiation) can be studied.
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0008]
FIG. 1 is a diagram schematically illustrating an example of an electronic device that is an object of power supply noise analysis according to the present invention.
[0009]
The electronic device of FIG. 1 includes a printed circuit board (PCB) 10, a semiconductor integrated circuit 11, a semiconductor integrated circuit 12, a signal wiring 13, and a bypass capacitor 14. The printed circuit board 10 includes a signal wiring layer 21, a ground layer 22, and a power supply layer 23. The semiconductor integrated circuit 11 and the semiconductor integrated circuit 12 are mounted on the printed board 10 and exchange signals with each other via the signal wiring 13. The signal wiring 13 is provided in the signal wiring layer 21 of the printed board 10. The semiconductor integrated circuits 11 and 12 are connected to the ground layer 22 to receive the ground voltage, and are connected to the power supply layer 23 to receive the power supply voltage. The bypass capacitor 14 is a capacitor provided between the ground layer 22 and the power supply layer 23 and provides a function of suppressing power supply noise of the printed circuit board 10.
[0010]
The power analysis method according to the present invention divides the interior of each of the semiconductor integrated circuits 11 and 12 vertically and horizontally into a plurality of unit regions (first unit regions), and distributes the power wiring in each unit region to a cross-shaped power network. The power supply wiring of the entire semiconductor integrated circuit is modeled as a mesh-like wiring in which the cross-shaped power supply network is connected vertically and horizontally. This cross-shaped power supply network includes resistances and inductances that represent resistance and inductance components of actual power supply wiring. Between the ground potential and the power supply potential, two cross-shaped power supply networks respectively corresponding to the power supply wirings of both potentials are connected by a current source and a capacitor. This current source represents the current consumed by the logic gate in the unit region, and the capacity is a capacity existing between the ground potential and the power supply potential (inter-wiring capacity, logic gate capacity, decoupling cell capacity, etc. ). Similarly, the ground layer 22 and the power supply layer 23 of the printed circuit board 10 are divided vertically and horizontally into a plurality of unit areas (second unit areas), and each unit area is approximated by a cross-shaped power supply network. The cross-shaped power supply network is modeled as a mesh-like wiring connected vertically and horizontally.
[0011]
FIG. 2 is a diagram for explaining modeling of a semiconductor integrated circuit. FIG. 2A shows the modeling of the package portion (input / output portion) of the semiconductor integrated circuit, and FIG. 2B shows the modeling of the power supply wiring inside the semiconductor integrated circuit.
[0012]
As shown in FIG. 2A, the inside of the semiconductor integrated circuit 11 (or 12) is divided into a plurality of unit regions 31 (only one is shown in the figure) by being divided vertically and horizontally. The power supply wiring inside the unit region 31 is approximated by a cross-shaped power supply network as will be described later. The semiconductor integrated circuit 11 further includes an input cell 33, an output cell 34, an input / output cell 35, and a power supply cell 36. The input cell 33, the output cell 34, and the input / output cell 35 are connected to the signal pin 38 through the bonding wire / lead frame 32 of the package of the semiconductor integrated circuit 11. The power cell 36 is connected to the power pin 39 via the bonding wire / lead frame 32 of the package of the semiconductor integrated circuit 11. In the present invention, the bonding wire / lead frame 32 includes an inductor 32a and a resistor 32b that represent the inductor component and the resistance component of the actual wire and frame.
[0013]
As shown in FIG. 2B, the power supply wiring inside the semiconductor integrated circuit 11 is divided into a power supply layer VDD and a ground layer VSS. Each of the power supply layer VDD and the ground layer VSS is modeled by unit regions 31 connected vertically and horizontally. Each unit region 31 is configured by a cross-shaped power supply network in which four power supply wirings 45 are connected at a node A. Each power supply wiring 45 includes an inductor 45a and a resistance 45b that represent an inductor component and a resistance component of the actual power supply wiring. In the two unit regions 31 facing each other between the power supply layer VDD and the ground layer VSS, the nodes A are connected to each other by the current source 41 and the capacitor 42. The current source 41 represents the current consumed by all the logic gates existing in the unit region 31, and the capacitor 42 is a capacitor (wiring) existing between the ground layer VSS and the power supply layer VDD in the unit region 31. Intercapacitance, logic gate capacity, decoupling cell capacity, etc.).
[0014]
Of the unit regions 31 of the ground layer VSS and the power supply layer VDD, a portion for supplying power to the output cell 34 is shown as a unit region 31a. In this unit region 31 a, three power supply wirings 45 are connected to the node B, and each node B of the ground layer VSS and the power supply layer VDD is connected to the output cell 34. A signal is supplied from the internal signal source 43 to the output cell 34 and is output from the signal pin 38 through the bonding wire / lead frame 32.
[0015]
A second power supply layer VDE is further provided, and second power is supplied to the output cell 34 from the unit region 31b of the second power supply layer VDE. In the unit region 31b, two power supply wirings 45 are connected to the node C.
[0016]
FIG. 3 is a diagram for explaining modeling of a printed circuit board and signal wiring on the printed circuit board. In FIG. 3, the same components as those in FIGS. 1 and 2 are referred to by the same numerals, and a description thereof will be omitted.
[0017]
In the semiconductor integrated circuit 11 and the semiconductor integrated circuit 12, each signal pin 38 is connected to the signal wiring of the signal wiring layer 21, and the power supply pin 39 is connected to the ground layer 22, the power supply layer 23a, and the power supply layer 23b. The power supply layer 23a and the power supply layer 23b correspond to the power supply layer 23 in FIG. The ground layer 22, the power supply layer 23a, and the power supply layer 23b are connected to the ground layer VSS, the power supply layer VDD, and the second power supply layer VDE in FIG. 2, respectively. With these connections, a predetermined power is supplied to the semiconductor integrated circuit 11 and the semiconductor integrated circuit 12, and signals are exchanged between the semiconductor integrated circuits 11 and 12.
[0018]
FIG. 4 is a diagram for explaining modeling of a printed circuit board and signal wiring on the printed circuit board in accordance with an actual form. 3 and 4, the same components are referred to by the same numbers. As shown in FIG. 4, each of the ground layer 22 and the power supply layer 23 is actually composed of a single conductor plate (in FIG. 4, only one of the power supply layer VDD and the second power supply layer VDE is represented. And shown as a power supply layer 23). In the modeling, each of the ground layer 22 and the power supply layer 23 is divided into a plurality of unit regions 51 vertically and horizontally. In addition, an epoxy glass is generally inserted as an interlayer material between the ground layer 22 and the power supply layer 23, and the resulting capacitance is expressed as an interlayer capacitor 52. The interlayer capacitor 52 connects between two corresponding unit regions 51 of the ground layer 22 and the power supply layer 23.
[0019]
The signal wiring 13 is provided on the signal wiring layer 21 and connected to the signal pins 38 of the semiconductor integrated circuits 11 and 12. The signal wiring layer 21 and the signal wiring 13 are divided into a plurality of unit regions 61, and each unit region 61 is represented as a transmission line 62. The bypass capacitor 14 is expressed as a bypass capacitor model 53. The bypass capacitor model 53 includes a resistor 53a, an inductor 53b, and a capacitor 53c that express the resistance component, the inductor component, and the capacitance component of the bypass capacitor 14.
[0020]
Returning to FIG. 3, only one unit region 51 is shown as the ground layer 22, the power supply layer 23 a, and the power supply layer 23 b in consideration of the simplicity of illustration, but as described with reference to FIG. 4. In practice, a plurality of unit areas 51 are arranged vertically and horizontally and connected to each other. The same applies to the signal wiring layer 21, and a plurality of unit regions 61 are provided in modeling.
[0021]
Each unit region 51 is configured by a cross-shaped power supply network in which four power supply wirings 55 are connected at a node C as in the case of the unit region 31 of FIG. Each power supply line 55 includes an inductor 55a and a resistor 55b that represent an inductor component and a resistance component of the actual power supply line. In the two unit regions 51 facing each other between the power supply layer 23 a and the ground layer 22, the nodes C are connected to each other by a bypass capacitor model 53 and an interlayer capacitor 52. Further, in the two unit regions 51 facing each other between the power supply layer 23 b and the power supply layer 23 a, the nodes C are connected to each other by an interlayer capacitor 54. The transmission line 62 in the unit region 61 of the signal wiring layer 21 may be a distributed constant line expressed by a resistance per unit length, an inductor, and a capacitance.
[0022]
FIG. 5 is a flowchart showing a power supply noise analysis method according to the present invention.
[0023]
In step ST1 of FIG. 5, a power supply noise analysis LSI model 102 is created based on the LSI layout information 101. A power noise analysis PKG (package) model 103 is generated from package layout information and the like. That is, a power noise analysis PKG model 103 as shown in FIG. 2A and a power noise analysis LSI model 102 as shown in FIG. 2B are generated.
[0024]
In step ST2, a power supply noise analysis PCB model 105 is created based on PCB (printed circuit board) layout information 104. The power supply noise analysis PCB model 105 corresponds to a portion provided between the semiconductor integrated circuit 11 and the semiconductor integrated circuit 12 shown in FIG.
[0025]
In step ST3, a power supply noise analysis circuit analysis simulator is executed based on the power supply noise analysis LSI model 102, the power supply noise analysis PKG model 103, and the power supply noise analysis PCB model 105. As a result, the power supply noise information 106 inside the LSI, the power supply noise information 107 on the printed circuit board, and the power supply pin current waveform information 108 for EMI noise analysis are output.
[0026]
Specifically, the power supply noise analysis LSI model 102, the power supply noise analysis PKG model 103, and the power supply noise analysis PCB model 105 are combined to form a single model, and each unit is solved by solving the entire circuit equation. Find the voltage variation of the nodes in the region. At this time, for the current source 41 indicating the current consumption of all the logic gates in the unit region 31, the current waveform of the current source 41 is determined assuming the operation of the logic gate. Thereby, the current consumption operation in the semiconductor integrated circuits 11 and 12 can be simulated. For the internal signal source 43 that generates a signal to be output from the output cell 34, for example, a signal in which all the output cells 34 are simultaneously switched is assumed as a worst case. Thus, it is possible to simulate the generation of power supply noise due to simultaneous switching of the output cell 34 (input / output cell 35). By solving the circuit equation based on such a simulation, the voltage fluctuation of the node in each unit region can be obtained.
[0027]
By using the power supply noise information 106 in the LSI thus obtained and the power supply noise information 107 on the printed circuit board, the location where there is a problem with the power supply noise is checked and the design is corrected. It becomes possible to cope with power supply noise. Further, each power pin current waveform information 108 can be used in an electromagnetic field analysis simulator in the next stage.
[0028]
FIG. 6 is a flowchart illustrating a method for determining an optimum capacity of a decoupling cell by executing an electromagnetic field simulation based on a power supply noise analysis method according to the present invention.
[0029]
A decoupling cell is a capacitor inserted as an actual element between a power supply potential and a ground potential for the purpose of reducing power supply noise in the semiconductor integrated circuit. FIG. 7 is a diagram for explaining the structure of the decoupling cell. As shown in FIG. 7, MOS transistors 120 and 121 are connected between the power supply potential VDD and the ground potential VSS. At this time, the gate end of the MOS transistor is connected to one of the power supply potential VDD and the ground potential VSS, and the source end, the drain end, and the substrate potential end are connected to the other. As a result, the gate capacitances of the MOS transistors 120 and 121 are used as the decoupling capacitance 122.
[0030]
In step ST1 of FIG. 6, a power supply noise analysis circuit analysis simulator is executed based on the power supply noise analysis LSI model 102 and the power supply noise analysis PCB model 105 (including the power supply noise analysis PKG model 103). As a result, the power supply pin current waveform information 108 for EMI noise analysis is output. This procedure is the same as step ST3 in FIG.
[0031]
In step ST2, an electromagnetic field analysis simulator is executed based on each power pin current waveform information 108 and the PCB model 109 for EMI noise analysis. Here, the PCB model 109 for EMI noise analysis is a model generated based on each electromagnetic characteristic of the printed circuit board. Based on this model and the current waveform of each power supply pin, the electromagnetic field analysis simulator calculates the Maxwell equation. By solving, the electromagnetic field distribution radiated from the printed circuit board is calculated. A generally available electromagnetic field analysis tool may be used as the electromagnetic field analysis simulator.
[0032]
Next, in step ST3, based on the calculated electromagnetic field distribution 110, it is determined whether the EMI noise radiated from the printed circuit board satisfies an allowable value. If the EMI tolerance is satisfied, the capacity of the current decoupling cell is output as the optimum capacity 111. As a result, an LSI with EMI countermeasures is created. If the EMI allowable value is not satisfied, a decoupling cell is additionally inserted into the LSI in step ST4. Then, based on the power supply noise analysis LSI model 102 with the additional decoupling cell inserted, the circuit analysis in step ST1 and the electromagnetic field analysis in step ST2 are executed again. By repeating this process, the optimum decoupling cell capacity can be calculated as an EMI countermeasure. As a result, the optimum decoupling cell capacity can be calculated for the EMI noise accompanying the simultaneous switching of the logic cells in the semiconductor integrated circuit.
[0033]
As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.
[0034]
The present invention includes the following contents.
(Appendix 1) Dividing a semiconductor integrated circuit into a plurality of first unit regions,
For each first unit region, power supply wiring and current consumption are represented by a simplified power supply network and current source,
An overall model of the semiconductor integrated circuit is obtained by collecting the power supply network and the current source for the plurality of first unit regions,
Dividing a printed circuit board on which the semiconductor integrated circuit is mounted into a plurality of second unit regions;
For each second unit region, the power layer is represented by a power network,
An overall model of the printed circuit board is obtained by collecting the power supply network for the plurality of second unit regions,
A power supply noise analysis method comprising the steps of solving a circuit equation by combining an entire model of the semiconductor integrated circuit and an entire model of the printed circuit board.
(Appendix 2) An internal signal source representing switching of input / output cells of the semiconductor integrated circuit is provided inside the semiconductor integrated circuit,
A signal line connected to the input / output cell on the printed board is represented by a distributed constant line,
The power supply noise analysis method according to claim 1, further comprising each step of including current consumption by the input / output cell in current consumption of the first unit region.
(Supplementary note 3) The step of solving the circuit equation further includes a step of obtaining a current waveform at a power supply pin of the semiconductor integrated circuit, and the power supply noise analysis method includes an electromagnetic field analysis of a printed circuit board based on the current waveform at the power supply pin. The power supply noise analysis method according to supplementary note 1, further comprising the step of:
(Supplementary Note 4) Based on the result of the electromagnetic field analysis, it is determined whether the electromagnetic field intensity satisfies a predetermined allowable value,
4. The power supply noise analysis method according to appendix 3, further comprising each step of determining the magnitude of the decoupling capacitance based on the determination.
(Supplementary note 5) The power supply noise analysis method according to supplementary note 1, wherein the power supply network further includes a capacity in addition to the power supply network.
(Supplementary note 6) The power source noise analysis method according to supplementary note 4, wherein the electromagnetic field strength is caused by a logic switching cell in the semiconductor integrated circuit.
(Supplementary note 7) The power source noise analysis method according to supplementary note 1, wherein the semiconductor integrated circuit includes at least two semiconductor integrated circuits.
【The invention's effect】
According to the power supply noise analysis method described above, a power supply analysis is performed by combining a power supply noise analysis model of a semiconductor integrated circuit and a power supply noise analysis model of a printed circuit board. The influence of power supply noise generated by other semiconductor integrated circuits on the printed circuit board can be taken into consideration, and power supply noise generated from the semiconductor integrated circuit and propagated on the printed circuit board can be analyzed. Therefore, the accuracy of power source noise analysis inside the semiconductor integrated circuit is improved, and the influence of power source noise on the printed circuit board (such as EMI noise due to electromagnetic radiation) can be studied.
[Brief description of the drawings]
FIG. 1 is a diagram schematically illustrating an example of an electronic device that is an object of power supply noise analysis according to the present invention.
2A is a diagram showing modeling of a package portion of a semiconductor integrated circuit, and FIG. 2B is a diagram showing modeling of power supply wiring inside the semiconductor integrated circuit.
FIG. 3 is a diagram for explaining modeling of a printed circuit board and signal wiring on the printed circuit board.
FIG. 4 is a diagram for explaining modeling of a printed circuit board and signal wiring on the printed circuit board in accordance with an actual form;
FIG. 5 is a flowchart illustrating a power supply noise analysis method according to the present invention.
FIG. 6 is a flowchart illustrating a method of determining an optimum capacity of a decoupling cell by executing an electromagnetic field simulation based on a power supply noise analysis method according to the present invention.
FIG. 7 is a diagram for explaining the structure of a decoupling cell.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Printed circuit board 11 Semiconductor integrated circuit 12 Semiconductor integrated circuit 13 Signal wiring 14 Bypass capacitor 21 Signal wiring layer 22 Ground layer 23 Power supply layer 31 Unit area 33 Input cell 34 Output cell 35 Input / output cell 36 Power supply cell 41 Current source 42 Capacity 43 Inside Signal source 45 Power supply wiring

Claims (5)

Dividing the semiconductor integrated circuit into a plurality of first unit regions;
For each first unit region, power supply wiring and current consumption are represented by a simplified power supply network and current source,
An overall model of the semiconductor integrated circuit is obtained by collecting the power supply network and the current source for the plurality of first unit regions,
Dividing a printed circuit board on which the semiconductor integrated circuit is mounted into a plurality of second unit regions;
For each second unit region, the power layer is represented by a power network,
An overall model of the printed circuit board is obtained by collecting the power supply network for the plurality of second unit regions,
A power supply noise analysis method comprising the steps of solving a circuit equation by combining an entire model of the semiconductor integrated circuit and an entire model of the printed circuit board. An internal signal source representing switching of input / output cells of the semiconductor integrated circuit is provided in the semiconductor integrated circuit;
A signal line connected to the input / output cell on the printed board is represented by a distributed constant line,
2. The power supply noise analysis method according to claim 1, further comprising the steps of including current consumption by the input / output cell in current consumption of the first unit region. Solving the circuit equation further includes obtaining a current waveform at a power supply pin of the semiconductor integrated circuit, and the power supply noise analysis method performs an electromagnetic field analysis of a printed circuit board based on the current waveform at the power supply pin. The power supply noise analysis method according to claim 1, further comprising: Based on the result of the electromagnetic field analysis, it is determined whether the electromagnetic field strength satisfies a predetermined allowable value,
4. The power supply noise analysis method according to claim 3, further comprising the steps of determining the magnitude of the decoupling capacitance based on the determination. 2. The power supply noise analysis method according to claim 1, wherein the power supply network further includes a capacity in addition to the power supply network.

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