JP2005019828A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress breakdown of a semiconductor chip due to thermal stress in a semiconductor device where the electrode of the semiconductor chip is bonded to solder. <P>SOLUTION: An Al electrode 19 formed on a semiconductor substrate 15 through an interlayer insulating film 17 is connected electrically with a P type layer 13 and an N<SP>+</SP>type layer 14 through a contact hole 18 formed in the interlayer insulating film 17 and an Ni plating layer 20 is formed on the Al electrode 19. In the semiconductor device having a constitution where the Ni plating layer 20 of the semiconductor chip is bonded to solder 6b, a void 25 is provided in the Al electrode 19 at a position on th upper side of the contact hole 18. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a configuration in which an electrode portion of a semiconductor chip is joined to solder.
[0002]
[Prior art]
FIG. 4 shows an example of a semiconductor device having a configuration in which an electrode portion of a semiconductor chip is bonded to solder. The semiconductor device 1 shown in FIG. 4 is a semiconductor device configured to dissipate heat from both the front and back surfaces of the semiconductor chip and to allow current to flow through both the front and back surfaces. And a block 5.
[0003]
The lower surface of the semiconductor chip 2 and the upper surface of the lower heat sink 3 are joined by solder 6a. Further, the upper surface of the semiconductor chip 2 and the lower surface of the heat sink block 5 are also joined by solder 6b. Further, the upper surface of the heat sink block 5 and the lower surface of the upper heat sink 4 are also joined by solder 6c.
[0004]
And the whole is sealed with the resin 7 for sealing so that each outer surface of the lower heat sink 3 and the upper heat sink 4 may be exposed (for example, refer patent document 1, 2).
In the semiconductor device having such a configuration, the difference in thermal expansion coefficient between the semiconductor chip 2, the heat sinks 3, 4, the heat sink block 5, and the sealing resin 7 is generally large. For this reason, when the semiconductor device is exposed to a thermal cycle, there is a problem that thermal stress acts on the semiconductor chip 2 and the semiconductor chip 2 is destroyed by the thermal stress.
[0005]
Therefore, conventionally, in order to suppress the destruction 2 of the semiconductor chip due to thermal stress, the material is selected so as to reduce the difference in thermal expansion coefficient.
[0006]
As another means for suppressing destruction of the semiconductor chip due to thermal stress, for example, when the thickness dimension of the semiconductor chip 2 is t1, and the thickness dimension of the heat sinks 3 and 4 is t2, t2 / t1 Some semiconductor devices are configured such that ≧ 5 holds (see Patent Document 1). With this configuration, it is possible to increase the compressive stress for holding the semiconductor chip 2 and reduce the shear stress on the surface of the semiconductor chip 2.
[0007]
[Patent Document 1]
JP 2003-110064 A
[Patent Document 2]
JP 2002-110893 A
[Problems to be solved by the invention]
However, even if the material is selected so as to reduce the difference in thermal expansion coefficient as in the former case, the semiconductor chip 2 may be destroyed because the thermal stress on the semiconductor chip 2 cannot be sufficiently relaxed.
[0010]
Moreover, when the present inventors evaluated the latter semiconductor device 1, it is possible to suppress the breakdown of the semiconductor substrate in the semiconductor chip, but as described below, the breakdown is caused by the electrode portion in the semiconductor chip. It was found that there is a risk of occurrence.
[0011]
Here, FIG. 5 shows a cross-sectional view of the semiconductor device evaluated by the present inventors. FIG. 5 is an enlarged view mainly of the semiconductor chip 2 and the solder 6. The semiconductor chip is configured to include a power semiconductor element. As the power semiconductor element, for example, a so-called trench gate type IGBT is used.
[0012]
Specifically, this semiconductor chip includes a P ⁺ type substrate 11, an N ⁻ type layer 12 as a drift layer, a P type layer 13 as a base layer, and an N ⁺ type layer 14 as an emitter layer. A semiconductor substrate 15 is provided.
[0013]
On the main surface (element formation surface) side of the semiconductor substrate 15, a gate insulating film (on the inner wall of the trench having a depth that penetrates the P-type layer 13 from the surface of the semiconductor substrate 15 and reaches the N ⁻ -type layer 12). A gate electrode 16 is formed through (not shown).
[0014]
On the surface of the semiconductor substrate 15 including the surface of the gate electrode 16, an Al electrode 19 as an emitter electrode is formed via an interlayer insulating film 17, and through a contact hole 18 formed in the interlayer insulating film 17. Thus, the N ⁺ type layer 14 and the Al electrode 19 are electrically connected. An Ni plating layer 20 is formed on the surface of the Al electrode 19. A portion where the Al electrode 19 and the Ni plating layer 20 are formed is an electrode portion 21.
[0015]
A protective film 22 made of polyimide resin or the like is formed on the surface of the Al electrode 19 except for the Ni plating layer 20. On the other hand, a collector electrode 23 is formed on the back side of the semiconductor substrate 15. On the upper surface of the semiconductor chip 2, the Ni plating layer 20 is bonded to the solder 6, and the Al electrode 19 is connected to the heat sink block 5 through the Ni plating 20 and the solder 6 b. The Al electrode 19 and the Ni plating 20 are much thinner than the semiconductor substrate 15 and the solder 6.
[0016]
In the semiconductor device configured as described above, the solder 6 expands and contracts more than the semiconductor substrate 15 when exposed to a cooling cycle, and the electrode portion 21 is much thinner than the semiconductor substrate 15 and the solder 6. The stress is applied to the electrode portion 21 from the solder 6b. For this reason, there is a possibility that when the crack is generated in the electrode portion 21 or the solder 6b contracts, the electrode portion is pulled by the solder 6b and the position of the electrode portion 21 is shifted with respect to the semiconductor substrate 15. .
[0017]
In view of the above, it is a first object of the present invention to provide a semiconductor device having a novel structure capable of suppressing the destruction of a semiconductor chip due to thermal stress.
[0018]
The semiconductor chip is configured to dissipate heat from both the front and back surfaces and cause a current to flow through both the front and back surfaces. The thickness dimension of the semiconductor chip is t1, and the thickness dimension of at least one of the pair of conductor members is t2. The second object of the present invention is to provide a semiconductor device that can suppress the destruction of the electrode portion due to thermal stress in the semiconductor device configured to satisfy t2 / t1 ≧ 5.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, there is provided a semiconductor in which an electrode portion (21) formed on a semiconductor substrate (15) and a conductor member (5) are joined by a joining member (6b). The apparatus is characterized in that a hole (25) is provided in the electrode portion (21).
[0020]
Thus, since the void | hole exists in an electrode part, when stress is applied from the outside, the deflection amount of an electrode part can be made larger than before. For this reason, even when the semiconductor device is exposed to a thermal cycle, the bonding member expands and contracts, and even when stress is applied to the electrode portion, the electrode portion bends and the electrode portion is bonded to the bonding member and the semiconductor substrate. The stress applied to the electrode part can be relaxed. As a result, destruction of the semiconductor chip due to thermal stress can be suppressed.
[0021]
In the invention according to claim 2, the thickness dimension of the semiconductor chip (2) is t1, and the thickness dimension of at least one of the second conductor member (3) and the third conductor member (4) is t2. In the semiconductor device configured so that t2 / t1 ≧ 5 is satisfied, a feature is that holes are provided in the electrode portion (21).
[0022]
Thus, since the void | hole exists in an electrode part, when stress is applied from the outside, the deflection amount of an electrode part can be made larger than before. Therefore, even when the semiconductor device is exposed to a thermal cycle, the first bonding member expands and contracts, and even when stress is applied to the electrode portion, the electrode portion bends so that the electrode portion becomes the first bonding member and The stress applied to the electrode portion can be relaxed while being bonded to the semiconductor substrate.
[0023]
As a result, the thermal stress applied to the electrode portion can be reduced as compared with the conventional case, so that when a crack occurs in the electrode portion or the first bonding member contracts, the stress applied to the electrode portion causes a stress on the semiconductor substrate. Thus, it is possible to suppress the destruction of the electrode part such as the position of the electrode part being shifted.
[0024]
In addition, as shown in Claim 3, a hole (25) can be provided in the site | part above a contact hole (18) among electrode parts (21). Moreover, as shown in claim 4, holes (25) can be provided in the Al electrode (19).
[0025]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
In the present embodiment, a semiconductor device having a configuration in which heat is radiated from both the front and back surfaces of the semiconductor chip and current is supplied to both the front and back surfaces will be described as an example in the same manner as described in the section of the prior art. As described below, the semiconductor device 1 of this embodiment differs from the semiconductor device 1 shown in FIGS. 4 and 5 in the shape of the Al electrode 19 formed on the semiconductor substrate. This is the same as the semiconductor device 1 shown in FIG.
[0027]
Also in the present embodiment, the semiconductor device is configured such that t2 / t1 ≧ 5 is satisfied when the thickness dimension of the semiconductor chip 2 is t1 and the thickness dimension of the heat sinks 3 and 4 is t2. Yes.
[0028]
The correspondence relationship between the semiconductor device of the present invention and the semiconductor device 1 of the present embodiment is as follows. The lower heat sink 3 in FIG. 4 is the second conductor member, the upper heat sink 4 is the third conductor member, and the heat sink block 5 corresponds to the first conductor member. The solder 6a between the lower surface of the semiconductor chip 2 and the upper surface of the lower heat sink 3 is the second bonding member, and the solder 6b between the upper surface of the semiconductor chip 2 and the lower surface of the heat sink block 5 is the first bonding member. The solder 6c between the upper surface of the heat sink block 5 and the lower surface of the upper heat sink 4 corresponds to a third bonding member. Further, the sealing resin 7 corresponds to a sealing member.
[0029]
The semiconductor chip 2 is composed of a power semiconductor element, for example, a trench gate type IGBT, as described in the section of the problem to be solved by the invention. Since the internal structure of the semiconductor substrate 15 is the same as that shown in FIG. 5, the description of the internal structure of the semiconductor substrate 15 is omitted in this embodiment.
[0030]
FIG. 1 is a partial cross-sectional view of the semiconductor device according to this embodiment. FIG. 1 is an enlarged view of a region A in FIG. 4 and is an enlarged view of an Al electrode 19 and a Ni plating layer 20 formed on a semiconductor substrate 15.
[0031]
As shown in FIG. 1, an Al electrode 19 is formed on a semiconductor substrate 15 (on an element formation surface) via an interlayer insulating film 17, and the Al electrode 19 is a contact hole formed in the interlayer insulating film 17. The P-type layer 13 and the N ⁺ -type layer 14 are electrically connected via 18. A Ni plating layer 20 is formed on the Al electrode 19, and the Ni plating layer 20 and the solder 6b are joined.
[0032]
A hole 25 is provided in a portion of the Al electrode 19 located above the contact hole 18. In the present embodiment, the number of holes 25 is the same as the number of contact holes 18.
[0033]
In the present embodiment, the thickness of the semiconductor substrate 15 is, for example, 250 μm or less, the thickness of the Al electrode 19 is approximately 5 μm, the thickness of the Ni plating layer 20 is approximately 5 μm, and is bonded to the Ni plating layer 20. The thickness of the solder 6b is about 100 μm.
[0034]
Further, a control electrode such as a gate pad (not shown) is formed on the surface of the semiconductor chip 2 thus configured, and the control electrode and the lead frame 9 are electrically connected via the bonding wire 10. Has been.
[0035]
4, the semiconductor chip 2, the surface 3a of the lower heat sink 3 bonded to the semiconductor chip 2, the surface 4a of the upper heat sink 4 bonded to the semiconductor chip, the heat sink block 5, the bonding wire 10 A part of the lead frame 9 is collectively sealed with a sealing resin 7.
[0036]
Next, a method for manufacturing this semiconductor device will be described. 2A, 2B, 3A, 3B, and 3C show the manufacturing process of the semiconductor device according to the present embodiment.
[0037]
First, as shown in FIGS. 2A and 2B, a process of forming the semiconductor chip 2 is performed. That is, as shown in FIG. 2A, a semiconductor substrate 15 including a P ⁺ type substrate 11, an N ⁻ type layer 12, a P type layer 13, and an N ⁺ type layer 14 is formed. Then, a trench that penetrates the P-type layer 13 from the surface of the semiconductor substrate 15 and reaches the N ⁻ -type layer 12 is formed, and a gate electrode 16 is formed in the trench through a gate insulating film. Thereafter, an interlayer insulating film 17 is formed on the surface of the semiconductor substrate 15. After forming the interlayer insulating film 17, a contact hole 18 is formed in the interlayer insulating film 17.
[0038]
Subsequently, an Al electrode 19 is formed by forming an Al—Si alloy film over the interlayer insulating film 17 from the inside of the contact hole 18 by, for example, sputtering or vapor deposition. At this time, the film formation temperature is set to, for example, 150 ° C., and the film thickness of the Al—Si alloy film is set to a film thickness in which holes are generated. Note that not only the Al—Si alloy film but also an Al film alone or another Al alloy film can be formed.
[0039]
When the Al—Si alloy film is formed, the Al—Si alloy film is formed along the shape of the contact hole 18. Therefore, when the Al—Si alloy film at the initial stage of film formation is thin, the Al—Si alloy film is formed. The film has a shape having a depression above the contact hole 18. As the Al-Si alloy film becomes thicker, the film thickness does not change in the lower part 19a of the side wall constituting the depression, and only the film thickness in the upper part 19b of the side wall constituting the depression increases. At the upper part 19b, the side walls facing each other contact each other. As a result, holes 25 are formed in the Al—Si alloy film. The side walls 19b above the holes 25 in the Al electrode 19 may be chemically bonded or may not be chemically bonded.
[0040]
Specifically, in the experiments by the present inventors, the thickness 17a of the interlayer insulating film 17 is about 1 μm, the opening width 18a of the contact hole 18 is about 1.2 μm, and the thickness of the Al electrode 19 is 5 μm or more. When the Al—Si alloy film is formed, it is confirmed that the holes 25 exist in the Al electrode 19. Therefore, it is desirable to form the Al—Si alloy film so that the thickness of the Al electrode 19 is 5 μm or more. Note that the film formation temperature is not limited to 150 ° C., and may be any other temperature as long as it is within room temperature to 350 ° C.
[0041]
In this way, using the shape of the contact hole 18, an Al—Si alloy film is formed in such a film thickness that the voids 25 exist inside. Note that the shape, size, and the like of the hole 25 can be changed by changing the opening width, depth, and the like of the contact hole 18.
[0042]
Thereafter, a protective film 22 is formed on the Al electrode 19 with a polyimide resin or the like. Then, as shown in FIG. 2B, a region where the electrode portion 21 is to be formed is removed from the protective film 22, and the Ni plating layer 20 is formed on the Al electrode 19. At this time, since the side walls 19 b are in contact with each other above the holes 25 in the Al electrode 19, the Ni plating layer 20 does not enter the holes 25 in the Al electrode 19.
[0043]
As a result, the Ni plating layer 20 is formed while the holes 25 are present in the Al electrode 19. When the Ni plating layer 20 is formed, a part of the surface layer of the Al electrode 19 is replaced with the Ni plating layer 20, so that the Al electrode 19 becomes thinner than the shape indicated by the broken line in FIG. For this reason, when the Al electrode 19 is formed, it is necessary to set the film thickness of the Al electrode 19 to be larger than a desired thickness after completion.
[0044]
Then, an oxidation-preventing Au plating layer 26 is formed on the Ni plating layer 20 so that the wettability of the solder does not deteriorate due to oxidation of the surface of the Ni plating layer 20, thereby completing the semiconductor chip 2. . The Au plating layer 23 is taken into the solder 6b at the time of joining with the solder 6b.
[0045]
In this embodiment, the Ni layer 20 and the Au layer 26 are formed by a plating method, but the Ni layer 20 and the Au layer 26 can also be formed by other methods such as a sputtering method and a vapor deposition method.
[0046]
Next, similarly to the manufacturing method described in Patent Document 1, a step of bonding the semiconductor chip 2 to the heat sinks 3 and 4 and the heat sink block 5 and sealing with the sealing resin 7 is performed.
[0047]
Specifically, first, as shown in FIG. 3A, a process of soldering the semiconductor chip 2 and the heat sink block 5 to the upper surface of the lower heat sink 3 is performed. In this case, the chip 2 is laminated on the upper surface of the lower heat sink 3 via the solder foil 8, and the heat sink block 5 is laminated on the chip 2 via the solder foil 8. Thereafter, the solder foil 8 is melted by a heating device (reflow device) and then cured. As the solder, for example, Sn-based Pb-free solder can be used.
[0048]
Subsequently, as shown in FIG. 3B, a process of wire bonding the control electrode of the chip 2 and the lead frame 9 is performed. Thereby, for example, the control electrode of the chip 2 and the lead frame 9 are connected by the wire 10 made of Al or Au.
[0049]
Next, as shown in FIG. 3C, a process of soldering the upper heat sink 4 on the heat sink block 5 is performed. The upper heat sink 4 is placed on the heat sink block 5 via the solder foil 8. Then, the solder foil 8 is melted by a heating device and then cured.
[0050]
Then, using a molding die (not shown), a step (molding step) of filling the sealing resin 7 in the gaps and the outer periphery of the heat sinks 3 and 4 is performed. As a result, as shown in FIG. 4, the sealing resin 7 is filled and sealed in the gaps and the outer periphery of the heat sinks 3 and 4. In this way, the semiconductor device 1 is completed.
[0051]
In the semiconductor device of this embodiment, as described above, since the Al electrode 19 has the holes 25, the Al electrode 19 can be bent when an external force is applied to the electrode portion 21. For this reason, even if this semiconductor device is exposed to a thermal cycle and the solder 6b bonded to the Ni plating layer 20 expands and contracts, the Al electrode 19 bends so that the Al electrode 19 is bonded to the semiconductor substrate 15. In addition, the stress applied to the electrode portion 21 from the solder 6b can be relaxed while the Ni plating layer 20 is bonded to the solder 6b.
[0052]
Thus, since the thermal stress applied to the electrode part 21 can be reduced as compared with the conventional case, when the crack is generated in the electrode part 21 or the solder 6b contracts, the stress applied to the electrode part 21 causes the semiconductor The destruction of the electrode part 21 such as the position of the electrode part 21 being shifted on the substrate 15 can be suppressed.
[0053]
In the present embodiment, the solder foil 8 is used as a bonding member for bonding the heat sinks 3 and 4, the semiconductor chip 2, and the heat sink block 5. However, instead of this, a solder paste or the like may be used. good.
[0054]
In the present embodiment, the semiconductor chip 2 is sandwiched between the heat sinks 3 and 4. However, the present invention is not limited to this, and two or more chips (or two or more types of chips) are sandwiched. You may comprise.
[0055]
In the present embodiment, the case where the Al electrode 19 is used as the electrode portion 21 has been described. However, the electrode portion 21 may be composed of Cu or the like. In this case, the Ni plating layer 20 is not necessary.
[0056]
(Other embodiments)
In the first embodiment, the semiconductor device having a configuration in which heat is radiated from both the front and back surfaces of the semiconductor chip and current is supplied to both the front and back surfaces has been described as an example, but another mounting structure in which solder is bonded to the electrode portion of the semiconductor chip. The present invention can also be applied to this semiconductor device.
[0057]
For example, the present invention can also be applied to a semiconductor device in which an electrode and a lead of a semiconductor chip are joined with solder by wireless bonding such as a flip chip method.
[Brief description of the drawings]
FIG. 1 is a partial cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
2 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 1; FIG.
FIG. 3 is a diagram illustrating the manufacturing process of the semiconductor device, following FIG. 2;
FIG. 4 is a cross-sectional view of a semiconductor device according to the related art and the first embodiment.
5 is an enlarged view of a semiconductor chip portion in the conventional semiconductor device shown in FIG. 4;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Semiconductor chip, 3 ... Lower heat sink,
4 ... Upper heat sink, 5 ... Heat sink block, 6 ... Solder,
7 ... Resin for sealing, 9 ... Lead frame, 10 ... Bonding wire,
11 ... P ⁺ type substrate, 12 ... N ^- type layer, 13 ... P type layer, 14 ... N ⁺ type layer,
15 ... Semiconductor substrate, 16 ... Gate electrode, 17 ... Interlayer insulating film,
18 ... Contact hole, 19 ... Al electrode, 20 ... Ni plating layer,
21 ... Electrode part, 22 ... Protective film, 23 ... Collector electrode, 25 ... Hole,
26: Au plating layer.

Claims (4)

In the semiconductor device in which the electrode part (21) formed on the semiconductor substrate (15) and the conductor member (5) are joined together by a joining member (6b) having electrical conductivity,
A semiconductor device, wherein a hole (25) is provided in the electrode portion (21). A semiconductor chip (2) having an electrode portion (21) formed on an element formation surface of a semiconductor substrate (15);
A first conductor member (5) joined to the electrode part (21) via a first joining member (6b) having electrical conductivity;
A second conductor member (3) joined to a surface opposite to the element formation surface of the semiconductor substrate (15) via a second conductor member (6a) having electrical conductivity;
The third conductor member (5) joined to the surface opposite to the surface to which the electrode portion (21) is joined via the third joining member (6c) having electrical conductivity. A conductor member (4);
The semiconductor chip (2), the first conductor member (5), the surface (3a) joined to the semiconductor chip (2) in the second conductor member (3), and the third conductor member A sealing member (7) for sealing the surface (4a) joined to the first conductor member (5) in (4);
When the thickness dimension of the semiconductor chip (2) is t1, and the thickness dimension of at least one of the second conductor member (3) and the third conductor member (4) is t2, t2 In a semiconductor device configured to satisfy / t1 ≧ 5,
A semiconductor device, wherein a hole (25) is provided in the electrode portion (21). The semiconductor substrate (15) and the electrode part (21) are connected via a contact hole (18) formed in an interlayer insulating film (17) located between the semiconductor substrate (15) and the electrode part (21). The semiconductor device according to claim 1, wherein the hole (25) is located above the contact hole (18). The electrode part (21) is formed on the semiconductor substrate (15), and comprises an Al electrode (19) made of Al or an Al alloy, and a Ni layer (20) formed on the Al electrode (19). 4. The semiconductor device according to claim 1, wherein the hole (25) exists in the Al electrode (19). 5.

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