JP2005005385A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can simultaneously achieve a low on-resistance and a high breakdown voltage. <P>SOLUTION: This semiconductor device is provided with a first-conductivity high-resistance semiconductor layer formed on the first principal surface of a semiconductor substrate, a second-conductivity first semiconductor region provided on the surface of the high-resistance semiconductor layer in a state where the region is faced to the substrate, and first-conductivity second semiconductor regions formed on the surface of the high-resistance semiconductor layer to hold the first semiconductor region in between and having shallower depths than the first semiconductor region has. This device is also provided with a second-conductivity embedded region having an embedded section provided with a notched section in a region held between the first semiconductor region and semiconductor substrate, and a contact section led out to the surface of the high-resistance semiconductor layer in the high-resistance semiconductor layer provided between the first and second semiconductor regions and semiconductor substrate. The current path between the second semiconductor region and semiconductor substrate is formed in the high-resistance semiconductor layer through the notched section of the embedded region. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly, to an electrostatic induction transistor with a reduced gate load.
[0002]
[Prior art]
As a conventional switching element, an electrostatic induction transistor (Static Induction Transistor, hereinafter abbreviated as SIT) and a junction field effect transistor (hereinafter, abbreviated as JFET) are known.
[0003]
This type of electrostatic induction semiconductor device is n ⁻ N on one surface portion of the type semiconductor substrate ⁺ Type source region and p ⁺ A type gate region is formed, and the source region is sandwiched between the gate regions. In general, the gate region is formed deeper than the source region, and n sandwiched between the gate regions ⁻ The mold region is called a channel region. N ⁻ N on the other surface portion of the type semiconductor substrate ⁺ Type drain region, n between the drain region and the gate region ⁻ It becomes a type drift region. A source electrode is provided in the source region, a gate electrode is provided in the gate region, and a drain electrode is provided in contact with the drain region.
[0004]
In this electrostatic induction semiconductor device, a channel region is depleted by a voltage signal applied to a gate electrode, and is made conductive / interrupted. However, the main junction of this electrostatic induction semiconductor device is generally formed by a pn junction of a gate layer and a drain layer, and charge / discharge occurs in the depletion layer between the drain and gate during switching. For this reason, for example, at the time of turn-off, the same amount of charge as that flowing to the drain flows into the gate circuit, and the gate driving power is increased.
[0005]
In contrast, n ⁺ Type source region and p ⁺ Type cathode region is contacted by the same cathode electrode, and the gate drive is performed by burdening the cathode electrode with a part of the charge discharged from the p-type region among the charge and discharge of the charge performed at the pn junction at the time of switching. A method for reducing electric power has been proposed (see, for example, Patent Document 1).
[0006]
However, in the case of unipolar static induction semiconductor devices such as SIT and JFET, p in this structure ⁺ The type cathode region becomes an unnecessary dead space other than the reduction of the gate driving power. p ⁺ When the area of the type cathode region is increased, the load on the gate circuit is reduced correspondingly, but the on-resistance is increased because the channel width is reduced. Conversely, p ⁺ If the area of the type cathode region is reduced, the on-resistance is reduced, but the load on the gate circuit is increased accordingly.
[0007]
In contrast, p ⁺ P type cathode region ⁺ Proposed a method to reduce the gate drive power by providing deeper than the gate region and selectively discharging the charge discharged from the p-type region from the cathode region out of the charge and discharge performed at the pn junction during switching. (For example, see Patent Document 2).
[0008]
However, since the gate region and the cathode region having the same p-type conductivity are uneven in the semiconductor substrate, there is a problem that electric field concentration occurs at the deep end of the cathode region and the breakdown voltage is impaired.
[0009]
Further, since the deeply provided cathode region is deeply provided perpendicular to the bottom direction from the surface, the distance that determines the switching performance and the on-resistance (gate region-cathode region interval) and the distance that determines the breakdown voltage (cathode region-cathode) There is also a problem that the degree of freedom in design is low because it is not possible to optimally design (space intervals) separately.
[0010]
An analysis result of the relationship between the breakdown voltage and the distance between the gate regions formed deeper than the source region has also been reported (see, for example, Non-Patent Document 1). This is an investigation of the relationship between the gate-to-gate distance and the breakdown voltage in the configuration as shown in FIG. 30A. FIG. 30B shows the result in a simplified manner. In this analysis, the ideal breakdown voltage is 5 kV, but it can be seen that the breakdown voltage decreases as the distance between the gates increases.
[0011]
When the cathode region is provided, since the cathode region is formed deeper than the gate region, the inter-gate distance in FIG. 30A can be replaced with the inter-cathode distance. From this, it can be understood that the withstand voltage decreases when the distance between the cathodes is increased in order to reduce the on-resistance.
[0012]
[Patent Document 1]
JP-A-4-338678
[0013]
[Patent Document 2]
JP-A-5-75143
[0014]
[Non-Patent Document 1]
Kenichi Ogura et al. ISPSD '95, p. 256
[0015]
[Problems to be solved by the invention]
In general, the wider the distance between the gate region and the cathode region, the lower the on-resistance, and the smaller the distance between the cathode region and the cathode region, the higher the breakdown voltage. Conventionally, either of the requirements of low resistance and high breakdown voltage must be sacrificed, and it has been very difficult to satisfy two contradictory requirements and their optimum values at the same time.
[0016]
The present invention has been made in view of the above circumstances, and provides a semiconductor device that can simultaneously achieve both low on-resistance and high breakdown voltage.
[0017]
[Means for Solving the Problems]
In order to solve the above problems, a first semiconductor device of the present invention includes a semiconductor substrate having first and second main surfaces, and a first conductivity type formed on the first main surface of the semiconductor substrate. A high-resistance semiconductor layer; a second-conductivity-type first semiconductor region provided on a surface of the first-conductivity-type high-resistance semiconductor layer; and the first-conductivity-type high-resistance semiconductor layer on the surface. A first conductivity type second semiconductor region formed so as to sandwich one semiconductor region and shallower than the first semiconductor region, and the first and second semiconductor regions and the semiconductor substrate. A buried portion embedded in the high-resistance semiconductor layer between the first and second semiconductor regions, and the buried portion connected to the buried portion and led to the surface of the high-resistance semiconductor layer A second conductivity type fill having a narrower contact portion A current path between the second semiconductor region and the semiconductor substrate is formed in the high resistance layer through a region sandwiched between the first semiconductor region and the semiconductor substrate. It is characterized by.
[0018]
Furthermore, a second semiconductor device of the present invention is a semiconductor substrate, a first conductivity type high-resistance semiconductor layer formed on the upper surface of the semiconductor substrate, and a second conductivity formed on the upper surface of the high-resistance semiconductor layer. A first semiconductor region of a first type and a second semiconductor of a first conductivity type formed on the upper surface of the high resistance semiconductor layer so as to sandwich the first semiconductor region and formed shallower than the first semiconductor region A region, a portion sandwiching the first semiconductor region and the second semiconductor region sandwiching the first semiconductor region from the outside, and proceeding below the first semiconductor region at a position deeper than the first semiconductor region A vertical cross-section having an overhanging portion in the horizontal direction is sandwiched between an inverted T-shaped or trapezoidal second conductivity type buried region, the horizontal overhanging portion of the buried region and the semiconductor substrate, and in the high-resistance semiconductor layer Formed first conductivity type A drift region, a channel region formed in the high resistance semiconductor layer sandwiched between the first semiconductor region and the buried region, and leading to the drift region, and a first region formed on the first semiconductor region An electrode, a second electrode formed so as to be connected to a portion of the buried region sandwiching the second semiconductor region and the second semiconductor region from the outside, and formed on the lower surface of the semiconductor substrate And a third electrode formed.
[0019]
Furthermore, a third semiconductor device according to the present invention includes a semiconductor substrate, a high-resistance semiconductor layer formed on the upper surface of the semiconductor substrate, and a second first conductivity type formed on the upper surface of the high-resistance semiconductor layer. A first conductive region of a second conductivity type formed on the upper surface of the high resistance semiconductor layer so as to sandwich the second semiconductor region, and formed deeper than the second semiconductor region; Formed in the high-resistance semiconductor layer at a position deeper than one semiconductor region so as to face the semiconductor substrate and having an opening in a region sandwiched between the first semiconductor region and the semiconductor substrate. A buried region of a second conductivity type having a buried portion, a contact portion exposed on the upper surface of the high-resistance semiconductor layer, and a first region formed in the high-resistance layer sandwiched between the buried region and the semiconductor substrate. Conductive drift A channel region that is sandwiched between the first semiconductor region and communicates with the drift region through the opening in the buried region, a first electrode formed on the first semiconductor region, and the second electrode And a third electrode formed on the lower surface of the semiconductor substrate. The second electrode is connected to the contact portion of the buried region.
[0020]
Furthermore, a fourth semiconductor device of the present invention includes a first conductive type high-resistance semiconductor layer, a third semiconductor region having a stripe-like planar shape formed on the surface of the high-resistance semiconductor layer, and the high-resistance semiconductor layer. On the surface of the semiconductor layer, the first semiconductor region of the second conductivity type provided to face the side surface of the striped third semiconductor region and the high resistance so as to sandwich the first semiconductor region A first conductivity type formed on the surface of the semiconductor layer and provided such that a distance from the third semiconductor region is greater than a distance between the first semiconductor region and the third semiconductor region. A planar shape having a second semiconductor region, a portion sandwiching the first semiconductor region and the second semiconductor region sandwiching the first semiconductor region from the outside, and a projecting portion wider than this portion is T-shaped. Type or trapezoid type second conductivity type intervention A first conductivity type drift region sandwiched between the region, the overhanging portion of the intervening region, and the third semiconductor region, and formed in the high-resistance semiconductor layer, the first semiconductor region, and the intervening region A channel region formed in the high-resistance semiconductor layer and connected to the drift region; a first electrode formed on the first semiconductor region; the second semiconductor region; and the intervening region. And a second electrode formed on the third semiconductor region, and a third electrode formed on the third semiconductor region.
[0021]
Furthermore, a fifth aspect of the semiconductor device of the present invention includes a first conductive type high-resistance semiconductor layer, a third semiconductor region having a stripe-like planar shape formed on the surface of the high-resistance semiconductor layer, and the high-resistance semiconductor layer. On the surface of the semiconductor layer, the high-resistance so as to sandwich the second semiconductor region with the second semiconductor region of the first conductivity type provided facing the side surface of the striped third semiconductor region A second conductivity type formed on the surface of the semiconductor layer and formed such that a distance from the third semiconductor region is smaller than a distance between the second semiconductor region and the third semiconductor layer. Formed on the surface of the high-resistance semiconductor layer between the first semiconductor region and the first and second semiconductor regions and the third semiconductor region so as to face the third semiconductor region; A first semiconductor region and the third semiconductor region; A second conductivity type intervening region having an intervening portion having a communication port to be directed, an extending portion connected to the intervening portion and extending in the direction of the second semiconductor region, and the intervening portion of the intervening region And a first conductivity type drift region formed in the high-resistance semiconductor layer sandwiched between the third semiconductor regions, the first and second semiconductor regions, and the intervening region are surrounded on three sides, A channel region communicating with the drift region through the communication port, a first electrode formed on the first semiconductor region, and a second electrode formed so as to be connected to the second semiconductor region and the intervening region. And a third electrode formed on the third semiconductor region.
[0022]
In the above semiconductor device, when the semiconductor substrate or the third semiconductor region is of the first conductivity type, it is an electrostatic induction transistor having the first, second, and third semiconductor regions as a gate, a source, and a drain, respectively. .
[0023]
In the above semiconductor device, when the semiconductor substrate or the third semiconductor region is of the second conductivity type, the electrostatic induction thyristor having the first, second, and third semiconductor regions as a gate, an emitter, and a collector, respectively. It is.
[0024]
In the semiconductor device of the present invention, the embedded (intervening) region that has the same conductivity as the gate region and is in contact with the source electrode is provided so as to be closer to the drain region than the gate region. The width of the portion facing the drain region is formed wider than the width of. For this reason, when the drift region is depleted by turn-off, electric field concentration at the end of the buried (intervening) region is suppressed, and the breakdown voltage is improved.
[0025]
In the semiconductor device of the present invention, the channel region is depleted by a voltage signal applied to the gate electrode, and conduction and interruption are performed. During switching, charge is discharged due to depletion of the drift layer, but the intervening region closer to the drain region than the gate region discharges charge from the drift layer, greatly reducing the load on the gate circuit. Furthermore, by setting the interval between the gate region and the intervening region and the interval between the intervening regions as desired, both low on-resistance and high breakdown voltage can be achieved.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0027]
(Embodiment 1)
FIG. 1 is a cross-sectional view showing the main configuration of the electrostatic induction semiconductor device according to the first embodiment. FIG. 2 is a top view of the entire chip, showing the configuration of the electrodes. A cross-sectional view along the line AA ′ in FIG. 2 corresponds to FIG.
[0028]
The electrostatic induction semiconductor device of this embodiment has a p-type surface on one surface portion of the n-type semiconductor substrate 1. ⁺ Type gate region (first semiconductor region) 2 and n ⁺ Type source region (second semiconductor region) 3 and p ⁺ And a mold embedding region 4. The source region 3 is formed so as to be sandwiched between the gate region 2 and the surface of the buried region 4. The gate region 2 is deeper than the source region 3 and the buried region 4 is deeper than the gate region 2. ing. Gate region 2 and p ⁺ N between mold embedding regions 4 ⁻ The mold region becomes a channel region 7 in which a drain-source current flows.
[0029]
On the other hand, the other surface of the semiconductor substrate 1 is n ⁺ A type drain region (third semiconductor region) 5 is provided. The space between the buried region 4 and the drain region 5 is n ⁻ The type drift layer 6 is formed. P ⁺ The mold embedding region 4 has an inverted T-shaped cross-sectional shape and is n larger than the substrate surface side. ⁺ The portion facing the type drain region 5 is wider. The space between the adjacent buried region 4 tips is set to a position including a line that vertically connects the gate region and the drain region. Further, the horizontally extending portion of the buried region 4 is disposed so as to block at least a part of the line that connects the source region 3 and the drain region 5 vertically.
[0030]
n ⁻ The impurity concentration of the type drift layer 6 is 10 ¹⁵ cm ^-3 -10 ¹⁷ cm ^-3 And other n ⁺ Type and p ⁺ The impurity concentration in the high impurity concentration region of the mold is 10 ²⁰ cm ^-3 -10 ²¹ cm ^-3 Degree. The concentration and thickness of the drift layer 6 are determined from design values of electrical characteristics such as withstand voltage and on-voltage, but when using a SiC substrate, it is about 10 μm at 1000 V class.
[0031]
Further, as shown in FIG. 2, the upper surface electrode of this electrostatic induction semiconductor device is a comb-shaped source electrode 11 and gate electrode 12 which are combined so as to face each other. The source electrode 11 is n ⁺ Type source region 3 and p ⁺ The gate electrode 12 is connected to the mold buried region 4 and p ⁺ It is connected to the mold gate region 2. On the back side of the semiconductor substrate 1, n ⁺ A drain electrode 13 connected to the type drain region 5 is provided.
[0032]
Next, the operation of the semiconductor device will be described. For example, when a positive potential is applied to the drain electrode 13, a ground potential is applied to the source electrode 11, and a predetermined potential of 0 or positive is applied to the gate electrode 12, the semiconductor device is turned on, and n ⁺ Type drain region 5 to n ⁺ A current flows through the mold source region 3.
[0033]
n ⁺ Type drain region 5 to n ⁺ When blocking the current to the source region 3, p ⁺ Type gate region 2 and n ⁻ When a reverse bias (the gate potential is negative with respect to the source potential) is applied to the pn junction between the channel regions 7, p ⁺ Type gate region 2 to n ⁻ A depletion layer extends to the channel region 7 and n ⁻ The mold channel region 7 is pinched off.
[0034]
As a result, the drain-source voltage recovers to the power supply voltage. ⁺ Type drain region 5 and p opposite thereto ⁺ A reverse bias is applied to the mold embedding region 4 and p ⁺ Mold embedding regions 4 to n ⁻ Depletion layer extends into the drift region and positive charge is p ⁺ It is discharged from the mold buried region 4 to the source electrode 11.
[0035]
That is, p ⁺ N than the type gate region 2 ⁺ P close to the type drain region 5 ⁺ Since the mold embedded region 4 mainly discharges positive charges, the load on the gate circuit can be greatly reduced.
[0036]
Although the operation at the time of turn-off has been described here, a positive potential is applied to the gate electrode 12 at the time of turn-on, and the positive charge is p. ⁺ Type gate region 2 and p ⁺ It flows in a direction in which the depletion layer is charged from the mold buried region 4.
[0037]
In this embodiment, p ⁺ The mold embedding area has an inverted T shape, and n ⁺ Since the area near the type drain region is formed large, the above-mentioned discharge or charge current sharing can be more effectively executed. Further, when the drift region is depleted due to turn-off, electric field concentration at the end of the buried (intervening) region is suppressed, and the breakdown voltage is improved.
[0038]
In addition, p which determines on-resistance ⁺ Type gate region and p ⁺ P that determines the interval between the buried regions and the breakdown voltage ⁺ The interval between the mold embedding regions can be determined independently. That is, p ⁺ Type gate region and p ⁺ After determining the space between the mold embedding regions, p ⁺ The interval between the embedded regions can be freely determined by adjusting the length of the inverted T-shaped horizontal portion. Thus, by setting the two intervals freely, both low on-resistance and high breakdown voltage can be achieved simultaneously.
[0039]
Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 3 and FIG. 4, the UC1 portion surrounded by the dotted line in FIG.
[0040]
First, as shown in FIG. 3A, n having a thickness of 10 μm ⁻ Type SiC layer 21 (impurity concentration 1 × 10 ¹⁵ ~ 1x10 ¹⁷ cm ^-3 N) on the surface ⁺ A type SiC substrate (with a substrate thickness of about 400 μm) is prepared, and after cleaning, an ion implantation mask 22 having a width of 4 μm is formed. In this example, the pitch of one unit cell is 16 μm.
[0041]
The ion implantation mask only needs to be able to block implanted ions, and an oxide film mask, a resist mask, a metal mask, and the like are candidates. For the patterning, a known photolithography technique or the like may be used.
[0042]
Next, using this mask 22, p-type impurities (Al or B) are implanted into the upper surface of the SiC layer 21 with an acceleration voltage of several keV to several MeV to a depth of 2 μm to obtain an impurity concentration of 1 × 10 6. ²⁰ ~ 1x10 ²¹ cm ^-3 P with ⁺ A mold region 23 is formed. Any p-type impurity may be used as long as it imparts p-type conductivity to SiC.
[0043]
Next, as shown in FIG. 3C, after removing the mask layer 22, an n layer is formed on the SiC layer 21. ⁻ Type SiC layer 25 (impurity concentration 1 × 10 ¹⁵ ~ 1x10 ¹⁷ cm ^-3 ) Is epitaxially grown to a thickness of 4 μm. N-type impurities such as N and P can be used as the n-type impurity, but any n-type impurity may be used as long as it imparts n-type conductivity to SiC. In addition, since this SiC layer 25 is integrated with the SiC layer 21, the reference numeral 21 is used hereinafter.
[0044]
Next, as shown in FIG. 3D, an ion implantation mask 27 having a width of 14 μm is formed, and exposed portions of 1 μm are provided at both ends of the unit region.
[0045]
Next, as shown in FIG. 3E, p-type impurities (Al or B) are ion-implanted at a depth of 4 μm with an acceleration voltage of several keV to several MeV using a mask 27, and p ⁺ P connected to mold region 23 ⁺ Mold region 28 (impurity concentration 1 × 10 ²⁰ ~ 1x10 ²¹ cm ^-3 ). This p ⁺ The mold region 28 is p ⁺ Since it is integrated with the mold region 23, it will be denoted by reference numeral 23 hereinafter. p ⁺ The mold region 23 becomes the embedded region 4 in FIG.
[0046]
P ⁺ For the formation of the mold region 28, n in FIG. ⁻ P of FIG. 3E from the epitaxial growth of the type SiC layer 25 ⁺ The process up to the ion implantation of the mold region 28 may be repeated a plurality of times until the total film thickness becomes 4 μm.
[0047]
Next, as shown in FIG. 3F, after removing the mask 27, a new ion implantation mask 29 is formed. The mask 29 masks 3 μm at both ends, and has an opening having a width of 10 μm at the center.
[0048]
Next, as shown in FIG. 4A, using a mask 29, a p-type impurity (Al or B) is ion-implanted at a depth of 2 μm with an acceleration voltage of several keV to several MeV. ⁺ Mold region 31 (impurity concentration 1 × 10 ²⁰ ~ 1x10 ²¹ cm ^-3 ). This p ⁺ The mold region 31 becomes the gate region 2 in FIG.
[0049]
Next, as shown in FIG. ⁺ An ion implantation mask 33 is formed so as to cover the mold regions 23 and 31. Subsequently, as shown in FIG. 4C, an n-type impurity (N or P) is ion-implanted with an acceleration voltage of several keV to several hundred keV. N ⁺ Mold region 35 (impurity concentration 1 × 10 ²⁰ ~ 1x10 ²¹ cm ^-3 ). This n ⁺ The mold region 35 becomes the source region 3 in FIG.
[0050]
Next, as shown in FIG. ⁺ Type region 35 and p ⁺ An insulating film 37 having a width of 4 μm is formed on the boundary of the mold region 31 at an interval of 3 μm. Subsequently, as shown in FIG. 4E, a source electrode 11 and a gate electrode are formed of a metal such as Ni, Co, Al, Ti or the like. 12 is formed. The insulating film 37 is provided so that the source electrode 11 and the gate electrode 12 are not short-circuited, and is omitted in FIG. The source electrode 11 is p ⁺ The mold region 23 is provided so as to overlap.
[0051]
Thus, the element on the upper surface side of the SiC substrate is formed. For the back surface side of the SiC substrate, n-type impurities are ion-implanted and diffused from the back surface side of the n-type SiC substrate 1 by n. ⁺ A type drain region 5 is formed, and a drain electrode 13 is formed of a metal such as Ni, Co, Al, Ti or the like. After the formation of the source electrode 11, the gate electrode 12, and the drain electrode 13, it is desirable to reduce the contact resistance of the electrode by applying a heat treatment. When the n-type impurity concentration of the n-type SiC substrate 1 is high, this n ⁺ The formation of the type impurity region can be omitted as necessary.
[0052]
In Embodiment 1, n is provided on the back side of the SiC substrate. ⁺ Type drain region 5 is formed as an electrostatic induction transistor, but n ⁻ P having a mold region on the surface ⁺ A static induction thyristor can also be obtained by using a mold substrate.
[0053]
(Embodiment 2)
The second embodiment is a modification of the first embodiment and provides an embodiment in which the mounting density is further improved. FIG. 5 is a perspective view of the second embodiment, and FIG. 6 is a top view of the chip. The chip top view of FIG. 6 is the same as FIG. 2, but the structure under the source electrode is different from that of the first embodiment (FIG. 2). A cross section taken along line BB ′ of FIG. 6 is shown as a perspective view of FIG.
[0054]
As is clear from FIG. 6, as in the first embodiment, n ⁺ Type source region 3, p ⁺ Type gate region 2, n ⁺ Both sides of the source region 3 are inverted T-shaped p ⁺ The mold embedding region 4 is sandwiched, and the portion sandwiched between the embedding regions 4 is n ⁻ The mold channel region 7 is formed. The channel region 7 extends in the depth direction of the paper and is orthogonal to the comb-teeth portion of the gate electrode 12. In FIG. 5, the channel region bridges adjacent comb teeth. That is, the arrangement direction of the gate region 2, the source region 3, and the buried region 4 is 90 degrees different from that of the first embodiment.
[0055]
The source electrode 11 is n ⁺ Type source region 3 and p ⁺ Although contact is made with the mold buried region 4, insulation is maintained with the gate region 2 through the insulating film 8. A signal is sent to the gate region 2 from a portion (not shown) of the gate electrode 12 (comb teeth) arranged perpendicular to the extending direction of the channel region 7.
[0056]
In the first embodiment, one channel region 7 is formed for each comb tooth of the gate electrode 12. Furthermore, it is necessary to consider the gap between the adjacent comb teeth of the gate electrode 12 to ensure the gap with the source electrode 11, and there is a limit to narrowing the gap.
[0057]
On the other hand, in the second embodiment, the gate region 2, the source region 3, and the buried region 4 can be repeatedly arranged without considering the clearance between the electrodes, so that the channel region 7 can be arranged at a high density. In addition, the on-resistance can be further reduced as compared with the first embodiment. Needless to say, the effects described in the first embodiment can be obtained in the second embodiment as well.
[0058]
Since the configuration of the unit cell is the same as that of the first embodiment, the manufacturing method can be substantially the same as that of the first embodiment. However, since it is not necessary to consider a short circuit between the source electrode and the gate electrode between the unit cells, the cell pitch can be set to 10 μm. Therefore, in FIG. 3A, the cell width is 10 μm, but the width of the ion implantation mask 22 remains 4 μm. Further, since the gate region 31 and the source region 35 are connected to the respective electrodes in different cross sections, the steps of FIGS. 4D and 4E are different. 7A and 7B show a process of forming the insulating film 37 and the source electrode 11 at the connection portion of the source electrode. 8A and 8B show a process of forming the insulating film 37 and the gate electrode 12 at the connection portion of the gate electrode.
[0059]
In the second embodiment, n ⁻ P having a mold region on the surface ⁺ A static induction thyristor can be obtained by using a mold substrate.
[0060]
(Embodiment 3)
In the third embodiment, the cross-sectional shape of the buried region 4 in the first embodiment is changed. The buried region 4 only needs to have a structure in which the width on the side facing the drain region 5 is wider than the width of the portion in contact with the source electrode 11. For example, the buried region 4 has a side surface formed obliquely as shown in FIG. It does not matter. The oblique embedded region 4 can be formed by using a method such as oblique ion implantation of p-type impurities. In this case, it is desirable that the side surface of the source region 3 is also inclined as shown in FIG. For example, the width of the upper surface of the gate region 2 is 10 μm, the width of the source region 3 is 2 μm, the depth of the buried layer 4 is 8 μm, and the interval between the adjacent buried layers 4 is 4 μm.
[0061]
In this embodiment, p ⁺ The cross section of the mold embedding region is formed in a trapezoidal shape, and n ⁺ Since the area near the type drain region is formed large, it is possible to more effectively execute charge discharge or charge sharing during switching. Further, when the drift region is depleted due to turn-off, electric field concentration at the end of the buried (intervening) region is suppressed, and the breakdown voltage is improved.
[0062]
In addition, p which determines on-resistance ⁺ Type gate region and p ⁺ P that determines the interval between the buried regions and the breakdown voltage ⁺ The interval between the mold embedding regions can be determined independently. That is, p ⁺ Type gate region and p ⁺ After determining the space between the mold embedding regions, p ⁺ The interval between the mold embedding regions can be freely determined by adjusting the length of the base of the trapezoid. Thus, by setting the two intervals freely, both low on-resistance and high breakdown voltage can be achieved simultaneously.
[0063]
(Embodiment 4)
In the fourth embodiment, the configuration of the embedded region 4 in the first embodiment is also changed. FIG. 10 shows a cross-sectional view of the main part of the fourth embodiment. A trench 9 is provided in a portion where the buried region 4 and the source electrode 11 are in contact with each other, and this is buried with at least one conductive charge 10 of polysilicon and metal. As a result, it is possible to reduce the resistance when discharging positive charges from the buried region 4 to the source electrode 11, and the switching speed can be further increased.
[0064]
The semiconductor device manufacturing method of the fourth embodiment is performed in the same manner as the manufacturing method of the first embodiment up to FIG. 4C, after the mask 33 is removed, a mask is formed that opens the center of the p + -type region 23 on both sides of the unit cell, and a trench is formed by RIE or the like using this mask. Embedded with polysilicon. Thereafter, by performing the steps after FIG. 4D, the semiconductor device of FIG. 10 can be obtained.
[0065]
With such a structure, the effects described in the first embodiment can be similarly achieved, and the switching speed can be further improved.
[0066]
(Embodiment 5)
FIG. 11 is a perspective view of an electrostatic induction semiconductor device according to the fifth embodiment. In order to facilitate understanding, the same parts as those in the first to fourth embodiments are denoted by the same reference numerals. The electrostatic induction semiconductor device of Embodiment 5 is formed on the upper surface portion of the n-type semiconductor substrate 1 with p. ⁺ Mold embedding region 4 and p ⁺ Type gate region (first semiconductor region) 2 and n ⁺ Type source region (second semiconductor region) 3. The source region 3 is arranged so as to be sandwiched between the gate regions 2, the gate region 2 is provided deeper than the source region 3, and the p region is more than the gate region 2. ⁺ The mold embedding region 4 is deeply provided.
[0067]
On the other hand, n below the semiconductor substrate 1 ⁺ Type drain region (third semiconductor region) 5 and p ⁺ The space between the mold buried region 4 and the drain region 5 is n ⁻ The type drift layer 6 is formed.
[0068]
p ⁺ At least a part of the mold embedding region 4 is connected to the source electrode 11, and the portion facing the drain region 5 is wider than the portion connecting to the source electrode 11. P ⁺ At least a part of the portion of the type buried region 4 facing the drain region 5 is opened (an n-type or i-type region other than p-type is provided), and electrons from the source electrode 11 are transferred to the drift layer 6. To flow.
[0069]
FIG. 12 is a top view showing the electrode structure, which is the same as in the first to fourth embodiments. A cross-sectional view taken along the line CC 'in FIG. 11 or 12 is shown in FIG. 13, and a cross-sectional view taken along the line DD' is shown in FIG.
[0070]
As is clear from FIG. 13 or FIG. ⁺ Type source region, n ⁻ P on both sides of the channel region 7 ⁺ P-type gate region 2 is sandwiched between p ⁺ P at a position deeper than the type gate region 2 ⁺ The mold embedding area extends horizontally and n ⁺ Type source region and p ⁺ A part of the mold embedding region is in contact with the source electrode 11. p ⁺ A gate electrode 12 is formed on the mold gate region 2.
[0071]
In Example 5, p ⁺ The mold buried region 4 is provided as a horizontal buried layer at a position deeper than the gate region 2, and the contact with the source electrode 11 may be made at least at one place. Therefore, the mounting density in the semiconductor device can be improved as compared with the first embodiment, and the size can be further reduced.
[0072]
P ⁺ Since the opening is provided in the buried layer portion of the mold buried region 4 so as to include a line that vertically connects the gate region 2 and the drain region 5, the channel region 7 can be reliably connected to the drift region 6. .
[0073]
The operation of the fifth embodiment is the same as that of the first embodiment, and the same effect as that of the first embodiment can be obtained. Similarly to the fourth embodiment, a trench may be provided in a portion where the buried region 4 and the source electrode 11 are in contact, and the trench may be buried with a conductive filler such as polysilicon or metal. By doing so, it becomes possible to reduce the resistance when discharging positive charges from the buried region 4, and the switching can be further speeded up.
[0074]
Next, a method for manufacturing the semiconductor device of Embodiment 5 will be described. In FIG. 11, a unit cell (indicated by UC2) including a contact portion to the source electrode 11 in the buried region 4 will be described step by step.
[0075]
Initially, the manufacturing method of the cross-section part along DD 'line is described. First, as shown in FIG. 15A, n having a thickness of 10 μm is used. ⁻ Type SiC layer 21 (impurity concentration 1 × 10 ¹⁵ ~ 1x10 ¹⁷ cm ^-3 Is prepared on the surface, and a mask 22 for ion implantation having a width of 4 μm is formed after cleaning. Using this mask 22, a p-type impurity (Al or B) is implanted into the upper surface of the SiC layer 21 with an acceleration voltage of several keV to several MeV to a depth of 2 μm to obtain an impurity concentration of 1 × 10. ²⁰ ~ 1x10 ²¹ cm ^-3 P with ⁺ A mold region 23 is formed. p ⁺ The width of the mold region 23 is 7 μm in the contact region (however, since only one side portion is displayed, it is 14 μm as a whole), and is 8 μm in the region other than the contact region.
[0076]
Next, as shown in FIG. 15B, after removing the mask layer 22, n SiC is formed on the SiC layer 21. ⁻ Type SiC layer 25 (impurity concentration 1 × 10 ¹⁵ ~ 1x10 ¹⁷ cm ^-3 ) Is epitaxially grown to a thickness of 4 μm. N, P or the like is used as the n-type impurity. In addition, since this SiC layer 25 is integrated with the SiC layer 21, the reference numeral 21 is used hereinafter.
[0077]
Next, as shown in FIG. 15C, an ion implantation mask 27 is formed, and an exposed portion of 2 μm is provided in a portion of the buried layer 4 where the contact is to be formed. In the figure, only half of the contact is shown, so the contact width is 4 μm.
[0078]
Next, as shown in FIG. 15C, p-type impurities (Al or B) are ion-implanted at a depth of 4 μm with an acceleration voltage of several keV to several MeV using a mask 27, and p ⁺ P connected to mold region 23 ⁺ Mold region 28 (impurity concentration 1 × 10 ²⁰ ~ 1x10 ²¹ cm ^-3 ). This p ⁺ The mold region 28 is p ⁺ Since it is integrated with the mold region 23, it will be denoted by reference numeral 23 hereinafter. p ⁺ The mold region 23 becomes the buried region 4 in FIG.
[0079]
Next, as shown in FIG. 15D, after the mask 27 is removed, a new ion implantation mask 29 is formed. The mask 29 has an opening having a width of 10 μm for forming a gate region. Using this mask 29, p-type impurities (Al or B) are ion-implanted at a depth of 2 μm at an acceleration voltage of several keV to several MeV, and p ⁺ Mold region 31 (impurity concentration 1 × 10 ²⁰ ~ 1x10 ²¹ cm ^-3 ). This p ⁺ The mold region 31 becomes the gate region 2 in FIG.
[0080]
Next, as shown in FIG. ⁺ An ion implantation mask 33 is formed so as to cover the mold regions 23 and 31, and n-type impurities (N or P) are ion-implanted with an acceleration voltage of several keV to several hundred keV, and n ⁺ Mold region 35 (impurity concentration 1 × 10 ²⁰ ~ 1x10 ²¹ cm ^-3 ). This n ⁺ The mold region 35 becomes the source region 3 in FIG.
[0081]
Next, as shown in FIG. ⁺ Type region 35 and p ⁺ An insulating film 37 having a width of 4 μm is provided on the boundary of the mold region 31, and the source electrode 11 and the gate electrode 12 are formed of a metal such as Ni, Co, Al, Ti or the like. The insulating film 37 is provided so that the source electrode 11 and the gate electrode 12 are not short-circuited. The source electrode 11 is p ⁺ It is provided so as to overlap the mold region 23. After forming the source electrode 11 and the gate electrode 12, heat treatment is performed to reduce the contact resistance.
[0082]
Next, a method of forming a cross section along the line CC ′ in FIG. 11 will be described with reference to FIG. FIG. 17A is a process corresponding to FIG. ⁺ The mold region 23 is formed continuously, and the points are different. Thereafter, the same steps as in FIGS. 15B to 16A are performed, and finally the shape of FIG. 17B is completed. Needless to say, the processes of the section CC ′ and the section DD ′ proceed simultaneously.
[0083]
Also in the fifth embodiment, n ⁻ P with mold layer on the surface ⁺ By using a type semiconductor substrate, an electrostatic induction thyristor can be obtained.
[0084]
(Embodiment 6)
The sixth embodiment is a modification of the fifth embodiment, and relates to the arrangement direction of the gate region 2 and the source region 3, and the form of the second embodiment (the arrangement direction of the gate region 2 and the source region 3 is changed by 90 degrees from the first embodiment). Is a combination. FIG. 18 is a perspective view of a semiconductor device according to the sixth embodiment. FIG. 19 is a top view showing the electrode structure, which is the same as in the first to fifth embodiments. A sectional view taken along the line EE ′ of FIG. 18 or FIG. 19 is shown in FIG. 20, and a sectional view taken along the line FF ′ is shown in FIG. Since the semiconductor device manufacturing method of the present embodiment may be carried out in the same manner as in FIGS.
[0085]
By configuring as described above, the same effects as those of the fifth embodiment can be achieved, and further downsizing can be realized as compared with the fifth embodiment. Similarly to the fourth embodiment, a trench may be provided in a portion where the buried region 4 is in contact with the source electrode 11, and the trench may be buried with a conductive filler such as polysilicon or metal. By doing so, the resistance at the time of discharging positive charges from the buried region 4 is lowered, and the switching can be further speeded up.
[0086]
(Embodiment 7)
The seventh embodiment is an embodiment in which the configuration of the electrostatic induction semiconductor device described so far is configured in a horizontal shape, and FIG. 22 is a top view showing the configuration of the main part thereof. The electrostatic induction semiconductor device of this embodiment is n ⁻ P juxtaposed on the upper surface portion of the high resistance semiconductor layer of the mold ⁺ Type gate region (first semiconductor region) 2 and n ⁺ Type source region (second semiconductor region) 3 and p ⁺ Mold intervening region 4 and n ⁺ A type drain region (third semiconductor region) 5 is provided.
[0087]
The source region 3 is formed so as to be sandwiched between the intervening region 4 and the gate region 2. The gate region 2 is closer to the drain region 5 than the source region 3, and the intervening region 4 is further drained than the gate region 2. It is provided near 5.
[0088]
Further, the intervening region 4 has a substantially T-shaped shape, and the portion closer to the drain region 5 is wider than the portion contacting the source region electrode 3. The space between the intervening region 4 and the drain region 5 is n ⁻ It is a type drift layer.
[0089]
The space between the adjacent distal end portions of the intervening region 4 (the portion facing the drain region 5) is set to a position including a line that connects the gate region 2 and the drain region 5 vertically. Further, the portion where the intervening region 4 extends in parallel to the drain region 5 is disposed so as to block at least a part of the line that connects the source region 3 and the drain region 5 vertically.
[0090]
In addition, in the intervening region 4, it is sufficient that the drain region 5 side has a wider width than the portion in contact with the source region 3. In addition to the above T shape, for example, as shown in FIG. May be formed in a trapezoidal shape. In this case, the source region 3 is preferably triangular.
[0091]
24 is a cross-sectional view taken along the line GG ′ of FIG. 22 or FIG. ⁻ P on the upper surface of the type semiconductor substrate 1 ⁺ Type gate region 2, n ⁺ Type source region 3, p ⁺ A mold intervening region is formed. p ⁺ N at the bottom of the gate region 2 of the mold ⁻ The mold layer 15 is provided and p ⁺ The gate region 4 of the mold is electrically separated.
[0092]
The method for manufacturing the semiconductor device of this embodiment is, for example, p. ⁻ N on the mold substrate ⁻ Each region may be formed by ion implantation or the like after epitaxially growing the mold layer. By repeating the process of epitaxial growth and each region creation (ion implantation) a plurality of times, an element having a thickness in the vertical direction can be formed. Or you may make it form said each area | region formed in a surface part in the semiconductor layer (for example, SOI layer) on an insulating film.
[0093]
In the semiconductor device of this embodiment, for example, when the width of the source region 3 is 2 μm, the closest distance between adjacent intervening regions 4 may be 4 μm (see FIGS. 22 and 23). The dimensions of the other element regions may be obtained by replacing the dimensions in the cross-sectional view of the first embodiment with a plan view. For example, the width of the gate region 2 is 10 μm, and the portion of the intervening region 4 facing the drain region 5 The width may be 12 μm or the like.
[0094]
22 and 23, the source electrode, the gate electrode, and the drain electrode are not shown. However, as shown in FIG. 24, the source electrode 11 is the source region 3 and the intervening region 4, and the gate electrode 12 is the gate region 2. The drain electrodes (not shown) may be formed so as to be in contact with the drain region 5 and to maintain insulation.
[0095]
A planar arrangement example (for one unit cell) of the source electrode 11 and the gate electrode 12 is shown in FIG. In FIG. 25, an insulating film is not shown, but an insulating film is interposed between the electrodes. In the first, second, fifth, and sixth embodiments, the example in which the source electrode 11 is formed in all the surface regions of the buried region 4 is shown. However, as shown in FIG. 25, the buried region (intervening region) 4 is formed. The source electrode 11 may be formed only in a portion in contact with the source region 3.
[0096]
Even with the above horizontal configuration, the effects described in the first embodiment can be similarly obtained. That is, p ⁺ The mold intervening region is T-shaped or trapezoidal, and n ⁺ Since the area near the type drain region is formed large, the above-mentioned discharge or charge current sharing can be more effectively executed. Further, when the drift region is depleted due to turn-off, electric field concentration at the end of the intervening region is suppressed and the breakdown voltage is improved.
[0097]
In addition, p which determines on-resistance ⁺ Type gate region and p ⁺ P that determines the interval between the mold intervening regions and the breakdown voltage ⁺ The interval between the mold intervening regions can be determined independently. That is, p ⁺ Type gate region and p ⁺ After determining the spacing of the mold intervening regions, p ⁺ The distance between the mold intervening regions can be freely determined by adjusting the length of the T-shaped horizontal portion or the length of the long side of the trapezoid. Thus, by setting the two intervals freely, both low on-resistance and high breakdown voltage can be achieved simultaneously.
[0098]
Also in the seventh embodiment, n ⁺ P type drain region 5 ⁺ By changing to a mold region, an electrostatic induction thyristor can be obtained.
[0099]
(Embodiment 8)
FIG. 26 is a schematic perspective view (partially perspective view) of the semiconductor device according to the eighth embodiment. This embodiment is also an example in which the electrostatic induction semiconductor device is formed in a horizontal shape. However, unlike Example 7, the n is provided on the substrate 1 ′ via the insulating film 16. ⁻ P-type high resistance semiconductor layer ⁺ Type gate region (first semiconductor region) 2 and n ⁺ Type source region (second semiconductor region) 3 and n ⁺ Type drain region (third semiconductor region) 5 and a T-shaped p ⁺ A mold intervening region 4 is provided between the gate region 2 and the drain region 5. A drift layer 6 is formed between the intervening region 4 and the drain layer 5. This configuration is substantially the same as the horizontal configuration of the configuration of the second embodiment.
[0100]
In the above configuration, n ⁺ Type source region 3 is p ⁺ N-type gate region 2 and n ⁺ N more than the type source region 3 ⁺ N type gate region 2 is n ⁺ Near the drain region 5 and p ⁺ P than the type gate region 2 ⁺ The T-shaped horizontal bar portion of the mold interposition region 4 is n ⁺ It is provided so as to be close to the type drain region 5.
[0101]
At least a part of the vertical bar portion of the T-shaped intervening region is n ⁺ A portion facing the drain region 5 is wider than a portion in contact with the source region 3 and in contact with the source region 3. In addition, at least a part of the buried layer of the T-hour type horizontal bar portion is opened (a non-p-type region is provided), and electrons from the source electrode 3 flow to the drift layer 6. Yes.
[0102]
The opening is set at a position including a line that connects the gate region 2 and the drain region 5 vertically. Further, the portion of the intervening region 4 where the opening is not provided in the T-shaped horizontal bar portion is disposed so as to block at least a part of the line that connects the source region 3 and the drain region 5 vertically.
[0103]
26, the source electrode, the gate electrode, and the drain electrode are not shown. However, as shown in the top view of FIG. 27, the source electrode 11 is in contact with the source region 3 and the intervening region 4, and the gate electrode 12 is The gate region 2 and the drain electrode 13 are in contact with the drain region 5, respectively, and each is insulated by an insulating film (not shown).
[0104]
In the present embodiment, each region for forming an element is provided on the insulating layer 16, but as in the seventh embodiment, p ⁻ Each of the above regions is formed on the upper surface of the type semiconductor substrate, and p ⁺ N at the bottom of the gate region ⁻ A mold layer may be inserted to electrically isolate the p-type region. When SiC is used for the semiconductor layer in the element formation region, the dimensions of the cross-sectional shape of the third embodiment (FIG. 11) can be replaced with the dimensions of the plan view.
[0105]
Even in the above configuration, the effects described in the third embodiment can be similarly achieved. That is, p ⁺ The mold intervening region is T-shaped and n ⁺ Since the area near the type drain region is formed large, the above-mentioned discharge or charge current sharing can be more effectively executed. Further, since the intervening region is formed continuously, the breakdown voltage is improved without causing electric field concentration at the end of the intervening region when the drift region is depleted by turn-off.
[0106]
In addition, p which determines on-resistance ⁺ Type gate region and p ⁺ Since the distance between the mold intervening regions can be determined independently without considering the breakdown voltage, both low on-resistance and high breakdown voltage can be achieved simultaneously.
[0107]
Also in the eighth embodiment, n ⁺ P type drain region 5 ⁺ By changing to a mold region, an electrostatic induction thyristor can be obtained.
[0108]
As mentioned above, although the structure which implement | achieves a desired withstand pressure | voltage without raising ON resistance was demonstrated through Embodiment 1-8, the effect is demonstrated through an actual model. FIG. 28 shows a conventional electrostatic induction semiconductor device having a cathode region 100 together with a gate region 102 and a source region 103 on the upper surface of a semiconductor substrate 101. When the width of the source region 103 is 2 μm and the width of the gate region is 4 μm (the margin is 1 μm to the left and right according to the gate electrode width of 2 μm), the distance between the cathodes is 8 μm. When this is applied to the graph of FIG. 30B described above, the withstand voltage is about 3.9 kV.
[0109]
On the other hand, when the model shown in FIG. 29 is considered as a representative example of the present invention, if the minimum width of the channel region is 2 μm as shown, the distance between the buried regions 4 is the sum of the left and right channel widths. Since it is considered that the above is sufficient, 4 μm is sufficient. When this is applied to the graph of FIG. 30, it can be seen that the breakdown voltage can be improved to about 4.6 kV.
[0110]
(Application examples)
In general, an inverter circuit forms a circuit by connecting one switching element and one rectifying element in parallel. However, in the switching element according to the present invention, the region having conductivity opposite to that of the drain region is in contact with the source electrode, so that when the source potential is raised above the drain potential with the gate turned off, Current flows through However, no current flows if the source potential is lowered below the drain potential with the gate turned off. By utilizing this property, as shown in FIG. 31, an inverter circuit can be assembled by using the semiconductor device 20 of the present invention as a switching element without preparing a new rectifying element. The number of elements can be reduced by half, and the inverter circuit can be made smaller, more reliable, and less expensive.
[0111]
The present invention is not limited to the embodiment described above. For example, the p-type and the n-type are reversed, which can be considered as another embodiment. In the above embodiment, the substrate is also exemplified by SiC, but other semiconductors such as Si can be used. The impurity concentration and the dimensions of each region at that time are values determined in consideration of electrical characteristics such as breakdown voltage and on-resistance.
[0112]
In the above embodiment, a unipolar electrostatic induction semiconductor is taken as an example. As described above, a bipolar electrostatic induction semiconductor is provided by providing a conductive region opposite to the drain region on the drain region side of the drift layer. can do.
[0113]
Further, the p-type region and the n-type region can be formed by a combination of ion implantation and epitaxial growth, and any means can be used.
[0114]
Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine the component covering different embodiment suitably.
[0115]
【The invention's effect】
A semiconductor device of the present invention includes a drain region (third semiconductor region) on the surface of a substrate, a gate region (first semiconductor region), a source region (second semiconductor region), a gate region opposite to the drain region (third semiconductor region). It has a buried (intervening) region having the same conductivity type and electrically connected to the source region. The buried (intervening) region has a larger width on the side facing the drain region than on the side in contact with the source region. For this reason, when the drift region is depleted by turn-off, electric field concentration at the end of the buried (intervening) region is suppressed, and the breakdown voltage is improved. At the same time, since the buried (intervening) region shares the discharge of positive charges to the source electrode when the drift region is depleted, the gate drive power can be reduced.
[0116]
Since the distance between the gate region and the embedded (intervening) region that determines the on-resistance at turn-on and the distance between the embedded (intervening) region that determines the breakdown voltage at the turn-off can be determined independently, the optimum conditions can be determined. The degree of freedom increases.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.
FIG. 2 is a top view of the semiconductor device according to the first embodiment.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment.
4 is a cross-sectional view of a semiconductor device illustrating a process following FIG. 3;
FIG. 5 is a perspective view of a semiconductor device according to a second embodiment.
FIG. 6 is a top view of a semiconductor device according to a second embodiment.
FIG. 7 is a cross-sectional view illustrating a manufacturing process of the semiconductor device of the second embodiment.
FIG. 8 is a cross-sectional view illustrating a manufacturing process of the semiconductor device of the second embodiment.
FIG. 9 is a cross-sectional view of a semiconductor device according to a third embodiment.
FIG. 10 is a perspective view of a semiconductor device according to a fourth embodiment.
FIG. 11 is a perspective view of a semiconductor device according to a fifth embodiment.
FIG. 12 is a top view of a semiconductor device according to a fifth embodiment.
FIG. 13 is a cross-sectional view of a semiconductor device according to a fifth embodiment.
FIG. 14 is another cross-sectional view of the semiconductor device according to the fifth embodiment.
FIG. 15 is a cross-sectional view illustrating a manufacturing step of the semiconductor device of the fifth embodiment.
16 is a cross-sectional view of a semiconductor device, illustrating a step following the step in FIG. 15;
FIG. 17 is another cross-sectional view illustrating the manufacturing process of the semiconductor device of the fifth embodiment.
FIG. 18 is a perspective view of a semiconductor device according to a sixth embodiment.
FIG. 19 is a top view of a semiconductor device according to a sixth embodiment.
FIG. 20 is a cross-sectional view of a semiconductor device according to a sixth embodiment.
FIG. 21 is another cross-sectional view of the semiconductor device according to the sixth embodiment.
FIG. 22 is a plan view of a semiconductor device according to a seventh embodiment.
FIG. 23 is a plan view of a semiconductor device according to a modification of the seventh embodiment.
FIG. 24 is a cross-sectional view of a semiconductor device according to a seventh embodiment.
FIG. 25 is a partial top view showing an electrode configuration of a semiconductor device according to a seventh embodiment.
FIG. 26 is a perspective view of a semiconductor device according to an eighth embodiment.
FIG. 27 is a top view of a semiconductor device according to an eighth embodiment.
FIG. 28 is a cross-sectional view of a conventional electrostatic induction semiconductor device.
FIG. 29 is a cross-sectional view illustrating a model representing a semiconductor device of the present invention.
30 is a diagram for explaining a relationship between a gate-to-gate distance and a withstand voltage cited from Non-Patent Document 2. FIG.
FIG. 31 is a circuit diagram showing an application example of a semiconductor device of the invention.
[Explanation of symbols]
1 ... Semiconductor substrate
2 ... Gate area
3 ... Source area
4 ... Embedded region, intervening region
5 ... Drain region
6 ... Drift region
7 Channel region
8 ... Insulating film
11 ... Source electrode
12 ... Gate electrode
13 ... Drain electrode
15 ... n ⁻ Type semiconductor layer
16 ... Insulating film
20 ... Semiconductor device

Claims (5)

A semiconductor substrate having first and second main surfaces;
A high-resistance semiconductor layer of a first conductivity type formed on the first main surface of the semiconductor substrate;
A second conductivity type first semiconductor region provided on a surface of the first conductivity type high-resistance semiconductor layer;
A first conductivity type second semiconductor region formed so as to sandwich the first semiconductor region on the surface of the first conductivity type high-resistance semiconductor layer and formed shallower than the first semiconductor region; ,
A buried portion buried in the high-resistance semiconductor layer between the first and second semiconductor regions and the semiconductor substrate and spaced apart from the first and second semiconductor regions; and connected to the buried portion And a second conductivity type buried region having a contact portion that is narrower than the buried portion led to the surface of the high resistance semiconductor layer, and is sandwiched between the first semiconductor region and the semiconductor substrate. A semiconductor device, wherein a current path between the second semiconductor region and the semiconductor substrate is formed in the high resistance layer through the region. A semiconductor substrate;
A first conductivity type high-resistance semiconductor layer formed on an upper surface of the semiconductor substrate;
A first semiconductor region of a second conductivity type formed on the upper surface of the high-resistance semiconductor layer;
A second semiconductor region of a first conductivity type formed on an upper surface of the high-resistance semiconductor layer so as to sandwich the first semiconductor region, and formed shallower than the first semiconductor region;
A portion that further sandwiches the first semiconductor region and the second semiconductor region sandwiching the first semiconductor region from the outside thereof, in a horizontal direction toward the lower side of the first semiconductor region at a position deeper than the first semiconductor region. A buried region of a second conductivity type in which the longitudinal section having the overhanging portion is an inverted T-shaped or trapezoidal shape;
A drift region of a first conductivity type sandwiched between the horizontal protruding portion of the buried region and the semiconductor substrate and formed in the high-resistance semiconductor layer;
A channel region formed in the high resistance semiconductor layer sandwiched between the first semiconductor region and the buried region, and leading to the drift region;
A first electrode formed on the first semiconductor region;
A second electrode formed to connect the second semiconductor region and the portion of the buried region sandwiching the second semiconductor region from the outside;
A third electrode formed on the lower surface of the semiconductor substrate;
A semiconductor device comprising: A semiconductor substrate;
A high-resistance semiconductor layer formed on the upper surface of the semiconductor substrate;
A second semiconductor region of a first conductivity type formed on the upper surface of the high-resistance semiconductor layer;
A second conductivity type first semiconductor region formed on an upper surface of the high-resistance semiconductor layer so as to sandwich the second semiconductor region, and formed deeper than the second semiconductor region;
Formed in the high-resistance semiconductor layer deeper than the first semiconductor region so as to face the semiconductor substrate, and having an opening in a region sandwiched between the first semiconductor region and the semiconductor substrate A buried portion of a second conductivity type having a buried portion formed and a contact portion exposed on the upper surface of the high-resistance semiconductor layer;
A drift region of a first conductivity type formed in the high resistance layer sandwiched between the buried region and the semiconductor substrate;
A channel region sandwiched between the first semiconductor regions and leading to the drift region through the opening of the buried region;
A first electrode formed on the first semiconductor region;
A second electrode formed to connect to the contact portion of the second semiconductor region and the buried region;
A third electrode formed on the lower surface of the semiconductor substrate;
A semiconductor device comprising: A first conductivity type high-resistance semiconductor layer;
A third semiconductor region having a stripe-like planar shape formed on the surface of the high-resistance semiconductor layer;
A first semiconductor region of a second conductivity type provided on the surface of the high-resistance semiconductor layer so as to face a side surface of the striped third semiconductor region;
A distance between the first semiconductor region and the third semiconductor region is formed on the surface of the high-resistance semiconductor layer so as to sandwich the first semiconductor region, and a distance from the third semiconductor region is greater than a distance between the first semiconductor region and the third semiconductor region. A second semiconductor region of the first conductivity type provided to be large;
A planar shape having a portion sandwiching the first semiconductor region and the second semiconductor region sandwiching the first semiconductor region from the outside, and having an overhanging portion wider than this portion is a T-shaped or trapezoidal second shape. A conductive type intervening region;
A drift region of a first conductivity type sandwiched between the protruding portion of the intervening region and the third semiconductor region and formed in the high-resistance semiconductor layer;
A channel region formed in the high-resistance semiconductor layer sandwiched between the first semiconductor region and the intervening region, and leading to the drift region;
A first electrode formed on the first semiconductor region;
A second electrode formed so as to connect to the second semiconductor region and the intervening region;
A third electrode formed on the third semiconductor region;
A semiconductor device comprising: A first conductivity type high-resistance semiconductor layer;
A third semiconductor region having a stripe-like planar shape formed on the surface of the high-resistance semiconductor layer;
A second semiconductor region of a first conductivity type provided on the surface of the high-resistance semiconductor layer so as to face a side surface of the striped third semiconductor region;
A distance between the second semiconductor region and the third semiconductor layer is formed on the surface of the high-resistance semiconductor layer so as to sandwich the second semiconductor region, and a distance between the second semiconductor region and the third semiconductor layer is larger A first semiconductor region of a second conductivity type formed to be small;
Formed on the surface of the high-resistance semiconductor layer between the first and second semiconductor regions and the third semiconductor region so as to face the third semiconductor region; and A second conductivity type intervening region having an intervening portion having a communication port facing the third semiconductor region, and an extending portion connected to the intervening portion and extending in the direction of the second semiconductor region;
A drift region of a first conductivity type formed in the high resistance semiconductor layer sandwiched between the intervening portion of the intervening region and the third semiconductor region;
A channel region surrounded on three sides by the first and second semiconductor regions and the intervening region and leading to the drift region through the communication port;
A first electrode formed on the first semiconductor region;
A second electrode formed to connect to the second semiconductor region and the intervening region;
A third electrode formed on the third semiconductor region;
A semiconductor device comprising:

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