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JP2005064187A - Semiconductor mounting board - Google Patents

Semiconductor mounting board Download PDF

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Publication number
JP2005064187A
JP2005064187A JP2003291542A JP2003291542A JP2005064187A JP 2005064187 A JP2005064187 A JP 2005064187A JP 2003291542 A JP2003291542 A JP 2003291542A JP 2003291542 A JP2003291542 A JP 2003291542A JP 2005064187 A JP2005064187 A JP 2005064187A
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bond pad
pad portion
wire bond
wire
chip component
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Satoshi Oe
聡 大江
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Wire Bonding (AREA)

Abstract

【課題】 半田の濡れ性が悪く、金ワイヤとの接合強度が向上されたワイヤボンドパッド部を備える半導体実装基板を提供する
【解決手段】 金ワイヤ１２を接合するために実装基板４に形成されたワイヤボンドパッド部４ｄは、結晶化されたアルミニウムによって構成されている。ワイヤボンドパッド部４ｄは、アルミニウムを含むので半田の濡れ性が悪く、チップ部品６を接合するための半田の飛散が防止されている。また、ワイヤボンドパッド部４ｄは、結晶化されたアルミニウムによって構成されているので、表面が平坦かつ、不純物の混入が少ない。さらに、ワイヤボンドパッド部４ｄはＡｕが拡散しやすいので、金ワイヤ１２が強い強度で接合される。
【選択図】 図２

PROBLEM TO BE SOLVED: To provide a semiconductor mounting substrate provided with a wire bond pad portion with poor solder wettability and improved bonding strength with a gold wire, formed on a mounting substrate 4 for bonding a gold wire 12. The wire bond pad portion 4d is made of crystallized aluminum. Since the wire bond pad portion 4d contains aluminum, the solder wettability is poor, and the solder for joining the chip component 6 is prevented from being scattered. Further, since the wire bond pad portion 4d is made of crystallized aluminum, the surface is flat and impurities are hardly mixed. Further, since the Au is easily diffused in the wire bond pad portion 4d, the gold wire 12 is bonded with high strength.
[Selection] Figure 2

Description

本発明は、半導体実装基板に関するものである。   The present invention relates to a semiconductor mounting substrate.

セラミックス製の基板と、基板に形成されチップ部品が実装されるチップ部品搭載部と、基板に形成され半導体素子とワイヤによって電気的に接続されるワイヤボンドパッド部とを備える半導体実装基板がある。ここで、半導体素子の配線はＡｕによって構成されているので、上記のワイヤには金ワイヤが用いられている。また、上記の半導体実装基板では、チップ部品搭載部にチップ部品を接合するための半田がワイヤボンドパッド部に飛散し、ボンディング強度が低下することを防止するために、ワイヤボンドパッド部には半田の濡れ性が悪いアルミが用いられている。
特開２００１−３２０１３９号公報 There is a semiconductor mounting substrate that includes a ceramic substrate, a chip component mounting portion that is formed on the substrate and on which a chip component is mounted, and a wire bond pad portion that is formed on the substrate and is electrically connected to the semiconductor element by a wire. Here, since the wiring of the semiconductor element is made of Au, a gold wire is used as the wire. Further, in the above semiconductor mounting substrate, the solder for bonding the chip component to the chip component mounting portion is scattered on the wire bond pad portion, and the bonding strength is reduced. Aluminum with poor wettability is used.
JP 2001-320139 A

しかしながら、上述した従来の半導体実装基板では、ワイヤボンドパッド部を構成するアルミは、アルミ箔を展開して形成されることが一般的であり、その表面の凹凸が大きく、ワイヤボンドパッド部への金ワイヤの接合強度が低いという問題点を有していた。   However, in the above-described conventional semiconductor mounting substrate, the aluminum constituting the wire bond pad portion is generally formed by developing an aluminum foil, and the surface has large unevenness, and the wire bond pad portion is There was a problem that the bonding strength of the gold wire was low.

本発明は上記問題点を解決するためになされたもので、半田の濡れ性が悪く、金ワイヤとの接合強度が向上されたワイヤボンドパッド部を備える半導体実装基板を提供することを課題としている。   The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor mounting substrate having a wire bond pad portion with poor solder wettability and improved bonding strength with a gold wire. .

上記課題を解決するため、本発明の半導体実装基板は、基板と、基板に形成され表層にＡｕを含みチップ部品が半田接合されるチップ部品搭載部と、基板に形成され金ワイヤと接合されるワイヤボンドパッド部とを備え、ワイヤボンドパッド部は結晶化されたアルミを含むことを特徴としている。   In order to solve the above problems, a semiconductor mounting substrate according to the present invention includes a substrate, a chip component mounting portion formed on the substrate and including Au on the surface layer and soldered to the chip component, and formed on the substrate and bonded to the gold wire. A wire bond pad portion, and the wire bond pad portion includes crystallized aluminum.

この発明によれば、ワイヤボンドパッド部は結晶化されたアルミニウムを含むので、その表面がアルミ箔を用いて形成されたワイヤボンドパッド部よりも平坦化される。また、ワイヤボンドパッド部への不純物の混入が抑制される。さらに、かかるワイヤボンドパッド部にはＡｕが拡散し易い。   According to the present invention, since the wire bond pad portion contains crystallized aluminum, the surface thereof is planarized more than the wire bond pad portion formed using the aluminum foil. In addition, contamination of impurities into the wire bond pad portion is suppressed. Furthermore, Au is likely to diffuse into the wire bond pad portion.

本発明によれば、ワイヤボンドパッド部はアルミニウムを含むので、半田の濡れ性が悪い。また、このワイヤボンドパッド部は結晶化されたアルミニウムによって構成されているので、アルミ箔を用いて形成されたものに比して平坦な表面とされ、不純物の混入が抑制され、Ａｕの拡散が生じやすくされている。したがって、金ワイヤとの接合強度が向上されたワイヤボンドパッド部を備える半導体実装基板が提供される。   According to the present invention, since the wire bond pad portion contains aluminum, the wettability of the solder is poor. In addition, since the wire bond pad portion is made of crystallized aluminum, it has a flat surface as compared with that formed using aluminum foil, the contamination of impurities is suppressed, and the diffusion of Au is suppressed. It is easy to occur. Therefore, a semiconductor mounting substrate provided with a wire bond pad portion with improved bonding strength with a gold wire is provided.

以下、図面を参照して本発明の好適な実施形態について詳細に説明する。なお、各図面において同一又は相当の部分に対しては同一の符号を附すこととする。図１は、本発明の実施形態にかかる半導体モジュール１の平面図である。また、図２は、図１のII−II線断面図である。   DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals. FIG. 1 is a plan view of a semiconductor module 1 according to an embodiment of the present invention. 2 is a cross-sectional view taken along line II-II in FIG.

図１及び図２に示すように、半導体モジュール１は、ベース基板２、実装基板４、チップ部品６、及び半導体素子８を備える。   As shown in FIGS. 1 and 2, the semiconductor module 1 includes a base substrate 2, a mounting substrate 4, a chip component 6, and a semiconductor element 8.

ベース基板２は、例えばＣｕ，ＣｕＷといった金属製の材料からなる。ベース基板２には、実装基板４と半導体素子８とが搭載されている。本実施形態では、半導体素子８は、ＦＥＴである。半導体素子８は、ＡｕＳｎといった半田によってベース基板２に接合されている。   The base substrate 2 is made of a metal material such as Cu or CuW. A mounting substrate 4 and a semiconductor element 8 are mounted on the base substrate 2. In the present embodiment, the semiconductor element 8 is an FET. The semiconductor element 8 is joined to the base substrate 2 by solder such as AuSn.

実装基板４は、例えばＡｌ2Ｏ3といったセラミックスによって構成されている。実装基板４の主面４ａ上には、配線パターン４ｂ、チップ部品搭載部４ｃ、ワイヤボンドパッド部４ｄが形成されている。また、実装基板４には、ベース基板２に搭載された半導体素子８が収容される孔４ｅが設けられている。 The mounting substrate 4 is made of ceramics such as Al 2 O 3 , for example. On the main surface 4a of the mounting substrate 4, a wiring pattern 4b, a chip component mounting portion 4c, and a wire bond pad portion 4d are formed. In addition, the mounting substrate 4 is provided with a hole 4 e in which the semiconductor element 8 mounted on the base substrate 2 is accommodated.

本実施形態では、配線パターン４ｂは、主面４ａに設けられた第１層４ｆと、第１層４ｆ上に形成された第２層４ｇとを含んでいる。第１層４ｆは、例えば厚さ１０μｍのタングステン、或いはモリブデンといった高融点金属によって構成されている。第２層４ｇは、厚さ１０μｍのＣｕによって構成されている。   In the present embodiment, the wiring pattern 4b includes a first layer 4f provided on the main surface 4a and a second layer 4g formed on the first layer 4f. The first layer 4f is made of a refractory metal such as tungsten or molybdenum having a thickness of 10 μm, for example. The second layer 4g is made of Cu having a thickness of 10 μm.

チップ部品搭載部４ｃは、配線パターン４ｂの端部に形成されている。チップ部品搭載部４ｃは、例えば、第２層４ｇ上に形成された厚さ０．１μｍのＮｉ層４ｈ、及びＮｉ層４ｈ上に形成された厚さ１μｍのＡｕ層４ｉから構成されている。   The chip component mounting portion 4c is formed at the end of the wiring pattern 4b. The chip component mounting portion 4c includes, for example, a Ni layer 4h having a thickness of 0.1 μm formed on the second layer 4g and an Au layer 4i having a thickness of 1 μm formed on the Ni layer 4h.

チップ部品搭載部４ｃには、チップ部品６が搭載されている。チップ部品６は、ＡｇＳｎといった材料の半田１０によってチップ部品搭載部４ｃに接合されている。   A chip component 6 is mounted on the chip component mounting portion 4c. The chip component 6 is joined to the chip component mounting portion 4c by a solder 10 made of a material such as AgSn.

ワイヤボンドパッド部４ｄは、孔４ｅの周縁のうち対向する一対の縁に沿って設けられている。ワイヤボンドパッド部４ｄは、配線パターン４ｂの端部に電気的に接続されている。ワイヤボンドパッド部４ｄは、金ワイヤ１２によって、半導体素子８と電気的に接続されている。   The wire bond pad portion 4d is provided along a pair of opposing edges in the periphery of the hole 4e. The wire bond pad portion 4d is electrically connected to the end portion of the wiring pattern 4b. The wire bond pad portion 4 d is electrically connected to the semiconductor element 8 by the gold wire 12.

ワイヤボンドパッド部４ｄは、結晶化されたアルミニウムによって構成される。ワイヤボンドパッド部４ｄは、１％程度のＳｉを含んでも良い。   The wire bond pad portion 4d is made of crystallized aluminum. The wire bond pad portion 4d may contain about 1% Si.

ワイヤボンドパッド部４ｄは、１〜２μｍの厚さであることが好ましい。図３は、ワイヤボンドパッド部４ｄの厚さと、ワイヤボンドパッド部４ｄと金ワイヤ１２の接合強度の関係を示す図である。図３において、横軸がワイヤボンドパッド部４ｄの厚さを示し、縦軸が金ワイヤ１２のプル強度を示している。図３には、２５μｍ径の金ワイヤ１２をワイヤボンドパッド部４ｄに接合した場合の、金ワイヤ１２のプル強度を計測した結果が示されている。   The wire bond pad portion 4d is preferably 1 to 2 μm thick. FIG. 3 is a diagram showing the relationship between the thickness of the wire bond pad portion 4 d and the bonding strength between the wire bond pad portion 4 d and the gold wire 12. In FIG. 3, the horizontal axis indicates the thickness of the wire bond pad portion 4 d, and the vertical axis indicates the pull strength of the gold wire 12. FIG. 3 shows the result of measuring the pull strength of the gold wire 12 when the 25 μm diameter gold wire 12 is bonded to the wire bond pad portion 4d.

図３に示すように、ワイヤボンドパッド部４ｄに接合された金ワイヤ１２のプル強度は、ワイヤボンドパッド部４ｄの厚さに伴って増加する。このプル強度は４〔ｇ〕以上必要との観点から、ワイヤボンドパッド部４ｄの厚さは、１μｍ以上必要であることが導かれる。一方、ワイヤボンドパッド部４ｄの厚さに伴って製造コストは増加する。したがって、本実施形態では、製造コストの観点から、ワイヤボンドパッド部４ｄの厚さは、２．０μｍ以下とされている。   As shown in FIG. 3, the pull strength of the gold wire 12 bonded to the wire bond pad portion 4d increases with the thickness of the wire bond pad portion 4d. From the viewpoint that the pull strength is 4 [g] or more, it is derived that the thickness of the wire bond pad portion 4d is 1 μm or more. On the other hand, the manufacturing cost increases with the thickness of the wire bond pad portion 4d. Therefore, in the present embodiment, from the viewpoint of manufacturing cost, the thickness of the wire bond pad portion 4d is set to 2.0 μm or less.

図２に示すように、半導体モジュール１では、金ワイヤ１２が接合されたワイヤボンドパッド部４ｄが樹脂１４によって覆われ、この接合部分が保護されている。また、半導体モジュール１は、チップ部品搭載部４ｃ及びワイヤボンドパッド部４ｄを除いて、ソルダーレジスト１６によって、覆われている。   As shown in FIG. 2, in the semiconductor module 1, the wire bond pad portion 4 d to which the gold wire 12 is bonded is covered with the resin 14, and this bonded portion is protected. The semiconductor module 1 is covered with a solder resist 16 except for the chip component mounting part 4c and the wire bond pad part 4d.

かかる構成を有する半導体モジュール１では、ワイヤボンドパッド部４ｄがアルミニウムを含むので、半田の濡れ性が悪く、飛散して当該箇所に付着した半田の除去が容易である。また、ワイヤボンドパッド部４ｄが結晶化されたアルミニウムによって構成されているので、アルミ箔により形成された場合に比べてワイヤボンドパッド部４ｄの表面が平坦とされ、かつ、それ故に不純物の混入が少ない。更に、ワイヤボンドパッド部４ｄは、金ワイヤ１２のＡｕが拡散し易い。したがって、ワイヤボンドパッド部４ｄには、金ワイヤ１２が強い強度で接合される。また、ワイヤボンドパッド部４ｄの厚さは、１μｍ〜２μｍの範囲とされているので、金ワイヤ１２がより強い強度で接合されると共に、製造コストが抑えられている。   In the semiconductor module 1 having such a configuration, since the wire bond pad portion 4d contains aluminum, the wettability of the solder is poor, and it is easy to remove the solder that has scattered and adhered to the portion. In addition, since the wire bond pad portion 4d is made of crystallized aluminum, the surface of the wire bond pad portion 4d is made flat compared to the case where the wire bond pad portion 4d is formed of aluminum foil, and therefore impurities are not mixed therein. Few. Furthermore, Au of the gold wire 12 is easily diffused in the wire bond pad portion 4d. Therefore, the gold wire 12 is bonded to the wire bond pad portion 4d with high strength. In addition, since the thickness of the wire bond pad portion 4d is in the range of 1 μm to 2 μm, the gold wire 12 is bonded with stronger strength and the manufacturing cost is suppressed.

以下、半導体モジュール１の製造方法を説明する。図４（ａ）〜（ｈ）は、半導体モジュール１の製造工程を順に示す図である。半導体モジュール１を製造するために、まず、実装基板４となるアルミナグリーンシートに、タングステンを含むペーストが印刷された後、１５００℃以上で焼成されることによって、実装基板４に配線パターン４ｂの第１層４ｆが形成される。   Hereinafter, a method for manufacturing the semiconductor module 1 will be described. 4A to 4H are views showing the manufacturing process of the semiconductor module 1 in order. In order to manufacture the semiconductor module 1, first, a paste containing tungsten is printed on an alumina green sheet to be the mounting substrate 4, and then baked at 1500 ° C. or higher, whereby the wiring pattern 4 b is formed on the mounting substrate 4. One layer 4f is formed.

そして、Ｃｕ電解めっきによって第１層４ｆ上に第２層４ｆが形成されることによって、図４（ａ）に示すように実装基板４に配線パターン４ｂが形成された中間生産物２０が製造される。なお、実装基板４にＣｕペーストを印刷し、これを８００℃で焼成することによって、配線パターン４ｂを形成しても良い。   Then, by forming the second layer 4f on the first layer 4f by Cu electrolytic plating, the intermediate product 20 in which the wiring pattern 4b is formed on the mounting substrate 4 as shown in FIG. 4A is manufactured. The Alternatively, the wiring pattern 4b may be formed by printing a Cu paste on the mounting substrate 4 and baking it at 800 ° C.

次に、チップ部品搭載部４ｃに対応する位置が開口されたパターンのレジストマスク２２が中間生産物２０に設けられる。そして、Ｎｉ、Ａｕの順に電解または無電解めっきが施されることによって、図４（ｂ）に示すように実装基板４にチップ部品搭載部４ｃが形成された中間生産物２４が製造される。   Next, a resist mask 22 having a pattern opened at a position corresponding to the chip component mounting portion 4 c is provided on the intermediate product 20. Then, by performing electrolytic or electroless plating in the order of Ni and Au, an intermediate product 24 in which the chip component mounting portion 4c is formed on the mounting substrate 4 as shown in FIG. 4B is manufactured.

次いで、上記のレジストマスク２２が除去された後、ワイヤボンドパッド部４ｄに対応する位置が開口されたパターンのレジストマスク２６が中間生産物２４に設けられる。そして、スパッタによってアルミニウムまたは１％のＳｉを含んだアルミニウム合金が１〜２μｍの厚さで成長されることによって、図４（ｃ）に示す中間生産物２８が製造される。   Next, after the resist mask 22 is removed, a resist mask 26 having a pattern opened at a position corresponding to the wire bond pad portion 4 d is provided on the intermediate product 24. Then, an intermediate product 28 shown in FIG. 4C is manufactured by growing aluminum or an aluminum alloy containing 1% Si with a thickness of 1 to 2 μm by sputtering.

次いで、レジストマスク２６が除去された中間生産物２８が、窒素−水素（１５％）の雰囲気中で４４０度に加熱されることによって、上記のアルミニウムまたはアルミニウム合金が結晶化される。さらに、チップ部品搭載部４ｃとワイヤボンドパッド部４ｄ以外にソルダレジスト１６を被せることによって、図４（ｄ）に示すように、ワイヤボンドパッド部４ｄ、及びソルダレジスト１６が設けられた実装基板４が製造される。   Next, the intermediate product 28 from which the resist mask 26 has been removed is heated to 440 ° C. in an atmosphere of nitrogen-hydrogen (15%), so that the aluminum or aluminum alloy is crystallized. Furthermore, by covering the solder resist 16 other than the chip component mounting portion 4c and the wire bond pad portion 4d, as shown in FIG. 4D, the mounting substrate 4 provided with the wire bond pad portion 4d and the solder resist 16 is provided. Is manufactured.

次いで、チップ部品搭載部４ｃにチップ部品６が搭載され、チップ部品６がチップ部品搭載部４ｃに半田（ＡｇＳｎ）によって接合されることによって、図４（ｅ）に示す中間生産物３０が製造される。   Next, the chip component 6 is mounted on the chip component mounting portion 4c, and the chip component 6 is joined to the chip component mounting portion 4c by solder (AgSn), whereby the intermediate product 30 shown in FIG. 4E is manufactured. The

次に、ベース基板２に半導体素子８がＡｕＳｎによって接合されることによって、図４（ｆ）に示す中間生産物３２が製造される。そして、中間生産物３０及び３２が接合され、半導体素子８とワイヤボンドパッド部４ｄがワイヤ１２によって接続されることによって、図４（ｇ）に示す中間生産物３４が製造される。   Next, the semiconductor element 8 is joined to the base substrate 2 by AuSn, whereby the intermediate product 32 shown in FIG. Then, the intermediate products 30 and 32 are joined, and the semiconductor element 8 and the wire bond pad portion 4d are connected by the wire 12, whereby the intermediate product 34 shown in FIG.

次いで、ワイヤボンドパッド部４ｄが樹脂１４によって覆われることによって、図４（ｈ）に示す本実施形態の半導体モジュール１が製造される。   Next, the wire bond pad portion 4d is covered with the resin 14, whereby the semiconductor module 1 of the present embodiment shown in FIG.

図１は、本発明の実施形態にかかる半導体モジュールの平面図である。FIG. 1 is a plan view of a semiconductor module according to an embodiment of the present invention. 図２は、図１のII−II線断面図である。2 is a cross-sectional view taken along line II-II in FIG. 図３は、ワイヤボンドパッド部の厚さと、ワイヤボンドパッド部と金ワイヤとの接合強度の関係を示すグラフである。FIG. 3 is a graph showing the relationship between the thickness of the wire bond pad portion and the bonding strength between the wire bond pad portion and the gold wire. 図４（a）〜（ｈ）は、実施形態にかかる半導体モジュールの製造工程を順に示す4A to 4H sequentially show the manufacturing process of the semiconductor module according to the embodiment.

符号の説明Explanation of symbols

１…半導体モジュール、２…ベース基板、４…実装基板、４ｃ…チップ部品搭載部、４ｄ…ワイヤボンドパッド部、６…チップ部品、８…半導体素子、１０…半田、１２…金ワイヤ、１４…樹脂、１６…ソルダーレジスト。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor module, 2 ... Base substrate, 4 ... Mounting substrate, 4c ... Chip component mounting part, 4d ... Wire bond pad part, 6 ... Chip component, 8 ... Semiconductor element, 10 ... Solder, 12 ... Gold wire, 14 ... Resin, 16 ... solder resist.

Claims (3)

基板と、
前記基板に形成され、表層にＡｕを含み、チップ部品が半田接合されるチップ部品搭載部と、
前記基板に形成され金ワイヤと接合されるワイヤボンドパッド部と
を備え、
前記ワイヤボンドパッド部は、結晶化されたアルミニウムを含む半導体実装基板。 A substrate,
A chip component mounting portion formed on the substrate, including Au on a surface layer, and chip components are solder-bonded;
A wire bond pad portion formed on the substrate and bonded to a gold wire;
The wire bond pad portion is a semiconductor mounting substrate containing crystallized aluminum. 前記ワイヤボンドパッド部は、厚さ１μｍ以上であることを特徴とする請求項１に記載の半導体実装基板。 The semiconductor mounting substrate according to claim 1, wherein the wire bond pad portion has a thickness of 1 μm or more. 前記結晶化されたアルミニウムは、Ｓｉを含むことを特徴とする請求項１又は２に記載の半導体実装基板。 The semiconductor mounting substrate according to claim 1, wherein the crystallized aluminum contains Si.
JP2003291542A 2003-08-11 2003-08-11 Semiconductor mounting board Pending JP2005064187A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007088114A (en) * 2005-09-21 2007-04-05 Sharp Corp Manufacturing method of nitride semiconductor laser device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007088114A (en) * 2005-09-21 2007-04-05 Sharp Corp Manufacturing method of nitride semiconductor laser device

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