JP2005056985A - Semiconductor device, method for manufacturing same and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device by which the thermal effect of a lower layer on an electric element layer can be reduced and yield can be improved. <P>SOLUTION: This method is used for the semiconductor device 1 to manufacture a plurality of electric element layers 100, 200 and 300 laminated on a substrate 90. It includes a step for forming an upper connection electrode 290 that electrically connects a second electric element layer 200 with a third electric element layer 300 in the second electric element layer 200 on a transfer substrate, a step for forming a lower connection electrode 280 that electrically connects a second electric element layer 200 with a first electric element layer 100 in the second electric element layer 200 on a transfer substrate, and a step for transferring the second electric element layer 200 wherein the upper and lower connection electrodes 290 and 280 are formed onto the substrate 90 from the transfer substrate. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, a semiconductor device, and an electronic apparatus.

  In recent years, portable electronic devices such as mobile phones, notebook personal computers, and personal data assistance (PDA) have been required to be smaller and lighter. Accordingly, the mounting space of the semiconductor chip in the electronic device described above is extremely limited. Therefore, high-density mounting of electrical elements on a semiconductor chip is a problem. Therefore, an electric element layer lamination technique and an electric element substrate lamination technique (three-dimensional mounting technique) have been proposed.

  The electric element layer stacking technique is a technique in which a plurality of electric element layers are stacked on the upper surface of one substrate. In addition, a connection electrode with an adjacent electric element layer is formed in each electric element layer to ensure conduction between the electric element layers. According to the stacking technique of the electric element layers, a plurality of electric elements can be mounted with a very high density.

On the other hand, the electric element substrate stacking technique is a technique of stacking a plurality of substrates on which electric elements are formed (see, for example, Patent Document 1). Note that a through electrode is formed on each substrate, and the through electrodes of adjacent substrates are connected to each other to ensure conduction between the substrates. Also in the electric element substrate lamination technique, a plurality of electric elements can be mounted with high density. Further, in the electric element substrate stacking technique, each substrate is individually formed and stacked, so that the manufacturing time of the semiconductor device can be shortened.
JP 2002-305283 A

  However, the electric element layer stacking technique has a problem in that the lower electric element layer is entirely affected by the heat necessary to form the upper electric element layer. Note that the characteristics of the electric element easily change depending on the thermal history, and it becomes difficult to manufacture a semiconductor device having good characteristics. Further, since each electric element layer is continuously formed, if any one of the electric elements finally has a defect, there is a problem that the whole semiconductor device becomes defective and the yield decreases.

  On the other hand, in the stacking technique of the electric element substrate, since a through electrode is formed on each substrate, it is necessary to form a trench with a high aspect ratio, which makes it difficult to form the trench itself and embed a conductive material in the trench. There's a problem. As a result, the manufacturing cost of the semiconductor device increases and the yield decreases. Further, since the through electrodes of each substrate are connected, there is a problem that the size of each substrate, the formation position of the through electrodes, and the like are limited.

The present invention has been made to solve the above-described problems, and can reduce the thermal effect on the lower electrical element layer, improve the yield, and does not require the formation of a high aspect ratio trench. An object of the present invention is to provide a semiconductor device that does not require the formation of a through electrode and a method for manufacturing the same.
Another object is to provide a highly reliable and low-cost electronic device.

In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a plurality of electric element layers are stacked on a substrate, wherein the intermediate electric element layer is electrically connected to the upper electric element layer. Forming an upper connection electrode for electrical connection in the intermediate electrical element layer on the first transfer substrate, and a lower connection electrode for electrically connecting the intermediate electrical element layer to the lower electrical element layer, Forming the intermediate electric element layer on the first transfer substrate and transferring the intermediate electric element layer on which the upper connection electrode and the lower connection electrode are formed from the first transfer substrate to the main substrate; And a process.
According to this configuration, since the intermediate electric element layer is formed on the first transfer substrate, the thermal influence on the lower electric element layer can be reduced. In addition, since it transfers to this board | substrate after forming an upper connection electrode on a 1st transfer board | substrate, the thermal influence with respect to a lower electric element layer can be reduced more. Further, since the intermediate electric element layer is separated from the first transfer substrate and laminated on the main substrate, it is not necessary to form a high aspect ratio trench.

A method of manufacturing a semiconductor device in which a plurality of electric element layers are stacked on a main substrate, wherein a lower connection electrode for electrically connecting the intermediate electric element layer to the lower electric element layer is provided on the first transfer substrate. Forming the intermediate electric element layer on the intermediate electric element layer; transferring the intermediate electric element layer on which the lower connection electrode is formed from the first transfer substrate onto the main substrate; and Forming an upper connection electrode for electrical connection to the electric element layer on the intermediate electric element layer on the main substrate.
According to this configuration, similarly to the above, the thermal influence on the lower electric element layer can be reduced. Further, it is not necessary to form a high aspect ratio trench.

A method of manufacturing a semiconductor device in which a plurality of electric element layers are stacked on a main substrate, wherein an upper connection electrode for electrically connecting the intermediate electric element layer to the upper electric element layer is provided on the first transfer substrate. Forming the intermediate electric element layer on the intermediate transfer element, transferring the intermediate electric element layer on which the upper connection electrode is formed from the first transfer substrate onto the second transfer substrate, and the intermediate electric element layer. Forming a lower connection electrode for electrical connection to the lower electric element layer on the intermediate electric element layer on the second transfer substrate; and the intermediate electric having the upper connection electrode and the lower connection electrode formed thereon. And a step of transferring the element layer from the second transfer substrate onto the main substrate.
According to this configuration, similarly to the above, the thermal influence on the lower electric element layer can be reduced. Further, it is not necessary to form a high aspect ratio trench.

In addition, it is preferable that a step of confirming the operation of the intermediate electric element layer is provided before the step of transferring the intermediate electric element layer onto the main substrate.
According to this configuration, the defective product of the intermediate electric element layer and the non-defective product of the other electric element layer are not stacked. Therefore, non-defective products of each electric element layer can be used efficiently, and the yield of the semiconductor device can be improved.

Moreover, it is desirable to have a step of confirming the operation of each intermediate electric element layer before the step of transferring the plurality of intermediate electric element layers onto the main substrate.
According to this configuration, it is possible to eliminate only defective portions in the intermediate electric element layer. Therefore, non-defective products of each electric element layer can be used more efficiently, and the yield of semiconductor devices can be improved.

In the step of transferring the intermediate electric element layer onto the main substrate, the intermediate electric element layer is preferably transferred to the lower electric element layer via an anisotropic conductive adhesive.
According to this configuration, the intermediate electric element layer and the lower electric element layer can be easily mechanically and electrically connected.

Further, after the step of transferring the intermediate electric element layer onto the main substrate, an extension electrode for electrically connecting the upper connection electrode to the upper electric element layer is formed on the intermediate electric element layer on the main substrate. It is desirable to have the process of forming in.
According to this configuration, since the upper surface of the electrode of the intermediate electric element layer is flattened, the electrical connection with the upper electric element layer can be reliably performed.

In addition, before the step of forming the extension electrode, a step of forming an insulating film by applying a liquid material including an insulating film material on the upper surface of the intermediate electric element layer transferred onto the main substrate. It is desirable to have.
According to this configuration, a flat insulating film can be easily formed.

Further, in the step of forming the upper connection electrode, the lower connection electrode and / or the extension electrode, a liquid material containing an electrode material is discharged from a droplet discharge device, whereby the upper connection electrode, the lower connection electrode, and It is desirable to form the extension electrode.
According to the droplet discharge means, it is possible to accurately discharge a predetermined amount of droplets to a predetermined position. Therefore, the upper connection electrode, the lower connection electrode and / or the extension electrode having a predetermined shape can be accurately formed at predetermined positions. Moreover, an electrode material can be used efficiently.

On the other hand, the semiconductor device of the present invention is manufactured by using the semiconductor device manufacturing method described above.
According to this configuration, since the thermal influence on the lower electric element layer is reduced, a semiconductor device having good characteristics can be provided.

On the other hand, an electronic apparatus according to the present invention includes the semiconductor device described above.
Thereby, it is possible to provide an electronic device with high reliability and low cost.

Embodiments of the present invention will be described below with reference to the drawings. In each drawing used for the following description, the scale of each member is appropriately changed to make each member a recognizable size. In the present specification, the side on which the electric element layer is formed with respect to the substrate is referred to as the upper side, and the opposite side is referred to as the lower side.
[First Embodiment]
First, the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a side sectional view of the semiconductor device of the first embodiment. The semiconductor device 1 of the present embodiment is configured by laminating electric element layers 100, 200, and 300 including a plurality of electric elements (120, 220, etc.) on the upper surface of the substrate 90. Each electric element layer is laminated using SUFTLA (Surface Free Technology by Laser Ablation (registered trademark)) technology. In this technique, an electric element layer is formed on the upper surface of a light-transmitting transfer substrate via a separation layer, and the transfer substrate and the electric element layer are reversed and placed on the main substrate 90. The transfer substrate is separated by irradiating light from the outside of the substrate, and only the electric element layer is laminated on the main substrate 90.

[Semiconductor device]
FIG. 2 is an enlarged view of the left portion of FIG. As shown in FIG. 2, the semiconductor device of this embodiment is configured by laminating a plurality of electric element layers 100, 200, 300 on the upper surface of the substrate 90. In the following, a case where three electric element layers are laminated will be described as an example, but the electric element layers to be laminated may be two layers or four or more layers. The substrate 90 is made of a rigid material having an insulating property such as glass or quartz, or a rigid material having a high thermal conductivity such as a metal having an insulating layer on the surface. When all the electric element layers 100 are formed by a transfer method, a flexible substrate made of an epoxy resin or the like can be used as the main substrate 90. In this case, flexibility can be imparted to the semiconductor device.

(Lower electrical element layer)
A first electric element layer (lower electric element layer) 100 is formed on the upper surface of the substrate 90. In the first electric element layer 100, a thin film transistor 120 is formed as an electric element. A specific configuration of the first electric element layer 100 including the thin film transistor 120 will be described below, but the configuration of the first electric element layer 100 is not limited to the following.

A base film 102 made of an electrically insulating material such as silicon oxide (SiO ₂ ) is formed on the upper surface of the substrate 90. A semiconductor island 122 made of polycrystalline silicon (p-Si) or the like is formed on the upper surface of the base film 102. A source region S1 and a drain region D1 are formed at both ends of the semiconductor island 122. A gate insulating film 104 made of an electrically insulating material such as silicon oxide is formed so as to cover the upper surface of the semiconductor island 122. A gate electrode G1 is formed so as to face the central portion of the semiconductor island 122 with the gate insulating film 104 interposed therebetween. The gate electrode G1 is made of polycrystalline silicon, a metal material, or the like. The gate electrode G 1 is connected to an electrode pad 124 formed outside the semiconductor island 122 and on the upper surface of the gate insulating film 104.

  A first interlayer insulating film 106 made of an electrically insulating material such as silicon oxide is formed so as to cover the upper surfaces of the gate electrode G 1 and the electrode pad 124. Contact electrodes 126 and 128 made of a metal material such as Al or Cu are formed on the upper surface of the first interlayer insulating film 106. The contact electrodes 126 and 128 are connected to the source region S1 and the drain region D1 through contact holes formed in the first interlayer insulating film 106 and the gate insulating film 104, respectively. Further, a second interlayer insulating film 108 made of an electrically insulating material such as silicon oxide is formed so as to cover the upper surfaces of the contact electrodes 126 and 128. Upper connection electrodes 192 and 194 made of a metal material such as Al or Cu are formed on the upper surface of the second interlayer insulating film 108. The upper connection electrodes 192 and 194 are terminals for electrically connecting the first electric element layer 100 to the second electric element layer 200. The upper connection electrode 192 is connected to the electrode pad 124 through a contact hole formed in the second interlayer insulating film 108 and the first interlayer insulating film 106, and is electrically connected to the gate electrode G1 of the thin film transistor 120. The upper connection electrode 194 is connected to the contact electrode 126 through a contact hole formed in the second interlayer insulating film 108 and is electrically connected to the source region S1 of the thin film transistor 120.

(Intermediate electrical element layer)
A second electric element layer (intermediate electric element layer) 200 is formed on the first electric element layer 100 described above via an anisotropic conductive adhesive 198. In addition, the 2nd electric element layer 200 formed using the SUFTLA technique mentioned above has the structure which turned the 1st electric element layer 100 upside down. In the second electric element layer 200, a thin film transistor 220 is formed as an electric element. A specific configuration of the second electric element layer 200 including the thin film transistor 220 will be described below, but the configuration of the second electric element layer 200 is not limited to the following. The constituent material of each member of the second electric element layer 200 is the same as the constituent material of the corresponding member in the first electric element layer.

  The second electric element layer 200 includes a base film 202. A semiconductor island 222 is formed on the lower surface of the base film 202. A source region S2 and a drain region D2 are formed at both ends of the semiconductor island 222. A gate insulating film 204 is formed so as to cover the lower surface of the semiconductor island 222. A gate electrode G2 is formed so as to face the central portion of the semiconductor island 222 with the gate insulating film 204 interposed therebetween. The gate electrode G 2 is connected to an electrode pad 224 formed outside the semiconductor island 222 and on the lower surface of the gate insulating film 204.

  A first interlayer insulating film 206 is formed so as to cover the lower surfaces of the gate electrode G2 and the electrode pad 224. Contact electrodes 226 and 228 are formed on the lower surface of the first interlayer insulating film 206. The contact electrodes 226 and 228 are connected to the source region S2 and the drain region D2 through contact holes, respectively. Further, a second interlayer insulating film 208 is formed so as to cover the lower surfaces of the contact electrodes 126 and 128. Lower connection electrodes 282 and 284 made of a metal material such as Al or Cu are formed on the lower surface of the second interlayer insulating film 208. The lower connection electrode 282 is connected to the electrode pad 224 through a contact hole formed in the first interlayer insulating film 206 and the second interlayer insulating film 208, and is electrically connected to the gate electrode G2 of the thin film transistor 220. . The lower connection electrode 284 is connected to the contact electrode 226 through a contact hole formed in the second interlayer insulating film 108 and is electrically connected to the drain region D2 of the thin film transistor 220.

  The lower connection electrodes 282 and 284 of the second electric element layer 200 described above are disposed to face the upper connection electrodes 192 and 194 of the first electric element layer 100. An anisotropic conductive adhesive 198 is disposed between the second electric element layer 200 and the first electric element layer 100. The anisotropic conductive adhesive 198 is obtained by dispersing conductive particles in a thermosetting adhesive made of an epoxy resin or the like. And between the lower surface of the 2nd electric element layer 200 and the upper surface of the 1st electric element layer 100 is adhere | attached with the thermosetting adhesive mentioned above. In addition, the conductive particles described above are sandwiched between the lower connection electrodes 282 and 284 of the second electric element layer 200 and the upper connection electrodes 192 and 194 of the first electric element layer 100 to ensure conduction between the two. Has been.

  On the other hand, an upper connection electrode 292 made of a metal material such as Al or Cu is formed so as to be in contact with the upper surface of the base film 202 described above. The upper connection electrode 292 is a terminal for electrically connecting the second electric element layer 200 to the third electric element layer 300. A protective layer 201 made of an electrically insulating material such as silicon oxide is formed so as to cover the upper surfaces of the base film 202 and the upper connection electrode 292. An extension electrode 293 made of a metal material such as Al or Cu is formed on the upper surface of the protective layer 201. The extension electrode 293 is connected to the upper connection electrode 292 through a contact hole formed in the protective layer 201. Thus, the upper connection electrode 292 is extended to the position where the extension electrode 293 is formed.

(Upper electrical element layer)
A third electric element layer (upper electric element layer) 300 is formed on the second electric element layer 200 described above via an anisotropic conductive adhesive 298. Note that the third electric element layer 300 is formed using the above-described SUFTLA technique, similarly to the second electric element layer 200. In the third electric element layer 300, a thin film transistor 320 is formed as an electric element. A specific configuration of the third electric element layer 300 including the thin film transistor 320 will be described below, but the configuration of the third electric element layer 300 is not limited to the following. The constituent material of each member of the third electric element layer 300 is the same as the constituent material of the corresponding member in the first electric element layer 100 and the second electric element layer 200.

  The third electric element layer 300 includes a base film 302. An upper connection electrode 392 is formed so as to be in contact with the upper surface from the inside of the base film 302. The upper connection electrode 392 is a terminal for electrically connecting the semiconductor device 1 to the outside. A protective layer 301 is formed so as to cover the upper surfaces of the base film 302 and the upper connection electrode 392. An extension electrode 393 is formed on the upper surface of the protective layer 301. The extension electrode 393 is connected to the upper connection electrode 392 through a contact hole formed in the protective layer 301. Thus, the upper connection electrode 392 is extended to the position where the extension electrode 393 is formed.

  On the other hand, a thin film transistor 320 is formed on the lower surface of the base film 302 described above, similarly to the second electric element layer 200. A gate insulating film 304 and a first interlayer insulating film 306 are sequentially formed below the base film 302. A relay electrode 324 made of a metal material such as Al or Cu is formed on the lower surface of the first interlayer insulating film 306. The relay electrode 324 may be formed independently of an electric element, or may be formed as part of a wiring between the thin film transistor 320 and another thin film transistor. The relay electrode 324 is connected to the above-described upper connection electrode 392 through contact holes formed in the first interlayer insulating film 306, the gate insulating film 304, and the base film 302. Further, a second interlayer insulating film 308 is formed so as to cover the lower surface of the relay electrode 324. A lower connection electrode 382 made of a metal material such as Al or Cu is formed on the lower surface of the second interlayer insulating film 208. The lower connection electrode 282 is connected to the relay electrode 324 through a contact hole formed in the second interlayer insulating film 308. As a result, the lower connection electrode 282 is electrically connected to the upper connection electrode 292.

The lower connection electrode 382 of the third electric element layer 300 described above is disposed to face the extension electrode 293 of the second electric element layer 200. An anisotropic conductive adhesive 298 is disposed between the third electric element layer 300 and the second electric element layer 200. Thereby, the lower surface of the third electric element layer 300 and the upper surface of the second electric element layer 200 are fixed. In addition, conduction between the lower connection electrode 382 of the third electric element layer 300 and the extension electrode 293 of the second electric element layer 200 is ensured.
The semiconductor device 1 of this embodiment is configured as described above.

[Method for Manufacturing Semiconductor Device]
Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS.
(Lower electrical element layer)
FIG. 3 is an explanatory diagram of a method for forming the first electric element layer 100. First, the base film 102 is formed on the upper surface of the substrate 90. The base film 102 can be formed by a CVD method, a PVD method, a coating method, or the like. In addition, when using the apply | coating method, the polysilazane mentioned later can be employ | adopted as a liquid containing an insulating film material. Next, a semiconductor island 122 is formed on the upper surface of the base film 102. Note that in the case where the semiconductor island 122 is made of polycrystalline silicon, the semiconductor island can be formed first by amorphous silicon, and can be made polycrystalline by irradiating it with an excimer laser or the like. In this case, the substrate 90 can be made of a material other than quartz. Next, the gate insulating film 104 is formed so as to cover the upper surface of the semiconductor island 122. The method for forming the gate insulating film 104 is the same as the method for forming the base film 102. Next, the gate electrode G1 and the electrode pad 124 are formed on the upper surface of the gate insulating film 104 by sputtering or the like. Here, it is also possible to dope the semiconductor island 122 with the gate electrode G1 as a mask to form the source region S1 and the drain region D1.

  Next, the first interlayer insulating film 106 is formed so as to cover the upper surfaces of the gate electrode G1 and the electrode pad 124. The method for forming the first interlayer insulating film 106 is the same as the method for forming the base film 102. Next, contact holes are formed from the upper surface of the first interlayer insulating film 106 to the source region S 1 and the drain region D 1 of the semiconductor island 122. The contact hole is formed by a photolithography method described later. Next, contact electrodes 126 and 128 are formed on the upper surface of the first interlayer insulating film 106. The contact electrodes 126 and 128 can be formed by discharging an electrode material from a droplet discharge device as will be described later. At the same time as the formation of the contact electrodes 126 and 128, the contact hole is filled with an electrode material to form a contact, thereby ensuring conduction between the contact electrodes 126 and 128 and the source region S1 and the drain region D1. As described above, the thin film transistor 120 is formed in the first electric element layer 100.

Next, the second interlayer insulating film 108 is formed so as to cover the contact electrodes 126 and 128. The second interlayer insulating film 108 can be formed by a CVD method, a PVD method, a coating method, or the like. The coating method is a method of forming an insulating film by applying a liquid containing an insulating film material on the upper surface of the first interlayer insulating film 106. Polysilazane (a general term for polymers having Si-N bonds) can be employed as the liquid containing the insulating film material. Among these, it is preferable to use inorganic polysilazane such as polyperhydrosilazane [SiH ₂ NH] n. This polysilazane is mixed with a liquid such as xylene and applied onto the substrate by, for example, spin coating. Furthermore, if the coating film is heat-treated in an atmosphere containing water vapor or oxygen, the second interlayer insulating film 108 made of silicon oxide can be formed. In this manner, a flat insulating film can be easily formed by forming the insulating film using a coating method. In particular, an oxide film formed of polysilazane has higher crack resistance and oxygen plasma resistance than an SOG (Spin-On-Glass) film, and can be used as a thick insulating film even to a single layer.

  Next, a contact hole is formed from the upper surface of the second interlayer insulating film 108 to the upper surfaces of the electrode pad 124 and the contact electrode 126. This contact hole is formed by photolithography. Specifically, first, a resist is applied to the entire upper surface of the second interlayer insulating film 108, and an opening corresponding to the planar shape of the contact hole is formed in the resist. Next, using the resist as a mask, the second interlayer insulating film 108 is dry-etched with a fluorine-based gas or the like. As a result, a contact hole penetrating the second interlayer insulating film 108 and the gate insulating film 104 is formed. Note that a relay electrode (not shown) that is electrically connected to the electrode pad 124 may be formed on the surface of the first interlayer insulating film 106 simultaneously with the formation of the contact electrodes 126 and 128 described above. In this case, a contact hole penetrating only the second interlayer insulating film 108 may be formed from the upper surface of the second interlayer insulating film 108 to the upper surface of the relay electrode. If the relay electrode is formed in this manner, the contact hole can be easily formed because the aspect ratio of the contact hole is reduced.

  Next, upper connection electrodes 192 and 194 are formed on the upper surface of the second interlayer insulating film 108. The upper connection electrodes 192 and 194 are formed by discharging a liquid containing an electrode material from a droplet discharge device. Specifically, first, a resist is applied to the entire upper surface of the second interlayer insulating film 108. Note that the resist is applied so that the thickness of the resist is larger than the height of the upper connection electrodes 192 and 194 to be formed. Next, openings corresponding to the planar shape of the upper connection electrodes 192 and 194 are formed in the applied resist. Then, a liquid containing an electrode material is discharged into the resist opening and the contact hole. The liquid material is discharged by a droplet discharge device such as an ink jet device. The droplet discharge device is a device that applies a pressure to the liquid filled in the liquid chamber and discharges the droplet from the nozzle on the wall surface of the liquid chamber. As the pressure applying means, a piezoelectric element that protrudes and deforms the liquid chamber wall surface outside the liquid chamber, a heater that generates bubbles in the liquid chamber, or the like can be used. According to this droplet discharge means, a predetermined amount of droplets can be accurately discharged to a predetermined position. Therefore, the upper connection electrodes 192 and 194 having a predetermined shape can be accurately formed at predetermined positions. Moreover, an electrode material can be used efficiently.

  Although the case where the first electric element layer 100 is directly formed on the substrate 90 has been described above, the first electric element layer 100 is formed on the transfer substrate in the same manner as the second electric element layer described below. This may be transferred onto the substrate 90. Although each of the formation steps of the first electric element layer 100 described above involves heating, the thermal influence on the main substrate 90 can be avoided by forming the first electric element layer 100 on the transfer substrate. Therefore, a flexible substrate made of an epoxy resin or the like can be used as the main substrate 90. As a result, a semiconductor device can be formed directly on a flexible substrate, and a flexible semiconductor device can be formed.

(Intermediate electrical element layer)
FIG. 4 is an explanatory diagram of a method for forming a second electric element layer (intermediate electric element layer). In addition, the formation method of each member of the 2nd electrical element layer 200 is the same as the formation method of the corresponding member in a 1st electrical element layer.
The second electric element layer 200 is formed on the transfer substrate 20. As the transfer substrate 20, a substrate made of a light transmissive material such as quartz is employed. First, a separation layer 22 is formed on the upper surface of the transfer substrate 20. The separation layer 22 is peeled off in the layer and / or at the interface by light irradiation. When amorphous silicon containing hydrogen is adopted as the constituent material of the separation layer 22, hydrogen gas is generated by light irradiation, and the separation layer 22 can be peeled off. Further, when an organic polymer material having an amide bond, an imide bond, or the like is employed as the constituent material of the separation layer 22, the separation portion 22 can be peeled off by cutting the bond portion by light irradiation. In addition to this, oxide ceramics, nitride ceramics, or the like can be employed as a constituent material of the separation layer 22. The separation layer 22 is preferably formed to a thickness of about 40 nm to 1 μm by a CVD method, a PVD method, a coating method, or the like.

  Then, the second electric element layer 200 is formed on the upper surface of the separation layer 22. Specifically, first, the upper connection electrode 292 is formed on the upper surface of the separation layer 22 by sputtering or the like. Next, the base film 202 is formed so as to cover the upper surface of the upper connection electrode 292. Further, a contact hole is formed from the upper surface of the base film 202 to the upper connection electrode 292. The method for forming this contact hole is the same as the method for forming each contact hole in the first electric element layer. Then, a semiconductor island 222 is formed on the upper surface of the base film 202. At that time, the contact hole is also filled with a semiconductor material. Further, impurities are doped from the end of the semiconductor island 222 to the inside of the contact hole. Thus, the source region S2 can be formed simultaneously with the contact with the upper connection electrode 292. Thereafter, the second electric element layer 200 is formed in the same manner as the first electric element layer. As will be described below, the second electric element layer 200 is transferred from the transfer substrate 20 onto the main substrate to form a semiconductor device. Therefore, the second electric element is formed on the transfer substrate 20 in a state reversed from FIG. Layer 200 is formed. Therefore, the second electric element layer 200 is formed by a procedure substantially similar to that of the first electric element layer.

  Here, the operation of the second electric element layer 200 formed as described above is confirmed. Specifically, an operation check of the thin film transistor 220, a check of circuit characteristics including a plurality of thin film transistors, a check of conduction of various wirings, and the like are performed. As described above, by confirming the operation of the second electric element layer 200 before transferring it to the substrate, a defective product of the second electric element layer 200 is not connected to a non-defective product of other electric element layers. Thereby, non-defective products of other electric element layers are not discarded, and the yield of the semiconductor device can be improved.

  FIG. 5 is an explanatory diagram of a transfer method of the second electric element layer. The second electric element layer 200 confirmed to be non-defective as described above is transferred from the transfer substrate onto the main substrate 90. First, the anisotropic conductive adhesive 198 is applied to the upper surface of the first electric element layer 100 formed on the substrate 90. Then, the second electric element layer 200 is turned upside down along with the transfer substrate 20 and placed on the main substrate 90. At that time, the upper connection electrodes 192 and 194 of the first electric element layer 100 and the lower connection electrodes 282 and 284 of the second electric element layer 200 are arranged to face each other. Further, the anisotropic conductive adhesive 198 is heated while pressing the transfer substrate 20 toward the main substrate 90. Thereby, the thermosetting resin constituting the anisotropic conductive adhesive 198 is cured, and the upper surface of the first electric element layer 100 and the lower surface of the second electric element layer 200 are mechanically connected. The conductive particles contained in the anisotropic conductive adhesive 198 are sandwiched between the upper connection electrodes 192 and 194 of the first electric element layer 100 and the lower connection electrodes 282 and 284 of the second electric element layer 200. Both are electrically connected.

  Next, the light 15 is irradiated from above the transfer substrate 20. Since the transfer substrate 20 is made of a light transmissive material, the irradiated light 15 passes through the transfer substrate 20 and reaches the separation layer 22. Thereby, peeling can be caused in the separation layer 22. As the light 15, it is desirable to employ a laser that can easily separate the separation layer 22. In particular, if an excimer laser that outputs high energy in a short wavelength region is employed, the separation layer 22 can be easily peeled off. As described above, the transfer substrate 20 can be separated from the second electric element layer 200. Note that if the constituent material of the separation layer 22 remains on the upper surface of the base film 202, it is removed by etching or cleaning. Accordingly, the upper connection electrode 292 can be exposed on the upper surface of the second electric element layer 200.

  The above-described upper connection electrode 292 may be used for electrical connection with the third electrical element layer as it is. However, if the upper surface of the upper connection electrode 292 has irregularities, the reliability of electrical connection is reduced. become. Therefore, it is desirable to form an extension electrode above the upper connection electrode 292. In this case, first, as shown in FIG. 6, a protective layer 201 made of an electrically insulating material such as silicon oxide is formed on the upper surface of the base film 202. The method for forming the protective layer 201 is the same as the method for forming each insulating film in the first electric element layer 100. Next, as shown in FIG. 7, a contact hole is formed from the upper surface of the protective layer 201 to the upper connection electrode 292. The method for forming this contact hole is the same as the method for forming each contact hole in the first electric element layer 100. Then, an extension electrode 293 made of a conductive material such as Al or Cu is formed on the surface of the protective layer 201. The method for forming the extension electrode 293 is the same as the method for forming each electrode in the first electric element layer 100. Thus, if the extension electrode 293 is formed above the upper connection electrode 292, the upper surface of the electrode can be flattened, and the electrical connection with the third electric element layer can be reliably performed.

  The case where the upper connection electrode 292 is formed on the transfer substrate 20 in advance has been described (see FIG. 4). However, it is also possible to form the upper connection electrode after transferring the second electric element layer from the transfer substrate onto the main substrate. In this case, as shown in FIG. 8, the base film 202 is formed on the upper surface of the separation layer 22 without providing the upper connection electrode, and the semiconductor island is formed in the base film 202 without providing the contact hole. Therefore, the second electric element layer 200b is formed by almost the same procedure as the first electric element layer. Thereafter, similarly to FIG. 5, the second electric element layer 200b is transferred from the transfer substrate 20 onto the main substrate. Further, a contact hole is formed from the upper surface of the base film 202 to the source region S2. The method for forming this contact hole is the same as the method for forming each contact hole in the first electric element layer 100. Then, an upper connection electrode is formed on the upper surface of the base film 202 to ensure conduction with the source region S2. The method for forming the upper connection electrode is the same as the method for forming each electrode in the first electric element layer 100. As described above, if the upper connection electrode is formed after the second electric element layer is transferred, the upper surface of the upper connection electrode becomes a flat surface, so that it is not necessary to form an extension electrode.

(Upper electrical element layer)
FIG. 9 is an explanatory diagram of a method of forming the third electric element layer (upper electric element layer). In addition, the formation method of each member of the 3rd electrical element layer 300 is the same as the formation method of the corresponding member in a 1st electrical element layer and a 2nd electrical element layer.
The third electric element layer 300 is formed on the transfer substrate 30 in the same manner as the second electric element layer. Specifically, first, the separation layer 32 is formed on the upper surface of the transfer substrate 30. Next, the upper connection electrode 392 is formed on the upper surface of the separation layer 32. Thereafter, the thin film transistor 320 is formed in the same manner as the second electric element layer. Then, a contact hole is formed from the surface of the first interlayer insulating film 306 to the upper connection electrode 392. The method for forming this contact hole is the same as the method for forming each contact hole in the first electric element layer 100. Further, a relay electrode 324 made of a conductive material such as Al or Cu is formed on the surface of the first interlayer insulating film 306. The formation method of the relay electrode 324 is the same as the formation method of each electrode in the first electric element layer. Thereafter, a second interlayer insulating film 308 and a lower connection electrode 382 are formed above the relay electrode 324. As a result, the lower connection electrode 382 is electrically connected to the upper connection electrode 392. Note that the through electrode may be formed by directly connecting the lower connection electrode 382 to the upper connection electrode 392 without using the relay electrode 324. Even in this case, since the depth of the contact hole is equal to the thickness of the third electric element layer 300, the aspect ratio of the contact hole can be kept low.

  Here, the operation of the third electric element layer 300 formed as described above is confirmed. Specifically, an operation check of the thin film transistor 320, a conduction check of various wirings, and the like are performed. As described above, by confirming the operation of the third electric element layer 300 before transfer to the substrate, defective products of the third electric element layer 300 are not stacked with non-defective products of other electric element layers. Therefore, non-defective products of each electric element layer can be used efficiently, and the yield of the semiconductor device can be improved.

Then, the third electric element layer 300 confirmed to be non-defective is transferred onto the main substrate 90 as shown in FIG. The specific method is the same as in the case of the second electric element layer 200. That is, the anisotropic conductive adhesive 298 is applied to the upper surface of the second electric element layer. Next, the third electric element layer is turned upside down with the transfer substrate, and placed on the substrate 90. And the 2nd electrical element layer 200 and the 3rd electrical element layer 300 are connected mechanically and electrically by heating and pressurizing the anisotropic conductive adhesive 298. Next, the transfer substrate is separated from the third electric element layer. Further, a protective layer 301 and an extension electrode 393 are formed above the upper connection electrode 392 as necessary. As in the case of the second electric element layer 200, it is also possible to form the upper connection electrode 392 after transferring the third electric element layer from the transfer substrate onto the main substrate 90.
As described above, the semiconductor device 1 of this embodiment is completed.

  In the present embodiment, the case where one electric element layer is formed by one transfer has been described. However, it is also possible to form one electric element layer by a plurality of times of transfer. In this case, a component part of one electric element layer is formed on the transfer substrate and transferred onto the substrate in the same manner as in the present embodiment. For example, as shown on the right side of FIG. 1, the electric element 221 that is a constituent part of the second electric element layer 200 is transferred to the upper surface of the first electric element layer 100 separately from the electric element 220. Note that a protective layer 201 is formed in a gap generated between the electric element 220 and the electric element 221. In this case, if a liquid material containing an insulating material is applied by the above-described application method, the protective layer 201 can be formed from the gap between the electric elements 220 and 221 to the upper surface. Thereafter, an extension electrode may be formed as described above. In addition, before transferring each component, an operation check is performed for each component. Thereby, only the component part in which the malfunction was confirmed can be discarded, and another component part can be used efficiently. Therefore, the yield can be improved as compared with the case where one electric element layer is formed by one transfer.

  As described in detail above, the method of manufacturing the semiconductor device according to the present embodiment includes the step of forming the upper connection electrode on the second electric element layer on the transfer substrate, and the lower connection to the second electric element layer on the transfer substrate. The method includes a step of forming an electrode and a step of transferring the second electric element layer from the transfer substrate onto the main substrate. According to this configuration, since the second electric element layer is formed on the transfer substrate, the thermal influence on the first electric element layer can be reduced. Since the upper connection electrode and the lower connection electrode are formed on the transfer substrate and then transferred to the main substrate, it is not necessary to form the upper connection electrode and the lower connection electrode on the main substrate, and the heat for the first electric element layer is not formed. The influence can be further reduced. Therefore, the change in characteristics of the electric element due to the thermal history is reduced, and a semiconductor device having good characteristics can be provided. In addition, since the thermal influence on the substrate is reduced, the substrate can be made of a material having a low melting point. For example, a flexible substrate made of an epoxy resin or the like can be used as the main substrate, and a semiconductor device that is three-dimensionally mounted on the surface of the flexible substrate can be directly formed.

  Moreover, since the intermediate electric element layer is separated from the first transfer substrate and laminated on the main substrate, it is not necessary to form a high aspect ratio trench in the substrate in order to form the through electrode. Therefore, an increase in manufacturing cost of the semiconductor device can be suppressed, and the yield of the semiconductor device can be improved. Furthermore, since it is not necessary to form a through electrode on each substrate, restrictions such as the size of each substrate and the formation position of the through electrode can be eliminated.

[Second Embodiment]
Next, a semiconductor device and a method for manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS. The method of manufacturing a semiconductor device according to the second embodiment includes a step of forming an upper connection electrode on the second electric element layer on the first transfer substrate, and a step of forming the second electric element layer on the second transfer substrate from the first transfer substrate. A step of transferring, a step of forming a lower connection electrode on the second electric element layer on the second transfer substrate, and a step of transferring the second electric element layer from the second transfer substrate onto the main substrate, This is different from the first embodiment. Accordingly, the configurations of the upper connection electrode and the lower connection electrode in the second electric element layer are different from those in the first embodiment. Note that the description of the same configuration as in the first embodiment is omitted.

  FIG. 10 is a first explanatory diagram of a method for forming a second electric element layer in the second embodiment. The second electric element layer 200c is formed on the first transfer substrate 20 similarly to the modification of the first embodiment shown in FIG. In the first embodiment shown in FIG. 4, the upper connection electrode 292 is formed below the second electric element layer 200. However, in the second embodiment shown in FIG. 10, the upper connection electrode is formed above the second electric element layer 200c. 292 is formed. Therefore, after forming the second interlayer insulating film 208, a contact hole is formed from the upper surface of the second interlayer insulating film 208 to the contact electrode 226. Further, the upper connection electrode 292 is formed on the upper surface of the second interlayer insulating film 208 while forming a contact with the contact electrode 226. As a result, an upper connection electrode 292 that can be electrically connected to the source region S2 is formed. The upper connection electrode 292 is formed to extend to a connection position with the lower connection electrode 382 of the third electric element layer 300 shown in FIG.

  FIG. 11 is a second explanatory diagram of the method of forming the second electric element layer in the second embodiment. The second electric element layer 200c formed as described above is transferred onto the second transfer substrate 25 from the first transfer substrate. As the second transfer substrate 25, a substrate made of a light transmissive material such as quartz is employed. Further, the separation layer 27 is formed on the upper surface of the second transfer substrate 25. Further, an adhesive 29 is applied to the upper surface of the separation layer 27. Then, the second electric element layer 200c is transferred from the first transfer substrate onto the second transfer substrate 25. In addition, as the adhesive agent 29, what has a thermoplastic resin as a main component can be used. If the adhesive 29 is plasticized and applied to the upper surface of the separation layer 27 and the adhesive is cured after the second electric element layer 200c is transferred, the second electric element layer is fixed on the second transfer substrate 25. Can be made.

  Next, lower connection electrodes 282 and 284 are formed on the second transfer substrate 25. Specifically, first, a contact hole is formed from the upper surface of the base film 202 to the drain region D2 of the thin film transistor 220 and the electrode pad 224. Further, the lower connection electrodes 282 and 284 are formed on the upper surface of the base film 202 while forming contacts to the drain region D2 and the electrode pads 224. As a result, lower connection electrodes 282 and 284 that are electrically connected to the drain region D2 and the gate electrode G2 are formed. The lower connection electrode 284 is formed to extend to a connection position with the upper connection electrode 194 of the first electric element layer 100 shown in FIG.

  FIG. 12 is an explanatory diagram of a transfer method of the second electric element layer in the second embodiment. The second electric element layer 200c formed as described above is transferred onto the main substrate 90 from the second transfer substrate. That is, similarly to the first embodiment, the first electric element layer 100 and the second electric element layer 200c are fixed through the anisotropic conductive adhesive 198. In the case where an adhesive 29 mainly composed of a thermoplastic resin is employed as the adhesive 29 shown in FIG. 11, the adhesive is in the process of curing the anisotropic conductive adhesive 198 mainly composed of a thermosetting resin. 29 can be plasticized. Thereby, the second transfer substrate can be separated from the second electric element layer 200c. In addition, when the adhesive remains on the upper surface of the second electric element layer 200c, it is dissolved and removed with a solvent or the like.

  As described above in detail, in the method of manufacturing the semiconductor device of the second embodiment, the upper connection electrode is formed on the second electric element layer on the first transfer substrate, and the second electric element layer is formed on the second transfer substrate. The lower connection electrode is formed on the substrate. Thereby, an upper connection electrode and a lower connection electrode can be formed easily. In addition to this, the second embodiment can achieve the same effects as those of the first embodiment.

[Electronics]
Next, an example of an electronic device including the above-described semiconductor device will be described with reference to FIGS. FIG. 13 is a perspective view of a mobile phone. The above-described semiconductor device is arranged inside the housing of the mobile phone 3000. Since the semiconductor device described above has favorable characteristics, a highly reliable mobile phone 3000 can be provided. In addition, a low-cost mobile phone 3000 can be provided.

  Note that the semiconductor device described above can be applied to various electronic devices other than cellular phones. For example, LCD projectors, multimedia-compatible personal computers (PCs) and engineering workstations (EWS), pagers, word processors, TVs, viewfinder type or monitor direct view type video tape recorders, electronic notebooks, electronic desk calculators, car navigation systems The semiconductor device of this embodiment can be applied to electronic devices such as a device, a POS terminal, and a device including a touch panel.

  It should be noted that the technical scope of the present invention is not limited to the above-described embodiments, and includes those in which various modifications are made to the above-described embodiments without departing from the spirit of the present invention. In other words, the specific materials and layer configurations described in the embodiments are merely examples, and can be changed as appropriate.

It is side surface sectional drawing of the semiconductor device of 1st Embodiment. It is an enlarged view of the left side part of FIG. It is explanatory drawing of the formation method of a 1st electric element layer. It is explanatory drawing of the formation method of a 2nd electric element layer. It is explanatory drawing of the transfer method of a 2nd electric element layer. It is explanatory drawing of the formation method of an insulating film. It is explanatory drawing of the formation method of an extended electrode. It is explanatory drawing of the modification of the formation method of a 2nd electric element layer. It is explanatory drawing of the formation method of a 3rd electric element layer. It is the 1st explanatory view of the formation method of the 2nd electric element layer in a 2nd embodiment. It is the 2nd explanatory view of the formation method of the 2nd electric element layer in a 2nd embodiment. It is explanatory drawing of the transfer method of the 2nd electric element layer in 2nd Embodiment. It is a perspective view of a mobile phone which is an example of the electronic apparatus of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor device 90 board | substrate 100 1st electric element layer 120,121 electric element 200 2nd electric element layer 220,221 electric element 280 lower connection electrode 290 upper connection electrode 300 3rd electric element layer

Claims (11)

A method of manufacturing a semiconductor device in which a plurality of electrical element layers are stacked on a substrate,
Forming an upper connection electrode on the first transfer substrate on the intermediate electric element layer for electrically connecting the intermediate electric element layer to the upper electric element layer;
Forming a lower connection electrode for electrically connecting the intermediate electrical element layer to the lower electrical element layer on the intermediate electrical element layer on the first transfer substrate;
Transferring the intermediate electrical element layer formed with the upper connection electrode and the lower connection electrode from the first transfer substrate onto the main substrate;
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device in which a plurality of electrical element layers are stacked on a substrate,
Forming a lower connection electrode for electrically connecting the intermediate electric element layer to the lower electric element layer on the intermediate electric element layer on the first transfer substrate;
Transferring the intermediate electric element layer on which the lower connection electrode is formed from the first transfer substrate onto the main substrate;
Forming an upper connection electrode for electrically connecting the intermediate electric element layer to the upper electric element layer on the intermediate electric element layer on the substrate;
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device in which a plurality of electrical element layers are stacked on a substrate,
Forming an upper connection electrode on the first transfer substrate on the intermediate electric element layer for electrically connecting the intermediate electric element layer to the upper electric element layer;
Transferring the intermediate electrical element layer having the upper connection electrode formed thereon from the first transfer substrate onto a second transfer substrate;
Forming a lower connection electrode on the second transfer substrate on the intermediate electric element layer for electrically connecting the intermediate electric element layer to the lower electric element layer;
Transferring the intermediate electrical element layer formed with the upper connection electrode and the lower connection electrode from the second transfer substrate onto the main substrate;
A method for manufacturing a semiconductor device, comprising: 4. The semiconductor according to claim 1, further comprising a step of confirming an operation of the intermediate electric element layer before the step of transferring the intermediate electric element layer onto the main substrate. Device manufacturing method. 5. The method according to claim 1, further comprising a step of confirming an operation of each of the intermediate electric element layers before the step of transferring the plurality of intermediate electric element layers onto the main substrate. The manufacturing method of the semiconductor device of description. 2. The intermediate electric element layer is transferred to the lower electric element layer through an anisotropic conductive adhesive in the step of transferring the intermediate electric element layer onto the main substrate. A method for manufacturing a semiconductor device according to claim 5. After the step of transferring the intermediate electric element layer onto the main substrate, an extension electrode for electrically connecting the upper connection electrode to the upper electric element layer is formed on the intermediate electric element layer on the main substrate. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of: Before the step of forming the extension electrode, the method includes a step of forming an insulating film by applying a liquid material including an insulating film material on the upper surface of the intermediate electric element layer transferred onto the main substrate. A method for manufacturing a semiconductor device according to claim 7. In the step of forming the upper connection electrode, the lower connection electrode, and / or the extension electrode, a liquid material containing an electrode material is discharged from a droplet discharge device, whereby the upper connection electrode, the lower connection electrode, and / or 9. The method of manufacturing a semiconductor device according to claim 1, wherein the extension electrode is formed. A semiconductor device manufactured using the method for manufacturing a semiconductor device according to claim 1. An electronic apparatus comprising the semiconductor device according to claim 10.

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