JP2005045123A - Trench gate type semiconductor device and its manufacturing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a trench gate type MOS FET of low ON resistance. <P>SOLUTION: An n<SP>-</SP>-type drift region 2 and a p-channel region 3 are laminated one by one on an n<SP>+</SP>-type substrate 1. An n<SP>+</SP>-type source region 4 and a p<SP>+</SP>-type body region 5 are formed to a stripe in an upper surface of the p-channel region 3. A trench 7 passes through the p(n)-type channel region 3 and attains to the n<SP>-</SP>-type drift region 2, and a gate 9 constituted of polycrystalline silicon is buried via a gate insulating film 8. The n<SP>+</SP>-type source region 4 and the p<SP>+</SP>-type body region 5 extend from the p(n)-type channel region 3 to a source electrode 20 and cross the trench 7. The upper surface of the gate 9 is located above the upper surface of the p-channel region 3. A layer insulating film 10 is inside the trench 7, and its upper surface is located below an opening of the trench 7. The source electrode 20, the n<SP>+</SP>-type source region 4 and the p<SP>+</SP>-type body region 5 are electrically connected each in a side wall of the trench 7. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a trench gate type semiconductor device and a method for manufacturing the same, and more particularly to a trench gate type MOS gate device having a low on-resistance.

  Semiconductor devices that control current are widely used from household appliances to industrial devices. In particular, semiconductor devices that support automobile electronics are used in many parts such as hydraulic valve controls such as ABS, motor controls such as power windows, and inverter systems that convert battery DC voltage of electric vehicles into alternating current.

  A MOS (Metal Oxide Semiconductor) gate device having characteristics that a high-speed switching is possible among current control semiconductor devices and a drive circuit can be reduced in loss due to a demand for high frequency and miniaturization of an inverter. Is attracting attention. The MOS gate device includes a field effect transistor (MOS FET) that is a unipolar device in which either electrons or holes operate as carriers, and an IGBT (insulated gate bipolar transistor) that is a bipolar device in which both electrons and holes operate as carriers. ) And can be broadly divided. Since MOS FETs do not accumulate minority carriers, they are particularly excellent in high speed performance.

  Problems required for the current control semiconductor device include a reduction in on-resistance for reducing reactive power and an increase in breakdown voltage for improving reliability. On-resistance is one of the most important characteristics of MOS FETs. It refers to the resistance value from the drain to the source through all the paths in the element through which the drain current flows. In general, the resistance of the channel region (channel resistance) contributes. large. On the other hand, the breakdown voltage refers to the breakdown voltage between the drain and the source, and it is known that the ON resistance is in a trade-off relationship.

  In order to lower the channel resistance, a trench gate structure has been developed in which a narrow and deep trench is formed from the semiconductor surface and a gate is formed on the side surface. As a result, the current path is three-dimensionally expanded on the trench sidewall, and the on-resistance can be drastically reduced. Further, in order to lower the on-resistance, a structure is adopted in which the trench gate interval is narrowed to increase the cell density to increase the effective current path density.

  An interlayer insulating film for insulation is disposed between a gate electrode that is embedded in the trench and applies a voltage for forming a channel and a source electrode that supplies a current to the channel. In general, an interlayer insulating film is formed on the surface of a substrate, and a contact hole is opened only in a predetermined region to be electrically connected to a source region and a source electrode deposited on the interlayer insulating film.

  Photolithography for forming the contact hole pattern requires high accuracy for aligning the contact hole pattern with a narrow source region adjacent to the trench opening on the substrate surface. In consideration of the alignment accuracy of the exposure mask in the production line, it is necessary to provide a design dimension between the trench and the contact hole, and there is a limit to reducing the trench interval in order to reduce the channel resistance.

  To solve this problem, the gate material in the trench is pushed deeper than the substrate surface, the interlayer insulating film is disposed only in the trench, the source region is formed by ion implantation or the like in the trench opening, and then the source electrode Has been proposed (see, for example, Non-Patent Document 1).

  According to this method, it is possible to realize a structure that obtains a desired insulation and electrical connection relationship without a photolithography process that requires highly accurate mask alignment.

  Similarly, the gate material in the trench is pushed deeper than the substrate surface, and an interlayer insulating film is formed so as to form a plane that is almost in common with the silicon substrate surface, and contact is made with the alternately formed body region and source region, respectively. There has been proposed a structure that is electrically connected to the source electrode without forming a hole (see, for example, Patent Document 1).

A. A. Finney et al., “Recessed Trench MOSFET Process Without Critical Aligments Masks Very High Densities Possible”, ISPSD '2001, Japan, IEEE, 2001, p. 283-286 JP 2000-252468 A

  Further, in order to reduce the channel resistance, when trying to reduce the cell pitch by narrowing the trench interval, the source region on the substrate surface also becomes narrow. For this reason, since the contact area between the source electrode and the source region is reduced, the contact resistance is increased, and the on-resistance may be increased as a whole.

  Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a trench gate type semiconductor device capable of realizing low on-resistance without photolithography requiring high-precision mask alignment and a method for manufacturing the same. It is to be.

  A trench gate type semiconductor device according to the present invention is a trench gate type semiconductor device having a plurality of gates embedded in a groove with a gate insulating film interposed therebetween, and is formed on an upper surface of an n (p) type semiconductor substrate. an n (p) type drift region; a p (n) type channel region formed on the upper surface of the n (p) type drift region; and a charge conduction region formed on the upper surface of the p (n) type channel region. A source electrode formed on an upper surface of the charge conductive region, and an interlayer insulating film that insulates the gate electrode and the source electrode, and the groove extends from the upper surface of the charge conductive region to the charge conductive region and The n (p) -type drift region is reached through the p (n) -type channel region, the interlayer insulating film is in the trench, its upper surface is located below the trench opening, and the source electrode is , Opening of the groove Filled, characterized by said charge transfer region and electrically connected at the groove side walls.

  According to this structure, since the charge conduction region and the source electrode are electrically connected on the trench side wall, even if the trench interval is narrowed, the increase in contact resistance can be suppressed and the on-resistance can be reduced. In addition, highly accurate mask alignment is not required in the manufacturing process.

  The charge conduction region includes a p (n) -type body region and an n (p) -type source region, and the p (n) -type body region and the n (p) -type source region correspond to the charge conduction. Preferably, it extends from the lower surface to the upper surface of the layer and traverses the groove.

  According to this structure, the p (n) type body region, the n (p) type source region, and the source electrode can be electrically connected to each other at the trench sidewall. Therefore, since the potential of the channel region is determined, the gate operation is stabilized, and holes generated by avalanche breakdown in the current channel can be efficiently extracted to increase the avalanche breakdown resistance.

  Further, it is preferable that D> L, where D is a depth of the source electrode buried in the trench and L is an interval between the adjacent trench gates on the upper surface of the charge conductive layer.

  According to this structure, since the electrical connection between the charge conduction region and the source electrode is mainly performed on the trench sidewall, even if the trench interval is narrowed, the increase in contact resistance can be suppressed and the on-resistance can be reduced. .

  Moreover, it is preferable that the side wall of the groove has a taper extending from the bottom toward the opening.

  According to this structure, it is possible to easily fill the gate material sufficiently into the groove.

  The method of the present invention is a method for manufacturing a trench gate type semiconductor device having a plurality of gates embedded in a trench with a gate insulating film interposed therebetween, wherein n (p) is applied to an n (p) type semiconductor substrate. A step of epitaxially growing a type drift region, a p (n) type channel region, and an n (p) type source region [p (n) type body region], and the n (p) type source region [p ( forming a p (n) type body region [n (p) type source region] penetrating through the n (p) type source region [p (n) type body region] in the n) type body region]; Forming trenches respectively traversing the n (p) type source region and the p (n) type body region to a depth reaching the n (p) type drift region through the p (n) type channel region; , Forming an insulating film on the inner wall of the groove, and p (n) type in the groove Filling the polycrystalline silicon to a height exceeding the upper surface of the channel region, depositing an interlayer insulating film on the polycrystalline silicon in the trench, the interlayer insulating film having a desired thickness, and Etching so that the upper surface is below the groove opening, filling the groove opening, and electrically connecting the p (n) type body region and the n (p) type source region with the inner wall of the groove And a step of forming a source electrode.

  According to this method, it is possible to realize a trench gate type semiconductor device having a low on-resistance without photolithography that requires highly accurate mask alignment. The p (n) type body region [n (p) type source region] is preferably formed in a stripe shape.

  The interlayer insulating film is preferably etched deeper from the groove opening than the interval between the adjacent trench gates on the upper surface of the n (p) type source region [p (n) type body region].

  Further, the step of forming the groove includes a first etching step in which an etching mask is provided and anisotropic etching is performed, and after the etching mask is removed, isotropic etching is performed to widen the groove opening. 2 etching steps.

  According to this method, the interval between adjacent trenches can be made smaller than the resolution of an exposure apparatus used for photolithography.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1
[Device structure]
FIG. 1 is a cross-sectional view of a MOS FET 100 according to the first embodiment. An n ⁻ type drift region 2 and a p channel region 3 in which a channel as an electron path is formed are sequentially stacked on an n ⁺ type substrate 1 made of silicon, and electrons and holes are respectively formed on the upper surface of the p channel region 3. Conductive n ⁺ -type source region 4 and p ⁺ -type body region 5 are formed in stripes. The p ⁺ -type body region 5 electrically connects the p-channel region 3 and the source electrode 20, fixes the potential of the p-channel region 3, stabilizes the gate operation, and is generated by avalanche breakdown in the current channel. By pulling out the holes from the p-channel region 3, the avalanche breakdown resistance is increased.

Further, n ⁺ type source region 4 and p ⁺ type body region 5 each extend to the upper surface, form the same surface on the upper surface, and a source electrode 20 is formed on the surface in contact with the upper surface. The trench gate 6 gates the trench 7, which is a groove that penetrates the p (n) type channel region 3 from the surface formed by the n ⁺ type source region 4 and the p ⁺ type body region 5 and reaches the n ⁻ type drift region 2. A gate 9 made of polycrystalline silicon is embedded via an insulating film 8. The gate 9 and the source electrode 20 are insulated by the interlayer insulating film 10. A drain electrode 21 is formed on the back surface of the n ⁺ type substrate 1.

What is characteristic in the present invention is that n ⁺ -type source regions 4 and p ⁺ -type body regions 5 are alternately arranged in stripes, and each region extends from p (n) -type channel region 3 to source electrode 20. And crossing the trench 7.

FIG. 2 is an enlarged view of the cross section of the trench portion of the MOS FET 100 of FIG. 1, and shows a cross section of the n ⁺ type source region 4.

  In the present invention, it is further characteristic that the upper surface of the gate 9 is located above the upper surface of the p-channel region 3, and the interlayer insulating film 10 disposed on the gate 9 is in the trench 7. The upper surface is located below the opening of the trench 7.

According to this configuration, the source electrode 20 penetrates to the upper surface of the interlayer insulating film 10 in the trench 7, and the source electrode 20, the n ⁺ -type source region 4 and the p ⁺ -type body region 5 are respectively connected to the trench groove sidewall 7 a and the substrate. Contact with the surface and electrical connection can be made. Compared with the conventional structure in which electrical connection is made only on the substrate surface, the contact area is widened, so that the contact resistance can be reduced. When the distance between adjacent trenches on the substrate surface is L and the depth of the source electrode 20 entering the trench is D, this effect becomes more prominent as the ratio between the trench distance: L and the source electrode depth: D decreases. Become. Therefore, in order to reduce the contact resistance and the on-resistance, it is desirable that L <D.

The dimension of the trench pattern is determined by the resolution of an exposure apparatus that performs pattern transfer of trench etching. For example, the resolution of a general exposure apparatus using a mercury lamp i-line with a wavelength of 365 nm as a light source is about 0.4 μm. Therefore, in this case, the trench interval L can be physically reduced to 0.4 μm. At this time, if the source electrode depth: D is 1 μm, paying attention to the current path flowing on one side of one trench, the contact area between the source electrode 20 and the n ⁺ -type source region 4 is calculated. The effective surface area is [width 0.2 (μm) × trench length], but the surface area on the side wall is [depth 1 (μm) × trench length], and the contact area at the side wall is the contact at the substrate surface. It turns out that it becomes 5 times the area. That is, in the conventional structure in which the source electrode 20 and the n ⁺ -type source region 4 are in contact with each other only on the substrate surface, when the trench interval is 2.4 μm, the structure according to the first embodiment has the same contact area of 0.4 μm. It can be realized with the trench interval. If an exposure apparatus with higher resolution is used, it is possible to further narrow the trench interval and increase the channel density.

Therefore, according to the present embodiment, the trench interval, which was 2.4 μm, for example, can be reduced to 0.4 μm while the contact resistance between the source electrode 20 and the n ⁺ -type source region 4 is maintained at the same level as the conventional one. . Thereby, a reduction in on-resistance due to an improvement in channel density can be realized.

  Further, according to the first embodiment, since the path from the region where the current channel of the p-channel region 3 is formed to the source electrode 20 is close, the conduction resistance therebetween is small, and the potential rise of the p-channel region 3 is small. Can be suppressed. Therefore, latch-up is unlikely to occur.

Here, in FIG. 1, the trench 7, the n ⁺ -type source region 4 and the p ⁺ -type body region 5 are shown to be orthogonal to each other, but the intersection angle may not be a right angle.

  The MOS FET 100 according to the first embodiment is an n-channel type using an n-type substrate and carriers as electrons, but each semiconductor layer and each region has a conductivity type opposite to that of the p-channel using carriers as holes. It is good as a type. Furthermore, although silicon is used as the semiconductor in the first embodiment, a compound semiconductor can also be used.

[Device manufacturing method]
A manufacturing process of the MOS FET 100 according to the first embodiment will be described with reference to the drawings. 3 to 10 are process diagrams for explaining this.

First, an n ⁻ type drift region 2, a p channel region 3, and an n ⁺ type source region 4 are epitaxially grown on the n type substrate 1 in order. Next, as shown in FIG. 3A and FIG. 3B which is a cross-sectional view taken along the line A-A, a p ⁺ type body region 5 is formed in a stripe shape in the n ⁺ type source region 4. The p ⁺ -type body region 5 is formed by ion implantation and diffusion. Here, the p ⁺ -type body region 5 may be epitaxially grown first, and the n ⁺ -type source region 4 may be formed in a stripe shape by ion implantation and diffusion therein.

Next, as shown in FIG. 4 (a) and FIG. 4 (b) which is a cross-sectional view taken along the line AA, a trench which is a groove traversing the formed n ⁺ type source region 4 and p ⁺ type body region 5 is formed. 7 is formed to a depth that reaches the n-type drift region 2 through the p-type channel region 3. In this step, first, an HTO (high temperature oxide) film is formed on the entire surface of the substrate by an HTOCVD (high temperature oxide chemical vapor deposition) method, and then a trench opening pattern is transferred from the mask to the surface by a photolithography method. HTO film etching is performed to form an HTO film in a trench opening pattern. Here, since the formation of the trench opening pattern does not require fine alignment of the mask in the photolithography process, the trench interval can be narrowed to the resolution limit of the exposure apparatus used for photolithography. Next, using the patterned HTO film as an etching mask 30, the n-type drift penetrates the p-type channel region 3 by an anisotropic dry etching method such as RIE (reactive ion etching apparatus) using CF-based gas and HBr-based gas. The trench 7 is formed by etching to a depth reaching the region 2.

Next, as shown in FIG. 5 (a), FIG. 5 (b) which is an AA cross-sectional view thereof, and FIG. 5 (c) which is a BB cross-sectional view thereof, a gate 9 is formed. In the process, first, the gate insulating film 8 is formed on the inner wall of the trench 7. The gate insulating film 8 is a silicon oxide film, and may be deposited by CVD, or the entire surface of the substrate is thermally oxidized, and the silicon exposed portion on the trench side wall is formed into a silicon oxide film by thermal oxidation. May be. Next, a gate 9 made of polycrystalline silicon is formed in the trench 7 covered with the gate insulating film 8. For the gate 9, polycrystalline silicon is deposited by CVD to fill the trench 7, and phosphorus is implanted and diffused at a high concentration to increase the conductivity. Then, an etching mask that opens only at the center of the trench 7 having the cross section shown in FIG. 5B is disposed, and the polycrystalline silicon on the upper surface of the substrate is removed. At this time, the upper surface of the gate 9 in the trench 7 is positioned higher than the upper surface of the p-channel region 3. That is, the gate 9, the n ⁺ -type source region 4 and the p ⁺ -type body region 5 are arranged so as to overlap in the horizontal direction, and an electric field applied from the gate can efficiently form a current channel. Here, in the region of FIG. 5C around the trench 7, polycrystalline silicon remains on the substrate surface and is used as the external connection electrode pad 10 a of the gate 9.

  Next, the interlayer insulating film 10 is formed. In this process, first, as shown in FIG. 6A and FIG. 6B, which is a cross-sectional view taken along the line AA, plasma is applied to BPSG (boron phosphorus glass) which is an insulating film so as to fill the trench 7. Deposited by CVD method.

  Next, as shown in FIG. 7A and FIG. 7B, which is a cross-sectional view taken along the line AA, the BPSG is etched back until the thickness in the trench 7 becomes a predetermined thickness. At this time, the BPSG on the external connection electrode pad 10a of the gate 9 arranged on the substrate surface is also removed.

Next, as shown in FIG. 8A and FIG. 8B, which is a sectional view taken along the line A-A, a source electrode 20 made of Al or the like is formed. Here, an insulating film is disposed between the external connection electrode pad 10a of the gate 9 and the source electrode 20 to insulate them from each other. The source electrode 20 is filled in the trench 7 and abuts on the n ⁺ -type source region 4 and the p ⁺ -type body region 5 on the side wall of the trench 7 to obtain electrical connection with both. Finally, the drain electrode 21 is formed on the n ⁺ type substrate 1.

According to the manufacturing method of the trench gate type semiconductor device of the first embodiment, the electrical connection between the source electrode 20 and the n ⁺ type source region 4 and the sp ⁺ type body region 5 and the connection between the source electrode 20 and the gate 9 are performed. The insulation relationship can be realized without a photolithography process that requires precise mask alignment. For this reason, it is not necessary to provide a margin for taking into account the mask alignment accuracy in the opening pattern of the trench 7, so that the trench interval can be narrowed and a structure with a high channel density can be easily realized.

Embodiment 2
[Device structure]
FIG. 9 is a cross-sectional view of the MOS FET 101 according to the second embodiment. The feature of the MOS FET 101 is that the side wall of the trench 7 in the MOS FET 100 of the first embodiment is tapered from the bottom of the trench toward the opening.

According to the second embodiment, the source electrode 20, the n ⁺ -type source region 4 and the p ⁺ -type body region 5 are in contact with each other on the side wall of the trench 7 to obtain electrical connection. There is no need to contact each other. Therefore, as shown in FIG. 9, it is not necessary to provide a flat top between adjacent trenches on the substrate surface, and even if the trenches overlap each other, the source electrode 20, the n ⁺ -type source region 4 and the p ⁺ The mold body region 5 can be electrically connected.

  According to this structure, since the opening is wider than the depth of the trench, it is easy to sufficiently fill the gate material to the depth of the trench.

[Device manufacturing method]
A manufacturing process of the MOS FET 101 according to the second embodiment will be described with reference to the drawings. 10 and 11 are process diagrams for explaining this. The manufacturing method of the MOS FET 101 according to the second embodiment is different from the manufacturing method of the MOS FET 100 according to the first embodiment and the trench etching method. There are two methods for etching a tapered trench depending on the trench interval.

  When the trench interval on the upper surface of the substrate is wider than the pattern transfer resolution of photolithography, an etching mask 50 that defines the trench opening width is provided as shown in FIG. 10, and dry etching is performed. By performing dry etching at this time under the condition that the protective film forming action on the trench sidewall during etching is high, the trench has a tapered shape that becomes narrower as the etching proceeds from the opening width defined by the etching mask.

  On the other hand, when the trench interval is narrow and the etching mask can no longer be disposed between the upper surface of the substrate and the adjacent trench, etching is performed in two stages. First, as shown in FIG. 11A, an etching mask 51 having an opening pattern narrower than the finished trench opening width is provided, and anisotropic dry etching is performed. The etching conditions at this time do not have to form a large taper angle. Next, after removing the etching mask 51, as shown in FIG. 11B, etching is performed by chemical dry etching which is an isotropic dry etching method. In this chemical dry etching, the closer to the trench opening, the faster the etching rate and the deeper the trench, the slower the etching rate. Therefore, the shape of the trench can be changed from 7a to 7b having a large taper angle.

It is sectional drawing which shows the structure of MOS FET100 concerning Embodiment 1 of this invention. It is a figure which shows contact | abutting relationship between the source electrode and source region (body region) in the trench side wall of MOS FET100 concerning Embodiment 1 of this invention. It is a figure explaining the manufacturing process of MOS FET100 concerning Embodiment 1 of this invention, Comprising: It is a figure which shows arrangement | positioning of a source region and a body region. It is a figure explaining the manufacturing process of MOS FET100 concerning Embodiment 1 of this invention, Comprising: It is a figure which shows a trench etching shape. It is a figure explaining the manufacturing process of MOS FET100 concerning Embodiment 1 of this invention, Comprising: It is a figure which shows formation of a gate electrode. It is a figure explaining the manufacturing process of MOS FET100 concerning Embodiment 1 of this invention, Comprising: It is a figure which shows deposition of an interlayer insulation film. It is a figure explaining the manufacturing process of MOS FET100 concerning Embodiment 1 of this invention, Comprising: It is a figure which shows the etch-back of an interlayer insulation film. It is a figure explaining the manufacturing process of MOS FET100 concerning Embodiment 1 of this invention, Comprising: It is a figure which shows arrangement | positioning of a source electrode. It is sectional drawing which shows the structure of MOS FET100 concerning Embodiment 1 of this invention. It is a figure explaining the manufacturing process of MOS FET101 concerning Embodiment 2 of this invention, Comprising: It is a figure which shows an etching mask and trench shape when a trench space | interval is wide. It is a figure explaining the manufacturing process of MOS FET101 concerning Embodiment 2 of this invention, Comprising: It is a figure which shows the etching divided into two steps when a trench space | interval is narrow.

Explanation of symbols

  1 substrate, 2 drift region, 3 channel region, 4 source region, 5 body region, 6 trench gate, 7 trench, 8 gate insulating film, 9 gate, 10 interlayer insulating film, 20 source electrode, 21 drain electrode, 30, 50 , 51 Etching mask.

Claims (9)

A trench gate type semiconductor device comprising a plurality of gates embedded in a trench through a gate insulating film,
an n (p) type drift region formed on the upper surface of the n (p) type semiconductor substrate;
A p (n) type channel region formed on the top surface of the n (p) type drift region, a charge conduction region formed on the top surface of the p (n) type channel region,
A source electrode formed on an upper surface of the charge conduction region;
An interlayer insulating film for insulating the gate and the source electrode;
With
The groove penetrates the charge conduction region and the p (n) type channel region from the upper surface of the charge conduction region and reaches the n (p) type drift region,
The interlayer insulating film is in the groove, and the upper surface thereof is located below the groove opening,
The trench gate type semiconductor device, wherein the source electrode fills the opening of the groove and is electrically connected to the charge conductive region on the side wall of the groove. The trench gate type semiconductor device according to claim 1,
The charge conduction region is composed of a p (n) type body region and an n (p) type source region, and the p (n) type body region and the n (p) type source region are formed of the charge conduction layer. A trench gate type semiconductor device that extends from a lower surface to an upper surface and traverses the groove. The trench gate type semiconductor device according to claim 2,
The trench gate type semiconductor device, wherein the p (n) type body region and the n (p) type source region are formed in a stripe shape. A trench gate type semiconductor device according to any one of claims 1 to 3,
A trench gate type semiconductor device in which D> L, where D is a depth of the source electrode buried in the groove and L is an interval between the adjacent trench gates on the upper surface of the charge conductive layer. . A trench gate type semiconductor device according to any one of claims 1 to 4,
A trench gate type semiconductor device, wherein a side wall of the groove has a taper extending from the bottom toward the opening. A method for manufacturing a trench gate type semiconductor device comprising a plurality of gates embedded in a trench through a gate insulating film,
a step of epitaxially growing an n (p) type drift region, a p (n) type channel region, and an n (p) type source region [p (n) type body region] in order on an n (p) type semiconductor substrate; ,
The n (p) type source region [p (n) type body region] penetrates the n (p) type source region [p (n) type body region], and the p (n) type body region [n (p ) Type source region],
Forming trenches respectively traversing the n (p) type source region and the p (n) type body region to a depth reaching the n (p) type drift region through the p (n) type channel region; ,
Forming an insulating film on the inner wall of the groove;
Filling the trench with polycrystalline silicon to a height exceeding the upper surface of the p (n) channel region;
Depositing an interlayer insulating film on the polycrystalline silicon in the trench;
Etching the interlayer insulating film so as to have a desired thickness and an upper surface of the interlayer insulating film being lower than the groove opening;
Forming a source electrode that fills the opening of the groove and is electrically connected to the p (n) type body region and the n (p) type source region at the inner wall of the groove;
A method of manufacturing a trench gate type semiconductor device including: It is a manufacturing method of the trench gate type semiconductor device according to claim 6,
The method of manufacturing a trench gate type semiconductor device, wherein the p (n) type body region [n (p) type source region] is formed in a stripe shape. A method for manufacturing a trench gate type semiconductor device according to claim 6 or 7,
The interlayer insulating film is etched deeper from the groove opening than an interval between the adjacent trench gates on the upper surface of the n (p) type source region [p (n) type body region]. A method for manufacturing a semiconductor device. A method for manufacturing a trench gate type semiconductor device according to any one of claims 6 to 8,
The step of forming the groove includes a first etching step in which an etching mask is provided and anisotropic etching is performed,
Removing the etching mask, and then performing isotropic etching to expand the groove opening,
A method of manufacturing a trench gate type semiconductor device, comprising:

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