JP2005044865A

JP2005044865A - Semiconductor package device and its manufacturing method

Info

Publication number: JP2005044865A
Application number: JP2003200646A
Authority: JP
Inventors: Tomoyuki Kosugi; 智之小杉
Original assignee: Casio Computer Co Ltd
Current assignee: Casio Computer Co Ltd
Priority date: 2003-07-23
Filing date: 2003-07-23
Publication date: 2005-02-17

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package device which is equipped with a soldered joint that has excellent resistance to stress induced by a physical external force and very reliable, and to provide a method of easily manufacturing the same. <P>SOLUTION: Bump electrodes 1e1 provided in the peripheral parts of CSP1 which are liable to undergo a physical external force and the corresponding terminal electrodes 2a of a wiring board 2 are joined together with concave solder bumps 3a whose sides are formed concave as one goes to the central part, and other bump electrodes 1e2 and the corresponding terminal electrodes 2a are joined together with convex solder bumps 3b whose sides are formed convex as one goes to the central part. Concentrating stress acting on the joint surfaces of the concave solder bumps 3a with the tip surface of the projecting electrode 1e1 and the terminal electrode 2a is relaxed by stress induced by a physical external force, so that crack can be restrained from occurring in a joint, or a joint itself can be protected against damage. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
この発明は、チップサイズパッケージ（ＣｈｉｐＳｉｚｅＰａｃｋａｇｅ；以下、ＣＳＰと略記する）を搭載した半導体パッケージ装置とその製造方法に関する。
【０００２】
【従来の技術】
従来、チップサイズ半導体パッケージつまりＣＳＰを製造する方法として、半導体ウエハの状態でウエハを加工し入出力端子とこれに対応する突起電極を形成した後に樹脂封止を行う、ウエハレベル半導体パッケージの製造方法が知られている。樹脂封止した後は、各突起電極の露出させた先端面に半田バンプ等の金属バンプを配置した後、個々のチップサイズに切り出し、複数のＣＳＰを一括製造する（例えば特許文献１）。
【０００３】
【特許文献１】
特開２０００−１８８３５２（第３頁、図２）
【０００４】
【発明が解決しようとする課題】
上述のようにして製造されたＣＳＰは、通常、配線基板上の所定位置に半田接合により搭載される。この場合、各突起電極と対応する配線基板上の端子電極とを半田バンプを介して対向配置させた後、リフロー炉中に通すリフロー処理を行い、半田バンプを溶融させ、対応する突起電極と端子電極とを半田バンプを介して接合する。これにより、ＣＳＰの配線基板上への搭載が完了する。
【０００５】
上述の配線基板上に搭載されたＣＳＰに対しては、基板実装工程や、携帯機器等の製品に組み込まれた後の流通過程或いは製品として使用される際等、様々な状況下において物理的外力が加えられ、これにより半田接合部分にクラックが発生したり半田接合が破断したりし、機器の動作不良が引き起こされる。この場合、その物理的外力による応力は、半田バンプが設けられた半田接合エリアの周辺部において強く作用する傾向があり、そのうちでも特にコーナー部における応力が最も大きく、半田接合不良はコーナー部において最も発生し易い。
【０００６】
本発明は、物理的外力による応力に対する耐久性に優れた半田接合部を備えた信頼性の高い半導体パッケージ装置とそれを容易に製造する方法を提供することを課題とする。
【０００７】
【課題を解決するための手段】
本発明の半導体パッケージ装置は、複数の入出力端子電極にそれぞれ導電接続された複数の突起電極が所定のエリアに配置され、前記突起電極間に封止材が設けられた半導体パッケージを、複数の端子電極を有する配線基板に、互いに対応する前記突起電極と前記端子電極とをそれぞれ半田バンプを介して接合された半導体パッケージ装置であって、複数の前記半田バンプのうちの少なくとも前記エリアの周辺のコーナー部に位置する半田バンプはストレート状または高さ方向における中央部が凹んだ柱状をなしていることを特徴とするものである。
【０００８】
また、本発明の半導体パッケージ装置の製造方法は、半導体ウエハの一方の主面の所定のチップサイズエリア毎に複数の入出力端子電極にそれぞれ導電接続された複数の突起電極を立設し、前記突起電極間に絶縁材料からなる封止材を前記突起電極間の各先端面が露出するように充填し、前記突起電極の各先端面に、所定の高さの半田ボールを形成し、前記半導体ウエハを前記チップサイズエリア毎に切断して、複数のチップサイズ半導体パッケージとなし、前記チップサイズ半導体パッケージの少なくとも１つを、前記各突起電極が前記配線基板の端子電極に前記半田ボールを介し対向させて配置し、リフロー処理により前記半田ボールを溶融させて、対応する前記突起電極と前記配線基板の端子電極とを接合してなる半導体パッケージ装置の製造方法であって、前記チップサイズエリアの少なくとも周辺部のコーナー部に位置する突起電極の各先端面に形成する半田ボールの高さを、前記チップサイズエリアの中央部に位置する突起電極の各先端面に形成する半田ボールの高さよりも小さくなした前記チップサイズ半導体パッケージを前記配線基板と対向した状態でリフロー処理を行い、前記チップサイズエリアのコーナー部に位置する突起電極の各先端面に形成する半田ボールをストレート状または高さ方向における中央部が凹んだ柱状となすことを特徴とするものである。
【０００９】
本発明の半導体パッケージ装置およびその製造方法によれば、物理的外力が最も加わり易いチップ周辺コーナー部の半田バンプを、ストレート状または高さ方向における中央部が凹んだ柱状に形成するので、換言すれば、半田バンプの高さ方向の中央部の面積に対し半田バンプの接合面における面積を同等または大きくするので、半田バンプ周縁部への応力集中を低減する作用が生じ、最も大きい応力が作用するチップ周辺コーナー部の半田バンプにクラックが発生したり或いは接合状態そのものが破壊される不具合の発生が、顕著に抑制される。その結果、耐久性に優れた半田接合部を備えた信頼性の高い半導体パッケージ装置を提供することができる。
【００１０】
【発明の実施の形態】
本発明の実施形態としての半導体パッケージ装置について、図１乃至図２に基づき説明する。図１は本実施形態の半導体パッケージ装置を示す模式的正断面図、図２はそのＩＩ−ＩＩ平断面図である。
【００１１】
本半導体パッケージ装置は、図１に示されるように、ＣＳＰ１が配線基板２上の所定位置に半田接合により搭載されてなる。
【００１２】
ＣＳＰ１は、シリコンウエハをチップサイズに切断したシリコン基板１ａを備えている。このシリコン基板１ａには、集積回路（不図示）が加工形成されており、その入出力端子として複数の電極パッド１ｂが一方の主面にマトリクス状に配列されている。この一方の主面には、各電極パッド１ｂの中央部を除いて、絶縁膜１ｃが被覆されている。各電極パッド１ｂの露出された中央部表面には、絶縁膜１ｃの表面にパターン形成された配線１ｄの一端部がそれぞれ導通接続されている。これら配線１ｄのそれぞれの他端には、突起電極１ｅがそれぞれ立設されている。そして、それら突起電極１ｅ間には、それぞれの先端面を露出させて封止樹脂（封止材）１ｆが充填設置されている。なお、本実施形態のＣＳＰ１では、電極パッド１ｂが配設される側の主面（以下、底面という）全体が、突起電極１ｅの配設エリアである。
【００１３】
図２に示すように、突起電極１ｅは、ＣＳＰ１の底面全体にわたり、例えば、５行×６列の配列でマトリクス状に配設されている。すなわち、電極パッド１ｂの配列に拘わらず突起電極１ｅが５行×６列の配列となるように、各配線１ｄがパターン形成されている。ただし、突起電極１ｅの数は、図面を簡略化したものであり、実際にはもっと多数の行と列からなるマトリクス配列となされている。
【００１４】
以上の様に構成されたＣＳＰ１は、各突起電極１ｅの先端を対応する配線基板２側の端子電極２ａにそれぞれ半田バンプ３を介して接合され、配線基板２の所定位置に搭載されている。
【００１５】
ここで、半田バンプ３は、突起電極の配設エリアつまりＣＳＰ１の底面の周辺部に配設された突起電極１ｅ１上に配置された半田バンプ３は、断面積が小さく、かつ、ストレート状、または側面が中央部に向かうに従い凹んだ湾曲面をなす柱状に形成された凹型半田バンプ３ａとされ、周辺部以外の突起電極１ｅ２上に配置された半田バンプ３は、凹型半田バンプ３ａより断面積が大きく、かつ、側面が中央部に向かうに従い突き出た湾曲面をなす柱状に形成された凸型半田バンプ３ｂとされている。
【００１６】
ここで、図３に基づいて、本願の発明の作用について説明する。半田バンプには、シリコン基板１ａと配線基板２との線膨張係数の相違に起因する応力が発生する。この応力は、高さ方向における中央部が突き出た凸型半田バンプ３ｂにおいては、図３に図示されている如く、断面積が大きい中央部から半田バンプ３ｂと突起電極１ｅ２との界面である接合面Ｓａ１に作用する。ここで、接合面Ｓａ１は半田バンプ３ｂの中央部よりも断面積が小さいため、半田バンプ３ｂの周縁部には応力が集中する。これにより、凸型半田バンプ３ｂは破壊されやすくなる。要するに、半田バンプ３ｂの破壊は、シリコン基板１ａと配線基板２との線膨張係数の相違に起因して生ずる、主として剪断応力の集中によるものである。これに対し、ストレート状または高さ方向における中央部が凹んだ凹型半田バンプ３ａでは、図３に図示されている如く、同様に、応力は、凹型半田バンプ３ａの中央部から凹型半田バンプ３ａと突起電極１ｅ１との界面である接合面Ｓａ２に作用するが、この場合には、凹型半田バンプ３ａの中央部の断面積に対し接合面Ｓａ２の断面積が同等または大きいため、凹型半田バンプ３ａの周縁部への応力の集中は低減されることになる。従って、その物理的外力による応力が強く作用する半田接合エリアの周辺部、特に、最も大きく作用するコーナー部に凹型半田バンプ３ａを形成すれば、応力集中が低減され、突起電極と端子電極との接合部におけるクラックの発生或いは接合状態そのものの破壊等を抑制することができる。
【００１７】
以上のように、本実施形態の半導体パッケージ装置によれば、ＣＳＰ１の突起電極１ｅの配設エリアつまりその底面において、周辺部の突起電極１ｅ１上にはストレート状または高さ方向における中央部が凹んだ凹型半田バンプ３ａを、周辺部以外の突起電極１ｅ２上には高さ方向における中央部が突き出た凸型半田バンプ３ｂを、それぞれ選択的に配置したから、物理的外力に応じて作用する応力により半田バンプと突起電極や接続端子との接合部にクラックが発生したり、或いは接合状態そのものが破壊される不具合の発生が顕著に抑制されるとともに、半導体パッケージ全体の配線基板に対する実装接続強度が増強される。
【００１８】
次に、上記半導体パッケージ装置の製造方法について、図４乃至図７に基づき説明する。
【００１９】
まず、シリコンウエハの状態で所定のチップサイズエリア毎に図１に示すＣＳＰ１が加工形成されたウエハレベルシリコン基板を準備する。
【００２０】
次に、図４に示すように、上記ウエハレベルシリコン基板１０の封止樹脂層１０ａが被着された底面１０ｂにハードマスク１１を重ね合わせ、半田印刷を行う。そのハードマスク１１には、図５に示すように、チップサイズエリアＡｃ毎に大、小２種類の平面形状が楕円の透孔１１ｂ、１１ａがマトリクス状に穿設されている。これら透孔１１ａ、１１ｂは、ＣＳＰ１の突起電極１ｅ１、１ｅ２（図１参照）に対応させて穿設されており、チップサイズエリアＡｃの周辺部に配設された突起電極１ｅ１には小透孔１１ａが、周辺部以外の突起電極１ｅ２には大透孔１１ｂが、それぞれ対応させて配設されている。このハードマスク１１を、ウエハレベルシリコン基板１０の底面１０ｂに、合せマーク（不図示）を基準に位置を合せながら重ね合わせる。なお、透孔１１ａ、１１ｂの平面形状は、楕円でなく真円であってもよい。
【００２１】
次に、ハードマスク１１上に半田ペーストｐを供給し、スキージ１２をハードマスク１１表面に摺接させつつ矢印方向に走行させ、図６に示すように半田ペーストｐをハードマスク１１表面に沿って薄く延ばしながら大、小の透孔１１ａ、１１ｂ内に充填し、突起電極１ｅ１および突起電極１ｅ２の各先端面に、それぞれ、半田ボール形成層ｐａ、ｐｂを形成する。
【００２２】
次いで、半田ペーストｐが固化しないうちにハードマスク１１をウエハレベルシリコン基板１０の底面１０ｂからその直角方向に向けて取り外し、この後、リフロー炉に通してリフロー処理を行うと、半田ボール形成層ｐａ、ｐｂが溶融して、表面張力によりボール状に変形し、図７に示すように、チップサイズエリアＡｃ毎に各突起電極１ｅの先端面に大、小２種類の半田ボール１３ｂ、１３ａがそれぞれ形成されたウエハレベル半導体パッケージＰＧｗが得られる。この場合、図５に示すハードマスク１１の大、小透孔１１ｂ、１１ａの配置に従い、チップサイズエリアＡｃの周辺部には小半田ボール１３ａが配置され、その他の部位には大半田ボール１３ｂが配置された構成となっている。
【００２３】
これら大半田ボール１３ｂと小半田ボール１３ａとは、図８に示すように、半田の量が異なると共に、高さがＧだけ異なっている。この高さギャップＧは、ハードマスク１１の大、小透孔１１ｂ、１１ａの容積比によって異なってくる。従って、図１に示す凹型半田バンプ３ａと凸型半田バンプ３ｂを形成するのに必要な半田ボール１３ａ、１３ｂ間の高さギャップＧは、ハードマスク１１の大、小透孔１１ｂ、１１ａの容積比つまり大、小透孔１１ｂ、１１ａの開口面積或いはハードマスク１１の厚さを適正に設定することにより得られる。
【００２４】
次に、図７に図示された大、小、半田ボール１３ｂ、１３ａが配置形成されたウエハレベル半導体パッケージＰＧｗを、チップサイズエリアＡｃを区画する切離ラインＬに沿って切断する。これにより、図８に示すように、周辺部の突起電極１ｅ１先端面に小半田ボール１３ａが形成され、その他の突起電極１ｅ２先端面に大半田ボール１３ｂが形成され、全体として大、小、半田ボール１３ｂ、１３ａがマトリクス配置で設置されたＣＳＰ１が、一括して効率良く得られる。
【００２５】
次いで、上述のようにして製造された半田ボール付きＣＳＰ１を、配線基板２の所定位置に、突起電極１ｅとこれらに対応する接続端子２ａが大、小、半田ボール１３ｂ、１３ａを介して対向するように位置合せして載置する。なお、この段階では、小半田ボール１３ａに配線基板２の対応する接続端子２ａが接触していない。
【００２６】
この後、上述のＣＳＰ１が載置された配線基板２をリフロー炉に通す。これにより、大、小、半田ボール１３ｂ、１３ａが溶融し、各半田ボール１３ｂ、１３ａがＣＳＰ１の重量および自重により、対応する突起電極１ｅ２、１ｅ１先端面と接続端子２ａ間で圧縮され、側面が高さ方向の中央部に向かうに従い突き出た湾曲面をなす略柱形状になる。この際、大半田ボール１３ｂは配線基板２の重量により大きく変形するので、小半田ボール１３ａの上端が配線基板２に形成された端子電極に接触するようになり、漸次、この端子電極側に移動する。加えて、このリフロー処理の後、溶融半田が冷却されて固化する際に体積が膨張し、特に大半田ボール１３ｂは高さ方向への膨張の度合いが大きく、これにより、ＣＳＰ１が若干押し戻される状態となる。その結果、小半田ボール１３ａを挟持する周辺部突起電極１ｅ１と対応する接続端子２ａの間隔もその分だけ広がるが、小半田ボール１３ａの半田量が少ないために、この小半田ボール１３ａが溶融した後に固化して形成される半田バンプ３は、図１に示されるように、ストレート状または側面が中央部に向かうに従い凹んだ湾曲面をなす柱状の凹型半田バンプ３ａとなる。このようにして、図１に示される半導体パッケージ装置が比較的少ない工数で容易に製造される。
【００２７】
以上のように、本実施形態の半導体パッケージ装置の製造方法によれば、ウエハレベルにおいて、チップサイズエリアの周辺部の突起電極１ｅ１に対応させて凹型半田バンプ３ａを形成するための小半田ボール１３ａを、その他の突起電極１ｅ２に対しては凸型半田バンプ３ｂを形成するための大半田ボール１３ｂを、それぞれ形成し、この後、個々のＣＳＰ１に切離し、こうして得られたＣＳＰ１を配線基板２に搭載した状態でリフロ−処理を行い、搭載されたＣＳＰ１のバンプエリア周辺の突起電極１ｅ１には物理的外力による応力の接合面への集中を低減するストレート状または高さ方向における中央部が凹んだ凹型半田バンプ３ａを形成し、それら以外の突起電極１ｅ２には高さ方向における中央部が突き出た凸型半田バンプ３ｂを形成するので、半田バンプによる接合強度が大きく且つ信頼性の高い高品質の半導体パッケージ装置を、少ない工数で容易に製造することができる。
【００２８】
なお、本発明の半導体パッケージ装置とその製造方法については、上記実施形態に限定されるものではない
【００２９】
例えば、凹型半田バンプ３ａはチップサイズエリアＡｃの周辺部全てに形成せずに周辺部コーナーにのみ形成するようにしてもよく、また、全ての半田バンプを凹型半田バンプ３ａとしてもよい。
【００３０】
また、大きさの異なる半田ボールを選択配置する方法としては、印刷法に限らず、大きさの異なる複数種類の半田ボールを吸着する治具を用い、それら複数種類の半田ボールを治具で決められた所定の配置で一括付着させる方法を用いることもできる。
【００３１】
【発明の効果】
本発明の半導体パッケージ装置およびその製造方法によれば、物理的外力が最も加わり易いチップ周辺コーナー部の半田バンプを、ストレート状または高さ方向における中央部が凹んだ柱状に形成するので、換言すれば、半田バンプの高さ方向の中央部の面積に対し半田バンプの接合面における面積を同等または大きくするので、半田バンプ周縁部への応力集中を低減する作用が生じ、最も大きい応力が作用するチップ周辺コーナー部の半田バンプにクラックが発生したり或いは接合状態そのものが破壊される不具合の発生が、顕著に抑制される。その結果、耐久性に優れた半田接合部を備えた信頼性の高い半導体パッケージ装置を提供することができる。
【図面の簡単な説明】
【図１】本発明の半導体パッケージ装置の一実施形態を示す模式的側断面図である。
【図２】上記半導体パッケージ装置を示すＩＩ−ＩＩ平断面図である。
【図３】上記半導体パッケージ装置における半田バンプに作用する応力を説明する模式的説明図である。
【図４】本発明の半導体パッケージ装置の製造方法の一実施形態における印刷工程を示す説明図である。
【図５】上記印刷工程で用いるマスクの一部分を示す部分平面図である。
【図６】上記印刷工程における作用を示す部分拡大説明図である。
【図７】上記製造方法により製造されたウエハレベル半導体パッケージを示す平面図である。
【図８】上記ウエハレベル半導体パッケージの要部を示す部分的側断面図である。
【符号の説明】
１…ＣＳＰ
１ｅ、１ｅ１、１ｅ２…突起電極
１ｆ…封止樹脂
２…配線基板
２ａ…端子電極
３…半田バンプ
３ａ…凹型半田バンプ
３ｂ…凸型半田バンプ
１０…ウエハレベルシリコン基板
１１…ハードマスク
１１ａ、１１ｂ…透孔
１２…スキージ
１３…半田ボール
１３ａ…小半田ボール
１３ｂ…大半田ボール[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor package device mounted with a chip size package (hereinafter abbreviated as CSP) and a manufacturing method thereof.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, as a method of manufacturing a chip size semiconductor package, that is, a CSP, a wafer level semiconductor package manufacturing method in which a wafer is processed in the state of a semiconductor wafer to form an input / output terminal and a protruding electrode corresponding thereto, and then resin sealing is performed. It has been known. After the resin sealing, metal bumps such as solder bumps are arranged on the exposed end surfaces of the protruding electrodes, and then cut into individual chip sizes to manufacture a plurality of CSPs (for example, Patent Document 1).
[0003]
[Patent Document 1]
JP 2000-188352 (3rd page, FIG. 2)
[0004]
[Problems to be solved by the invention]
The CSP manufactured as described above is usually mounted at a predetermined position on the wiring board by solder bonding. In this case, after each protruding electrode and the corresponding terminal electrode on the wiring board are arranged to face each other via the solder bump, a reflow process is performed by passing through a reflow furnace to melt the solder bump, and the corresponding protruding electrode and terminal The electrodes are joined via solder bumps. This completes the mounting of the CSP on the wiring board.
[0005]
For the CSP mounted on the above-mentioned wiring board, physical external force is used under various circumstances such as board mounting process, distribution process after being incorporated in products such as portable devices, or when used as products. As a result, cracks are generated in the solder joints or the solder joints are broken, resulting in malfunction of the device. In this case, the stress due to the physical external force tends to act strongly in the peripheral portion of the solder joint area where the solder bumps are provided, and among them, the stress at the corner portion is the largest, and the solder joint failure is the most at the corner portion. It is easy to generate.
[0006]
An object of the present invention is to provide a highly reliable semiconductor package device having a solder joint excellent in durability against stress caused by a physical external force and a method for easily manufacturing the semiconductor package device.
[0007]
[Means for Solving the Problems]
In the semiconductor package device of the present invention, a plurality of protruding electrodes that are conductively connected to a plurality of input / output terminal electrodes are arranged in a predetermined area, and a semiconductor package in which a sealing material is provided between the protruding electrodes A semiconductor package device in which the protruding electrode and the terminal electrode corresponding to each other are joined to a wiring board having a terminal electrode via a solder bump, respectively, and at least around the area of the plurality of the solder bumps The solder bumps located at the corners are characterized by a straight shape or a columnar shape with a recessed central portion in the height direction.
[0008]
Further, in the method for manufacturing a semiconductor package device of the present invention, a plurality of protruding electrodes that are conductively connected to a plurality of input / output terminal electrodes for each predetermined chip size area on one main surface of a semiconductor wafer are provided, A sealing material made of an insulating material is filled between the projecting electrodes so that the respective front end surfaces between the projecting electrodes are exposed, solder balls having a predetermined height are formed on the respective front end surfaces of the projecting electrodes, and the semiconductor A wafer is cut into each chip size area to form a plurality of chip size semiconductor packages, and at least one of the chip size semiconductor packages is opposed to the terminal electrodes of the wiring board via the solder balls. A semiconductor package device in which the solder balls are melted by a reflow process and the corresponding protruding electrodes and terminal electrodes of the wiring board are joined. The height of the solder ball formed on each tip surface of the protruding electrode located at the corner of at least the peripheral portion of the chip size area is set to the height of the protruding electrode positioned at the center of the chip size area. Each tip surface of the protruding electrode located at the corner portion of the chip size area is subjected to a reflow process in a state where the chip size semiconductor package made smaller than the height of the solder ball formed on each tip surface is opposed to the wiring board. The solder balls to be formed in a straight shape or a columnar shape with a recessed central portion in the height direction.
[0009]
According to the semiconductor package device and the manufacturing method thereof of the present invention, the solder bumps at the corners around the chip, to which physical external force is most easily applied, are formed in a straight shape or a column shape having a recessed central portion in the height direction. For example, since the area of the solder bump bonding surface is equal to or larger than the area of the central portion of the solder bump in the height direction, the effect of reducing stress concentration on the solder bump peripheral edge occurs, and the largest stress acts. Occurrence of defects that cause cracks in the solder bumps at the corners around the chip or the bonded state itself is significantly suppressed. As a result, it is possible to provide a highly reliable semiconductor package device including a solder joint having excellent durability.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
A semiconductor package device as an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic front sectional view showing a semiconductor package device of this embodiment, and FIG. 2 is a II-II plane sectional view thereof.
[0011]
As shown in FIG. 1, the semiconductor package device includes a CSP 1 mounted on a predetermined position on a wiring board 2 by solder bonding.
[0012]
The CSP 1 includes a silicon substrate 1a obtained by cutting a silicon wafer into a chip size. An integrated circuit (not shown) is formed on the silicon substrate 1a, and a plurality of electrode pads 1b as input / output terminals are arranged in a matrix on one main surface. This one main surface is covered with an insulating film 1c except for the central portion of each electrode pad 1b. One end of the wiring 1d patterned on the surface of the insulating film 1c is electrically connected to the exposed central surface of each electrode pad 1b. A protruding electrode 1e is erected on the other end of each wiring 1d. Between the protruding electrodes 1e, a sealing resin (sealing material) 1f is filled and installed with the respective end surfaces exposed. In the CSP 1 of the present embodiment, the entire main surface (hereinafter referred to as the bottom surface) on the side where the electrode pad 1b is disposed is an area where the protruding electrode 1e is disposed.
[0013]
As shown in FIG. 2, the protruding electrodes 1 e are arranged in a matrix in an array of, for example, 5 rows × 6 columns over the entire bottom surface of the CSP 1. That is, each wiring 1d is patterned so that the protruding electrodes 1e are arranged in 5 rows × 6 columns regardless of the arrangement of the electrode pads 1b. However, the number of the protruding electrodes 1e is a simplification of the drawing, and is actually a matrix array composed of a larger number of rows and columns.
[0014]
The CSP 1 configured as described above is mounted at a predetermined position on the wiring board 2 by bonding the tip of each protruding electrode 1 e to the corresponding terminal electrode 2 a on the wiring board 2 side via the solder bump 3.
[0015]
Here, the solder bump 3 has a small sectional area and a straight shape, or the solder bump 3 disposed on the protruding electrode 1e1 disposed in the peripheral area of the bottom surface of the CSP1. The solder bumps 3a are formed in a columnar shape having a curved surface that is concave as the side faces the center, and the solder bumps 3 disposed on the protruding electrodes 1e2 other than the peripheral part have a cross-sectional area that is larger than that of the concave solder bumps 3a. The convex solder bumps 3b are formed in a columnar shape that is large and has a curved surface that protrudes toward the center.
[0016]
Here, the operation of the present invention will be described with reference to FIG. A stress caused by a difference in linear expansion coefficient between the silicon substrate 1a and the wiring substrate 2 is generated in the solder bump. As shown in FIG. 3, in the convex solder bump 3b whose central portion protrudes in the height direction, this stress is a junction that is an interface between the solder bump 3b and the protruding electrode 1e2 from the central portion having a large cross-sectional area. It acts on the surface Sa1. Here, since the joint surface Sa1 has a smaller cross-sectional area than the central portion of the solder bump 3b, stress is concentrated on the peripheral portion of the solder bump 3b. Thereby, the convex solder bump 3b is easily destroyed. In short, the breakage of the solder bumps 3b is mainly due to the concentration of shear stress caused by the difference in the linear expansion coefficient between the silicon substrate 1a and the wiring substrate 2. On the other hand, in the concave solder bump 3a having a straight shape or a recessed central portion in the height direction, similarly, as shown in FIG. 3, stress is applied from the central portion of the concave solder bump 3a to the concave solder bump 3a. This acts on the joint surface Sa2 that is the interface with the protruding electrode 1e1, but in this case, the cross-sectional area of the joint surface Sa2 is equal to or larger than the cross-sectional area of the central portion of the concave solder bump 3a. The concentration of stress on the peripheral edge will be reduced. Therefore, if the concave solder bumps 3a are formed in the peripheral portion of the solder joint area where the stress due to the physical external force acts strongly, particularly the corner portion where the stress acts most greatly, the stress concentration is reduced, and the protrusion electrode and the terminal electrode are reduced. Generation | occurrence | production of the crack in a junction part or destruction of the joining state itself can be suppressed.
[0017]
As described above, according to the semiconductor package device of the present embodiment, in the area where the protruding electrode 1e of the CSP 1 is disposed, that is, the bottom surface thereof, the central portion in the straight or height direction is recessed on the protruding electrode 1e1 in the peripheral portion. Since the concave solder bumps 3a are selectively disposed on the protruding electrodes 1e2 other than the peripheral portions, and the convex solder bumps 3b protruding in the center in the height direction are selectively disposed, the stress acting according to the physical external force As a result, the occurrence of cracks in the joints between the solder bumps and the protruding electrodes and connection terminals, or the occurrence of defects that destroy the bonding state itself, is significantly suppressed, and the mounting connection strength of the entire semiconductor package to the wiring board is reduced. Be enhanced.
[0018]
Next, a method for manufacturing the semiconductor package device will be described with reference to FIGS.
[0019]
First, a wafer level silicon substrate is prepared in which the CSP 1 shown in FIG. 1 is processed and formed for each predetermined chip size area in a silicon wafer state.
[0020]
Next, as shown in FIG. 4, the hard mask 11 is superimposed on the bottom surface 10b of the wafer level silicon substrate 10 on which the sealing resin layer 10a is adhered, and solder printing is performed. As shown in FIG. 5, in the hard mask 11, through holes 11b and 11a having two large and small planar shapes are formed in a matrix for each chip size area Ac. These through holes 11a and 11b are formed so as to correspond to the protruding electrodes 1e1 and 1e2 (see FIG. 1) of the CSP 1, and the protruding electrodes 1e1 disposed in the peripheral portion of the chip size area Ac have small through holes. The large through holes 11b are arranged corresponding to the protruding electrodes 1e2 other than the peripheral portion 11a. The hard mask 11 is overlaid on the bottom surface 10b of the wafer level silicon substrate 10 while aligning the positions with reference to an alignment mark (not shown). The planar shape of the through holes 11a and 11b may be a perfect circle instead of an ellipse.
[0021]
Next, the solder paste p is supplied onto the hard mask 11, and the squeegee 12 is caused to travel in the direction of the arrow while being in sliding contact with the surface of the hard mask 11, so that the solder paste p is moved along the surface of the hard mask 11 as shown in FIG. While extending thinly, the large and small through holes 11a and 11b are filled, and solder ball forming layers pa and pb are formed on the respective tip surfaces of the protruding electrode 1e1 and the protruding electrode 1e2.
[0022]
Next, before the solder paste p is solidified, the hard mask 11 is removed from the bottom surface 10b of the wafer level silicon substrate 10 in the direction perpendicular thereto, and then subjected to a reflow process through a reflow furnace. Pb melts and deforms into a ball shape due to surface tension. As shown in FIG. 7, two large and small solder balls 13b and 13a are formed on the tip surface of each protruding electrode 1e for each chip size area Ac. The formed wafer level semiconductor package PGw is obtained. In this case, according to the arrangement of the large and small through holes 11b and 11a of the hard mask 11 shown in FIG. 5, the small solder balls 13a are arranged in the peripheral portion of the chip size area Ac, and the large solder balls 13b are arranged in other portions. It is an arranged configuration.
[0023]
As shown in FIG. 8, the large solder balls 13b and the small solder balls 13a differ in the amount of solder and in height by G. The height gap G differs depending on the volume ratio of the large and small through holes 11b and 11a of the hard mask 11. Therefore, the height gap G between the solder balls 13a and 13b necessary for forming the concave solder bump 3a and the convex solder bump 3b shown in FIG. 1 is large in the hard mask 11 and the volume of the small through holes 11b and 11a. It can be obtained by appropriately setting the ratio, that is, the opening area of the large through holes 11b and 11a or the thickness of the hard mask 11.
[0024]
Next, the wafer level semiconductor package PGw on which the large and small solder balls 13b and 13a shown in FIG. 7 are arranged and cut is cut along a cutting line L that divides the chip size area Ac. As a result, as shown in FIG. 8, a small solder ball 13a is formed on the tip surface of the protruding electrode 1e1 in the peripheral portion, and a large solder ball 13b is formed on the tip surface of the other protruding electrode 1e2. CSP1 in which the balls 13b and 13a are installed in a matrix arrangement can be obtained efficiently in a lump.
[0025]
Next, the solder ball CSP 1 manufactured as described above is placed at a predetermined position on the wiring board 2 so that the protruding electrodes 1e and the corresponding connection terminals 2a are large and small, with the solder balls 13b and 13a facing each other. And align and place. At this stage, the corresponding connection terminal 2a of the wiring board 2 is not in contact with the small solder ball 13a.
[0026]
Thereafter, the wiring board 2 on which the above-described CSP 1 is placed is passed through a reflow furnace. As a result, the large and small solder balls 13b and 13a are melted, and the solder balls 13b and 13a are compressed between the tip surfaces of the corresponding protruding electrodes 1e2 and 1e1 and the connection terminals 2a by the weight and weight of the CSP 1, and the side surfaces are compressed. It becomes the substantially columnar shape which makes the curved surface which protruded toward the center part of the height direction. At this time, since the large solder ball 13b is largely deformed by the weight of the wiring board 2, the upper end of the small solder ball 13a comes into contact with the terminal electrode formed on the wiring board 2, and gradually moves to the terminal electrode side. To do. In addition, after the reflow process, the volume of the molten solder expands when the molten solder is cooled and solidified, and particularly the large solder ball 13b has a large degree of expansion in the height direction, whereby the CSP1 is slightly pushed back. It becomes. As a result, the distance between the peripheral protruding electrode 1e1 sandwiching the small solder ball 13a and the corresponding connecting terminal 2a is increased by that amount. However, since the solder amount of the small solder ball 13a is small, the small solder ball 13a is melted. As shown in FIG. 1, the solder bump 3 formed by solidification later becomes a column-shaped concave solder bump 3a having a straight shape or a curved surface that is concave as the side faces toward the center. In this way, the semiconductor package device shown in FIG. 1 is easily manufactured with relatively few man-hours.
[0027]
As described above, according to the manufacturing method of the semiconductor package device of the present embodiment, the small solder balls 13a for forming the concave solder bumps 3a corresponding to the protruding electrodes 1e1 in the peripheral portion of the chip size area at the wafer level. For the other protruding electrodes 1e2, large solder balls 13b for forming the convex solder bumps 3b are respectively formed, and then separated into individual CSP1, and the CSP1 thus obtained is applied to the wiring board 2. The reflow treatment is performed in the mounted state, and the protruding electrode 1e1 around the bump area of the mounted CSP 1 has a straight shape or a central portion in the height direction that reduces stress concentration on the joint surface due to a physical external force. Concave solder bumps 3a are formed, and other protruding electrodes 1e2 are provided with convex solder bumps 3b protruding from the center in the height direction. Since formed, the semiconductor package device bonding strength of large and reliable high quality due to the solder bumps can be easily manufactured by a reduced number of steps.
[0028]
The semiconductor package device and the manufacturing method thereof according to the present invention are not limited to the above embodiment.
For example, the concave solder bumps 3a may be formed only in the peripheral corners without being formed in the entire peripheral part of the chip size area Ac, or all the solder bumps may be the concave solder bumps 3a.
[0030]
In addition, the method for selectively arranging solder balls having different sizes is not limited to the printing method, and a jig for adsorbing plural types of solder balls having different sizes is used, and the plural types of solder balls are determined by the jig. It is also possible to use a method of making a lump attachment in a predetermined arrangement.
[0031]
【The invention's effect】
According to the semiconductor package device and the manufacturing method thereof of the present invention, the solder bumps at the corners around the chip, to which physical external force is most easily applied, are formed in a straight shape or a column shape having a recessed central portion in the height direction. For example, since the area of the solder bump bonding surface is equal to or larger than the area of the central portion of the solder bump in the height direction, the effect of reducing stress concentration on the solder bump peripheral edge occurs, and the largest stress acts. Occurrence of defects that cause cracks in the solder bumps at the corners around the chip or the bonded state itself is significantly suppressed. As a result, it is possible to provide a highly reliable semiconductor package device including a solder joint having excellent durability.
[Brief description of the drawings]
FIG. 1 is a schematic sectional side view showing an embodiment of a semiconductor package device of the present invention.
FIG. 2 is a II-II plane sectional view showing the semiconductor package device.
FIG. 3 is a schematic explanatory view illustrating stress acting on a solder bump in the semiconductor package device.
FIG. 4 is an explanatory view showing a printing process in an embodiment of a method for manufacturing a semiconductor package device of the present invention.
FIG. 5 is a partial plan view showing a part of a mask used in the printing process.
FIG. 6 is a partially enlarged explanatory view showing an operation in the printing process.
FIG. 7 is a plan view showing a wafer level semiconductor package manufactured by the manufacturing method.
FIG. 8 is a partial side sectional view showing a main part of the wafer level semiconductor package.
[Explanation of symbols]
1 ... CSP
1e, 1e1, 1e2 ... protruding electrode 1f ... sealing resin 2 ... wiring substrate 2a ... terminal electrode 3 ... solder bump 3a ... concave solder bump 3b ... convex solder bump 10 ... wafer level silicon substrate 11 ... hard mask 11a, 11b ... Through hole 12 ... Squeegee 13 ... Solder ball 13a ... Small solder ball 13b ... Large solder ball

Claims

A wiring board having a plurality of terminal electrodes, a plurality of protruding electrodes that are conductively connected to a plurality of input / output terminal electrodes, disposed in a predetermined area, a semiconductor package provided with a sealing material between the protruding electrodes, A semiconductor package device in which the protruding electrodes and the terminal electrodes corresponding to each other are joined via solder bumps,
2. A semiconductor package device, wherein a solder bump positioned at least at a corner portion around the area among the plurality of solder bumps is formed in a straight shape or a column shape having a recessed central portion in the height direction.

Among the plurality of solder bumps, the solder bump located at the periphery of the area is formed in a straight shape or a columnar shape with a recessed central portion in the height direction, and the solder bump located in the central portion of the area is in the height direction. The semiconductor package device according to claim 1, wherein the semiconductor package device is formed in a columnar shape with a protruding central portion.

A plurality of protruding electrodes electrically connected to a plurality of input / output terminal electrodes for each predetermined chip size area on one main surface of the semiconductor wafer,
Filled with a sealing material made of an insulating material between the protruding electrodes so that each tip surface between the protruding electrodes is exposed,
A solder ball having a predetermined height is formed on each tip surface of the protruding electrode,
Cutting the semiconductor wafer for each chip size area, and a plurality of chip size semiconductor packages,
At least one of the chip size semiconductor packages is arranged such that each protruding electrode faces the terminal electrode of the wiring board via the solder ball,
A method of manufacturing a semiconductor package device, wherein the solder balls are melted by a reflow process, and the corresponding protruding electrodes and terminal electrodes of the wiring board are joined.
Solder formed on each tip surface of the protruding electrode located at the center of the chip size area with the height of the solder ball formed on each tip surface of the protruding electrode located at the corner portion of at least the peripheral portion of the chip size area A reflow process is performed on the chip size semiconductor package, which is smaller than the height of the ball, facing the wiring board, and solder balls formed on the respective end surfaces of the protruding electrodes located at the corners of the chip size area are straightened. A method for manufacturing a semiconductor package device, characterized in that the central portion in the shape or height direction has a recessed columnar shape.

4. The method of manufacturing a semiconductor package device according to claim 3, wherein the solder balls are formed by printing using a mask having through holes corresponding to the protruding electrodes.

In the mask, at least the size of the through hole corresponding to the protruding electrode located in the corner portion around the chip size area is formed larger than the size of the through hole corresponding to the other protruding electrode. A method for manufacturing a semiconductor package device according to claim 4.