JP2004335611A - Semiconductor inspection apparatus and inspection method, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor inspection apparatus and an inspection method capable of obtaining the information of height and widthwise directions of a portion to be inspected, and a semiconductor device using the same. <P>SOLUTION: A stage 11 has a very subtle round shape, e.g. along a Y direction, and is controlled to move so that a portion P1 to be inspected is always included on the top T1 of a wafer 10. An inspection beam generating mechanism 121 irradiates the portion to be inspected on the wafer 10 with an inspection light Lin1 so as to have an incident angle θ. An inspection light generating mechanism 122 irradiates an inspection light Lin2 in parallel with a tangent direction of the wafer 10 and immediately above the portion P1. A detecting mechanism 131 for detecting a reflection light Lre1 of the inspection light Lin1 from the top of the wafer 10 and a detecting mechanism 132 for detecting the inspection light Lin2 passing if a foreign matter does not exist are provided. An operation control mechanism 14 obtains information including the information of the height and width of an object at an inspection point according to correlation of the data of each detection amount obtained by the mechanisms 131, 132. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to semiconductor device manufacturing, and more particularly, to a semiconductor inspection apparatus and an inspection method for detecting an abnormality such as a pattern defect or the attachment of a foreign substance on a semiconductor wafer, and a semiconductor device including the use thereof.
[0002]
[Prior art]
With the increase in the functions of LSIs, chip products are constantly required to be integrated on a large scale and to reduce design rules. Then, it is necessary to secure as many chip products as possible from a single semiconductor wafer according to the design rule at that time, such as logic products and memory products. In addition, the mass production must be performed with uniform performance and high yield.
[0003]
The number of defects in the wafer increases or decreases due to the search for optimization conditions and process control in the LSI manufacturing process. Inspection of foreign matter adhering to a wafer due to pattern defects or particles generated due to a defect in an exposure pattern is generally achieved by a comparative inspection. That is, an image of the same pattern area in an adjacent integrated circuit chip area is fetched and compared and inspected. The inspection speed of the comparative inspection by taking in the image differs depending on the inspection magnification and the inspection mode, and depending on the inspection recipe, it affects the actual efficiency of the production line.
[0004]
In addition, there is also a technique for detecting a defect such as a foreign substance adhesion by capturing irregular reflection of inspection light instead of an image. This technique is highly dependent on the light receiving sensitivity of the inspection light and has a high possibility of detecting a defect up to a portion that does not need to be recognized as a defect. Conventionally, for example, a foreign substance inspection on a deposition surface of an aluminum thin film has been disclosed, but a technique as an improvement measure has been disclosed (see Patent Document 1). This technology utilizes the fact that the directivity of the scattered light differs from that of a laser beam projected onto a deposition surface of an aluminum thin film at a predetermined angle when it is applied to a foreign substance.
[0005]
[Patent Document 1]
JP-A-6-174655 (pages 4, 5; FIG. 2)
[0006]
[Problems to be solved by the invention]
However, in the above-mentioned Patent Document 1, although the accuracy of foreign matter determination is improved, information on the size (height and width) of the foreign matter cannot be obtained as to whether it is appropriate as a defect.
The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor inspection device, an inspection method, and a semiconductor device that can obtain information on the height and width of an inspection point.
[0007]
[Means for Solving the Problems]
A semiconductor inspection apparatus according to the present invention includes a stage capable of supporting a semiconductor wafer while warping it in a round shape along an X direction or a Y direction and capable of controlling movement so that an inspection portion is included on a top of the semiconductor wafer; A first inspection light generating mechanism that irradiates a first inspection light at a predetermined incident angle to the inspection location above, and a first inspection light that detects the first inspection light reflected from at least the semiconductor wafer (1) a detection mechanism, a second inspection light generating mechanism that irradiates a second inspection light parallel to a tangential direction to the semiconductor wafer and directly above the inspection location, and the second inspection light that passes at least immediately above the inspection location A second detection mechanism for detecting the light intensity, and the inspection location relatively determined according to the correlation between the data on the detected light quantity obtained by the first detection mechanism and the data on the detected light quantity obtained by the second detection mechanism. And arithmetic control mechanism for checking the status, characterized by comprising a.
[0008]
According to the semiconductor inspection apparatus of the present invention, the first inspection light generation mechanism and the first detection mechanism, and the second inspection light generation mechanism and the second detection mechanism are provided. One is a first inspection light having a predetermined incident angle, the other is a second inspection light having no incident angle, and the correlation between the light receiving detection degrees of these two is used. Further, a stage is provided to support the semiconductor wafer while warping it into a round shape so that the inspection location is always at the top. Thereby, detailed information on the height direction of the inspection location can be obtained, and the inspection accuracy can be improved.
[0009]
In the above-described semiconductor inspection apparatus according to the present invention, preferably, the arithmetic control mechanism measures or evaluates at least a height and a width of the object at the inspection location. That is, the target object is analyzed in detail from the correlation between the first and second inspection light beams and the degree of detection of the light reception. Further, the first inspection light generation mechanism and the second inspection light generation mechanism are operated exclusively. Thus, highly accurate information can be obtained using the same inspection light and detection mechanism.
[0010]
A semiconductor inspection method according to the present invention includes a step of supporting a semiconductor wafer while warping it in a round shape along an X direction or a Y direction and moving the semiconductor wafer so that an inspection portion is included at the top of the semiconductor wafer, and at a predetermined timing, respectively. Irradiating a first inspection light having a predetermined incident angle on the inspection location, and a second inspection light in parallel with a tangential direction to the semiconductor wafer and directly above the inspection location; A step of obtaining at least information on the height of the object at the inspection location in accordance with the correlation of the light intensities of the respective inspection light beams captured by the plurality of light receiving units around the semiconductor wafer.
[0011]
According to the semiconductor inspection method according to the present invention, the top portion of the semiconductor wafer supported while being warped into a round shape is included in the inspection location, the first inspection light having a predetermined incident angle, and the horizontal inspection light having no incident angle. The inspection light of No. 2 is applied to the inspection location. With respect to both of these inspection lights, information on the height of the object at the inspection location is obtained from the correlation between the degree of detection of the received light such as reflected light and transmitted light.
[0012]
The semiconductor inspection method according to the present invention has at least one of the following features as a preferred embodiment.
The inspection step is to compare inspection locations of a predetermined pattern adjacent to each other across a scribe line area of the semiconductor wafer, and determine whether or not the inspection location is abnormal based on whether the comparison result is within a predetermined range. It is characterized by.
The inspection step is characterized in that a specified range is provided in information including at least the height and width of the object at the inspection location, and whether or not the inspection location is abnormal is determined based on whether the information is within the specified range. I do.
When an abnormality is determined in the inspection location, the inspection location is moved to a predetermined pattern area different from the predetermined pattern area including the inspection location.
[0013]
According to another aspect of the invention, there is provided a semiconductor device formed using any one of the semiconductor inspection apparatuses or semiconductor inspection methods described above. Mass production of semiconductor devices with high yield while maintaining reliability can be expected.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram showing a main part of the semiconductor inspection device according to the first embodiment of the present invention. A semiconductor wafer (hereinafter, also referred to as a wafer) 10 includes a wafer in the course of manufacturing a semiconductor process, and has a predetermined pattern region of an integrated circuit or the like repeatedly arranged with a scribe line (not shown) interposed therebetween. The stage 11 supports the wafer 10 while warping it in a round shape along the X direction or the Y direction, and is configured to be able to control the movement so that the inspection point P1 is always included in the top T1 of the wafer 10. In order to realize such a configuration, the stage 11 has, for example, a very slight round shape along the Y direction. The mounted wafer 10 has a thin shape of 725 μm or less, and has a round shape according to the round shape of the stage 11. For example, the stage 11 is configured such that the height difference h1 between the top T1 and the lowest part of the wafer 10 is a predetermined value in the range of 1 to 5 μm. The stage 11 includes a positioning device such as a piezo actuator (not shown), and can variably control the top T1 of the wafer 10 as indicated by an arrow A1 and can control the movement in the X and Y directions. As a result, the inspection locations are sequentially moved on the semiconductor wafer 10.
[0015]
The inspection light generating mechanism 121 irradiates the inspection position P1 on the wafer 10 with the inspection light Lin1 at an incident angle θ. The incident angle θ is selected from a range of 0 ° to 10 °. The inspection light generating mechanism 122 irradiates the inspection light Lin2 parallel to the tangential direction to the wafer 10 having the round shape and directly above the inspection location P1. That is, the incident angle of the inspection light Lin2 with respect to the horizontal plane is zero, and the inspection light Lin2 passes just above the inspection point P1 unless there is an object to be detected at the inspection point P1. The distance by which the passing inspection light Lin2 is separated from the top T1 of the wafer 10 serving as the inspection location may be determined according to the height of the foreign matter (defect) that must be detected. As the inspection light Lin1 and Lin2, for example, laser light having the same wavelength and having a wavelength that does not affect the irradiation location (inspection location) is selected. For example, a He-based laser, a Ne-based laser or the like can be considered. It is desirable that the beam spot diameter of such a laser beam be variable. This is because it is better that the beam spot diameter can be adjusted according to the size of the foreign matter to be detected.
[0016]
Further, a detection mechanism 131 that receives and detects the reflected light Lre1 of the inspection light Lin1 from above the wafer 10 is provided around the upper part of the wafer 10. The detection mechanism 131 includes, for example, a plurality of photomultiplier tubes (PMTs 1 to 4). The detection mechanism 131 includes a photomultiplier tube PMT1 installed so that the light receiving unit faces at least in the regular reflection direction when the inspection light Lin1 is applied to the mirror surface. Further, a detection mechanism 132 that detects and detects the inspection light Lin2 passing just above the wafer 10 is provided. The detection mechanism 132 is, for example, a photomultiplier tube (PMT0) similar to the detection mechanism 131.
[0017]
That is, the detection mechanism 131 captures the scattered reflected light Lre1 of the inspection light Lin1 applied to the target object at the inspection location by using the PMTs 1 to 4. Further, the detection mechanism 131 captures the scattered reflected light Lre2 of the inspection light Lin2 applied to the target object at the inspection location by using the PMTs 1 to 4. The detection mechanism 132 catches the inspection light Lin2 that passes immediately above the inspection location with the PMT0. In addition, the detection mechanism 132 may capture the scattered reflected light Lre1 of the inspection light Lin1 applied to the target object at the inspection location with the PMT0.
[0018]
The arithmetic control mechanism 14 is a mechanism for setting an inspection method of the semiconductor inspection apparatus. The arithmetic and control unit 14 includes a memory unit, and relatively inspects the state of the inspection location according to the correlation between the detected light amount data obtained by the detection mechanism 131 and the detected light amount data obtained by the detection mechanism 132. I do. That is, the arithmetic and control unit 14 obtains information including at least the height and width of the object at the inspection location from the correlation between the light intensities obtained by the detection mechanisms 131 and 132.
[0019]
The arithmetic and control unit 14 determines whether the obtained information on the height and width of the object at the inspection location is abnormal by comparing it with the information on the inspection location in the same adjacent predetermined pattern. The specified range for determining the abnormality is set in consideration of the manufacturing process. The setting may be changed by the input unit 15. Thus, the inspection location can be inspected for defects, foreign matter, and the like. Further, it can be determined whether or not the detected defect, foreign matter, or the like affects the yield. The output unit 16 displays the abnormal location obtained by the arithmetic and control unit 14 on, for example, a map on a wafer.
[0020]
In addition, the arithmetic control mechanism 14 sets a limit on the number of abnormalities in the inspection location, and when the number reaches a specified number in a predetermined pattern area (chip area) to be inspected, a predetermined pattern area (chip area) including the inspection location is set. The inspection location may be moved to another predetermined pattern area (chip area). Therefore, the movement of the stage 11 may be controlled based on the inspection result in the arithmetic and control unit 14. This makes it possible to avoid unnecessary inspection of a chip area including a large number of abnormal locations.
[0021]
FIG. 2 is a timing chart of the inspection light irradiation and detection operation. FIGS. 3A and 3B are schematic diagrams of inspection light incidence and reflection on an inspection location. The stage 10 supports the wafer 10 in a round shape, and scans the wafer 10 in a predetermined direction so that the inspection point is always included on the top T1 of the wafer 10. With the movement of the wafer 10, the inspection light is irradiated with the inspection light Lin1 by the inspection light generation mechanism 121 and the inspection light Lin2 by the inspection light generation mechanism 122 at exclusive timing. The inspection light Lin1 hitting the inspection location is irregularly reflected, and the detection mechanism 131 (or 132) captures the reflected light Lre1. The inspection light Lin2 passes right above the inspection location or is irregularly reflected upon hitting the object, and the detection mechanism 132 captures the inspection light Lin2 that has passed, and the detection mechanism 131 captures the reflected light Lre2.
[0022]
As shown in FIGS. 3A and 3B, there is a large difference in the light intensity detected and received by each of the PMTs 0 to 4 when an abnormal foreign substance is present at the inspection location and when it is not present. The arithmetic and control unit 14 obtains information including at least the height and width of the object at the inspection location according to the degree of detection of the light intensity of the reflected lights Lre1 and Lre2.
[0023]
According to the above embodiment and method, the stage 11 that warps and supports the wafer 10 in a round shape controls the movement so that the top of the wafer 10 is always included in the inspection location. Further, an inspection light generation mechanism 121 and a detection mechanism 131, and an inspection light generation mechanism 122 and a detection mechanism 132 are provided. One is the inspection light Lin1 having a predetermined incident angle θ, and the other is the inspection light Lin2 having no incident angle. By using the correlation between the two light reception detection degrees, information including at least the height and width of the object at the inspection location can be obtained. As a result, it is possible to inspect and determine whether or not there is a defect, a foreign substance, or the like at the inspection location. As a result, the inspection accuracy of the defect (foreign matter) on the wafer can be improved.
[0024]
FIG. 4 is a block diagram showing a main part of a semiconductor inspection device according to a second embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals. The arithmetic and control unit 24 takes in the manufacturing process reference data. The arithmetic control mechanism 24 controls the inspection light as shown in FIG. 2, and the information on the height and the width at the inspection location obtained by the detection mechanisms 131 and 132 is compared with the specified range set in comparison with the manufacturing process. To determine if it is large. That is, it is determined whether the information including the height and width of the target object at the inspection location is normal by comparing with information of the manufacturing process reference data instead of comparing with information of the same adjacent predetermined pattern. . The output unit 16 displays an abnormal location obtained by the arithmetic and control unit 24 on, for example, a map on a wafer.
[0025]
As described above, according to the present invention, detailed information on the height and width directions of an object at an inspection location can be obtained using inspection light having a predetermined incident angle and inspection light having no incident angle. Preferably, a specified range is provided in information on the height and width of the object at the inspection location or comprehensive information including the information, and an abnormality in the inspection location is recognized based on information outside the specified range. In addition, if one pattern area including an abnormal location is skipped and moved to another inspection location, there is an advantage that memory overflow can be avoided. This can be reflected in optimization of defect inspection in an actual device product. This contributes to mass production of high-yield semiconductor devices while maintaining reliability. As a result, it is possible to provide a semiconductor inspection device and an inspection method capable of obtaining information in the height and width directions of an inspection portion, and a highly reliable semiconductor device using the same.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a main part of a semiconductor inspection device according to a first embodiment.
FIG. 2 is a timing chart of inspection light irradiation and detection operations.
FIG. 3 is a schematic diagram of inspection light incidence and reflection on an inspection location.
FIG. 4 is a block diagram showing a main part of a semiconductor inspection device according to a second embodiment.
[Explanation of symbols]
Reference Signs List 10: semiconductor wafer, 11: stage, 121, 122: inspection light generation mechanism, 131, 132: detection mechanism, 14, 24: arithmetic control mechanism, 15: input unit, 16: output unit.

Claims (9)

A stage capable of supporting the semiconductor wafer while warping it in a round shape along the X direction or the Y direction and controlling the movement so that an inspection point is included at the top of the semiconductor wafer;
A first inspection light generation mechanism for irradiating the inspection location on the semiconductor wafer with a first inspection light at a predetermined incident angle;
A first detection mechanism for detecting the first inspection light reflected from at least the semiconductor wafer;
A second inspection light generation mechanism that irradiates a second inspection light in parallel with a tangential direction to the semiconductor wafer and directly above the inspection location;
A second detection mechanism that detects at least the second inspection light passing directly above the inspection location;
An arithmetic control mechanism for relatively inspecting the state of the inspection location in accordance with the correlation between the detected light quantity data obtained by the first detection mechanism and the detected light quantity data obtained by the second detection mechanism;
A semiconductor inspection device comprising: 2. The semiconductor inspection apparatus according to claim 1, wherein the arithmetic control mechanism measures or evaluates at least a height and a width of the object at the inspection location. 3. The semiconductor inspection apparatus according to claim 1, wherein the first inspection light generation mechanism and the second inspection light generation mechanism are operated exclusively. Supporting the semiconductor wafer while warping it in a round shape along the X direction or the Y direction, and moving the semiconductor wafer so that an inspection point is included on the top of the semiconductor wafer;
At each predetermined timing, a first inspection light having a predetermined incident angle on the inspection location, and a step of irradiating the second inspection light parallel to a tangential direction to the semiconductor wafer and directly above the inspection location,
An inspection step of obtaining at least information on the height of an object at the inspection location according to a correlation of light intensities captured by the plurality of light receiving units around the semiconductor wafer with each of the first and second inspection lights;
A semiconductor inspection method comprising: The inspection step compares the inspection locations of a predetermined pattern adjacent to each other across a scribe line area of the semiconductor wafer, and determines whether the inspection location is abnormal based on whether the comparison result is within a predetermined range. The semiconductor inspection method according to claim 4, wherein: The inspection step provides a specified range in the information including at least the height and width of the object at the inspection location, and determines whether there is an abnormality in the inspection location based on whether the information is within the specified range. 5. The semiconductor inspection method according to claim 4, wherein: When an abnormality is determined in the inspection location, the inspection location is moved to a predetermined pattern area different from the predetermined pattern area including the inspection location. A semiconductor device formed by utilizing the semiconductor inspection device according to claim 1.
The semiconductor inspection method according to any one of claims 4 to 6, wherein A semiconductor device formed by utilizing the semiconductor inspection method according to claim 4.

Images