JP2004327982A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having high reliability and capable of improving a processing yield and productivity, and its manufacturing method. <P>SOLUTION: A manufacturing method of the semiconductor device comprises: forming a surface electrode 6 in a semiconductor element 1; forming a solder layer 4 on a main surface of the surface electrode 6 by plating; disposing the semiconductor element 1 on a submount 2 so that the solder layer 4 is brought into contact with the main surface of the submount 2; and fixing the submount 2 and the semiconductor element 1 through the solder layer 4. Since a processing yield and productivity of the semiconductor device can be improved, this method can be used for manufacturing various semiconductor devices. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same. In particular, the present invention relates to a semiconductor laser device in which a semiconductor laser device is mounted on a submount and a method of manufacturing the semiconductor laser device.

  Optical semiconductor elements, particularly semiconductor lasers, have been put into practical use in the fields of optical information processing and optical communication, and high output of lasers is required in both fields. However, if the output is increased, the reduction in reliability due to heat generation of the element becomes a problem. Therefore, it is important to develop an element structure and a manufacturing process that can ensure high reliability.

  For example, in order to promote heat dissipation of a semiconductor laser device, a structure in which a material having a high thermal conductivity as a heat sink is used as a base, and a material having a thermal expansion coefficient close to that of the laser device is used as a submount, and the respective components are sequentially stacked and fixed is well known. (For example, see Patent Documents 1 and 2).

  FIG. 12 is a side sectional view showing a configuration of a conventional semiconductor laser device. As shown in FIG. 12, the conventional semiconductor laser device has a configuration in which a semiconductor laser element 101, a submount 102, and a base 103 are stacked. The semiconductor laser device 101 has a semiconductor laminate 131, a back electrode 107, and a front electrode 106. On one surface of the semiconductor laminated body 131 on which the active layer 111 is formed, a surface electrode 106 which is a pattern electrode composed of a plurality of patterned layers is formed, and on the other surface of the semiconductor laminated body 131, a plurality of patterned electrodes are formed. A back electrode 107 made of a layer is formed. The light emitting point 112 of the semiconductor laser device is shown in the drawing.

  The submount 102 has an electrically insulating material 132, a front electrode 108, a solder layer 104, a back electrode 109, and a solder layer 105. On one surface of the electrically insulating material 132, a surface electrode 108 composed of a plurality of layers and the solder layer 104 are formed, and on the other surface, a back electrode 109 composed of a plurality of layers is formed. A layer 105 is formed.

  The base 103 has a heat radiator 133 and an Au plating layer 110. The Au plating layer 110 is formed on the surface of the heat radiator 133.

  The semiconductor laser element 101 and the submount 102 shown in FIG. 10, and the submount 102 and the base 103 are fixed by melting and fixing the solder layers 104 and 105 therebetween, as shown in FIG. A device is formed.

  When the driving current of such a conventional semiconductor laser element 101 is in a large current range of, for example, several tens mA to several hundred mA, the amount of heat generated is large. A heat radiator made of metal such as Cu covered with the formed metal film 110 or the like is used. Further, for the submount 102, a material having a thermal expansion coefficient close to that of the semiconductor laser element 101 is selected in consideration of a bonding process such as melting and fixing of the solder layers 104 and 105 and heat generated during operation of the semiconductor laser device.

  As a material used for the solder layer 104, an alloy of Au and Sn (hereinafter, referred to as an AuSn alloy), an alloy of Ag and Sn (hereinafter, referred to as an AgSn alloy), PbSn, AuSi, AuGe, AuZe, and InSb are generally cited. Can be In particular, AuSn alloys are often used in semiconductor laser devices because of their excellent corrosion resistance, high-temperature strength, and thermal shock resistance and low specific resistance.

  In particular, since the AuSn alloy and the AgSn alloy have low melting points, they also have an effect that they can be fixed at a low temperature. For example, although the melting point of Au is 1063 ° C., a sharp decrease in the melting point is seen by adding Sn, and the eutectic point of 278 ° C. in the eutectic composition of Au (80 wt%) — Sn (20 wt%). Down to When the Sn content is higher than this, the melting point tends to increase gradually.

  Ag also contains Sn, which causes a sharp drop in the melting point, and lowers the eutectic point of 221 ° C. in the eutectic composition of Ag (3.5 wt%) — Sn (96.5 wt%). The AgSn alloy can be mounted at a lower temperature than the AuSn alloy. When the Sn content is higher than this, the melting point tends to increase gradually.

  In mounting the semiconductor laser element 101, it is required to fix at a lower temperature for the following reasons. Hereinafter, the case where the AuSn alloy is used as the material of the plating layer will be described. The surface electrode 106 provided on the semiconductor laser element 101 and the surface electrode 108 provided on the surface of the submount 102 are mainly made of a plating layer mainly composed of Au. When heat bonding is performed, the AuSn alloy and Au of the solder layer 104 are further alloyed and integrated and fixed. When the temperature is lowered to room temperature after bonding, stress is accumulated inside the semiconductor laser element 101 due to a dimensional change of both materials caused by a difference in thermal expansion coefficient between the semiconductor laser element 101 and the submount 102. This causes distortion in the semiconductor laser device 101, and greatly reduces the reliability of the semiconductor laser device 101.

  Therefore, as the material of the submount 102, a material such as SiC, AlN, diamond, or Mo having physical properties such as a thermal expansion coefficient and a Young's modulus close to those of the material of the semiconductor laser element 101 is selected. Furthermore, in order to reduce the thermal stress, it is required to fix at a lower temperature, and a measure is taken to select a low melting point solder material for the solder layer 104.

  In the joining of the solder layer 104 and the surface electrodes 106 and 108 by the AuSn alloy, the content of Sn with respect to the total amount of Au becomes Au (80 wt%)-Sn (20 wt%) eutectic composition although these are alloyed. In that case, fixation at the lowest melting point is possible. However, when a deviation from the eutectic composition occurs, the melting point increases. Therefore, if the fixing temperature is set in accordance with the lowest melting point, the AuSn alloy of the solder layers 104 and 105 does not melt, or sufficient fixing strength cannot be obtained even if the AuSn alloy melts. In order to avoid this, if the fixing temperature is increased, thermal stress increases and distortion occurs. Therefore, it is important to control the Sn content with respect to the total amount of Au in the surface electrodes 106 and 108 and the solder layer 104.

  Here, a method for forming the solder layer 104 using an AuSn alloy will be described. The first formation method is a method by vapor deposition, in which Au and Sn are each used as a vapor deposition source and an Au layer and a Sn layer are alternately laminated to form a desired thickness (for example, see Patent Document 3). There is a method of forming an AuSn layer to a desired thickness by using an AuSn alloy whose composition is controlled as an evaporation source (for example, see Patent Document 4). According to these methods, the thickness and composition of the Au layer and the Sn layer can be controlled with the thickness accuracy possible by vapor deposition.

  However, the thickness of the solder layer 104 is desirably 1 μm or more in order to obtain a stable fixing strength, and in order to obtain a desired thickness, the film forming time becomes longer and the amount of the vapor deposition material increases. There is a problem that it becomes expensive.

  The second method is a method in which the Au layer and the Sn layer are formed by plating, respectively. In the case where the Au plating layer and the Sn plating layer are sequentially laminated, and then the heat treatment is performed to form the AuSn alloy solder layer 104. Alternatively, there may be a case where an Au plating layer is formed on one of the opposing surfaces of the semiconductor laser element 101 and the submount 102 to be fixed, and an Sn plating layer is formed on the other, and the two are contacted and heated so as to be fixed. For example, see Patent Document 5). According to this method, a thick layer can be obtained in a short time, so that the solder layer 104 can be manufactured at a lower cost than the method by vapor deposition.

  Next, the mounting of the semiconductor laser device on the submount 102 will be described.

  In general, the mounting mode of the semiconductor laser element 101 on the submount 102 is a junction-down (hereinafter, J-down) method in which the surface electrode 106 side of the semiconductor laser element 101 is fixed on the submount 102. Many. In the semiconductor laser element 101, the active layer 111 is formed on a side near the surface electrode 106. The J-down method has a configuration in which the surface electrode 106, which is an electrode close to the active layer 111 that generates heat, is fixed to the submount 102 so as to approach the base 103, which is a radiator. Thus, heat generated in the active layer 111 can be quickly diverted to the submount 102. Therefore, the heat dissipation of the semiconductor laser device can be improved.

  However, in the case of the J-down method, since the distance between the active layer 111 including the light emitting point 112 and the submount 102 is only a few μm, the solder layer 104 is melted at the time of bonding and goes around the side wall of the semiconductor laser element 101. In this case, there is a problem that a short-circuit defect occurs or the laser beam is blocked by covering the light emitting point 112.

  Therefore, as shown in FIG. 10, the solder layer 104 is often formed in a pattern so that the formation area is smaller than the outer area of the semiconductor laser element 101. However, even with such a structure, if a misalignment occurs when the semiconductor laser element 101 is disposed on the submount 102, the solder material of the solder layer 104 can wrap around the side wall surface of the semiconductor laser element 101. There is.

  FIG. 11 shows components of another conventional semiconductor laser device before being fixed. FIG. 11 differs from FIG. 10 in that the solder layer 104 is not provided on the surface electrode 108 of the submount 102, This is a point formed on the surface electrode 106 of the element 101.

  As shown in FIG. 11, when the solder layer 104 is formed on the semiconductor laser element 101 side, the solder material of the solder layer 104 does not easily reach the side wall surface of the semiconductor laser element 101 even if a displacement occurs during mounting. . When a two-wavelength laser element, a GaN laser element, or the like is used as the semiconductor laser element 101, the surface electrode 106 is formed of two or more pattern electrodes having the same thickness, and the distance between the electrodes is as narrow as about 100 μm. . However, even in such a case, since the solder layer 104 does not spread more than necessary, it is possible to prevent the occurrence of short-circuit failure due to the interval between the pattern electrodes.

  Further, advantages of the case where the solder layer 104 is formed on the semiconductor laser element 101 side will be described with reference to FIGS. FIGS. 13A to 13C are explanatory views showing an example of a mounting process of a semiconductor laser element when a solder layer is formed on the submount side.

  First, as shown in FIG. 13A, the submount 102 is held at a needle-shaped suction collet 129 and arranged at a predetermined position on the base 103. Next, as shown in FIG. 13B, the semiconductor laser element 101 is held at another suction collet 130 and is arranged at a predetermined position on the submount 102. Next, as shown in FIG. 13C, the temperature is raised to the melting point of the solder layers 104 and 105, whereby the solder layer 104 and the solder layer 105 are melted at the same time. And the semiconductor laser element 101 are simultaneously fixed.

  FIGS. 14A to 14D are explanatory views illustrating an example of a mounting process of the semiconductor laser device when a solder layer is formed on the semiconductor laser device side. First, as shown in FIG. 14A, the submount 102 is held at a needle-shaped suction collet 129 and arranged at a predetermined position on the base 103. Next, as shown in FIG. 14B, the temperature is raised to the melting point of the solder layer 105 by heating, so that the solder layer 105 is melted and the base 103 and the submount 102 are fixed. Next, as shown in FIG. 14C, the semiconductor laser element 101 is held by another suction collet 130 and arranged at a predetermined position on the submount 102. Next, as shown in FIG. 14D, the solder layer 104 is melted by heating to raise the temperature to the melting point of the solder layer 104, and the submount 102 and the semiconductor laser element 101 are fixed. The semiconductor laser device may be manufactured by first fixing the semiconductor laser element 101 to the submount 102 and then fixing it to the base 103.

  In such a manufacturing process, when fixing the semiconductor laser element 101 and the submount 102, when the temperature is raised to the melting point, a load of about 10 g is applied by the suction collet 129 or 130 so as not to shift from a predetermined position. In many cases, heating is performed as it is.

  According to the method shown in FIGS. 14 (a) to 14 (d), the steps of FIGS. 14 (a) and 14 (b) and the steps of FIGS. 14 (c) and 14 (d) are different. It is possible to do at the same time at the location. Thus, there is an advantage that the production efficiency is higher than the methods shown in FIGS. 13B to 13C. In addition, since the submount 102 and the semiconductor laser element 101 are respectively fixed at a predetermined position and immediately fixed, there is an advantage that the positional accuracy is high.

  On the other hand, when the solder layer 104 is formed on the submount 102 side as shown in FIG. 13A, first, the base 103 and the submount 102 are fixed, and then the semiconductor laser element 101 is mounted on the submount. , The following problem occurs. In other words, the solder layer 104 on the submount 102 is arranged at a predetermined position on the base 103 with the surface of the solder layer 104 held by the suction collet 129. Furthermore, since the solder layer 104 is heated as it is, the solder layer 104 is also melted at the same time as the solder layer 105 is melted, and a mark of the adsorption collet 129 is formed on the surface of the solder layer 104 to generate a step. Further, there is a problem that the solder material adheres to the tip of the suction collet 129. When the solder layer 104 is melted when the base 103 and the submount 102 are fixed, Au in the surface electrode 108 is diffused to increase the melting point or oxidize. Therefore, there is a problem that the temperature required when the semiconductor laser element 101 is subsequently fixed on the submount 102 via the solder layer 104 becomes high.

  In order to solve these problems, it has been proposed that the solder materials of the solder layers 104 and 105 be different materials having different melting points, or that the composition ratio of the same solder material be changed (for example, In these methods, there is a possibility that the cost of the submount 102 increases, the fixing temperature varies, and the solder composition varies as the number of steps increases.

  On the other hand, when the solder layer 104 is formed on the semiconductor laser element 101 side as in the method shown in FIGS. 14A to 14D, the solder layer 104 is not formed on the opposing submount 102 surface. Even if the submount 102 is sucked and held by the suction collet 129 or is heated with a load applied thereto, the solder layer 104 may have a mark of the suction collet or the solder layer may adhere to the suction collet. Never. However, when the semiconductor laser element 101 on which the solder layer 104 is formed is mounted on the submount 102, the following problem occurs. For example, as disclosed in Patent Literature 5, when a solder layer 104 of AuSn alloy or the like is formed by a plating method, a thick film can be obtained in a shorter time than in a vapor deposition method. Since an alloy layer or the like is formed, the number of steps is increased. Further, since each layer is thick, the composition after alloying becomes non-uniform in the layer, and there is a problem of variation in melting point, variation in composition, and increase in stress due to segregation of Sn. Patent Document 5 proposes a method in which a pair layer in which an Au plating layer and a Sn plating layer are respectively thinned is repeatedly formed several times to control the total Sn plating thickness and Au plating thickness. However, this method requires a long working time as in the case of vapor deposition.

  Further, as described above with reference to FIG. 11, since the solder layer 104 is formed on the side of the semiconductor laser element 101, it is possible to prevent the solder material from wrapping around the side wall surface of the semiconductor laser element 101, Although there are advantages such as application of a highly efficient mounting method, there is a problem in cleavage processing.

  The cleaving process is a process of forming a plurality of semiconductor laser devices 101 integrally and then dividing the semiconductor laser devices 101 into individual semiconductor laser devices 101 when manufacturing the semiconductor laser device 101. In the following, the cleaving process and the problems that occur at that time are described with reference to the drawings. FIGS. 15A to 15C are process diagrams for explaining the cleaving process of the semiconductor laser device. As shown in FIG. 15A, a plurality of semiconductor layers including an active layer are sequentially laminated on a semiconductor substrate to form a plurality of integrally formed semiconductor laminates 131. Further, the semiconductor laser device 101 (see FIG. 11) along the cavity length direction (X direction in the figure) is provided on the surface of the semiconductor laminate 131 on the side where the semiconductor layer is formed. A plurality of cleavage grooves 121 are formed in parallel with each other at equal intervals. Next, a surface electrode 106 patterned in a lattice pattern is provided over the entire upper surface of the semiconductor layer of the semiconductor multilayer body 131 except for the cleavage region, and a back electrode 107 is provided on the entire back surface of the semiconductor multilayer body 131. Can be On the surface electrode 106, a solder layer 104 of an AuSn alloy is further formed. Since the solder layer 104 is formed in a region narrower than the surface electrode 106, a part of the surface electrode 106 is exposed so as to surround the solder layer 104. Next, in order to cut out the semiconductor laminated body 131 into a rectangle whose longitudinal direction is the Y direction in the figure, a plurality of short scribe scratches 122 are equal to the side edges of the rectangular semiconductor laminated body 131 along the resonator length direction. Formed at intervals.

  Subsequently, as shown in FIG. 15B, starting from each scribe flaw 122 (see FIG. 15A) provided on the semiconductor laminate 131 cut into a rectangle, the semiconductor laminate 131 is moved in the Y direction. The front surface electrode 106 and the back surface electrode 107 are each cleaved integrally (primary cleaving), whereby a plurality of bar-like element combined bodies 123 are obtained.

  Next, as shown in FIG. 15 (c), each bar-like element assembly 123 (see FIG. 15 (b)) is cleaved (secondary cleavage) along the cleavage groove 121, whereby a plurality of Is obtained.

  Each of the semiconductor laser elements 101 has a surface electrode 106 provided on the surface of a semiconductor laminate 131, a back electrode 107 provided on the back surface, and a solder layer 104 provided on the surface electrode 106. When a voltage is applied between the front electrode 106 and the back electrode 107, laser light is emitted from the end face formed by the primary cleavage face.

  In the above process, the primary cleavage and the secondary cleavage are usually performed by irradiating the surface of the semiconductor laminate 131 with light, and performing pattern recognition using a difference in light reflection between the surface electrode 106 region and other regions. The cleavage angle and cleavage position are adjusted from the recognized pattern. In particular, in the primary cleavage, if the cleavage direction does not match the cleavage direction of the semiconductor laminate 131, the cleavage plane does not match the crystal plane. Or the characteristics are significantly deteriorated.

  Therefore, the recognition rate of the surface electrode 106 is improved by increasing the difference in reflectance between the surface electrode 106 and another region (for example, the solder layer 104). For example, countermeasures have been taken such that one of the surface of the surface electrode 106 and the other region is roughened with an etchant or the like to reduce the flatness of the surface.

  However, since the AuSn alloy used for the solder layer 104 has extremely high flatness and high resistance to an etching solution, it is difficult to form irregularities on the surface. Therefore, there is a problem that a clear difference in reflectance between the surface electrode 106 and other regions cannot be obtained, and pattern recognition cannot be performed properly. In addition, even after the primary cleavage step, the same problem arises because there are many steps of performing pattern recognition of the shape of the surface electrode 106 to perform positioning and direction adjustment.

On the other hand, since the AuSn solder layer is dark green, the difference in color under visible light from the surface layer in other regions, for example, the surface where Pt is exposed is clear. Therefore, if pattern recognition is performed by color extraction or the like, these problems may be solved. However, in this method, the recognition becomes unstable and a device having a color identification function is expensive.
JP-A-56-27988 JP-A-63-233591 JP-A-6-69608 JP-A-8-181392 JP-A-11-204884 JP-A-11-214791 JP-A-9-172224

  The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device having high reliability and capable of improving processing yield and productivity, and a method for manufacturing the same.

  According to the method of manufacturing a semiconductor device of the present invention, a step of forming a surface electrode on a semiconductor element, a step of forming a solder layer on one main surface of the surface electrode by plating, and a step of forming the solder layer on a main surface of a submount A step of mounting the semiconductor element on the submount so that the layers are in contact with each other, and a step of fixing the submount and the semiconductor element via the solder layer.

  Further, according to the semiconductor device of the present invention, in a semiconductor device having a submount and a semiconductor element fixed via a solder layer, a surface electrode formed on a main surface on a submount side of the semiconductor element; A solder layer partially formed on the surface electrode and a coating layer formed on the entire surface of the solder layer are provided, and a part of the surface electrode is exposed.

  It is possible to provide a semiconductor device having high reliability and capable of improving processing yield and productivity and a method for manufacturing the same.

  According to the method of manufacturing a semiconductor device of the present embodiment, a step of forming a surface electrode on a semiconductor element, a step of forming a solder layer by plating on one main surface of the surface electrode, A step of mounting the semiconductor element on the submount so that the solder layer is in contact with the semiconductor element; and a step of fixing the semiconductor element to the submount via the solder layer. Therefore, a semiconductor device can be manufactured at a low temperature. In addition, no trace of the suction collet remains on the solder layer, and no solder adheres to the suction collet. Furthermore, there is no wraparound of the solder layer on the side wall of the semiconductor element. For these reasons, the reliability of the semiconductor device does not decrease.

Preferably, when the submount is fixed to the semiconductor element, a solder layer is not formed on the submount. As a result, no trace of the suction collet remains on the solder layer, and no solder adheres to the suction collet. In addition, preferably, the solder layer does not wrap around the side wall portion of the semiconductor element. Preferably, the solder layer is partially formed on the surface electrode, and the surface electrode has an exposed portion, Before mounting on the submount, a coating layer having a flatness different from that of the surface electrode is formed on the solder layer. Thereby, the pattern recognition of the surface electrode and the coating layer can be easily performed, and the semiconductor element can be positioned with high accuracy. Further, the cleavage step at the time of manufacturing the semiconductor element can be easily performed.

  Preferably, the solder layer contains an alloy of Au and Sn. Thereby, the semiconductor element can be mounted at a low temperature. Therefore, the semiconductor element is not distorted by heat at the time of fixing, and the reliability of the semiconductor element does not decrease.

  Preferably, after forming a solder layer, which is a plating of an alloy of Au and Sn, an Au-rich layer is formed on the surface of the solder layer by plating, and an etching process for roughening the surface of the Au-rich layer is performed. do. Thus, the flatness of the surface of the solder layer can be reduced, and the pattern of the semiconductor element can be easily recognized. Note that the surface roughness of the Au-rich layer may be 0.01 μm or more. Desirably, it is 0.05 μm or more.

  Preferably, the solder layer, which is a plating of an alloy of Au and Sn, is formed by applying a current to the surface electrode immersed in a plating solution to adjust a current density in the plating solution. Thus, the composition of the alloy of Au and Sn is changed, and an Au-rich layer, which is a coating layer, is formed on the surface of the solder layer. Thereby, an Au-rich layer can be easily formed.

  Preferably, the thickness of the Au-rich layer after the etching treatment is 0.02 μm or more. Thereby, oxidation of the solder layer can be prevented.

  Preferably, the Au-rich layer has an Au content of 90 wt% or more. Thereby, sufficient irregularities are formed on the surface of the Au-rich layer. Therefore, pattern recognition of the semiconductor element can be easily performed.

  Preferably, the etching treatment is a step of impregnating the Au-rich layer with a mixture of iodine and water to roughen the surface of the Au-rich layer. Thereby, the flatness of the Au-rich layer can be reduced.

  Preferably, the solder layer contains an alloy of Ag and Sn. Thus, a semiconductor device can be manufactured at a low temperature, whereby the semiconductor element is not distorted by heat at the time of fixing, and the reliability of the semiconductor element does not decrease.

Preferably, after forming a solder layer, which is a plating of an alloy of Ag and Sn,
An Au-rich layer is formed on the surface of the solder layer, and an etching process is performed to roughen the surface of the Au-rich layer. Thus, the flatness of the surface of the solder layer can be reduced, and the pattern of the semiconductor element can be easily recognized.

  Further, the Au-rich layer may be formed by plating.

  Further, the Au-rich layer may be formed by vapor deposition.

  Preferably, the thickness of the Au-rich layer after the etching treatment is 0.02 μm or more. Thereby, oxidation of the solder layer can be prevented.

  Preferably, the Au-rich layer has an Au content of 90 wt% or more. Thereby, sufficient irregularities are formed on the surface of the Au-rich layer. Therefore, pattern recognition of the semiconductor element can be easily performed.

  Further, before the step of mounting the semiconductor element on the submount, a step of fixing the base and the submount with a solder layer for a base may be included.

  Preferably, the base solder layer is formed on one of the submount and the base, and the other of the submount and the base includes the base solder layer containing an alloy of Au and Sn. In the case where the base solder layer contains an alloy of Ag and Sn, a plating layer containing Ag is formed, and in order to fix the base and the submount, the base solder layer is formed. Heat so that the layer and the plating layer are melted. Thus, even if the same material is used for the solder layer for fixing the semiconductor element and the submount and the base solder layer for fixing the submount and the base, their melting temperatures are different. Can be performed individually. Therefore, work can be performed efficiently, and work efficiency increases.

  After the step of fixing the submount and the semiconductor element via the solder layer, the method may further include a step of fixing the base and the submount with a base solder layer.

  Further, the semiconductor element may be a semiconductor laser element.

  Preferably, the surface electrode is formed on a side of the semiconductor laser device on which an active layer is formed. Thus, a semiconductor device with high heat dissipation efficiency can be manufactured.

  Preferably, in the step of forming the surface electrode, the surface electrode has a plurality of layer structures, and as at least one of the surface electrodes, a barrier layer for preventing diffusion into the inside of the semiconductor element. The method further includes the step of forming Thus, a highly reliable semiconductor device can be manufactured.

  According to the semiconductor device of the present invention, high-precision positioning is performed, so that the reliability is high.

  Preferably, the solder layer contains an alloy of Au and Sn, and the content of Sn relative to the total amount of Au is around 20 wt%. Thus, the submount and the semiconductor element are fixed at a low temperature. Therefore, the semiconductor device has high reliability.

  Preferably, the solder layer contains an alloy of Ag and Sn, and the content of Sn with respect to the total amount of Ag is around 95 wt%. Thus, the submount and the semiconductor element are fixed at a low temperature. Therefore, the semiconductor device has high reliability.

  The coating layer is made of an Au-rich layer. Thereby, high-precision positioning of the semiconductor element is performed. Therefore, the reliability of the semiconductor device is high.

  Preferably, the Au-rich layer has an Au content of 90 wt% or more. Thereby, sufficient irregularities are formed on the surface of the Au-rich layer. Therefore, the semiconductor element is positioned with high accuracy, and the reliability of the semiconductor device is high.

  Also, preferably, the formation region of the solder layer on the surface electrode is inside a surface of the semiconductor element on which the surface electrode is formed. This prevents the solder layer from wrapping around the side wall of the semiconductor element, and does not reduce the reliability of the semiconductor element.

  Further, the semiconductor element may be a semiconductor laser element.

  Preferably, in the semiconductor laser device, an active layer that emits laser light is formed on the surface electrode side. Thereby, the active layer that generates heat is configured to approach the submount, so that the heat radiation efficiency is high.

  Preferably, a base as a heat radiator is further provided, and a submount and the semiconductor element are sequentially laminated and fixed on the base. Thereby, heat radiation efficiency is high.

  Preferably, the surface electrode has a multilayer structure, and at least one of the surface electrodes has a barrier for preventing metal contained in the solder layer from diffusing into the semiconductor element. Layer. Thereby, it is possible to prevent a decrease in the reliability of the semiconductor element.

  Hereinafter, more specific embodiments of the present invention will be described.

(Embodiment 1)
First Embodiment A semiconductor device according to a first embodiment of the present invention and a method for manufacturing the same will be described with reference to the drawings. In the first embodiment, a semiconductor laser device having a configuration in which a semiconductor laser element is mounted on a submount is illustrated as the semiconductor device of the present invention. However, the present invention is not limited to this. A semiconductor device having a configuration in which another semiconductor element is mounted may be used.

  FIG. 1 is a side sectional view showing a laminated structure of the semiconductor laser device according to the first embodiment of the present invention. The semiconductor laser device according to the first embodiment includes a semiconductor laser element 1, a submount 2 and a base 3, wherein the semiconductor laser element 1 and the submount 2 are fixed with a solder layer 4, and the submount 2 and the base are fixed with a solder layer 5. 3 is fixed.

  The semiconductor laser device 1 is a high-output red semiconductor laser having a cavity length of 800 μm, a chip width of 300 μm, and a thickness of 100 μm, and a surface on which the semiconductor layer including the active layer 11 is formed is fixed to the submount 2. It is a junction-down (hereinafter, J-down) assembly method. The J-down method has a configuration in which a surface electrode 6 which is an electrode close to the active layer 11 is fixed to the submount 2. Therefore, the active layer 11 that generates heat is configured to be closer to the base 3 that is a radiator, so that the heat radiation efficiency of the semiconductor laser device is increased.

  In addition, the semiconductor laser device 1 has a semiconductor laminate 20, a front electrode 6, a solder layer 4, and a back electrode 7. On the surface side of the semiconductor laminate 20, a Cr layer 6a having a thickness of 0.05 μm, a Pt layer 6b having a thickness of 0.1 μm, an Au layer 6c having a thickness of 0.05 μm, and a The solder layers 4 mainly composed of an AuSn alloy are stacked in this order. The components other than Au and Sn contained in the solder layer 4 may be, for example, Cu or Zn.

  Here, the Cr layer 6a, the Pt layer 6b, and the Au layer 6c are formed on the entire surface of the semiconductor laser device 1 to form the surface electrode 6. The solder layer 4 containing the AuSn alloy is formed 20 μm inside each of the four sides of the surface of the semiconductor laser device 1. However, the shape of the solder layer 4 is not limited to a rectangle, but may be an island shape or a comb shape. The Pt layer 6b also serves as a barrier layer for preventing Au and Sn in the solder layer 4 and Au in the Au layer 6c from diffusing into the semiconductor laser device 1.

  The composition of the solder layer 4 is controlled so that the Sn content relative to the total amount of Au is close to 20%. On the back surface of the semiconductor laser device 1, a back electrode 7 composed of a plurality of layers is formed on the entire surface.

  The thickness of the solder layer 4 is preferably in the range of 1 μm to 10 μm. If it is less than 1 μm, it is difficult to obtain a sufficient adhesive strength between the semiconductor laser device 1 and the submount 2. Further, if the thickness of the solder layer 4 exceeds 10 μm, there is a concern that the solder material may flow around the side wall of the semiconductor laser device 1 when the semiconductor laser device 1 is mounted. When the thickness is 1 μm to 10 μm, the semiconductor laser device 1 has a sufficient adhesive force, and the solder material does not wrap around the side wall of the semiconductor laser device 1.

  Furthermore, if the solder layer 4 is formed in a region 20 μm inside each of the four sides of the surface of the semiconductor laser element 1, the solder material does not protrude during mounting. The solder layer 4 may be formed in a range in which the solder material does not protrude during mounting. For example, the solder layer 4 may be 10 μm inward from four sides of the surface of the semiconductor laser device 1. If the pattern shape of the solder layer 4 is large, the bonding area with the submount 2 becomes large, so that the heat radiation can be further improved.

  Further, the content of Sn with respect to the total amount of Au in the solder layer 4 is preferably about 20 wt%, and in this case, mounting at a low temperature of 300 ° C. or less is possible. The mounting temperature of the semiconductor laser device 1 can be set to 350 ° C. or lower even when the Sn content relative to the total amount of Au is in the range of 18 wt% to 26 wt%.

  The submount 2 has an electrically insulating material 21 having high thermal conductivity, a front electrode 8, a back electrode 9, and a solder layer 5. For example, the electric insulating material 21 is made of SiC and has a thickness of 300 μm. A surface electrode 8 is formed on the surface of the submount 2 on the side to which the semiconductor laser element 1 is fixed. The surface electrode 8 is composed of a Ti layer 8a, a Pt layer 8b, and an Au layer 8c. From the surface of the submount 2, a Ti layer 8a having a thickness of 0.1 μm and a Pt layer 8b having a thickness of 0.2 μm are formed. , 0.05 μm thick Au layers 8c are stacked in this order. On the side (back surface) of the submount 2 fixed to the base 3 (back surface), a back surface electrode 9 is formed, and further, a solder layer 5 is formed. The back surface electrode 9 includes a Ti layer 9a, a Pt layer 9b, and an Au layer 9c. From the back surface of the submount 2, a Ti layer 9a having a thickness of 0.1 μm, a Pt layer 9b having a thickness of 0.2 μm, an Au layer 9c having a thickness of 0.05 μm, and a solder layer 5 containing an AuSn alloy having a thickness of 3 μm Are stacked in this order. These are formed on the entire back surface. Here, the solder layer 5 may be made of a solder other than the AuSn alloy, or may be an Ag paste or the like.

  The base 3 has a radiator 22 made of Cu or the like and the metal film 10. On the surface of the heat radiator 22, the metal film 10 is formed by coating a 0.2 μm thick Au layer on a 2 μm thick Ni plating.

Note that even in a semiconductor device other than the semiconductor laser device, the submount and the base have a function of radiating heat of the semiconductor element. For example, when the semiconductor device is a GaAs electronic device, AIN, Al ₂ O ₃ or the like is used as a submount.

  The procedure for forming the AuSn alloy solder layer 4 in the first embodiment will be described below with reference to FIG. A Cr layer 6a, a Pt layer 6b, and an Au layer 6c are sequentially formed with a predetermined thickness by EB vapor deposition on the entire surface of the semiconductor laminate 20 on which the semiconductor layer including the active layer 11 is formed. After that, a resist is applied and mask exposure is performed to form an opening pattern. Here, the opening shape of the resist pattern is not limited to a rectangle, and may be an island shape, a comb shape, or the like, if necessary, and is not limited.

  Next, a solder layer 4 made of an AuSn alloy is formed on the surface of the surface electrode 6 on which the resist opening pattern has been formed to a thickness of 3 μm using a three-point jet type wafer plating apparatus.

  Thereafter, the resist pattern is removed, and etching is further performed using an etching solution that is a mixture of iodine and water. For example, an etchant in which iodine and water are mixed at a ratio of 1: 1 may be used. As a result, the portion of the Au layer 6c that is not covered with the solder layer 4 is removed, and the Pt layer 6b is exposed on the surface.

  On the other hand, the portion of the Au layer 6c covered by the solder layer 4 remains as it is, and the solder layer 4 is not deteriorated by the etchant. By the above method, the surface electrode 6 and the solder layer 4 are formed.

As the plating solution used for forming the solder layer 4 containing the AuSn alloy, for example, a cyan-free sulfite complex containing sodium sulfite as a complexing agent for Au is used. The solder layer 4 can be formed, for example, under such plating conditions that the flow rate of the plating solution is 15 L / min, the current density is 0.4 A / dm ² , the plating bath temperature is 35 ° C., and the pH is 9.0. The plating bath temperature and pH are determined in consideration of the influence on the resist film. The plating conditions are not limited to the conditions described above.

The Sn content of the solder layer 4 produced under the plating conditions was 21 wt%, that is, a composition of Au (79 wt%)-Sn (21 wt%). The film formation rate was 10 μm / hour. Further, the solder layer 4 was extremely smooth and dense, and exhibited a dark green specular gloss. In addition, evaluation by X-ray diffraction confirmed that the mixture was a mixture of only AuSn and Au ₅ Sn. Further, the obtained solder layer 4 was instantaneously melted at around 280 ° C., and excellent meltability was obtained. Also, even after melting, only AuSn and Au ₅ Sn were detected, no peak of Au alone or Sn alone was observed, and it was confirmed that a stable AuSn alloy without Sn segregation was formed.

  Note that a layer of Ni or the like may be provided on the lower surface of the solder layer 4 in order to improve the wettability of the solder layer 4. In this case, an Au—Sn—Ni alloy layer is formed by mutual diffusion of Ni and Sn.

  As described above, since the composition of the solder layer 4 in the alloy is controlled in advance by the plating process, the fixing temperature between the semiconductor laser element 1 and the submount 2 can be stabilized at a low level.

  In the first embodiment, the solder layer 4 may be formed of an AgSn alloy instead of the AuSn alloy. By using the AgSn alloy, the mounting temperature can be lower than in the case of the AuSn alloy, and the strain applied to the semiconductor laser device 1 during mounting can be further reduced. Therefore, the reliability of the semiconductor laser device 1 can be further improved.

  When plating the AgSn alloy, similarly to the case of the AuSn alloy, the AgSn alloy plating layer is formed to a thickness of 3 μm on the surface of the surface electrode 6 on which the resist opening pattern is formed by using a three-point jet type wafer plating apparatus. It forms until it becomes.

As a plating solution used for forming the solder layer 4 containing an AgSn alloy, a cyan-free sulfurous acid complex containing sodium sulfite as a complexing agent for Ag is used. The AgSn alloy plating layer can be formed, for example, under such plating conditions that the flow rate of the plating solution is 10 L / min, the current density is 3 A / dm ² , the plating bath temperature is 25 ° C., and the pH is 9.0. The plating bath temperature and pH are determined in consideration of the influence on the resist film. The plating conditions are not limited to the conditions described above.

  The Sn content of the solder layer 4 produced under the above plating conditions was 96 wt%, that is, a composition of Ag (4 wt%)-Sn (96 wt%). The film formation rate was 10 μm / hour. In the solder layer 4 containing Ag and Sn, the content of Sn with respect to the total amount of Ag is desirably around 95 wt%. In such a case, a sharp drop in the melting point of the solder layer 4 is observed.

  In the first embodiment, AuSn or AgSn is used as the alloy solder plating material for the solder layers 4 and 5. However, similar effects can be obtained with an alloy plating material whose composition is controlled in advance. For example, an alloy solder material such as PbSn, InSn, AuGe, or AuSi may be used.

FIG. 3 is a side sectional view showing a laminated structure of each component of another semiconductor laser device according to the first embodiment. The semiconductor laser device shown in FIG. 3 differs from the semiconductor laser device of FIG. 2 in that a GaN blue semiconductor laser having a resonator length of 600 μm, a chip width of 500 μm, and a thickness of 100 μm is used for the semiconductor laser element 1. Therefore, the surface electrode is divided into two, that is, a p-type electrode 6 _p and an n-type electrode 6 _n . Solder layers 4 _p and 4 _n are formed on each of the electrodes. On the surface side of the semiconductor stack 20 from the surface, Cr layer 6a _p of the thickness of 0.05 .mu.m, and 6a _n, Pt layer 6b _p of the thickness of 0.1 [mu] m, and 6b _n, of 0.05 .mu.m thickness is the Au layer 6c _p, and 6c _n, solder layer 4 _p, 4 _n consisting AuSn alloy 3μm thickness is formed. The distance between the p-type electrode 6 _p and the n-type electrode 6 _n is 175 μm.

The surface electrode formed on the side of the semiconductor laser element 1 of the submount 2 is also divided into two, that is, a p-type electrode _8p and an n-type electrode _8n . On the surface side of the electrically insulating material 21, from the surface, the thickness of the Ti layer 8a _p of 0.1 [mu] m, 8a _n and, in the thickness of 0.2 [mu] m Pt layer 8b _p, and 8b _n, 0.05 .mu.m of thick Au layer 8c _p, 8c _n are formed. As described above, even if the surface electrode is the p-type electrode 6 _p and the n-type electrode 6 _n divided into two, as described above, the solder layer 4 _p has a thickness in the range of 1 μm to 10 μm. , 4 _n , the solder layers 4 _p , 4 _n are small even if the semiconductor laser device 1 and the submount 2 are fixed. Therefore, the distance between the p-type electrode 6 _p and the n-type electrode 6 _n is small. No short circuit failure occurs.

(Embodiment 2)
Second Embodiment A semiconductor laser device according to a second embodiment of the present invention and a method for manufacturing the same will be described.

  The semiconductor laser device according to the second embodiment is different from the semiconductor laser device according to the first embodiment in that an Au-rich layer is further provided on the surface of the solder layer 4, and the other configurations are the same.

  In the semiconductor laser device according to the second embodiment, processing is performed to make the solder layer 4 easily recognizable. The surface of the solder layer 4 containing the AuSn alloy formed by the method described in the first embodiment has a dark green luster and is not deteriorated by the etching solution, so that the surface of the other region is not changed. There is no difference in flatness as compared with the Pt layer 6b which is a layer. Therefore, when fabricating a semiconductor laser device, a plurality of semiconductor laser devices are integrally formed, and when dividing into individual semiconductor laser devices (cleavage step), an electrode pattern cannot be recognized. Therefore, in order to facilitate pattern recognition between the solder layer 4 and the surface of the Pt layer 6b, it is preferable to provide a difference in flatness between the solder layer 4 and the Pt layer 6b.

  Here, a conventional general method for controlling the flatness of the plating surface will be described. Since the gloss of the plating surface depends on the particle size of the plating crystal, if the fine particles are sufficiently optically promoted, the flatness becomes higher and a surface with less diffuse reflection of light is obtained. Further, the fineness of the plating crystal can be achieved by increasing the number of metal ions reaching the electrode. In order to increase the number of metal ions reaching the electrode, the current density in the plating bath may be increased. For example, the current flowing through the electrode may be increased, or the concentration of metal ions in the plating bath may be increased. In addition, the addition of organic ions having a high adsorptivity to the plating solution can also promote the arrival of metal ions at the electrode. Further, by using an additive having an effect of adjusting a crystal of a plating crystal, a crystal of an AuSn alloy having a semi-glossy, smooth and small crystal grain size can be obtained.

  As described above, by adjusting the current density in the plating bath or the amount of the additive in the plating solution to be reduced, the particle size of the plating crystal is increased, and the unevenness is formed on the surface of the solder layer containing the AuSn alloy. be able to.

  Using the above method, a solder layer having a composition of Au (79 wt%)-Sn (21 wt%) was obtained. Furthermore, the surface irregularities can be increased, and the flatness with respect to the surrounding Pt layer can be reduced. As a result, pattern recognition can be performed without any problem in the above-described cleavage step and subsequent steps such as mounting of the semiconductor laser element 1.

  However, while the solder layer containing the AuSn alloy of the semiconductor laser device according to the first embodiment was stably melted at 280 ° C., the solder layer according to this method had the same composition and temperature up to 340 ° C. Unless raised, melting could not be achieved and wettability was low. This is considered to be due to the variation in the particle size of the plating crystals in the AuSn alloy. That is, if the surface roughness of the AuSn alloy plating layer is increased by the above-described method of reducing the number of metal ions reaching the electrode, a low melting point solder layer cannot be formed.

  Therefore, the inventors made a difference in flatness between the outermost surface of the solder layer 4 containing the AuSn alloy and the Pt layer 6b by the method described below. 4 and 5 show an example of a side sectional view of a solder layer of the semiconductor laser device according to the second embodiment of the present invention.

The structure shown in FIG. 4 is formed by the following method. After manufacturing a semiconductor laminate 20 having a resist pattern film formed thereon in the same manner as in the first embodiment, a solder layer 4 containing an AuSn alloy was formed using a three-point jet type wafer plating apparatus to a thickness of 2.8 μm. It formed until it became thickness. Thereafter, while immersed semiconductor stack 20, for example, the current density was 0.4 A / dm ^2, down to about 0.1 A / dm ^2. Thus, an Au-rich layer 25 having a thickness of 0.2 μm was formed on the solder layer 4 containing the AuSn alloy. The Au-rich layer 25 is a layer whose Au content is at least 80 wt% or more. The surface of the obtained Au-rich layer 25 has a thin golden luster. The Au-rich layer 25 was composed of Au (97 wt%)-Sn (3 wt%) with a Sn content of 3 wt%, and a composition of almost Au was obtained.

  Thereafter, the resist film was removed, and etching was further performed using an etching solution that was a mixture of iodine and water. For example, an etchant in which iodine and water are mixed at a ratio of 1: 1 may be used. At this time, the Au layer 6c formed by the EB evaporation was removed, and the thickness from the surface of the Au-rich layer 25 was about 0.1 μm. Therefore, the Au-rich layer 25 remained 0.1 μm, and irregularities were formed on the surface.

  The Cr layer 6a and the Pt layer 6b are formed on the entire surface, the Au layer 6c and the solder layer 4 thereon are formed in a pattern with the same shape, and the outermost surface is an Au-rich layer 25 having irregularities. . Since the Au-rich layer 25 has irregularities, its flatness is lower than that of the surrounding Pt layer 6b, so that pattern recognition can be easily performed in the primary cleavage step, the mounting step of the semiconductor laser device 1, and the like.

  If the content of Sn in the Au-rich layer 25 exceeds 10 wt%, that is, exceeds Au (90 wt%)-Sn (10 wt%), sufficient irregularities are formed on the surface even when etching is performed with an etchant. And it becomes difficult to obtain a required pattern recognition rate. Therefore, the Au content of the Au-rich layer 25 is preferably 90 wt% or more.

  Also, the solder layer 4 has a composition of Au (79 wt%)-Sn (21 wt%), and the entire composition including the Au rich layer 25 is controlled, so that the Au rich layer 25 is formed. Melted at 280 ° C. as stable as in the absence. This is presumably because the solder layer 4 on which the Au-rich layer 25 was formed was a plating crystal having a small particle size and formed uniformly as in the first embodiment, so that there was no melting variation.

  Also, by changing the plating conditions during the same plating production step, a plated layer having excellent composition and workability can be obtained. The plating conditions can be changed by changing the plating current value.

  In order to prevent oxidation, the thickness of the Au-rich layer 25 after the surface is roughened by etching is preferably at least 0.02 μm or more. If the film thickness is smaller than this, the Au-rich layer 25 is formed in an island shape, and may not function to prevent oxidation.

  In addition, the higher the Au content of the Au-rich layer 25 is, the more preferable the unevenness can be formed on the surface. Naturally, instead of the Au-rich layer 25, an Au plating layer 26 made of Au alone may be used. In this case, it is desirable to immerse in another Au plating apparatus instead of vapor deposition or the like. That is, as shown in FIG. 5, after forming the solder layer 4 containing a single AuSn alloy, the Au plating layer 26 containing only Au is continuously formed using the Au plating solution containing only Au. Just fine. This is because both films (the solder layer 4 and the Au plating layer 26) can be formed while covering the same resist film.

  When the Au plating layer 26 is formed by vapor deposition, it is necessary to remove the resist film covered with the Au layer later by a method such as lift-off. Further, also for the layer obtained by this method, the same fusibility and pattern recognizability as in the case of forming the Au-rich layer 25 shown in FIG. 4 could be obtained.

  As described above, by providing the Au-rich layer 25 or the Au plating layer 26 on the outermost surface, it is possible to improve the environmental resistance of the solder layer 4 including the AuSn alloy containing Sn which is easily oxidized, and Even after a lapse of time, it is possible to obtain the same meltability as when immediately after melting.

  Although the case where the solder layer 4 contains the AuSn alloy has been described above, the case where the solder layer 4 contains the AgSn alloy will be described below. Ag and Sn are both easily oxidizable materials. Therefore, when the solder layer 4 contains an AgSn alloy, providing the Au-rich layer 25 on the outermost surface of the solder layer 4 can provide a particularly large oxidation prevention effect. Therefore, even if the time elapses after the formation of the solder layer 4, it is possible to obtain the same meltability as in the case where the solder layer 4 is immediately melted, and it is possible to reduce the variation in the adhesive strength.

  The Au-rich layer 25 on the outermost surface is formed on the solder layer 4 and then etched with an etching solution that is a mixture of iodine and water, similarly to the case of the solder layer 4 made of the AuSn alloy described above. It is preferable to provide irregularities on the surface. Thereby, the flatness is lower than that of the surrounding Pt layer 6b, and the pattern can be easily recognized in the primary cleavage step, the mounting step of the semiconductor laser element 1, and the like.

  When the Au-rich layer 25 is etched, if the Au content of the Au-rich layer 25 is less than 90 wt%, sufficient irregularities cannot be formed on the surface, and a required pattern recognition rate is obtained. Therefore, the Au content of the Au-rich layer 25 is desirably 90 wt% or more.

  In order to prevent the oxidation of the solder layer 4 containing the AgSn alloy, it is desirable that the thickness of the Au-rich layer 25 after the surface is roughened by etching is at least 0.02 μm or more. If the film thickness is smaller than this, the Au-rich layer 25 is formed in an island shape, and may not function to prevent oxidation.

  In addition, the higher the Au content of the Au-rich layer 25 is, the more preferable the unevenness can be formed on the surface. Further, similarly to the case of the solder layer 4 made of the AuSn alloy described above, the Au plating layer 26 made of Au alone may be used instead of the Au rich layer 25. In this case, it is desirable to form the Au plating layer 26 by vapor deposition or by immersion in an Au plating apparatus.

  In the second embodiment, AuSn and AgSn alloys are used as the alloy solder plating material of the solder layer 4. However, similar effects can be obtained with an alloy plating material whose composition is controlled in advance. For example, an alloy solder material such as AuGe or AuSi may be used.

(Embodiment 3)
In the third embodiment of the present invention, a method for manufacturing the semiconductor laser device according to the first or second embodiment will be described with reference to the drawings. Here, an example of manufacturing a semiconductor device in which a semiconductor laser element is mounted on a submount will be described. However, the present invention is not limited to this. The present invention can also be applied to a method for manufacturing a semiconductor device.

  FIG. 6 is a plan view showing a configuration of a semiconductor laser device assembling apparatus according to the third embodiment. FIG. 7 is an enlarged perspective view of a tape of the semiconductor laser device assembling apparatus. A metal tape 100 is moving on the tape transport line 50. Note that the tape 100 moves from right to left in FIG. As shown in FIG. 7, a plurality of bases 3 are placed on the tape 100, and each base 3 is conveyed as the tape 100 moves.

  A sub-mount suction collet 29 is provided at the tip of the sub-mount transfer arm 54. The sub-mount transfer arm 54 is movable, and the sub-mount suction collet 29 can move to the sub-mount fixing position 53, the sub-mount recognition position 52, and the sub-mount supply position 51 on the tape 100. The laser device suction collet 30 is provided at the tip of the laser device transfer arm 58. The laser element transfer arm 58 is movable, and the laser suction collet 30 can move to the laser element fixing position 57, the laser element recognition position 56, and the laser element supply position 55 on the tape 100. Cameras 59a and 59b for recognizing the directions of the submount 2 and the semiconductor laser device 1 are provided.

  Further, a heating mechanism for melting the solder layer by plating is installed at the submount fixing position 53 and the laser element fixing position 57.

  The procedure for assembling the semiconductor laser device by the semiconductor laser device assembling apparatus will be described with reference to FIGS. 8 (a) to 8 (c) and FIGS. 9 (a) to 9 (c) are plan views illustrating the steps of assembling the semiconductor laser device by the semiconductor laser device assembling apparatus.

  As shown in FIG. 8A, when the first base 3 reaches the submount fixing position 53, the submount suction collet 29 moves to the submount supply position 51, and the submount 2 is moved to the submount. Pickup is performed by the suction collet 29. The sub-mount suction collet 29 moves as the sub-mount transfer arm 54 moves.

  As shown in FIG. 8B, the sub-mount suction collet 29 moves to the sub-mount recognition position 52 while holding the sub-mount 2. At the submount recognition position 52, the direction of the submount 2 held by the submount suction collet 29 is recognized by a camera 59a equipped with a CCD or an image sensor.

  The sub-mount suction collet 29 holds the sub-mount 2 and moves to the sub-mount fixing position 53 as shown in FIG. The submount 2 is arranged at a predetermined position. Then, a load of 15 g is applied to the submount 2 in the direction of the base 3 (downward) by the submount suction collet 29. In this state, the submount 2 and the base 3 are heated to 310 ° C. by the heating mechanism installed at the submount fixing position 53, and the solder layer 5 of the submount 2 and the Au plating layer 10 covering the surface of the base 3 are fused with each other. Then, the submount 2 and the base 3 are fixed by reaction. At this time, since the surface of the sub-mount 2 on the side of the sub-mount suction collet 29 is the surface electrode 8 on which the plating layer is not formed, the sub-mount 2 is not deformed by heating, and no trace of the sub-mount suction collet 29 is formed. Although the fixing temperature of the base 3 and the submount 2 was set to 310 ° C., even if the fixing temperature of the submount 2 is higher than this, the reliability of the semiconductor laser device 1 is not affected. There is no particular limitation on the fixing temperature.

  When the first base 3 and the submount 2 are fixed, the tape 100 is pitch-fed, the second base 3 reaches the submount fixing position, and the above operation is repeated.

  As shown in FIG. 9A, when the base 3 to which the submount 2 is fixed reaches the laser element fixing position 57, the laser element suction collet 30 moves to the laser element supply position 55 and The laser element 1 is picked up by the laser element suction collet 30. The laser element suction collet 30 moves as the laser element transfer arm 58 moves.

  The laser-element suction collet 30 holding the semiconductor laser element 1 moves to the laser-element recognition position 56 as shown in FIG. At the laser element recognition position 56, the direction of the semiconductor laser element 1 held by the laser element suction collet 30 is recognized by a camera 59b equipped with a CCD or an image sensor.

  Further, as shown in FIG. 9C, the laser element suction collet 30 holds the semiconductor laser element 1, moves to the laser element fixing position 57, and reaches the laser element fixing position 57. The semiconductor laser element 1 is arranged at a predetermined upper position.

  When the semiconductor laser device 1 has the Au-rich layer 25 or the Au-plated layer 26 as described in the second embodiment, the surface is roughened, so that the pattern can be recognized by the difference in light intensity. Therefore, positioning and orientation can be performed without any problem.

  When the semiconductor laser device 1 is arranged at a predetermined position of the submount 2, a load of 10 g is applied to the semiconductor laser device 1 in the direction of the submount 2 (downward) by the laser device suction collet 30. . In this state, the submount 2, the base 3, and the semiconductor laser device 1 are heated to 310 ° C. by the heating mechanism installed at the laser device fixing position 57, and the solder layer 4 of the semiconductor laser device 1 is melted. The Au layer 8c and the solder layer 4 react with each other to fix the submount 2 and the semiconductor laser device 1 together. At this time, the back surface electrode 7 of the semiconductor laser element 1 held by the laser element suction collet 30 does not deteriorate due to heating.

  Further, since the solder layer 4 is formed on the semiconductor laser device 1, even if the semiconductor laser device 1 is displaced, the solder layer 4 does not go around the side surface of the semiconductor laser device 1.

  The solder layer 5 made of an AuSn alloy fixing the base 3 and the submount 2 has a higher Au content than the solder layer 4 made of an AuSn alloy fixing the semiconductor laser device 1 and the submount 2. Since the melting point is high, there is no re-melting by heating in this case. When the base 3 and the submount 2 are fixed to each other, Au melts out of the metal film 10 in the solder layer 5 and the melting point of the solder layer 5 increases, so that the solder layer 4 and the solder layer 5 May have the same composition.

  Thereafter, similarly, the fixing work between the submount 2 and the base 3 and the fixing work between the semiconductor element 1 and the submount 2 are sequentially performed in parallel, and the semiconductor laser device according to the first or second embodiment is performed. Is produced.

  According to such a manufacturing method, the submount 2 and the semiconductor laser device 1, which are the respective components, can be securely fixed to the base 3 separately, and unnecessary melting of the plating layer does not occur. In addition, since the operations can be performed in parallel in one assembling apparatus, it is possible to assemble the semiconductor laser device in a short time, with stable temperature and with accurate positional accuracy.

  The time required for assembling the semiconductor laser device when such a semiconductor laser device assembling device was actually manufactured and operated was 10 seconds / piece. On the other hand, in an apparatus using a conventional method in which the submount 102 and the semiconductor laser element 101 are continuously arranged on the base 103 shown in FIGS. Seconds / piece. Therefore, the assembly speed could be reduced to about 1/3.

  In the third embodiment, the case where AuSn alloy plating is used for the solder layers 4 and 5 has been described. However, AgSn may be used as in the case of the first embodiment. In that case, it is desirable that the metal film 10 contains Ag. As a result, when the base 3 and the submount 2 are fixed to each other, Ag melts out of the metal film 10 into the solder layer 5, and the melting point of the solder layer 5 increases. Therefore, even if the solder layer 4 and the solder layer 5 have the same composition, each fixing step can be performed separately.

  In the third embodiment, the base 3, the submount 2, and the submount 2 and the semiconductor laser device 1 are separately assembled. However, if necessary, the base 3, the submount 2, and the semiconductor laser device 1 are simultaneously fixed. May be. After the submount 2 and the semiconductor laser element 1 are fixed via the solder layer 4, the base 3 and the submount 2 may be fixed via the solder layer 5.

  In the third embodiment, the submount 2 and the semiconductor laser element 1 are held and pressed by the submount suction collet 29 and the laser element suction collet 30, but these submount suction collet 29 and laser element suction collet 30 are held. May be used only for moving the submount 2 and the semiconductor laser element 1, and the position of the submount 2 and the semiconductor laser element 1 may be adjusted or fixed by another mechanism.

  In the first to third embodiments, the case where the semiconductor laser device 1 is installed on the submount 2 has been described, but the present invention is not limited to this. That is, the present invention can be widely applied to a semiconductor device having an element fixed on a submount and a method of manufacturing the same.

  In the first to third embodiments of the present invention, a plating layer is not formed on the surface of the submount 2 facing the semiconductor laser element 1, but may be formed as necessary.

  The semiconductor devices according to the first to third embodiments of the present invention have high reliability and can be manufactured at low cost. Further, according to the semiconductor device manufacturing methods according to the first to third embodiments of the present invention, it is possible to improve the processing yield and productivity of the semiconductor device.

  The materials and structures specifically described in the embodiments are merely examples, and the present invention is not limited to these specific examples.

  The method for manufacturing a semiconductor device of the present invention can improve the processing yield and productivity of the semiconductor device, and can be used when manufacturing various semiconductor devices.

FIG. 2 is a side cross-sectional view showing a laminated structure of the semiconductor laser device according to the first embodiment of the present invention. 1 is a side sectional view showing a laminated structure of each component of a semiconductor laser device according to a first embodiment of the present invention. Sectional side view showing the laminated structure of each component of another semiconductor laser device according to the first embodiment of the present invention. Side sectional view showing a laminated structure of a semiconductor laser device according to a second embodiment of the present invention. Side sectional view showing a laminated structure of another semiconductor laser device according to a second embodiment of the present invention. 3 is a plan view showing a configuration of a semiconductor laser device assembling apparatus according to Embodiment 3 of the present invention. Embodiment 3 An enlarged perspective view of a tape of a semiconductor laser device assembling apparatus according to Embodiment 3 of the present invention. Assembly process diagram of a semiconductor laser device assembling apparatus according to Embodiment 3 of the present invention. Assembly process diagram of a semiconductor laser device assembling apparatus according to Embodiment 3 of the present invention. FIG. 4 is a side sectional view showing a state before fixing a semiconductor laser element, a submount, and a base of a conventional semiconductor laser device. Sectional side view showing a state before fixing a semiconductor laser element, a submount, and a base of another conventional semiconductor laser device. Side sectional view showing the configuration of a conventional semiconductor laser device Mounting process diagram of semiconductor laser device when solder layer is formed on submount side Mounting process diagram of a semiconductor laser device when a solder layer is formed on the semiconductor laser device side Process drawing for explaining cleavage processing of a semiconductor laser device

Explanation of reference numerals

1 semiconductor laser element 2 submount 3 base 4 solder layer 5 the solder layer 6 surface electrode 6a, 6a _p, 6a _n Cr layer 6b, 6b _p, 6b _n Pt layer 6c, 6c _p, 6c _n Au layer 7 back surface electrode 8 surface electrode layer 8a, 8a _p, 8a _n Ti layer 8b, 8b _p, 8b _n Pt layer 8c, 8c _p, 8c _n Au layer 9 back electrode 9a Ti layer 9b Pt layer 9c Au layer 10 metal film 11 active layer 12 emitting point _6p , _8pp P-type electrode _6n , _8n N-type electrode 20 Semiconductor laminate 21 Electrical insulating material 22 Heat radiator 25 Au-rich layer 26 Au plating layer 29 Submount suction collet 30 Laser element suction collet 50 Tape transport line 51 Submount supply position 52 Submount recognition position 53 Submount fixing position 54 Submount transfer arm 55 Laser element supply position 56 Laser element recognition position 57 Laser element fixing position 58 Laser element transfer arm 59a, 59b Camera 100 Tape 101 Semiconductor laser element 102 Submount 103 Base 104 Solder layer 105 Solder layer 106 Front surface electrode 107 Back surface electrode 108 Front surface electrode 109 Back surface electrode 110 Metal film 111 Active layer 112 Light emitting point 120 Semiconductor laminate 121 Cleaving groove 122 Scribe scratch 123 Bar-shaped element assembly 129 Adsorption collet 130 Adsorption collet 131 Semiconductor laminate 132 Electrical insulating material 133 Heat radiator

Claims (31)

Forming a surface electrode on the semiconductor element;
Forming a solder layer by plating on one main surface of the surface electrode,
Mounting the semiconductor element on the submount so that the solder layer is in contact with the main surface of the submount,
Fixing the submount and the semiconductor element via the solder layer.   2. The method according to claim 1, wherein a solder layer is not formed on the submount when the submount is fixed to the semiconductor element. 3. The solder layer is partially formed on the surface electrode, and the surface electrode has an exposed portion,
3. The manufacturing of the semiconductor device according to claim 1, wherein a covering layer having a flatness different from that of the surface electrode is formed on the solder layer before the semiconductor element is mounted on the submount. 4. Method.   The method according to claim 1, wherein the solder layer includes an alloy of Au and Sn. After forming a solder layer, which is a plating of an alloy of Au and Sn,
Forming an Au-rich layer on the surface of the solder layer by plating;
The method of manufacturing a semiconductor device according to claim 4, wherein an etching process is performed to roughen the surface of the Au-rich layer. Forming the solder layer, which is a plating of an alloy of Au and Sn, by passing a current through the surface electrode immersed in a plating solution;
By adjusting the current density in the plating solution, the composition of the alloy of Au and Sn is changed,
The method for manufacturing a semiconductor device according to claim 5, wherein an Au-rich layer, which is a coating layer, is formed on a surface of the solder layer.   The method of manufacturing a semiconductor device according to claim 5, wherein the thickness of the Au-rich layer after the etching process is 0.02 μm or more.   The method of manufacturing a semiconductor device according to claim 5, wherein the Au-rich layer has an Au content of 90 wt% or more.   The semiconductor device according to claim 5, wherein the etching treatment is a step of impregnating the Au-rich layer with a mixture of iodine and water to roughen the surface of the Au-rich layer. Production method.   The method according to claim 1, wherein the solder layer includes an alloy of Ag and Sn. After forming a solder layer, which is a plating of an alloy of Ag and Sn,
Forming an Au-rich layer on the surface of the solder layer;
The method of manufacturing a semiconductor device according to claim 10, wherein an etching process is performed to roughen the surface of the Au-rich layer.   The method of manufacturing a semiconductor device according to claim 11, wherein the Au-rich layer is formed by plating.   The method according to claim 11, wherein the Au-rich layer is formed by vapor deposition.   The method of manufacturing a semiconductor device according to claim 11, wherein the thickness of the Au-rich layer after the etching process is 0.02 μm or more.   The method of manufacturing a semiconductor device according to claim 11, wherein the Au-rich layer has an Au content of 90 wt% or more.   11. The method of manufacturing a semiconductor device according to claim 4, further comprising, before the step of mounting the semiconductor element on the submount, fixing a base and the submount with a solder layer for a base. . The base solder layer is formed on one of the submount and the base,
The other of the submount and the base contains Au when the base solder layer contains an alloy of Au and Sn, and Ag when the base solder layer contains an alloy of Ag and Sn. Containing plating layer is formed,
17. The method of manufacturing a semiconductor device according to claim 16, wherein heating is performed so that the base solder layer and the plating layer are melted in order to fix the base and the submount. After the step of fixing the submount and the semiconductor element via the solder layer,
The method of manufacturing a semiconductor device according to claim 4, further comprising a step of fixing the base and the submount with a base solder layer.   19. The method according to claim 1, wherein the semiconductor element is a semiconductor laser element.   20. The method according to claim 19, wherein the surface electrode is formed on a side of the semiconductor laser device on which an active layer is formed. In the step of forming the surface electrode, the surface electrode has a plurality of layer structures,
21. The semiconductor device according to claim 1, further comprising a step of forming, as at least one layer of the surface electrodes, a barrier layer for preventing diffusion into the inside of the semiconductor element. Production method. In a semiconductor device having a submount and a semiconductor element fixed via a solder layer,
A surface electrode formed on the main surface on the submount side of the semiconductor element,
On the surface electrode, a solder layer partially formed,
A coating layer formed on the entire surface of the solder layer,
A semiconductor device, wherein a part of the surface electrode is exposed.   23. The semiconductor device according to claim 22, wherein the solder layer includes an alloy of Au and Sn, and a content ratio of Sn with respect to a total amount of Au is around 20 wt%.   23. The semiconductor device according to claim 22, wherein the solder layer includes an alloy of Ag and Sn, and a content ratio of Sn with respect to a total amount of Ag is around 95 wt%.   25. The semiconductor device according to claim 22, wherein the covering layer is formed of an Au-rich layer.   The semiconductor device according to claim 25, wherein the Au-rich layer has an Au content of 90 wt% or more.   27. The semiconductor device according to claim 22, wherein a formation region of the solder layer on the surface electrode is inside a surface of the semiconductor element on which the surface electrode is formed.   28. The semiconductor device according to claim 22, wherein said semiconductor element is a semiconductor laser element.   29. The semiconductor device according to claim 28, wherein in the semiconductor laser element, an active layer that emits laser light is formed on the surface electrode side. It further includes a base that is a radiator,
30. The semiconductor device according to claim 22, wherein the submount and the semiconductor element are sequentially stacked and fixed on the base. The surface electrode has a multilayer structure,
31. The semiconductor device according to claim 22, wherein at least one of the surface electrodes is a barrier layer for preventing a metal contained in the solder layer from diffusing into the semiconductor element. Semiconductor device.

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