JP2004327820A - Power-supply stabilizing circuit, and semiconductor integrated circuit device having same stabilizing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power-supply stabilizing circuit and a semiconductor integrated circuit device having the same stabilizing circuit which can suppress the increase of its consumption current caused by the leakages of its gates. <P>SOLUTION: The power-supply stabilizing circuit 200 includes an N-channel MOS transistor 10 and a P-channel MOS transistor 11 which are provided jointly and respectively between power-supply and grounding lines 1, 2 coupled to an LSI 100, and includes switching circuits SW1, SW2 which are provided jointly and respectively between the gate of the MOS transistor 10 and the power-supply line 1 and between the gate of the MOS transistor 11 and the grounding line 2. During the operational term of the LSI 100, the switching circuits SW1, SW2 are so turned-on as to perform the power-supply stabilizing by MOS capacitors comprising the MOS transistors 10, 11. During the non-operational term of the LSI 100, the switching circuits Sw1, Sw2 are so turned-off as to cut the routed paths of power-supply and grounding potentials VDD, VSS to the respective MOS capacitors and as to suppress the current consumptions caused by the leakages of their gates. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a power supply stabilization circuit, and more particularly to a power supply stabilization circuit added to a power supply circuit for supplying a power supply potential and a ground potential, and a semiconductor integrated circuit device including the same.
[0002]
[Prior art]
For the purpose of guaranteeing a stable operation of an LSI (semiconductor integrated circuit), a decoupling capacitance as a power supply stabilizing circuit is provided between a power supply line transmitting a power supply potential to an internal circuit of the LSI and a ground line transmitting a ground potential. Be placed.
[0003]
As the decoupling capacitance, a so-called MOS capacitance formed by the gate capacitance of a MOS (Metal Oxide Semiconductor) transistor is generally used (for example, see Patent Document 1).
[0004]
Since the larger the capacitance value of the decoupling capacitor is, the more effective the stabilization of the power supply voltage is. The capacity of the MOS capacitor is increased by increasing the gate area of the MOS transistor and reducing the thickness of the gate oxide film. ing.
[0005]
On the other hand, in recent LSI manufacturing process technology, as transistor miniaturization progresses, in a miniaturized transistor of 100 nanonodes or less, the thickness of the gate oxide film becomes thinner, and gate leakage occurs between the gate electrode and the substrate. There is a problem that occurs.
[0006]
Since the current due to the gate leakage causes an increase in the power consumption of the entire circuit, it is becoming more and more remarkable in today's thinner gate oxide film.
[0007]
Note that a current due to gate leakage is generated by charges penetrating through a gate oxide film, and thus increases in proportion to a gate area and a gate applied voltage of the transistor.
[0008]
In particular, in the above MOS capacitor, the gate area of the MOS transistor is often designed to be as large as possible in order to increase the capacitance value, and the problem of gate leakage becomes serious due to the progress of miniaturization. is expected.
[0009]
[Patent Document 1]
JP-A-2-58275 (FIG. 1)
[0010]
[Problems to be solved by the invention]
As described above, the MOS capacitor is used for stabilizing the power supply, and is a so-called auxiliary device for guaranteeing the stable operation of the LSI body.
[0011]
By the way, it is said that in the generations after the 90 nano node, the gate leakage current in the MOS transistor mounted on the LSI occupies most of the leakage current and becomes equal to the active current.
[0012]
This is only a prediction regarding the LSI body, and does not include the current consumption in the power supply stabilizing circuit which is an auxiliary device for stabilizing the power supply.
[0013]
On the other hand, in the power supply stabilizing circuit, it is not uncommon for the gate area of the MOS transistor forming the MOS capacitor to be equal to the gate area of the MOS transistor mounted on the LSI body.
[0014]
In this case, in the future of LSIs that are being miniaturized, it is determined that the current consumption of the LSI main body and the current consumption of the power supply stabilization circuit will be substantially the same. It is expected that
[0015]
SUMMARY OF THE INVENTION An object of the present invention is to provide a power supply stabilizing circuit capable of suppressing an increase in current consumption due to gate leakage, and a semiconductor integrated circuit device including the same.
[0016]
[Means for Solving the Problems]
According to the power supply stabilizing circuit according to the present invention, there is provided a power supply stabilizing circuit for stabilizing a power supply potential and a ground potential supplied to an internal circuit of a semiconductor integrated circuit, provided between the power supply potential and the ground potential. A capacitive element; and a switch circuit connected between the power supply potential and the capacitive element or between the capacitive element and the ground potential. The switch circuit electrically couples a corresponding power supply potential or ground potential to a capacitance element in an operation state of the semiconductor integrated circuit, and a corresponding power supply potential or ground potential and a capacitance in a non-operation state of the semiconductor integrated circuit. It is electrically separated from the element.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.
[0018]
[Embodiment 1]
FIG. 1 is a diagram showing a configuration of a power supply stabilizing circuit according to the first embodiment of the present invention.
[0019]
Referring to FIG. 1, power supply stabilizing circuit 200 is coupled to power supply terminal 111 for supplying power supply potential VDD to LSI 100 and a ground terminal 112 for supplying ground potential VSS.
[0020]
In LSI 100, power supply terminal 111 and ground terminal 112 are coupled to internal power supply line 101 and internal ground line 102, respectively. Power supply potential VDD and ground potential VSS are supplied to internal circuit 110 via internal power supply line 101 and internal ground line 102.
[0021]
Power supply stabilizing circuit 200 includes an N-channel MOS transistor 10 and a P-channel MOS transistor 11 coupled between power supply line 1 transmitting power supply potential VDD and ground line 2 transmitting ground potential VSS, and an N-channel MOS transistor. And a switch circuit SW2 coupled between the gate electrode of the P-channel MOS transistor 11 and the ground line 2.
[0022]
The N-channel MOS transistor 10 has a gate electrode connected to the power supply line 1 via the switch circuit SW1, a source, a drain, and a substrate electrode connected to the ground line 2, and forms a MOS capacitance.
[0023]
The switch circuit SW1 is turned on / off in response to a control signal CNT1 for controlling the operation / non-operation of the LSI 100, thereby electrically coupling / separating the power supply line 1 and the gate electrode of the N-channel MOS transistor 10. I do.
[0024]
The P-channel MOS transistor 11 has a gate electrode connected to the ground line 2 via the switch circuit SW2, a source, a drain, and a substrate electrode connected to the power supply line 1 to form a MOS capacitor.
[0025]
The switch circuit SW2 is electrically turned on / off in response to the control signal CNT2 to electrically couple / separate the gate electrode of the P-channel MOS transistor 11 from the ground line 2.
[0026]
In the above configuration, during the operation period of the LSI 100, the switch circuit SW1 is turned on, and electrically couples the power supply line 1 and the gate electrode of the N-channel MOS transistor 10. At the same time, switch circuit SW2 is turned on, and electrically couples ground line 2 to the gate electrode of P-channel MOS transistor 11.
[0027]
As described above, the MOS capacitor including the N-channel MOS transistor 10 and the P-channel MOS transistor 11 enables stable supply of the power supply potential VDD and the ground potential VSS as the decoupling capacitance during the operation period of the LSI 100.
[0028]
On the other hand, during the non-operation period of the LSI 100, the switch circuit SW1 is turned off, and electrically separates the power supply line 1 from the gate electrode of the N-channel MOS transistor 10. As a result, the path between the power supply potential VDD and the ground potential VSS is cut off in the MOS capacitor including the N-channel MOS transistor 10.
[0029]
At the same time, the switch circuit SW2 is turned off, and electrically separates the ground line 2 from the gate electrode of the P-channel MOS transistor 11. As a result, the path between the power supply potential VDD and the ground potential VSS is cut off even in the MOS capacitor including the P-channel MOS transistor 11.
[0030]
Therefore, during the non-operation period of the LSI 100, no gate leakage occurs in the MOS capacitor, so that current consumption due to the gate leakage current can be suppressed.
[0031]
In this case, the effect of stabilizing the power supply by the MOS capacitor cannot be obtained, but no problem occurs because the LSI 100 itself is in the non-operation state.
[0032]
Further, in the present embodiment, the power supply stabilizing circuit 200 has a configuration in which the MOS capacitor formed of the N-channel MOS transistor 10 and the MOS capacitor formed of the P-channel MOS transistor 11 are paired. The same effect can be obtained by adopting the configuration used in.
[0033]
[Modification of First Embodiment]
FIG. 2 shows a configuration of a power supply stabilizing circuit according to a modification of the first embodiment of the present invention.
[0034]
Referring to FIG. 2, power supply stabilizing circuit 200 includes N-channel MOS transistor 10 and P-channel MOS transistor 11 coupled between power supply line 1 and ground line 2 coupled to LSI 100, and N-channel MOS transistor A switch circuit SW3 coupled between the source, drain and substrate electrodes of 10 and the ground line 2, and a switch circuit SW4 coupled between the source, drain and substrate electrodes of the P-channel MOS transistor 11 and the power supply line 1 And
[0035]
N-channel MOS transistor 10 has a gate electrode connected to power supply line 1, a source, a drain, and a substrate electrode connected to ground line 2 via switch circuit SW3, and forms a MOS capacitor as in the first embodiment. .
[0036]
The switch circuit SW3 turns on / off in response to a control signal CNT3 for controlling operation / non-operation of the LSI 100, thereby electrically connecting the ground line 2 with the source, drain and substrate electrode of the N-channel MOS transistor 10. Binding / separating to
[0037]
P-channel MOS transistor 11 has a gate electrode connected to ground line 2, a source, a drain, and a substrate electrode connected to power supply line 1 via switch circuit SW4, and forms a MOS capacitor as in the first embodiment. .
[0038]
The switch circuit SW4 is turned on / off according to the control signal CNT4 to electrically couple / separate the power supply line 1 from the source, drain and substrate electrode of the P-channel MOS transistor 11.
[0039]
In the above configuration, during the operation period of the LSI 100, the switch circuit SW3 is turned on, and electrically connects the ground line 2 to the source and drain of the N-channel MOS transistor 10 and the substrate electrode. At the same time, switch circuit SW4 is turned on, and electrically couples power supply line 1 with the source and drain of P-channel MOS transistor 11 and the substrate electrode.
[0040]
Thus, the power supply potential VDD and the ground potential VSS supplied to the LSI 100 are stabilized by the MOS capacitance including the N-channel MOS transistor 10 and the P-channel MOS transistor 11.
[0041]
On the other hand, during the non-operation period of the LSI 100, the switch circuit SW3 is turned off, and electrically separates the ground line 2 from the source and drain of the N-channel MOS transistor 10 and the substrate electrode. As a result, the path between the power supply potential VDD and the ground potential VSS is cut off in the MOS capacitor including the N-channel MOS transistor 10.
[0042]
At the same time, the switch circuit SW4 is turned off, and electrically separates the power supply line 1 from the source and drain of the P-channel MOS transistor 11 and the substrate electrode. As a result, a path between the power supply potential VDD and the ground potential VSS is cut off in the MOS capacitor including the P-channel MOS transistor 11.
[0043]
Therefore, since no gate leakage occurs in each MOS capacitor, current consumption due to gate leakage current can be suppressed.
[0044]
As described above, according to the first embodiment of the present invention, in the power supply stabilizing circuit, the switch circuit for coupling / separating between the power supply potential and the ground potential according to the operation / non-operation state of the LSI is provided by the MOS transistor In addition to stabilizing the power supply of the LSI, it is possible to suppress an increase in current consumption due to gate leakage of the MOS transistor.
[0045]
[Embodiment 2]
FIG. 3 shows a configuration of a power supply stabilizing circuit according to the second embodiment of the present invention.
[0046]
Referring to FIG. 3, power supply stabilizing circuit 200 is provided inside LSI 100, and is coupled to internal power supply line 101 and internal ground line 102. Power supply potential VDD and ground potential VSS are applied to internal power supply line 101 and internal ground line 102 via power supply terminal 111 and ground terminal 112, respectively.
[0047]
Power supply stabilizing circuit 200 includes an N-channel MOS transistor 10 and a P-channel MOS transistor 11 coupled between internal power supply line 101 and internal ground line 102, and a gate between N-channel MOS transistor 10 and internal power supply line 101. A switch circuit SW1 coupled between the gate electrode of P-channel MOS transistor 11 and internal ground line 102 is included.
[0048]
This embodiment is different from the first embodiment shown in FIG. 1 only in that a power supply stabilizing circuit 200 is arranged inside an LSI 100, and has a common circuit configuration. Therefore, a detailed description of the overlapping part will be omitted.
[0049]
As shown in FIG. 3, control signals CNT1 and CNT2 for controlling on / off operations of the switch circuits SW1 and SW2 are output from a control circuit 120 in the LSI 100. The control circuit 120 outputs the control signals CNT1 and CNT2 at the timing when the operation / non-operation of the LSI 100 is switched.
[0050]
In the above configuration, during the operation period of the LSI 100, the switch circuit SW1 is turned on, and electrically connects the internal power supply line 101 and the gate electrode of the N-channel MOS transistor 10. At the same time, switch circuit SW2 is turned on, and electrically couples internal ground line 102 to the gate electrode of P-channel MOS transistor 11. Thus, the MOS capacitor including N-channel MOS transistor 10 and P-channel MOS transistor 11 stably supplies power supply potential VDD and ground potential VSS to internal circuit 110.
[0051]
On the other hand, during the non-operation period of the LSI 100, the switch circuit SW1 is turned off, and electrically separates the internal power supply line 101 from the gate electrode of the N-channel MOS transistor 10. As a result, the path between internal power supply line 101 and internal ground line 102 is cut off in the MOS capacitor formed of N-channel MOS transistor 10.
[0052]
At the same time, switch circuit SW2 is turned off, and electrically separates internal ground line 102 from the gate electrode of P-channel MOS transistor 11. As a result, the path between the internal power supply line 101 and the internal ground line 102 is cut off even in the MOS capacitor including the P-channel MOS transistor 11.
[0053]
Therefore, during the non-operation period of the LSI 100, no gate leakage occurs in the MOS capacitor, so that current consumption due to the gate leakage current can be suppressed.
[0054]
FIG. 4 is a diagram schematically showing an example of arrangement of power supply stabilizing circuit 200 in FIG.
Referring to FIG. 4, power supply stabilizing circuit 200 is provided in a hatched area on an outer peripheral portion of LSI 100.
[0055]
In the shaded region, an internal power supply line 101 and an internal ground line 102 are wired, and the power supply potential VDD and the ground potential VSS are transmitted to the internal circuit 110.
[0056]
In the present embodiment, as an example, the configuration in which the power supply stabilizing circuit 200 is arranged in an empty area on the outer periphery of the LSI 100 has been described. , Can be arranged in any area.
[0057]
Further, the power supply stabilization circuit 200 mounted inside the LSI 100 is not limited to the configuration shown in the present embodiment, and the same effect can be obtained by employing the configuration shown in FIG.
[0058]
Further, the MOS capacitor can be configured with only one of the N-channel MOS transistor 10 and the P-channel MOS transistor 11.
[0059]
As described above, according to the second embodiment of the present invention, in the power supply circuit disposed inside the LSI, by controlling the ON / OFF of the switch circuit according to the operation / non-operation of the LSI, the power supply can be stabilized. It is possible to suppress an increase in current consumption due to gate leakage.
[0060]
Since the power supply stabilization circuit is formed in a free area in the LSI or in a trunk area such as an internal power supply line, an increase in circuit size due to the arrangement of the power supply stabilization circuit is avoided.
[0061]
[Embodiment 3]
FIG. 5 shows a configuration of a power supply stabilizing circuit according to the third embodiment of the present invention.
[0062]
Referring to FIG. 5, LSI 100 is divided into a plurality of blocks 100a, 100b... (Not shown) according to the operation content. Power supply stabilization circuits 200a, 200b (not shown) for stabilizing the power supply potential VDD and the ground potential VSS supplied to the internal circuits 110a, 110b,. Is established.
[0063]
The power stabilizing circuits 200a, 200b,... May be arranged only in blocks that require power supply according to the operation of each block 100a, 100b,.
[0064]
Also in the present embodiment, the power supply stabilizing circuits 200a, 200b,..., As in the arrangement example of the second embodiment shown in FIG. As long as the element does not exist, the element can be arranged in any area.
[0065]
The circuit configuration of each of the power stabilizing circuits 200a, 200b,... Is the same as the configuration shown in FIG. For example, referring to block 100a, power supply stabilizing circuit 200a includes a MOS capacitor including MOS transistors 10a and 11a coupled between internal power supply line 101a and internal ground line 102a, an N-channel MOS transistor 10a and an internal It has a switch circuit SW1a coupled between the power supply line 101a and a switch circuit SW2a coupled between the P-channel MOS transistor 11a and the internal ground line 102a.
[0066]
The internal power supply lines 101a, 101b,... And the internal ground lines 102a, 102b,... Are separately arranged corresponding to the blocks 100a, 100b,. Thus, the power supply potential VDD and the ground potential VSS are independently supplied for each block.
[0067]
At this time, since the substrate electrodes of the P-channel MOS transistors 11a, 11b,... Are connected to the internal power supply lines 101a, 101b,. The substrate of the MOS transistor is also separated for each block.
[0068]
In the above configuration, on / off control of the switch circuits SW1a, SW2a, SW1b, SW2b,... Included in each of the power stabilizing circuits 200a, 200b,. .. Are performed independently in block units in accordance with control signals CNT1a, CNT2a, CNT1b, CNT2b...
[0069]
For example, when the block 100a is in the operating state and the blocks 100b are inoperative, the power supply potential VDD and the ground potential VSS are supplied only to the block 100a. Further, in power supply stabilizing circuit 200a, switch circuits SW1a and SW2a are turned on in response to control signals CNT1a and CNT2a. Thus, N-channel MOS transistor 10a and P-channel MOS transistor 11a act as decoupling capacitors.
[0070]
On the other hand, in power supply stabilizing circuit 200b, switch circuits SW1b and SW2b are turned off, and the path between internal power supply line 101b and internal ground line 102b is disconnected. In the power supply stabilizing circuits 200c (not shown), the paths between the internal power supply lines 101c and the internal ground lines 102c are similarly disconnected.
[0071]
.., The power supply stabilization circuits 200b, 200c,... In the non-operational blocks 100b, 100c,. Is suppressed.
[0072]
As described above, according to the third embodiment of the present invention, LSI 100 is divided into a plurality of blocks, and a power supply potential and a ground potential supply source and a power supply stabilization circuit are provided for each block as necessary. By activating only the power supply stabilization circuit corresponding to the block in operation and activating the power supply stabilization circuit corresponding to the block in non-operation, current consumption due to gate leakage can be reduced. It can be further reduced.
[0073]
[Embodiment 4]
FIG. 6 shows an example of a configuration of a power supply stabilizing circuit according to the fourth embodiment of the present invention.
[0074]
Referring to FIG. 6, power supply stabilizing circuit 200 includes an N-channel MOS transistor 10 and a P-channel MOS transistor coupled between power supply line 1 transmitting power supply potential VDD to LSI 100 and ground line 2 transmitting ground potential VSS. MOS transistor 11, P-channel MOS transistor 20 coupled between the gate electrode of N-channel MOS transistor 10 and power supply line 1, and coupled between the gate electrode of P-channel MOS transistor 11 and ground line 2 N channel MOS transistor 21.
[0075]
The power supply stabilization circuit 200 of the present embodiment is configured by a P-channel MOS transistor 20 as an example of the switch circuit SW1 in the power supply stabilization circuit 200 of the first embodiment of FIG. Further, as an example of the switch circuit SW2, the switch circuit SW2 is configured by an N-channel MOS transistor 21. Therefore, a detailed description of common parts is omitted.
[0076]
P-channel MOS transistor 20 has a gate electrode connected to an input terminal (not shown) of control signal CNT1 for controlling the operation state of LSI 100, a source connected to power supply line 1, and a drain connected to the gate of N-channel MOS transistor 10. Connected to electrodes.
[0077]
When turned on / off according to the potential of control signal CNT1, P channel MOS transistor 20 electrically couples / separates power supply line 1 and the gate electrode of N channel MOS transistor.
[0078]
Here, the control signal CNT1 input from a control signal input terminal (not shown) is a signal that transitions between two potential states corresponding to H (logic high) and L (logic low). It becomes L level and becomes H level in the non-operation state.
[0079]
Therefore, when P-channel MOS transistor 20 is turned on in response to L-level control signal CNT1 during the operation of LSI 100, power supply line 1 and the gate electrode of N-channel MOS transistor 10 are electrically coupled.
[0080]
On the other hand, when the P-channel MOS transistor 20 is turned off in response to the H-level control signal CNT1 during the non-operation period of the LSI 100, the path between the power supply potential VDD and the ground potential VSS for the MOS capacitor is cut off. Therefore, occurrence of gate leak is suppressed.
[0081]
The N-channel MOS transistor 21 has a gate electrode connected to the input terminal of the control signal CNT2 (not shown), a drain connected to the gate electrode of the P-channel MOS transistor 11, and a source connected to the ground line 2.
[0082]
When turned on / off according to the potential of control signal CNT2, N-channel MOS transistor 21 electrically couples / separates ground line 2 from the gate electrode of P-channel MOS transistor 11.
[0083]
Here, the control signal CNT2 is a signal that transitions between two potential states corresponding to H and L, and is at the H level when the LSI 100 is in the operating state, and is at the L level when the LSI 100 is not operating.
[0084]
Therefore, when N-channel MOS transistor 21 is turned on in response to H-level control signal CNT2 during the operation period of LSI 100, ground line 2 and the gate electrode of P-channel MOS transistor 11 are electrically coupled.
[0085]
On the other hand, when the N-channel MOS transistor 21 is turned off in response to the L-level control signal CNT2 during the non-operation period of the LSI 100, the path between the power supply potential VDD and the ground potential VSS for the MOS capacitor is cut off. Therefore, occurrence of gate leak is suppressed.
[0086]
To summarize the above, during the operation period of the LSI 100, both the P-channel MOS transistor 20 and the N-channel MOS transistor 21 are turned on, and the MOS capacitance of the N-channel MOS transistor 10 and the P-channel MOS transistor 11 causes Power supply stabilization is achieved.
[0087]
On the other hand, during the non-operating period of the LSI 100, both the P-channel MOS transistor 20 and the N-channel MOS transistor 21 are turned off, and a gate leak occurs in the MOS capacitor including the N-channel MOS transistor 10 and the P-channel MOS transistor 11. Can be suppressed.
[0088]
Note that, during the operation period of the LSI 100, since no potential drop occurs between the source and the drain of the turned on P-channel MOS transistor 20, the gate potential of the N-channel transistor 10 becomes equal to the power supply potential VDD.
[0089]
Further, since the potential does not increase between the drain and the source of the turned on N-channel MOS transistor 11, the gate potential of the P-channel MOS transistor 11 becomes equal to the ground potential VSS.
[0090]
Therefore, the MOS capacitor composed of the N-channel MOS transistor 11 and the P-channel MOS transistor 11 stores a maximum amount of charge due to the potential difference between the power supply potential VDD and the ground potential VSS, so that a high power supply stabilizing effect can be obtained. it can.
[0091]
[Modification of Embodiment 4]
FIG. 7 shows an example of a configuration of a power supply stabilizing circuit according to a modification of the fourth embodiment of the present invention.
[0092]
Referring to FIG. 7, power supply stabilizing circuit 200 includes an N-channel MOS transistor 10 and a P-channel MOS transistor 11 coupled between power supply line 1 and ground line 2 coupled to LSI 100, and an N-channel MOS transistor An N-channel MOS transistor 22 coupled between the source, drain and substrate electrodes of P10 and ground line 2 and a P-channel MOS transistor 11 coupled between the source, drain and substrate electrodes of P-channel MOS transistor 11 and power supply line 1 And a channel MOS transistor 23.
[0093]
The power supply stabilization circuit 200 of the present embodiment is configured by an N-channel MOS transistor 22 as an example of the switch circuit SW3 in the power supply stabilization circuit 200 of FIG. Further, as an example of the switch circuit SW4, the switch circuit SW4 is configured by a P-channel MOS transistor 23. Therefore, a detailed description of common parts is omitted.
[0094]
N-channel MOS transistor 22 has a gate electrode connected to an input terminal (not shown) of control signal CNT3, a drain connected to the source and drain of N-channel MOS transistor 10, and a substrate electrode, and a source connected to ground line 2. Is done.
[0095]
When turned on / off according to the potential of control signal CNT3, N-channel MOS transistor 22 electrically couples / separates ground line 2 from the source / drain of N-channel MOS transistor 10 and the substrate electrode.
[0096]
Here, the control signal CNT3 input from a control signal input terminal (not shown) is a signal that transitions between two potential states corresponding to H and L, becomes H level when the LSI 100 is operating, and becomes non-operating Sometimes, it is at L level.
[0097]
Therefore, when the N-channel MOS transistor 22 is turned on in response to the H-level control signal CNT3 during the operation period of the LSI 100, the ground line 2 and the source, drain and substrate electrode of the N-channel MOS transistor 10 are electrically connected. Join.
[0098]
On the other hand, when the N-channel MOS transistor 22 is turned off in response to the L-level control signal during the non-operation period of the LSI 100, the path between the power supply potential VDD and the ground potential VSS for the MOS capacitor is disconnected. Thus, the occurrence of gate leak is suppressed.
[0099]
The P-channel MOS transistor 23 has a gate electrode connected to an input terminal of a control signal CNT4 (not shown), a source connected to the power supply line 1, and a drain connected to the source, drain and substrate electrode of the P-channel MOS transistor 11.
[0100]
When turned on / off according to the potential of control signal CNT4, P-channel MOS transistor 23 electrically couples / separates power supply line 1 from the source / drain of P-channel MOS transistor 11 and the substrate electrode.
[0101]
The control signal CNT4 is a signal that transitions between two potential states corresponding to H and L, and goes to L level when the LSI 100 is in the operating state, and goes to H level when the LSI 100 is in the inactive state.
[0102]
Therefore, when P-channel MOS transistor 23 is turned on in response to L-level control signal CNT4 during the operation period of LSI 100, power supply line 1 and the source, drain and substrate electrode of P-channel MOS transistor 11 are electrically connected. Join.
[0103]
On the other hand, when the P-channel MOS transistor 23 is turned off in response to the H-level control signal CNT4 during the non-operation period of the LSI 100, the path between the power supply potential VDD and the ground potential VSS for the MOS capacitor is disconnected. Therefore, occurrence of gate leak is suppressed.
[0104]
In summary, during the operation period of the LSI 100, both the N-channel MOS transistor 22 and the P-channel MOS transistor 23 are turned on, and the MOS capacitance of the N-channel MOS transistor 10 and the P-channel MOS transistor 11 causes Power supply stabilization is achieved.
[0105]
On the other hand, during the non-operating period of the LSI 100, both the N-channel MOS transistor 22 and the P-channel MOS transistor 23 are turned off, and the gate leakage in the MOS capacitor formed by the N-channel MOS transistor 10 and the P-channel MOS transistor 11 occurs. Can be suppressed.
[0106]
Note that during the operation period of the LSI 100, no potential rise occurs between the source and the drain of the turned on N-channel MOS transistor 22 due to the threshold voltage, and the potential between the source and the drain of the turned on P-channel MOS transistor 23 does not rise. Since no drop occurs, the MOS capacitor composed of the N-channel MOS transistor 10 and the P-channel MOS transistor 11 stores a maximum amount of charge due to the potential difference between the power supply potential VDD and the ground potential VSS.
[0107]
As described above, according to the fourth embodiment of the present invention, by turning on / off the switch circuit between the MOS capacitor and the power supply potential and the ground potential in accordance with the operation / non-operation of the LSI, Power supply potential and ground potential can be supplied stably, and current consumption due to gate leakage can be reduced.
[0108]
Further, since both the switch circuit and the decoupling capacitance are formed by MOS transistors, a power supply stabilizing circuit can be easily formed.
[0109]
Note that the same effect can be obtained when the power supply stabilizing circuit 200 according to the present embodiment shown in FIGS. 6 and 7 is provided inside the LSI 100 as shown in FIG. At this time, the control signals CNT1 and CNT2 of the switch circuit are respectively output from the control unit 120 inside the LSI 100. 6 and 7 are replaced with an internal power supply line 101 and an internal ground line 102, respectively.
[0110]
[Embodiment 5]
FIG. 8 shows an example of a configuration of a power supply stabilizing circuit according to the fifth embodiment of the present invention.
[0111]
Referring to FIG. 8, power supply stabilizing circuit 200 includes an N-channel MOS transistor 10 and a P-channel MOS transistor 11 coupled between power supply line 1 and ground line 2 coupled to LSI 100, and an N-channel MOS transistor 10 includes an N-channel MOS transistor 22 coupled between the gate electrode 10 and power supply line 1, and a P-channel MOS transistor 23 coupled between the gate electrode of P-channel MOS transistor 11 and ground line 2.
[0112]
The power supply stabilizing circuit 200 of the present embodiment is configured by an N-channel MOS transistor 22 as an example of the switch circuit SW1 in the power supply stabilizing circuit 200 of the first embodiment of FIG. In addition, as an example of the switch circuit SW2, a P-channel MOS transistor 23 is used. Therefore, a detailed description of common parts is omitted.
[0113]
The N-channel MOS transistor 22 has a gate electrode connected to the input terminal of the control signal CNT3 (not shown), a drain connected to the power supply line 1, and a source connected to the gate electrode of the N-channel MOS transistor 10.
[0114]
When turned on / off according to the potential of control signal CNT3, N-channel MOS transistor 22 electrically couples / separates power supply line 1 and the gate electrode of N-channel MOS transistor 10.
[0115]
N-channel MOS transistor 22 electrically connects power supply line 1 and the gate electrode of N-channel MOS transistor 10 when turned on in response to H-level control signal CNT3 during the operation period of LSI 100.
[0116]
On the other hand, when the N-channel MOS transistor 22 is turned off in response to the L-level control signal CNT3 during the non-operation period of the LSI 100, the path between the power supply potential VDD and the ground potential VSS for the MOS capacitor is disconnected. Therefore, occurrence of gate leak is suppressed.
[0117]
The P-channel MOS transistor 23 has a gate electrode connected to the input terminal of the control signal CNT4 (not shown), a source connected to the gate electrode of the P-channel MOS transistor 11, and a drain connected to the ground line 2.
[0118]
When turned on / off in response to the potential of control signal CNT4, P-channel MOS transistor 23 electrically couples / separates ground line 2 from the gate electrode of P-channel MOS transistor 11.
[0119]
P channel MOS transistor 23 electrically connects ground line 2 and the gate electrode of P channel MOS transistor 11 when turned on in response to L level control signal CNT4 during the operation period of LSI 100.
[0120]
On the other hand, when the P-channel MOS transistor 23 is turned off in response to the H-level control signal CNT4 during the non-operation period of the LSI 100, the path between the power supply potential VDD and the ground potential VSS for the MOS capacitor is disconnected. Therefore, occurrence of gate leak is suppressed.
[0121]
In summary, during the operation period of the LSI 100, both the N-channel MOS transistor 22 and the P-channel MOS transistor 23 are turned on, and the MOS capacitance of the N-channel MOS transistor 10 and the P-channel MOS transistor 11 causes Power supply stabilization is achieved.
[0122]
On the other hand, during the non-operating period of the LSI 100, both the N-channel MOS transistor 22 and the P-channel MOS transistor 23 are turned off, and the gate leakage in the MOS capacitor formed by the N-channel MOS transistor 10 and the P-channel MOS transistor 11 occurs. Can be suppressed.
[0123]
Note that during the operation period of the LSI 100, a potential drop corresponding to the threshold voltage occurs between the source and the drain of the turned on N-channel MOS transistor 22, so that the gate potential of the N-channel transistor 10 is only the threshold voltage from the power supply potential VDD. The potential becomes low.
[0124]
Further, since a potential rise corresponding to the threshold voltage occurs between the source and the drain of the turned on P-channel MOS transistor 23, the gate potential of the P-channel MOS transistor 11 becomes higher than the ground potential VSS by the threshold voltage.
[0125]
Therefore, the MOS capacitor composed of N-channel MOS transistor 10 and P-channel MOS transistor 11 has a potential corresponding to the sum of the threshold voltages of N-channel MOS transistor 22 and P-channel MOS transistor 23 based on the potential difference between power supply potential VDD and ground potential VSS. That is, a potential obtained by subtracting the applied potential is applied. Since the amount of gate leakage current generated by the MOS capacitor is proportional to the gate applied voltage, according to this configuration, it is possible to reduce the gate leakage current and realize low power consumption even during the operation period of the LSI 100. It becomes possible.
[0126]
[Modification of Embodiment 5]
FIG. 9 shows an example of a configuration of a power supply stabilizing circuit according to a modification of the fifth embodiment of the present invention.
[0127]
Referring to FIG. 9, power supply stabilizing circuit 200 includes an N-channel MOS transistor 10 and a P-channel MOS transistor 11 coupled between power supply run 1 and ground line 2 coupled to LSI 100, and an N-channel MOS transistor A P-channel MOS transistor 20 coupled between the source, drain and substrate electrodes of P10 and ground line 2 and an N-channel transistor coupled between the source, drain and substrate electrodes of P-channel MOS transistor 11 and power supply line 1 And a channel MOS transistor 21.
[0128]
The power supply stabilization circuit 200 of the present embodiment is configured by a P-channel MOS transistor 20 as an example of the switch circuit SW3 in the power supply stabilization circuit 200 according to the modification of the first embodiment of FIG. Further, as an example of the switch circuit SW4, an N-channel MOS transistor 21 is used. Therefore, a detailed description of common parts is omitted.
[0129]
P-channel MOS transistor 20 has a gate electrode connected to an input terminal of control signal CNT1 (not shown), a source connected to the source and drain and a substrate electrode of N-channel MOS transistor 10, and a drain connected to ground line 2.
[0130]
When P-channel MOS transistor 20 is turned on in response to L-level control signal CNT1 during the operation of LSI 100, ground line 2 is electrically coupled to the source and drain of N-channel MOS transistor 10 and the substrate electrode. .
[0131]
On the other hand, when the P-channel MOS transistor 20 is turned off in response to the H-level control signal CNT1 during the non-operation period of the LSI 100, the path between the power supply potential VDD and the ground potential VSS for the MOS capacitor is cut off. Therefore, occurrence of gate leak is suppressed.
[0132]
The N-channel MOS transistor 21 has a gate electrode connected to the input terminal of the control signal CNT2 (not shown), a drain connected to the power supply line 1, and a source connected to the source, drain and substrate electrode of the P-channel MOS transistor 11.
[0133]
When the N-channel MOS transistor 21 is turned on in response to the H-level control signal CNT2 during the operation period of the LSI 100, the N-channel MOS transistor 21 electrically couples the power supply line 1 with the source, drain and substrate electrode of the P-channel MOS transistor 11. .
[0134]
On the other hand, when the N-channel MOS transistor 21 is turned off in response to the L-level control signal CNT2 during the non-operation period of the LSI 100, the path between the power supply potential VDD and the ground potential VSS for the MOS capacitor is cut off. Therefore, occurrence of gate leak is suppressed.
[0135]
To summarize the above, during the operation period of the LSI 100, both the P-channel MOS transistor 20 and the N-channel MOS transistor 21 are turned on, and the MOS capacitance of the N-channel MOS transistor 10 and the P-channel MOS transistor 11 causes Power supply stabilization is achieved.
[0136]
On the other hand, during the non-operating period of the LSI 100, both the P-channel MOS transistor 20 and the N-channel MOS transistor 21 are turned off, and a gate leak occurs in the MOS capacitor including the N-channel MOS transistor 10 and the P-channel MOS transistor 11. Can be suppressed.
[0137]
In the operation period of the LSI 100, a potential rise corresponding to the threshold voltage occurs between the source and the drain of the turned on P-channel MOS transistor 20, and the threshold voltage is generated between the source and the drain of the turned on N-channel MOS transistor 21. Therefore, the MOS capacitor formed of the N-channel MOS transistor 10 and the P-channel MOS transistor 11 has a potential difference between the power supply potential VDD and the ground potential VSS, so that the P-channel MOS transistor 20 and the N-channel MOS transistor 21 A potential obtained by subtracting a potential corresponding to the sum of the threshold voltages is applied. Therefore, even in the operation state of the LSI 100, current consumption due to gate leakage in each MOS capacitor can be suppressed.
[0138]
As described above, according to the fifth embodiment of the present invention, the power supply of the LSI can be stabilized, and the current consumption due to the gate leak can be suppressed in the operating state and the non-operating state of the LSI. Electricity can be realized.
[0139]
Note that the same effect can be obtained when the power supply stabilizing circuit 200 of the present embodiment is provided inside the LSI 100 as shown in FIG. In this case, the control signals CNT1 and CNT2 of the switch circuit are respectively output from the control unit 120 inside the LSI 100. 8 and 9 are replaced with an internal power supply line 101 and an internal ground line 102, respectively.
[0140]
Embodiment 6
FIG. 10 shows a structure of a power supply stabilizing circuit according to a sixth embodiment of the present invention.
[0141]
Referring to FIG. 10, power supply stabilizing circuit 200 includes an N-channel MOS transistor 10 and a P-channel MOS transistor 11 coupled between power supply line 1 and ground line 2 coupled to LSI 100, power supply 3 and power supply And a P-channel MOS transistor 20 coupled between the line 1.
[0142]
N channel MOS transistor 10 has a gate electrode connected to power supply line 1, and a source, drain and substrate electrode connected to ground line 2.
[0143]
P channel MOS transistor 11 has a source, a drain, and a substrate electrode connected to power supply line 1, and a gate electrode connected to ground line 2.
[0144]
The power supply stabilizing circuit 200 of the present embodiment is configured by a P-channel MOS transistor 20 as an example of the switch circuit SW1 in the first embodiment of FIG. 1 and the switch circuit SW4 in the second embodiment of FIG. .
[0145]
The P-channel MOS transistor 20 has a gate electrode connected to an input terminal of a control signal CNT1 (not shown), a drain connected to the power supply line 1, and a source connected to the power supply 3.
[0146]
In the present embodiment, the MOS capacitance formed by N-channel MOS transistor 10 and P-channel MOS transistor 11 is directly connected between power supply line 1 and ground line 2 without through P-channel MOS transistor 20 as a switch circuit. Be combined. In this point, the configuration is different from the configurations of the fourth and fifth embodiments in which the MOS capacitor and the P-channel MOS transistor 20 as the switch circuit are integrally connected between the power supply line 1 and the ground line 2.
[0147]
When turned on in response to an L-level control signal CNT1 during the operation of LSI 100, P-channel MOS transistor 20 electrically couples power supply 3 and power supply line 1.
[0148]
When power supply line 1 is driven to power supply potential VDD by coupling power supply 3 and power supply line 1, the gate electrode of N-channel MOS transistor 10 and the source, drain and substrate electrodes of P-channel MOS transistor 11 are connected to the power supply. It becomes the potential VDD.
[0149]
Therefore, power supply potential VDD and ground potential VSS are stably supplied to LSI 100 by N-channel MOS transistor 10 and P-channel MOS transistor 11.
[0150]
Here, the P-channel MOS transistor 20 that has been turned on has a resistance component connected in series to the MOS capacitor as an on-resistance.
[0151]
Therefore, as shown in the previous embodiment, when P-channel MOS transistor 20 and MOS capacitor are integrated between power supply line 1 and ground line 2, power supply line 1 and ground line 2 Between them, a MOS capacitor is added via a resistor.
[0152]
When the internal circuit 110 operates at a predetermined speed during the operation period of the LSI 100, charging and discharging of the MOS capacitor are repeated according to the operation speed of the internal circuit 110. As the operation of the internal circuit 110 increases, the speed of charging and discharging the MOS capacitor also increases.
[0153]
However, when the MOS capacitance is added via a resistor, the time constant in the transient characteristics of charging and discharging increases due to the resistance. Cannot follow the operation speed, which is equivalent to a state in which no MOS capacitor exists between the power supply line 1 and the ground line 2.
[0154]
That is, during the high-speed operation of the internal circuit 110, the effect of stabilizing the power supply by the MOS capacitor cannot be sufficiently obtained due to the resistance component of the switch circuit using the MOS transistor.
[0155]
Therefore, as shown in FIG. 10, according to the present embodiment in which the MOS capacitance is directly coupled between the power supply line 1 and the ground line 2 without passing through the P-channel MOS transistor 20 as a switch circuit, The effect of stabilizing the power supply can be maximized even in high-speed operation without deteriorating high-frequency characteristics due to the on-resistance of the transistor 20.
[0156]
Note that, during the non-operation period of the LSI 100, when the P-channel MOS transistor 20 is turned off in response to the control signal CNT1 at the H level, the power supply 3 does not supply the power supply potential VDD to the power supply line 1.
[0157]
Therefore, the path between the power supply potential VDD and the ground potential VSS is cut off with respect to the MOS capacitor including the N-channel MOS transistor 10 and the P-channel MOS transistor 11, thereby suppressing the occurrence of gate leak current.
[0158]
Further, since the path between the power supply potential VDD and the ground potential VSS for the internal circuit 110 of the LSI 100 (not shown) is also disconnected, the occurrence of a leak current in the internal circuit 110 can be suppressed.
[0159]
[Modification 1 of Embodiment 6]
FIG. 11 shows a structure of a power supply stabilizing circuit according to a first modification of the sixth embodiment of the present invention.
[0160]
Referring to FIG. 11, power supply stabilizing circuit 200 includes N-channel MOS transistor 10 and P-channel MOS transistor 11 coupled between power supply line 1 and ground line 2 coupled to LSI 100, and ground line 2 N-channel MOS transistor 22 coupled to ground potential.
[0161]
N channel MOS transistor 10 has a gate electrode connected to power supply line 1, and a source, drain and substrate electrode connected to ground line 2.
[0162]
P channel MOS transistor 11 has a source, a drain, and a substrate electrode connected to power supply line 1, and a gate electrode connected to ground line 2.
[0163]
The power supply stabilizing circuit 200 of the present embodiment is configured by an N-channel MOS transistor 22 as an example of the switch circuit SW3 of the second embodiment of FIG. 2 and the switch circuit SW2 of the first embodiment of FIG. .
[0164]
N-channel MOS transistor 22 has a gate electrode connected to an input terminal of control signal CNT3 (not shown), a drain connected to ground line 2, and a source connected to ground potential.
[0165]
In FIG. 11, as in FIG. 10, the MOS capacitance is directly coupled between the power supply line 1 and the ground line without passing through the N-channel MOS transistor 22 which is a switch circuit.
[0166]
Thus, as described above, during the operation period of the LSI 100, the effect of power supply stabilization can be maximized even in high-speed operation without deteriorating high-frequency characteristics due to the on-resistance of the N-channel MOS transistor 22. .
[0167]
When the N-channel MOS transistor 22 is turned off in response to the L-level control signal CNT3 during the non-operating period of the LSI 100, the gate leakage current of the MOS capacitor including the N-channel MOS transistor 10 and the P-channel MOS transistor 11 is reduced. Generation can be suppressed, and generation of leakage current in the internal circuit 110 can also be suppressed.
[0168]
[Modification 2 of Embodiment 6]
FIG. 12 shows a configuration of a power supply stabilizing circuit according to a second modification of the sixth embodiment of the present invention.
[0169]
12, power supply stabilizing circuit 200 includes N-channel MOS transistor 10 and P-channel MOS transistor 11 coupled between power supply line 1 and ground line 2 coupled to LSI 100, power supply 3 and power supply P-channel MOS transistor 20 coupled between line 1 and N-channel MOS transistor 22 coupled between ground line 2 and ground potential.
[0170]
The power supply stabilizing circuit 200 of the present embodiment is configured by a P-channel MOS transistor 20 as an example of the switch circuit SW1 in the first embodiment of FIG. 1 and the switch circuit SW4 in the second embodiment of FIG. .
[0171]
Further, as an example of the switch circuit SW3 in the second embodiment of FIG. 2 and the switch circuit SW2 in the first embodiment of FIG. 1, an N-channel MOS transistor 22 is used.
[0172]
The P-channel MOS transistor 20 has a gate electrode connected to an input terminal of a control signal CNT1 (not shown), a source connected to the power supply 3, and a drain connected to the power supply line 1.
[0173]
When turned on in response to an L-level control signal CNT1 during the operation of LSI 100, P-channel MOS transistor 20 electrically couples power supply 3 and power supply line 1. As a result, the power supply line 1 is driven to the power supply potential VDD.
[0174]
On the other hand, when the P-channel MOS transistor 20 is turned off in response to the H-level control signal CNT1 during the non-operation period of the LSI 100, the power supply 3 and the power supply line 1 are electrically separated.
[0175]
N-channel MOS transistor 22 has a gate electrode connected to an input terminal of control signal CNT3 (not shown), a drain connected to ground line 2, and a source connected to ground potential.
[0176]
N-channel MOS transistor 22 electrically couples the ground potential to ground line 2 when turned on in response to H-level control signal CNT3 during the operation period of LSI 100. As a result, the ground line 2 is driven to the ground potential VSS.
[0177]
On the other hand, when the N-channel MOS transistor 22 is turned off in response to the L-level control signal during the non-operation period of the LSI 100, the N-channel MOS transistor 22 electrically separates the ground potential from the ground line 2.
[0178]
In FIG. 12, as in FIGS. 10 and 11, the MOS capacitor is directly coupled between the power supply line 1 and the ground line without passing through the P-channel MOS transistor 20 and the N-channel MOS transistor 22, which are switch circuits.
[0179]
Therefore, during the operation period of the LSI 100, the effect of power supply stabilization can be maximized even in high-speed operation without deteriorating high-frequency characteristics due to the on-resistance of the P-channel MOS transistor 20 and the N-channel MOS transistor 22. .
[0180]
Further, during the non-operating period of the LSI 100, when both the P-channel MOS transistor 20 and the N-channel MOS transistor 22 are turned off, the gate leakage current of the MOS capacitor including the N-channel MOS transistor 10 and the P-channel MOS transistor 11 is reduced. Generation can be suppressed, and generation of leakage current in the internal circuit 110 can also be suppressed.
[0181]
As described above, according to the sixth embodiment of the present invention, during the operation period of the LSI, the MOS capacitance is directly connected between the power supply line and the ground line without passing through the switch circuit including the MOS transistor. Deterioration of high-frequency characteristics due to the ON resistance of the MOS transistor is avoided, and stable operation due to power supply stabilization is ensured even in high-speed operation.
[0182]
Further, by cutting the path between the power supply potential and the ground potential during the non-operation period of the LSI, it is possible to suppress the generation of the gate leak current in the MOS capacitor and the generation of the leak current in the internal circuit. Therefore, a further reduction in current consumption is realized.
[0183]
In the fifth and sixth embodiments among the first to sixth embodiments described above, the configuration using the MOS transistor as an example of the switch circuit has been described. Here, if the gate oxide film of the MOS transistor of the switch circuit is made thicker than the gate oxide films of the other MOS transistors included in the internal circuit and the like, the ON state of the switch circuit, that is, the ON state of the MOS transistor, Gate leak current generated in the switch circuit can be reduced. Therefore, lower current consumption can be achieved during the operation period of the LSI.
[0184]
The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0185]
【The invention's effect】
As described above, according to the power supply stabilization circuit of the present invention, a switch circuit for electrically coupling / separating between the power supply potential and the ground potential is added to the MOS capacitor according to the operation state of the LSI. This makes it possible to stabilize the power supply of the LSI and suppress an increase in current consumption due to gate leakage of the MOS transistor forming the MOS capacitor.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a power supply stabilizing circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a configuration of a power supply stabilizing circuit according to a modification of the first embodiment of the present invention.
FIG. 3 is a diagram showing a configuration of a power supply stabilizing circuit according to a second embodiment of the present invention.
FIG. 4 is a diagram schematically showing an example of arrangement of a power supply stabilizing circuit 200 in FIG. 3;
FIG. 5 is a diagram showing a configuration of a power supply stabilizing circuit according to a third embodiment of the present invention.
FIG. 6 is a diagram showing a configuration of a power supply stabilizing circuit according to a fourth embodiment of the present invention.
FIG. 7 shows an example of a configuration of a power supply stabilizing circuit according to a modification of the fourth embodiment of the present invention.
FIG. 8 is a diagram showing a configuration of a power supply stabilizing circuit according to a fifth embodiment of the present invention.
FIG. 9 is a diagram showing a configuration of a power supply stabilizing circuit according to a modification of the fifth embodiment of the present invention.
FIG. 10 is a diagram showing a configuration of a power supply stabilizing circuit according to a sixth embodiment of the present invention.
FIG. 11 is a diagram showing a configuration of a power supply stabilizing circuit according to a first modification of the sixth embodiment of the present invention.
FIG. 12 is a diagram showing a configuration of a power supply stabilizing circuit according to a second modification of the sixth embodiment of the present invention.
[Explanation of symbols]
1 power supply line, 2 ground line, 3 power supply, 10, 10a, 10b ..., 20, 22 N-channel MOS transistor, 11, 11a, 11b ..., 21, 23 P-channel MOS transistor, 100 LSI, 100a, 100b ... block, 101, 101a, 101b ... internal power supply line, 102, 102a, 102b ... internal ground line, 110, 110a, 110b ... internal circuit, 111 power supply terminal, 112 ground terminal, 120 Control unit, 200, 200a, 200b ... Power stabilization circuit, SW1, SW1a, SW1b ..., SW2, SW2a, SW2b ..., SW3, SW4 Switch circuit, CNT1, CNT1a, CNT1b ..., CNT2 , CNT2a, CNT2b ..., CNT3, CNT4 control signal, VDD power supply potential, VSS ground potential.

Claims (13)

A power supply stabilization circuit for stabilizing a power supply potential and a ground potential supplied to an internal circuit of a semiconductor integrated circuit,
A capacitor provided between the power supply potential and the ground potential;
A switch circuit connected between the power supply potential and the capacitance element or between the capacitance element and the ground potential;
The switch circuit,
In the operating state of the semiconductor integrated circuit, the corresponding power supply potential or the ground potential and the capacitive element are electrically coupled,
A power supply stabilization circuit for electrically separating a corresponding one of the power supply potential or the ground potential and the capacitance element when the semiconductor integrated circuit is not operating. The power supply stabilization circuit according to claim 1, wherein the capacitance element includes a capacitance formed by a field effect transistor. The switch circuit is activated / deactivated in response to a control signal corresponding to an operation / non-operation state of the semiconductor integrated circuit, and electrically switches between the power supply potential and the ground potential corresponding to the capacitance element. The power supply stabilizing circuit according to claim 2, further comprising a field effect transistor coupled / separated from the power supply. The switch circuit electrically coupled between the capacitance element and the power supply potential includes a P-channel field effect transistor, and the switch electrically coupled between the capacitance element and the ground potential The power supply stabilization circuit according to claim 3, wherein the circuit includes an N-channel field effect transistor. The switch circuit electrically coupled between the capacitance element and the power supply potential includes an N-channel field effect transistor, and the switch electrically coupled between the capacitance element and the ground potential The power supply stabilization circuit according to claim 3, wherein the circuit includes a P-channel field effect transistor. The switch circuit electrically coupled between the capacitor and the power supply potential includes a P-channel field-effect transistor, and a connection node between the P-channel field-effect transistor and the capacitor is connected to the semiconductor integrated circuit. 4. The power supply stabilizing circuit according to claim 3, wherein the power supply stabilizing circuit is a power supply potential supply node to the circuit. The switch circuit electrically coupled between the capacitance element and the ground potential includes an N-channel field-effect transistor, and a connection node between the N-channel field-effect transistor and the capacitance element is connected to the semiconductor integrated circuit. 4. The power supply stabilization circuit according to claim 3, wherein the power supply stabilization circuit is a node for supplying a ground potential to the circuit. 4. The power supply stabilization circuit according to claim 3, wherein in the switch circuit, the field-effect transistor has a thicker gate oxide film than other field-effect transistors mounted on the semiconductor integrated circuit. 5. A semiconductor integrated circuit device that performs a predetermined operation in response to a power supply potential and a ground potential,
A plurality of blocks divided according to the operation content of the internal circuit included therein,
A control unit for driving each of the plurality of blocks to an operation / non-operation state;
An internal power supply line and an internal ground line arranged for each of the plurality of blocks, for supplying the power supply potential and the ground potential to the internal circuit, respectively;
A power supply stabilizing circuit arranged for a block that performs the predetermined operation of the plurality of blocks, for stabilizing the power supply potential and the ground potential;
The power stabilization circuit includes:
A capacitive element provided between the internal power supply wiring and the internal ground wiring,
A switch circuit connected between the internal power supply line and the capacitive element or between the capacitive element and the internal power supply line,
The switch circuit,
In response to a control signal indicating an operation state of the block output from the control unit, electrically coupled between the corresponding internal power supply wiring or the internal ground wiring and the capacitive element,
A semiconductor integrated circuit device electrically separating a corresponding one of the internal power supply wiring or the internal ground wiring and the capacitive element in response to a control signal output from the control unit and indicating a non-operation state of the block. The capacitor includes a capacitor formed by a field-effect transistor. In the plurality of blocks, the internal power supply wiring, the internal ground wiring, and the substrate electrode of the field-effect translator are separated from each other between the blocks. The semiconductor integrated circuit device according to claim 9, wherein: The switch circuit is activated / deactivated in response to the control signal, and includes a field effect transistor that electrically couples / isolates the corresponding internal power supply line or the internal ground line with the capacitor. The semiconductor integrated circuit device according to claim 10, comprising: The switch circuit electrically coupled between the internal power supply line and the capacitance element includes a P-channel field effect transistor, and is electrically coupled between the capacitance element and the internal ground line. 12. The semiconductor integrated circuit device according to claim 11, wherein said switch circuit includes an N-channel field effect transistor. The switch circuit electrically coupled between the internal power supply line and the capacitance element includes an N-channel field effect transistor, and is electrically coupled between the capacitance element and the internal ground line. 12. The semiconductor integrated circuit device according to claim 11, wherein said switch circuit includes a P-channel field-effect transistor.

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