JP2004326237A - Test case creation device, test case creation method, test case, and test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test case creation device capable of preventing a rerun of a test and greatly reducing an analysis time. <P>SOLUTION: In a system LSI function verification method outputting analysis support information, this test case creation device is provided with a test case creation part 105 creating and storing a test case 106, which is provided with a test procedure for testing operation of a function model modeling a circuit having a plurality of H/W resources such as a program counter, a versatile register, a memory, and a register controlling input/output (I/O), and a cause analysis information creation part 156 creating error cause analysis information for analyzing an error cause and storing the error cause analysis information in the test case 106 when the test procedure created by the test case creation part 105 is executed by a simulator 108 and the operation test of the function model results in an error. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
According to the present invention, when performing a function test, after activating a resource of a product to be verified as a test, a result of comparison between an expected value of the resource and an effective value (value of the resource after activation) is obtained. The present invention relates to a function verification system that reduces the workload when analyzing the cause of an error when the error occurs or when a result error occurs when the timing of resource change differs from an expected value.
[0002]
[Prior art]
When performing a functional test, the test program is executed on the simulator. After extracting the test cases that resulted in an error, the test programs for the resources that make up the product are sequentially executed on the simulator to analyze the cause of the error. In order to reproduce the error, the test case is re-executed on the logic simulator, using a commercially available tool for recording transition information that changes when the test is performed. After the reproduction, the location of the test program in which the error occurred, the resources involved, and the time involved are identified stepwise while considering the transition information for all resources and the execution order of the test program. The cause was clarified.
[0003]
[Patent Document 1]
JP-A-2000-2753
[Patent Document 2]
JP 2001-5841A
[0004]
[Problems to be solved by the invention]
The test case in which the error occurred is extracted and re-executed, and the transition information of all resources owned by the product during the execution of the test case is recorded using a commercially available tool, etc., so a simulator for the test case when reproducing the error The above execution time requires several times longer than the normal execution time without recording. In the error analysis work, as the functionality of the product increases, the number of resources that make up the product increases and the function of the product becomes more complex, so the test cases for testing this also become more complex. I do. For this reason, in the error analysis work when the test execution results in an error, while grasping the execution order of the program, extracting the location where the error occurs and the resources involved, and manually analyzing it, It took a lot of time and effort.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method and method for verifying functions of a system LSI (large-scale integrated circuit) or the like, which can suppress re-execution of a test and significantly reduce analysis time.
[0005]
[Means for Solving the Problems]
A test case generation device of the present invention includes: a test case generation unit that generates a test procedure for testing an operation of a functional model obtained by modeling a circuit having a plurality of resources and stores the test procedure as a test case;
If the result of the test of the operation of the functional model by the test procedure generated by the test case generation unit results in an error, a cause analysis information generation unit that generates and stores error cause analysis information for analyzing the cause of the error;
It is characterized by having.
[0006]
BEST MODE FOR CARRYING OUT THE INVENTION
In a system LSI (large-scale integrated circuit) function verification method according to an embodiment described below, when a test case is generated, a product resource used in each step, an execution order of the step, a resource inheritance relationship, and the like. By having a means to generate and record in the memory as error cause analysis information and a means to add and record this error cause analysis information to the test case, it is possible to suppress the re-execution of the test and significantly reduce the analysis time. Realize.
[0007]
This system LSI function verification method can reduce labor and time required for re-executing a test case for reproducing an error and analyzing a cause of an error, which have been generated in the conventional method, in a large amount of analysis. .
[0008]
Embodiment 1 FIG.
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is an overall configuration diagram of the system LSI verification method with error analysis support.
The function verification work of the system LSI is a work of confirming that the system LSI to be verified operates correctly and functionally. Therefore, H / W (hardware) resources (hereinafter, also simply referred to as resources), which are possessed to fulfill the functions of the system LSI, are extracted from the product specification 101 in which the functional description of the system LSI is described. A configuration scenario 103 and a test scenario 102 for performing a test on each function of the system LSI are created. In addition, a function model 104 that models a circuit of the system LSI is created from the product specification 101 in which a description of functions related to the system LSI is described. The function model 104 describes the function description of the system LSI to be verified. In addition, a test bench 107 for testing the function model 104 is created from the product specification 101 in which a description of functions related to the system LSI is described. The test bench 107 is connected to the function model 104 and controls input / output to the function model.
[0009]
Here, the H / W resource refers to, for example, a program counter, a general-purpose register, a memory, a register for controlling input / output (I / O), and the like. The specification of the H / W resource means that a plurality of H / W resources are identified by identifiers such as a program counter ID, a general-purpose register number, a memory address, and a register number for controlling input / output (I / O). , One type and one H / W resource are uniquely determined. The effective value of the H / W resource refers to information, data, and a value set in the H / W resource, for example, a value set in a program counter, a value set in a general-purpose register, and set in a memory. Value, a value set in a register for controlling input / output (I / O), and the like. The effective value of the H / W resource is held in the H / W resource by identifying the H / W resource by an identifier and using a setting command or a write command. The data is read from the H / W resource by a read command.
[0010]
Next, the test case generation unit 105 converts the resource configuration information 103 and the test scenario 102 into a function model 104 describing the function description of the system LSI to be verified, and inputs / outputs the function model 104 by connecting to the function model 104. A test case 106 which is a test program for controlling a test bench 107 for controlling the test bench 106 is generated. The test case 106 is a test program, and may or may not include test data. Further, the test case 106 of this embodiment holds various types of information (error cause analysis information) that supports error analysis to be described later, and outputs a message for analyzing an error result based on the various types of information. The test case 106 is recorded on a recording medium such as a magnetic disk as a program file.
[0011]
The test case 106, the function model 104, and the test bench 107 are executed by the simulator 108, and a test case execution result 109 as a simulation execution result indicating normal end or error end is obtained.
[0012]
The error analysis unit 110 is, for example, a program routine that is included in the test case 106 as a part of the test procedure and operates after the execution of the test case 106. The error analysis unit 110 may be an independent program.
The error analysis unit 110 analyzes the cause of the error with respect to the test case execution result 109 that has ended in the error among the simulation execution results. At this time, conventionally, a human has described a function description written in the product specification 101, an effective value of each H / W resource held by the function model 104, and a test case 106 representing the contents of a test procedure. In the present system LSI verification method, the test case 106 including information for supporting the error analysis (error cause analysis information) is output. The error analysis unit 110 can clarify the cause of the error without particularly investigating the specification 101 and the function model 104. The error analysis unit 110 performs error analysis automatically or semi-automatically by referring to information (error cause analysis information) supporting error analysis included in the test case 106. Alternatively, the error analysis unit 110 searches for information (error cause analysis information) supporting the error analysis included in the test case 106, estimates or determines the cause of the error, and displays the estimated determination result in the test case. Support human error analysis work.
[0013]
In order to output information (error cause analysis information) supporting the error analysis, the present system LSI verification method has a cause analysis information generation unit 156 shown in FIG. The cause analysis information generation unit 156 may exist independently as shown in FIG. 1 or may be inside the test case generation unit 105. Further, the cause analysis information generation unit 156 may be inside the test case 106. When generating the test case 106, the cause analysis information generating unit 156 stores a test procedure-specific resource recording unit 105a that records the relationship with the H / W resource used for each test procedure, and is stored after executing each test procedure. An access order / expected value generation unit 105b as an example of a resource expected value generation unit for generating expected values to be generated for each H / W resource, and a test procedure execution order expectation for generating an expected value of a test procedure execution order. A value generation unit 105c, an error analysis message generation unit 105d that outputs a message for supporting a task of analyzing the cause of the error in preparation for a case where an error is determined in the test case execution result, A pseudo data generation unit 105e for arranging data near the H / W resources to be used, and a test procedure inheritance relationship generator for generating an inheritance relationship between test procedures. And it includes a section 105f.
[0014]
The pseudo data generation unit 105e generates pseudo data that is set for each of a plurality of resources as error cause analysis information and that can specify which resource the resource is. The test case generator 105 sets a pseudo data value generated by the pseudo data generator 105e in each resource before executing the test procedure, and then generates a test procedure for testing the operation of the functional model. In this manner, as a result of the execution of the test procedure of the test case, it is possible to specify which resource is the resource that provided the result value from the result value obtained from the resource.
[0015]
Further, the error analysis message generation unit 105d generates an error analysis message in which an expected error result is associated with the error factor as error cause analysis information.
When a test is performed on at least one of a plurality of resources constituting the circuit function, the test case generation unit 105 executes a test whose expected value to be obtained from the resource is known, and executes the test. As a result, it is determined whether the test result is an error by comparing the result value obtained from the resource with the expected value generated by the resource-specific access order / expected value generation unit 105b, and the test result is an error. A test procedure that outputs an error analysis message when it is determined that
[0016]
FIG. 2 is an explanatory diagram of test procedure configuration information 106a generated by the test procedure-specific resource recording unit 105a in the memory and recorded in the test case 106.
The test case 106 includes a plurality of test procedures (hereinafter, also referred to as test access). When the test procedure is generated, the contents of the test procedure are described as “test access type” that describes the outline of the operation means possessed by the system LSI and the outline of the operation means possessed by the test bench. A “test access ID”, an “address storage resource” used to store an address, a “data storage resource” used to store data, a “memory access resource” accessed through the address storage resource, It is classified and recorded as "immediate value" when a value is set in "data storage resource". “Address storage resources”, “data storage resources”, and “memory access resources” are H / W resources used when accessed as a test.
As described above, the test case generation unit 105 generates a test procedure including a plurality of test procedures to be executed in a predetermined order, and the test procedure-specific resource recording unit 105a generates a test procedure (test access test) as error cause analysis information. (2) Separately, generates information on the contents of the test procedure and H / W resources used by the test procedure, and records them in the memory as test procedure configuration information 106b.
The error analysis message generation unit 105d generates the error analysis message information 106d using the test procedure configuration information 106a recorded in the memory by the test procedure-specific resource recording unit 105a.
The test procedure configuration information 106b and the error analysis message information 106d are output to the test case 106 and recorded.
[0017]
FIG. 3 is an explanatory diagram of the resource-specific access order / expected value information 106b generated in the memory by the resource-specific access order / expected value generation unit 105b and recorded in the test case 106.
The resource-specific access order / expected value generation unit 105b generates a list of test procedures for accessing the H / W resource for each H / W resource.
For example, in FIG.
Test access ID-0002
Test access ID-0005
Test access ID-0007
In that order.
[0018]
Further, the resource-specific access order / expected value generation unit 105b performs a test access to the H / W resource used by the test access according to the “test access type” of the test procedure configuration information 106a generated by the test procedure-specific resource recording unit 105a. The value after the execution (the value after the change) or the value held just before the execution of the test access when it does not change is held for each H / W resource as the “expected value” immediately after the execution of the test access. Here, the “expected value” is a value that should be obtained from the H / W resource after the execution of the test access when the function model operates normally.
For example, in FIG. 3, the value held in the register 3 is
After the execution of the test access ID-0002, the value becomes 0,
After the execution of the test access ID-0005, the value becomes 3000,
After execution of the test access ID-0007, the value becomes 3300
It is shown that.
[0019]
The resource-specific access order / expected value generation unit 105b generates a list of test procedures for accessing the H / W resource for each H / W resource, and executes the test procedure to test the resources and holds the list of resources. The expected value expected to be obtained is generated and stored in the memory, and also stored in the test case 106. The test case generation unit 105 compares the result value obtained from the resource test with the expected value generated by the resource-specific access order / expected value generation unit 105b, and determines whether the test result is an error. Then, a test procedure for outputting an error analysis message including an expected value when the test result is determined to be an error is generated, for example, as a part of the error analysis unit 110.
[0020]
FIG. 4 is an explanatory diagram of the resource-specific pseudo-data information 106e generated in the memory by the pseudo-data generating unit 105e and recorded in the test case 106.
H / W resources that are not used at all as test accesses to identify the way in which a system LSI to be verified operates erroneously in test access, but used to identify erroneous locations Indicates that pseudo data is set in advance in the vicinity of. Here, the pseudo data is a value by which the H / W resource to be accessed originally can be specified. By analyzing the pseudo data, the H / W resource such as a memory or a register to be originally accessed can be detected.
[0021]
For example, it is assumed that the functional model has an arithmetic unit capable of performing calculations in 32-bit units, and that the memory is accessed in units of 4 bytes (4 addresses). With the test access ID-0005, pseudo data is generated as follows, for example, for the address 2000 (“RAM-2000”) of the memory accessed via the register.
For the address 1FF8 (“RAM-1FF8”), the pseudo data is “F88F1FF1”.
For the address 1FFC (“RAM-1FFC”), the pseudo data is “FCCF1FF1”.
The pseudo data for the address 2004 (“RAM-2004”) is “04400220”.
The pseudo data for the address 2008 (“RAM-2008”) is “08802002”.
The pseudo data is a value obtained by processing an address of a memory that is erroneously accessed by a predetermined algorithm.
[0022]
As shown in FIG. 2, in the test access ID-0005, the data “RAM-2000” corresponding to the value (address 2000) stored in the register 2 (REG2) is changed from the data “RAM-2000” stored in the “RAM-2000”. A test access to a system LSI function called “CPU READ” that stores “3000” in a register 3 (REG3) is executed. In the test access ID-0005, if the system LSI erroneously reads data from the adjacent “RAM-2004”, the REG3 is not the expected value “3000” but the erroneous data that is pseudo data. "04400220" is stored. By searching this data, the address 2004 is calculated from the data "04400220". "Accessed" can be detected.
[0023]
Alternatively, the address of a memory that is erroneously accessed may be used as the pseudo data as described below.
The pseudo data for the address 1FF8 (“RAM-1FF8”) is “00001FF8”.
The pseudo data for the address 1FFC (“RAM-1FFC”) is “00001FFC”.
The pseudo data for the address 2004 (“RAM-2004”) is “0000002004”.
The pseudo data for the address 2008 (“RAM-2008”) is “00002008”.
[0024]
Alternatively, as the pseudo data, a difference value between the address of the memory to be accessed originally and the address of the memory accessed erroneously may be used as described below.
For the address 1FF8 (“RAM-1FF8”), the pseudo data is “−8 (decimal number)”.
The pseudo data for the address 1FFC (“RAM-1FFC”) is “−4 (decimal number)”.
The pseudo data for the address 2004 (“RAM-2004”) is “+4 (decimal number)”.
For the address 2008 (“RAM-2008”), the pseudo data is set to “+8 (decimal number)”.
[0025]
As described above, the pseudo data generation unit 105e is set in each of a plurality of resources (memory of a plurality of addresses) as error cause analysis information, and can specify which resource (memory of which address). Generate a pseudo data value.
The test case generation unit 105 sets the resource-specific pseudo data information 106e generated by the pseudo data generation unit 105e for each resource before executing the test procedure, and then generates a test procedure for testing the operation of the functional model. The error analysis message generation unit 105d generates an error analysis message including the resource-specific pseudo data information 106e generated by the pseudo data generation unit 105e. In this way, as a result of executing the test procedure of the test case 106, it is possible to specify which resource is the resource that provided the result value from the result value obtained from the resource (resource-specific pseudo data information 106e).
[0026]
FIG. 5 is an explanatory diagram of the test procedure execution order information 106c generated by the test procedure execution order expected value generation unit 105c in the memory and recorded in the test case 106.
The test procedure execution order expected value generation unit 105c holds an expected value of the execution order when test accesses are sequentially generated according to the test scenario 102. As shown in FIG. 5, the execution order of the test access is not always the order of the test access IDs.
[0027]
As described above, the test case generation unit 105 generates a test procedure (test access) including a plurality of test procedures executed in a predetermined order. The test procedure execution order expectation value generation unit 105c generates an execution order of a plurality of test procedures as error cause analysis information, and records it as test procedure execution order information 106c.
The error analysis message generation unit 105d executes a test procedure that outputs an error analysis message in accordance with the test procedure execution order using the test procedure execution order information 106c generated by the execution order expected value generation unit 105c. Generated as a part of the unit 110.
[0028]
FIG. 6 is an explanatory diagram of the inter-test-access inheritance information 106f generated by the inter-test procedure inheritance relationship generation unit 105f and recorded in the test case 106.
The test case generation unit 105 generates a plurality of test procedures for realizing the test scenario 102. When the test case generation unit 105 determines the H / W resources used in the test access that realizes the test procedure, information on the H / W resources used in the test access generated so far (the test procedure illustrated in FIG. 2). Reference is made to the separate resource record information 105a) and the expected value of the test access execution order (the test procedure execution order information 106c shown in FIG. 5). When the test case generation unit 105 determines the H / W resource to be used in the test access to be generated this time, the test procedure inheritance relationship generation unit 105f extracts the test access ID that has already used the H / W resource.
For example, the test procedure inheritance relationship generation unit 105f uses REG2 and REG3 for the test access ID-0005, but according to the expected value of the execution order of the test procedure execution order information 106c shown in FIG. The test access ID using REG2 and the test access ID using REG3 are extracted from the test access IDs executed before -0005, and the test access ID related to the test access ID-0005 is extracted. Then, an inheritance relationship is generated in the reverse order of the execution order, that is, in the order of the test access ID-0002 and the test access ID-0001, and is held in the memory as inter-test procedure inheritance information 106f.
[0029]
FIG. 7 is an explanatory diagram of the error analysis message information 106e generated in the memory by the error analysis message generation unit 105e and recorded in the test case 106.
The error analysis message generation unit 105d includes test procedure configuration information 106a (FIG. 2), resource-specific access order / expected value information 106b (FIG. 3), resource-specific pseudo data information 106e (FIG. 4), and test procedure execution. From the order information 106c (FIG. 5) and the inter-test procedure inheritance information 106f (FIG. 6), the error analysis message information 106d is started from a test access that compares a resource value with an expected value among a plurality of test accesses. It is generated in a memory and output to the test case 106.
[0030]
For example, as shown in FIG. 7, the test access ID-0008 is a “test access type” that compares the expected value “3300” with respect to REG3 and the execution value stored in REG3 at the stage of executing the main test access. However, as a result of executing the test case 106 by the simulator 108, an error is detected at the test access ID-0008, and in preparation for a case where the test case is stopped, the expected value of the resource REG3 to be compared with the test access ID is obtained. Is displayed along with the error cause. That is, the result value obtained from the resource, the predicted error value (expected value), and one or more predicted error causes are displayed. If the cause of the error is determined, only the cause of the error is displayed.
[0031]
That is, with reference to the test procedure execution order information 106c (FIG. 5), the closest (previous) test access ID that accessed the resource REG3 was searched from the test access IDs executed before the test access ID-0008. As a result, the test access ID-0007 is extracted. Similarly, for the test access ID-0007, the test access ID-0005 that accessed the resource REG3 most recently is extracted. At this time, since the expected value “3000” should be stored in REG3 as a result of executing the test access ID-0005, “3000” is adopted as one of the error prediction values of the test access ID-0008. Then, a message "Test access-0005 is normal, test access-0007 failed" is displayed. Similarly, by presenting some error prediction values, when the value of REG3 at the stage of stopping the error with the test access ID-0008 during the execution of the test case matches any of these error prediction values, By reading the message, the cause of the error can be quickly pointed out.
[0032]
FIG. 7 shows the case where the starting point is a test access (test access ID-0008) that compares the value of the resource with the expected value. However, the present invention is not limited to the case where the starting point is the test access to be compared. Alternatively, an error result and an error factor may be generated and output. For example, in the test access ID-0005 in FIG. 7, the following error results and error factors may be generated and stored on the assumption that the pseudo data shown in FIG. 4 is set.
1. First error result and error factor of test access ID-0005
Expected value comparison error REG3: DATA-F88F1FF1.
The test access ID-0005 has failed, and the data “F88F1FF1” at address 1FF8 has been erroneously received.
2. Second error result and error factor of test access ID-0005
Expected value comparison error REG3: DATA-FCCF1FF1.
The test access ID-0005 has failed, and the data “FCCF1FF1” at the address 1FFC has been erroneously received.
3. Third error result and error factor of test access ID-0005
Expected value comparison error REG3: DATA-04400220.
The test access ID-0005 has failed, and the data “04400220” at the address 2004 is erroneously received.
4. Fourth error result and error factor of test access ID-0005
Expected value comparison error REG3: DATA-08802002.
The test access ID-0005 has failed, and the data “08802002” at the address 2008 is erroneously received.
[0033]
As described above, the test case generation unit 105 generates a test procedure including a plurality of test procedures executed in a predetermined order.
A cause analysis information generation unit 156 generates test procedure contents and information on resources used by the test procedure for each test procedure as error cause analysis information, and records the test procedure-specific resource recording unit 105a as test procedure configuration information 106a;
A test procedure execution order expected value generation unit 105c that generates an execution order of a plurality of test procedures as error cause analysis information and records the test procedure execution order information 106c as a test procedure execution order expected value;
Using the test procedure configuration information 106a generated by the test procedure-specific resource recording unit 105a and the test procedure execution order information 106c generated by the test procedure execution order expected value generation unit 105c, an error result is generated when the test procedure is executed. A test procedure inheritance relationship generation unit 105f that generates a test procedure to be caused as test procedure inheritance information 106f.
The error analysis message generation unit 105d stores the error analysis message information 106d in which a test procedure causing an error result is an error factor using the inter-test procedure inheritance information 106f generated by the inter-test procedure inheritance relationship generation unit 105f. And record it in the test case 106.
[0034]
The error cause analysis information described above may be the data and information shown in FIGS. 2 to 7, but may include a program or a routine that outputs analysis support information or an error analysis message using such information. These programs and routines constitute the error analysis unit 110.
[0035]
As described above, the system LSI function verification method of this embodiment is characterized in that error cause analysis information, analysis support information, and an error analysis message are output. That is, the system LSI function verification method according to the present embodiment includes a test procedure (step) that embodies a test item based on a product specification, which is created to verify a certain system LSI from a functional aspect. When a program (test case 106) is created, the test case 106 is executed by the simulator 108, and the procedure in which the error occurred and the system determined to be an error are prepared in case the result is determined to be an error. It is characterized in that it has means for estimating the cause of the error for each combination with the value (effective value) of the resource constituting the LSI and outputting it to the test case 106.
[0036]
Further, the system LSI function verification method of this embodiment is characterized in that information of each test procedure is recorded. That is, the system LSI function verification method according to the present embodiment prepares for the case where the execution result of the test case 106 results in an error. It is characterized by having a means for outputting information about and the contents of the procedure to the test case 106.
[0037]
Further, the system LSI function verification method of this embodiment is characterized in that an access order history of H / W resources is recorded. That is, the system LSI function verification method of this embodiment has means for outputting a procedure using resources for each resource configuring the system LSI in case an execution result of the test case 106 results in an error. It is characterized by.
[0038]
Further, the system LSI function verification method of this embodiment is characterized in that the inheritance between test procedures is recorded. That is, the system LSI function verification method according to the present embodiment includes a procedure for comparing a value (effective value) stored in the resources of the system LSI with an expected value in case an execution result of the test case 106 becomes an error. When the test case 106 executes another test procedure that uses the resources that are compared and compared with the procedure as a starting point, there is provided a means for outputting to the test case 106 an inheritance relationship based on an expected value of the execution order of each procedure. It is characterized by the following.
[0039]
Further, the system LSI function verification method of this embodiment is characterized in that information for analyzing the cause of an error is arranged in advance around resources where an error may occur. That is, the system LSI function verification method according to the present embodiment predicts an error and prepares a pseudo-simulation in the vicinity or all of the resources used in the test case 106 in preparation for an error in the execution result of the test case 106. In this case, there is provided a means for outputting information about the pseudo data to the test case 106 in case the effective value of the resource to be compared with the expected value matches the pseudo data.
[0040]
As a result, the created test case 106 has the following configuration.
1. A pseudo data setting unit that sets pseudo data to a resource before testing the operation of the functional model.
2. A test procedure section that tests the operation of a functional model that models circuit functions.
3. A cause analysis information storage unit that stores error cause analysis information for analyzing the cause of the error when the result of the test of the operation of the functional model by the test procedure unit results in an error, in association with the test procedure.
4. An error cause information providing unit (error analysis unit) that provides information for analyzing an error cause using the error cause analysis information stored in the cause analysis information storage unit.
[0041]
The cause analysis information storage unit stores the following information as error cause analysis information.
Test procedure configuration information 106a (FIG. 2)
Resource-specific access order / expected value information 106b (FIG. 3)
Resource-specific pseudo data information 106e (FIG. 4)
Test procedure execution order expected value information 106c (FIG. 5)
Test procedure inheritance information 106f (FIG. 6)
Error analysis message information 106d (FIG. 7)
[0042]
The cause analysis information storage unit may not be provided in the test case 106. It may be independently recorded in a file format on a memory or a disk.
[0043]
Further, the error cause information providing unit (error analyzing unit) may not be provided in the test case 106. It may be independently recorded in a file format on a memory or a disk.
[0044]
The cause analysis information storage unit does not need to store all the information as the error cause analysis information. What is necessary is just to hold at least one or more pieces of information. Desirably, the error analysis message information 106d (FIG. 7) contains a large amount of other information and is used for displaying and outputting a message to a user. It may be included in the error cause analysis information.
[0045]
FIG. 8 is a diagram illustrating an appearance of a program generation device (test case generation device) according to the first embodiment.
8, a program generation device (test case generation device) 100 includes a system unit 200, a CRT (Cathode Ray Tube) display device 41, a keyboard (K / B) 42, a mouse 43, a compact disk device (CDD) 86, and a printer. An apparatus 87 and a scanner 88 are provided, and these are connected by a cable. Further, the program generating device (test case generating device) 100 is connected to the FAX machine 310 and the telephone 320 by cables, and is also connected to the Internet 501 via the local area network (LAN) 5 and the web server 500. .
[0046]
FIG. 9 is a hardware configuration diagram of the program generation device (test case generation device) according to the first embodiment.
In FIG. 9, a program generation device (test case generation device) 100 includes a CPU (Central Processing Unit) 37 that executes a program. The CPU 37 includes a ROM 39 (an example of a nonvolatile storage device), a RAM 40 (an example of a memory and a volatile storage device), a communication board 44, a CRT display device 41, a K / B 42, a mouse 43, It is connected to an FDD (Flexible Disk Drive) 45, a magnetic disk device 46 (an example of a non-volatile storage device), a CDD 86, a printer device 87, and a scanner device 88. The communication board 44 is connected to the FAX machine 310, the telephone 320, the LAN 5, and the like.
For example, the communication board 44, the K / B 42, and the FDD 45 are examples of an information input unit. Alternatively, when the processing performed by the information input unit is configured by a program, the program may perform the processing using, for example, input devices such as the communication board 44, the K / B 42, and the FDD 45. Alternatively, the processing may be performed as an internal process of the CPU 37 by using the CPU 37.
Further, for example, the communication board 44 is an example of an output unit. When the processing performed by the output unit is configured by a program, the program may perform the processing using, for example, an output device called the communication board 44. Alternatively, the processing may be performed as an internal process of the CPU 37 by using the CPU 37.
Further, for example, the ROM 39, the RAM 40, and the magnetic disk device 46 are examples of a storage unit. When the processing performed by the storage unit is configured by a program, the program may perform the processing using, for example, a storage device such as the ROM 39, the RAM 40, and the magnetic disk device 46.
When each unit other than the above is configured by hardware, for example, the CPU 37 is an example of each unit other than the above. When the processing performed by each unit other than the above is configured by a program, the program causes the CPU 37 to perform the processing.
[0047]
Here, the communication board is not limited to the LAN 5 and may be directly connected to the Internet or a WAN (Wide Area Network) such as ISDN. When directly connected to the Internet or a WAN such as ISDN, the program generation device 100 is connected to the Internet or a WAN such as ISDN, and the web server 500 is unnecessary.
The magnetic disk device 46 stores an operating system (OS) 47, a window system 48, a program group 49, and a file group 50. The program group is executed by the CPU 37, the OS 47, and the window system 48.
[0048]
In the program group 49, when what is described as “test work”, “simulator” or “section” in the description of the embodiment is realized by a program, the program is stored. Also, what is described as "test work", "simulator" or "-unit" is referred to as "-process", "-routine", "-means", "-process", "-step", "-device". By substituting, the invention of the program, the invention of the method, and the invention of the system can be made.
[0049]
In the file group, those described as “test scenario”, “test case”, “functional model”, “test bench”, “—result”, and “—information” in the description of the above-described embodiment are “—files”. It is stored as
[0050]
Also, what is described as “-unit” in the description of the embodiment may be realized by firmware stored in the ROM 39. Alternatively, the present invention may be implemented only with software, only with hardware, a combination of software and hardware, or a combination with firmware.
[0051]
Further, the program for implementing the embodiment is also provided by other recording media such as a magnetic disk device, an FD (Flexible Disk), an optical disk, a CD (Compact Disk), an MD (Mini Disk), and a DVD (Digital Versatile Disk). It may be stored using a recording device.
[0052]
In the above description, the operation of “storing” and “holding” refers to electrically or magnetically storing information or data in a file format or a variable format in a program in a memory or a storage device. In addition, the operations of “test”, “execute”, “generate”, “analyze”, and “determine” are also performed by storing information or data in a memory or a storage device electrically or magnetically in a file format. Or in the form of variables in the program.
[0053]
【The invention's effect】
According to the present invention, for example, when a test case representing a test procedure for a system LSI to be tested is executed on a simulator, an error analysis operation, which is an operation that occurs when an error occurs, is displayed on the test case. It is possible to greatly reduce the number of errors by comparing the estimated error values with the effective values of the error occurrence location and the error target resource displayed in the execution result of the test case.
[Brief description of the drawings]
FIG. 1 is an overall configuration diagram according to a first embodiment.
FIG. 2 is an explanatory diagram of test procedure configuration information a generated by a test procedure-specific resource recording unit 105a in a memory and recorded in a test case 106;
FIG. 3 is an explanatory diagram of resource-specific access order / expected value information 106b generated in a memory by a resource-specific access order / expected value generation unit 105b and recorded in a test case 106;
FIG. 4 is an explanatory diagram of resource-specific pseudo data information 106e generated by a pseudo data generation unit 105e in a memory and recorded in a test case 106.
FIG. 5 is an explanatory diagram of test procedure execution order information 106c generated in a memory by a test procedure execution order expected value generation unit 105c and recorded in a test case 106.
FIG. 6 is an explanatory diagram of test access inheritance information 106f generated by a test procedure inheritance relationship generation unit 105f and stored in a test case 106;
FIG. 7 is an explanatory diagram of error analysis message information 106e generated in a memory by an error analysis message generation unit 105e and recorded in a test case 106;
FIG. 8 is a diagram illustrating an appearance of a program generation device (test case generation device) according to the first embodiment.
FIG. 9 is a hardware configuration diagram of a program generation device (test case generation device) according to the first embodiment.
[Explanation of symbols]
5 LAN, 37 CPU, 38 bus, 39 ROM, 40 RAM, 41 CRT display device, 42 K / B, 43 mouse, 44 communication boat, 45 FDD, 46 magnetic disk device, 47 OS, 48 window system, 49 program group, 50 files, 86 CDD, 87 printer, 88 scanner, 100 program generator, 101 product specification, 102 test scenario, 103 resource configuration information, 104 functional model, 105 test case generator, 105a resource record for each test procedure Section, 105b resource-specific access order / expected value generator, 105c test procedure execution order expected value generator, 105d error analysis message generator, 105e pseudo data generator, 105f test procedure inheritance relationship generator, 106 test case, 106a Examination procedure Configuration information, 106b Access order / expected value information for each resource, 106c Test procedure execution order information, 106d Error analysis message information, 106e Pseudo data information for each resource, 106f Inheritance information between test procedures, 107 test bench, 108 simulator, 109 test Case execution result, 110 error analysis unit, 200 system unit, 310 fax machine, 320 telephone, 500 web server, 501 Internet.

Claims (10)

A test case generation unit that generates a test procedure for testing the operation of a functional model obtained by modeling a circuit having a plurality of resources and stores the test procedure as a test case;
When a result of a test of the operation of the functional model by the test procedure generated by the test case generation unit results in an error, a cause analysis information generation unit that generates and stores error cause analysis information for analyzing the cause of the error is provided. A test case generation device. The cause analysis information generation unit includes a pseudo data generation unit that generates pseudo data that is set for each of a plurality of resources as error cause analysis information and that can specify which resource the resource is,
The test case generation unit generates a test procedure for setting the pseudo data generated by the pseudo data generation unit to each resource before testing the operation of the functional model,
2. The method according to claim 1, wherein, as a result of the execution of the test procedure, when a result value obtained from the resource is pseudo data, it is possible to specify which resource provided the result value. Test case generator. The cause analysis information generation unit includes an error analysis message generation unit that generates a correspondence between an error result and the error factor and an error analysis message as error cause analysis information,
The test case generation unit executes a test in which an expected value to be held in the resource when the test is executed on the resource is known, and by executing the test, a result value obtained from the resource is obtained. Determining whether the test result is an error by comparing the expected value with an expected value, and generating a test procedure for outputting an error analysis message when the test result is determined to be an error. Item 3. The test case generation device according to item 1 or 2. The cause analysis information generation unit includes:
An expected value generation unit for each resource that generates an expected value expected to be held in the resource when the test procedure is executed and the resource is tested,
The test case generator is configured to compare a result value obtained from the resource when the resource is tested with the expected value generated by the resource-specific expected value generator to determine whether the test result is an error. The test case generation device according to claim 1, wherein the test case generation device generates a procedure. The test case generation unit generates a test procedure including a plurality of test procedures to be executed in a predetermined order,
The cause analysis information generating unit includes a test procedure-specific resource recording unit that generates test procedure contents and resource information used by the test procedure for each test procedure as error cause analysis information, and records the information as test procedure configuration information.
4. The test case generation apparatus according to claim 3, wherein the error analysis message generation unit generates the error analysis message using the test procedure configuration information recorded by the test procedure-specific resource recording unit. The test case generation unit generates a test procedure including a plurality of test procedures to be executed in a predetermined order,
The cause analysis information generation unit includes a test procedure execution order expected value generation unit that generates an execution order of a plurality of test procedures as error cause analysis information and records the execution order as a test procedure execution order expected value.
4. The test case generation device according to claim 3, wherein the error analysis message generation unit generates the error analysis message using the test procedure execution order expected value generated by the cause analysis information generation unit. The test case generation unit generates a test procedure including a plurality of test procedures to be executed in a predetermined order,
The cause analysis information generation unit includes:
A test procedure-specific resource recording unit that generates test procedure contents and resource information used by the test procedure for each test procedure as error cause analysis information, and records the information as test procedure configuration information;
A test procedure execution order expected value generation unit that generates an execution order of a plurality of test procedures as error cause analysis information and records the test procedure execution order expected value;
A test procedure that causes an error result when a test procedure is executed using the test procedure configuration information generated by the test procedure resource recording unit and the test procedure execution order expected value generated by the test procedure execution order expected value generation unit. And an inter-procedure inheritance relationship generation unit that generates
The error analysis message generation unit generates an error analysis message using a test procedure that causes an error result as an error factor, using the inter-test procedure inheritance information generated by the inter-test procedure inheritance relationship generation unit. The test case generation device according to claim 3. A test case generating step of generating a test procedure for testing the operation of a functional model obtained by modeling a circuit having a plurality of resources and storing the test procedure as a test case;
A cause analysis information generation step of generating and storing error cause analysis information for analyzing the cause of the error when the result of the test of the operation of the functional model by the test procedure generated by the test case generation step results in an error; A test case generation method characterized in that: A test procedure unit for testing the operation of the functional model that models the circuit,
When the result of the test of the operation of the functional model by the test procedure unit results in an error, a cause analysis information storage unit for storing error cause analysis information for analyzing the cause of the error in association with the test procedure is provided. Test case to be characterized. A test procedure for testing the operation of the functional model that models the circuit; and
A cause analysis information generating step of generating error cause analysis information for analyzing an error cause in advance corresponding to a test procedure and storing the information in a memory;
A cause analysis information display step of displaying the error cause analysis information stored in the memory in the cause analysis information generation step in accordance with the test procedure when the result of the test of the operation of the functional model in the test procedure step results in an error. A test method characterized by the following:

Images