JP2004319848A - Semiconductor device and its manufacturing process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a compound function which can be provided as a thin and compact product where a semiconductor chip is mounted on a wiring board while being embedded. <P>SOLUTION: A substrate where a wiring pattern 17 is connected electrically between layers through copper bumps is formed by hot pressing a copper foil provided with copper bumps through a prepreg 20. The wiring pattern 17 is formed on the outer surface of the substrate by etching the copper foil exposed to the outer surface of the substrate according to a specified pattern. One side of the substrate is then counterbored to form a cavity 22 for mounting a semiconductor chip, the end face of a copper bump 16b is exposed to the mounting surface of the semiconductor chip on the inner surface of the cavity 22 and the copper bump 16b and the semiconductor chip 30 are connected electrically. The semiconductor chip 30 is then mounted in the cavity 22 and the cavity 22 is filled with resin 24 thus sealing the semiconductor chip 30. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device formed using a copper foil with a copper bump formed with a copper bump integrally with a copper foil and a method for manufacturing the same.
[0002]
[Prior art]
In a wiring board on which a semiconductor chip is mounted, while the wiring pattern is formed at a high density with the increase in the integration of the semiconductor chip, the thickness of the board is reduced. Further, in addition to a product in which a single semiconductor chip is mounted in one package, a composite product in which a plurality of semiconductor chips are mounted in one package is also manufactured as a semiconductor device.
As a method of manufacturing such a wiring board, a manufacturing method such as a so-called build-up method in which wiring patterns are sequentially laminated while electrically connecting wiring patterns between layers via vias has been used.
[0003]
By the way, recently, there has been proposed a method of forming a wiring board using a copper foil with a copper bump in which a copper bump is formed integrally with the copper foil (for example, see Patent Documents 1 and 2). This copper foil with copper bumps can be formed by etching a copper foil to form a wiring pattern, and by laminating wiring patterns by using the copper bumps as vias to electrically connect the wiring patterns between layers. It can be used for the production of a wiring board to be used.
Since the copper foil with the copper bumps is formed as thin as 100 μm or less, it is possible to reduce the thickness of the wiring board, and since the copper bumps are formed with a small diameter, the wiring patterns are arranged at a high density. It becomes possible. Further, by using the copper bumps for the vias, it is not necessary to form a via hole in the insulating layer by laser processing or to perform plating, and it is possible to easily manufacture the wiring board.
[0004]
On the other hand, as a method of manufacturing a wiring substrate, the applicant has formed a cavity by a method of performing counterboring with a cutting blade from one surface side of a substrate having a wiring pattern formed on an inner layer to expose a required portion of the inner layer. A method of manufacturing a wiring board by mounting a semiconductor chip in a cavity has been proposed (for example, see Patent Document 3). The method of forming the cavity for mounting the semiconductor chip by using the counterbore processing has the advantage that the wiring board can be prevented from being deformed and can be provided as a highly reliable semiconductor device.
[0005]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2001-326559 [Patent Document 2]
Japanese Patent Application Laid-Open No. 2002-26479 [Patent Document 3]
JP-A-2002-26479
[Problems to be solved by the invention]
As described above, a method of forming a cavity for mounting a semiconductor chip by performing a counterboring process on a substrate having a wiring pattern formed in an inner layer, and forming a semiconductor device by mounting a semiconductor chip in the cavity is performed by forming a thin substrate. If it is possible, the thickness of the semiconductor device can be reduced. However, in the case of a conventional method of manufacturing a wiring board in which wiring patterns are stacked by a build-up method or the like, there is a problem that the wiring board cannot always be formed effectively thinly. There was a problem of becoming complicated.
[0007]
In addition, in order to form a cavity for mounting a semiconductor chip on a wiring board, a method of manufacturing a wiring board by laminating substrates with windows corresponding to portions where the cavities are to be formed, a method of forming a cavity when the substrates are laminated. If the lower substrate is pushed into the inside of the prepreg and it becomes a curved shape, and if the flowability of the prepreg is insufficient when laminating the substrates via the prepreg, the gap between the laminated substrates is not filled with resin. When the prepreg has high flowability, the resin oozes into the cavity.
[0008]
Therefore, the present invention has been made to solve these problems, and an object of the present invention is to provide a semiconductor device that can easily form a wiring pattern with high density and can easily form a thin wiring pattern. And a method of manufacturing the same.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention has the following configuration.
That is, in a semiconductor device in which a semiconductor chip is mounted in a cavity formed in a wiring substrate by being sealed with a resin, the wiring substrate is electrically connected to a wiring pattern between layers via filled vias or inner layer pads, The cavity is counterbored to expose the end face of the filled via or the inner layer pad on the mounting surface of the semiconductor chip on the inner surface of the cavity, and the end face of the filled via or the inner layer pad is electrically connected to the semiconductor chip. Features.
[0010]
Further, in a semiconductor device in which a semiconductor chip is mounted in a cavity formed in a wiring board by being sealed with a resin, the wiring pattern is formed by a copper foil with a copper bump, and an interlayer is formed by a copper bump. Are formed by electrically connecting the wiring patterns, the cavity is counterbored, and the end surface of the copper bump is formed on the mounting surface of the semiconductor chip on the inner surface of the cavity, and the end surface of the copper bump and the semiconductor chip are formed. Are electrically connected to each other.
Further, the entire area of the wiring board including the area where the cavity is formed, on the side of the wiring board where the cavity is formed, is formed as a circuit area where a wiring pattern is formed or a circuit component is mounted. It is characterized by.
Further, the end face of the copper bump and the semiconductor chip are electrically connected by flip chip connection, and the end face of the copper bump and the semiconductor chip are electrically connected by wire bonding connection. And
[0011]
Further, in the method of manufacturing a semiconductor device, a copper foil with copper bumps is pressed and heated via a prepreg to form a board in which wiring patterns are electrically connected between layers by the copper bumps, and the board is exposed to an outer surface of the board. By etching the copper foil into a predetermined pattern, a wiring pattern is formed on the outer surface of the substrate, and a counterboring process is performed from one surface side of the substrate to form a cavity for mounting a semiconductor chip, and an inner surface of the cavity is formed. Exposing the end surface of the copper bump to the mounting surface of the semiconductor chip, electrically connecting the copper bump to the semiconductor chip, mounting the semiconductor chip in the cavity, filling the cavity with resin, and sealing the semiconductor chip. It is characterized by stopping.
Further, a wiring pattern is formed in a predetermined pattern on the entire surface of the substrate on which the cavity is formed.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. 1 and 2 are explanatory views showing a method for manufacturing a semiconductor device according to the present invention.
FIG. 1A shows a resin substrate 10 serving as a core portion of a wiring substrate constituting a semiconductor device. The resin substrate 10 is formed by forming a through hole in a double-sided copper-clad substrate, plating the through hole with a through hole, forming a conductor portion 12 in the through hole, and etching the copper foil on both surfaces of the substrate into a predetermined pattern. Are obtained by forming the wiring patterns 14 on both sides of the substrate. The conductor portion 12 may be formed so as to fill the through hole by plating, or a conductor layer may be formed on the inner wall surface of the through hole so that the wiring patterns 14 on both surfaces are electrically connected. .
[0013]
In the actual manufacturing process, a large-sized resin substrate for multi-cavity processing is used as a work, and the large-sized work is processed as required to manufacture a semiconductor device. FIG. 1A shows, for the sake of explanation, one unit portion which becomes an individual semiconductor device in a multi-piece resin substrate. The same applies to the following drawings.
[0014]
FIG. 1B shows a step of forming a wiring pattern by laminating a wiring pattern on an upper layer and a lower layer of the resin substrate 10. In the figure, reference numerals 16 and 18 denote copper foils with copper bumps used for forming a wiring pattern. 16a and 16b are copper bumps formed integrally with the copper foil 16 with copper bumps, and 18a is a copper bump formed integrally with the copper foil 18 with copper bumps. The copper bumps 16a and 18a are formed in alignment with the plane arrangement of the wiring pattern 14 formed on the resin substrate 10, and the copper bumps 16b are aligned with the plane arrangement of connection electrodes of a semiconductor chip mounted on the substrate. It is formed.
[0015]
In this embodiment, since the semiconductor chip is electrically connected to the copper bump 16b by flip-chip connection, the copper bump 16b is arranged in the same plane as the connection electrode of the semiconductor chip. When electrically connecting by wire bonding, the arrangement position of the copper bump 16b is set in accordance with the bonding position with the semiconductor chip.
[0016]
In FIG. 1B, reference numeral 20 denotes a prepreg for integrally joining the copper foils 16 and 18 with copper bumps to the resin substrate 10. When the copper foils with copper bumps 16 and 18 are pressed and heated with the prepreg 20 sandwiching the resin substrate 10 from both sides, the tops of the copper bumps 16 a and 18 a of the copper foil with copper bumps 16 are formed on the resin substrate 10. In this case, the copper bumps 16a, 18a and the wiring pattern 14 are joined in a state where they are electrically connected. The tops of the copper bumps 16a and 18a are formed to have a small diameter, and are formed so as to be securely inserted into the wiring pattern 14 so that electrical conduction is ensured.
Then, the prepreg is melted and hardened, so that the copper foils 16 and 18 with copper bumps are integrally joined to the resin substrate 10 in a state where the copper bumps 16a and 18a are embedded in the wiring pattern 14. FIG. 1C shows a state where the copper foils 16 and 18 with copper bumps are bonded to the resin substrate 10 via the prepreg 20.
[0017]
FIG. 2A shows that, after bonding copper foils 16 and 18 with copper bumps to the resin substrate 10, the copper foil of copper foil 16 with copper bumps and the copper foil of copper foil 18 with copper bumps are etched into a predetermined pattern. The state where the wiring patterns 17 and 19 are formed is shown.
Since the copper foil and the copper bumps 16a, 16b, 18a are previously formed integrally with the copper foils with copper bumps 16, 18, the copper bumps 16a, 16b, 18a are formed by etching the copper foil to form wiring patterns. The wiring patterns 17 and 19 can be obtained in a state where they are electrically connected.
[0018]
FIG. 2 (b) shows the counterboring of the substrate from one side of the substrate, which is the side opposite to the side on which the copper bumps 16b connected to the semiconductor chip are formed, to form a cavity 22 for mounting the semiconductor chip. It shows the state where it was done. In the counterboring process, a cavity 22 is formed by rotating a cutting blade for counterboring into the substrate from one surface side of the substrate and cutting required portions of the prepreg 20 and the resin substrate 10.
In the present embodiment, the counterbore processing is performed so that the end face A of the copper bump 16b formed in an upright shape on the lower surface of the substrate is exposed on the mounting surface of the cavity 22 on which the semiconductor chip is mounted. By controlling the cutting position by the cutting blade while detecting the height position of the end face of the copper bump 16b by the cutting blade, it is possible to form the cavity 22 so as to open on one surface side of the substrate as shown in the figure. it can.
[0019]
After the cavities 22 are formed by counterboring, the exposed end faces of the copper bumps 16b are plated with nickel, gold, or the like, and the semiconductor chip 30 is mounted in each of the cavities 22 as a large-sized work. . The semiconductor chips 30 may be individually mounted after cutting a large-sized work into individual pieces.
FIG. 2C shows a state in which the connection electrodes of the semiconductor chip 30 are aligned with the copper bumps 16b, the semiconductor chip 30 is mounted by flip-chip connection, and then the semiconductor chip 30 is underfilled with the resin 24. . In the figure, the outer surface of the semiconductor chip 30 is sealed with the resin 24. However, the resin 24 only needs to underfill the connection portion between the connection electrode of the semiconductor chip 30 and the copper bump 30 at least to the outer surface portion of the semiconductor chip 30. It does not have to be completely sealed.
[0020]
FIG. 3 shows a state in which an external connection terminal 26 is joined to the wiring pattern 19 of the substrate to form a mountable semiconductor device. The example shown in FIG. 3 is an example formed as a face-down type semiconductor device. Of course, the semiconductor device is not limited to the face-down type.
The copper bumps 16a and 18a are used as vias for electrically connecting wiring patterns between layers, and the copper bumps 16b are used as vias for electrically connecting the semiconductor chip 30 and the wiring pattern 17.
The semiconductor device of the present embodiment is formed by using the copper foils 16 and 18 with copper bumps with the resin substrate 10 as a core portion, and is a very thin semiconductor device having a thickness of about 0.3 to 0.5 mm. Is obtained as
[0021]
The semiconductor device of the above embodiment is an example in which the semiconductor chip 30 is mounted by flip chip connection. FIG. 4 shows an example in which the semiconductor chip 30 is mounted by wire bonding connection. 28 is a bonding wire. When the semiconductor chip 30 is mounted by wire bonding connection, a copper foil with copper bumps in which the copper bumps 16b are slightly displaced from the position where the semiconductor chip 30 is mounted in the cavity 22 may be used. A copper foil 16 with copper bumps 16c used as thermal vias may be used as the copper foil 16 with copper bumps. By exposing the end face of the copper bump 16c by counterboring, it can be used as a suitable thermal via.
[0022]
As described above, in the method of manufacturing a semiconductor device according to the present invention, after forming the wiring board using the resin substrate 10 and the copper foils 16 and 18 with copper bumps, the cavity for mounting the semiconductor chip 30 by counterboring processing. 22 are formed. In the case where the cavity 22 is formed by the counterbore processing as described above, the substrate can be manufactured without warping and deforming the substrate in the step of laminating and forming the wiring layers, so that a thin semiconductor device is manufactured. It is extremely effective as a method.
Further, in the case of the counterbore processing, when forming the cavity 22, the depth position of the cavity can be accurately processed, and there is an advantage that the cavity can be easily processed accurately even in a thin package. .
[0023]
In particular, in the present embodiment, since the wiring board is formed by combining the resin substrate 10 and the copper foils 16 and 18 with copper bumps, there is a method of laminating wiring patterns by a conventional build-up method or the like to form a board. There is an advantage that a thin substrate can be easily formed as compared with the above. In the case of using a copper foil with copper bumps to create a wiring board, as in the case of the build-up method, laser processing is applied to the insulating layer to form a via hole, or plating is applied to the board to form a conductive layer. Is not required.
[0024]
In addition, since copper bumps can be formed with a very small diameter in copper foil with copper bumps, it is easy to form copper bumps according to the electrode arrangement in flip-chip connection and the bonding part arrangement in wire bonding connection. is there. If the wiring board is formed using copper foil with copper bumps, the copper bumps are used as vias to electrically connect wiring patterns between layers, and counterboring is performed to expose the end faces of the copper bumps There is an advantage that the end face of the copper bump can be formed at the connection portion with the semiconductor chip by itself. This is because the entire area of the end face of the copper bump, like the filled via, is a conductor, and the entire end face exposed by the counterboring process can be used as a connection terminal portion.
[0025]
In the semiconductor device shown in FIGS. 3 and 4, the wiring pattern 19 is formed on the surface of the wiring substrate on which the semiconductor chip 30 is mounted, excluding the region where the cavity 22 is formed. Since the semiconductor chip 30 is completely sealed with the resin 24, the entire surface including the region where the cavity 22 is formed on the surface side on which the semiconductor chip 30 is mounted can be used as a region for forming a wiring pattern. It is.
[0026]
FIG. 5 shows an example of manufacturing a semiconductor device in which the entire surface of the substrate including the region where the cavity 22 is formed is used as a region for forming a wiring pattern.
FIG. 5A shows a state in which a semiconductor chip 30 is mounted in a cavity formed by performing a counterboring process on a substrate by flip-chip connection, and the semiconductor chip 30 is sealed with a resin 24 on a substrate 40 via a prepreg 32 with copper bumps. The step of bonding the attached copper foil 34 is shown. In the case of this manufacturing method, the cavity 22 is preferably filled with the resin 24 because the copper foil 34 with copper bumps is bonded to the substrate 40. On the copper foil with copper bumps 34, copper bumps 34a are formed in alignment with the wiring patterns 19 formed on one end surface of the substrate 40.
[0027]
FIG. 5B shows a state in which the prepreg 32 and the copper foil with copper bumps 34 are pressed and heated with respect to the substrate 40, and the copper foil with copper bumps 34 is bonded to the substrate 40 via the prepreg 32.
FIG. 5C shows a state in which the copper foil 34b of the copper foil 34 with copper bumps is etched into a predetermined pattern to form the wiring pattern 36 on one surface of the substrate 40. By etching the copper foil 34, it is possible to obtain a semiconductor device in which the entire area of one surface of the substrate 40 is a region where the wiring pattern 36 is formed.
[0028]
As described above, by setting the entire area of the substrate including the area where the cavity 22 is formed on the surface side on which the semiconductor chip 30 is mounted as the area for forming the wiring pattern, the wiring pattern can be easily routed within the substrate, It is possible to combine the components such as mounting circuit components on the outer surface of the substrate. Thereby, the semiconductor chip 30 is mounted so as to be embedded in the substrate, and it is possible to provide a semiconductor device having more complex functions.
[0029]
In the above-described embodiment, an example in which one semiconductor chip 30 is mounted on one package has been described. However, it is of course possible to form a plurality of semiconductor chips on one package. As a semiconductor device. Further, by mounting circuit components such as a capacitor and a resistor on the semiconductor device, a semiconductor device having a more complex function can be obtained.
As a method of mounting a plurality of semiconductor chips and circuit components in one semiconductor device, a method of mounting a plurality of semiconductor chips and circuit components in one cavity is possible, and a counterboring process is performed in one semiconductor device. It is also possible to form a plurality of cavities and mount one or a plurality of semiconductor chips in each cavity.
[0030]
FIG. 6 shows an example in which the wiring substrate is formed using only the copper foil with the copper bumps without using the resin substrate 10 as the core of the wiring substrate.
FIG. 6A shows a process in which the prepreg 20 is arranged so as to be sandwiched between the copper foil 11 with the copper bumps 11a formed with the copper bumps 11a and the copper foil 11b, and is pressed and heated to form a core portion of the substrate. After integrating the copper foil with copper bump 11 and the copper foil 11b via the prepreg 20, the copper foil portion of the copper foil with copper bump 11 and the copper foil 11b are etched into a predetermined pattern to form wiring patterns 11c and 11d. To form a core.
[0031]
6B, copper foils 16 and 18 with copper bumps are applied to both surfaces of a core portion formed by using copper foil 11 with copper bumps via a prepreg 20 in the same manner as shown in FIG. 3 shows a step of pressing under pressure and heating.
FIG. 6C shows a substrate on which copper foils 16 and 18 with copper bumps are integrally joined via a prepreg 20.
FIG. 6D shows a state in which the cavity 22 is formed in the substrate by counterbore processing, the end face of the copper bump 16 b is exposed, the semiconductor chip 30 is mounted by flip-chip connection, and the semiconductor chip 30 is sealed with the resin 24. Is shown. As described above, it is also possible to form a substrate using only a copper foil with a copper bump without using a resin substrate.
[0032]
As described above, in the method of manufacturing a semiconductor device according to the present invention, efficient manufacturing is possible by manufacturing a large-sized substrate for multi-piece fabrication as a work. Using a large-sized copper foil with a copper bump and a prepreg, pressurizing and heating the copper foil with a copper bump so as to be aligned to form a large-sized substrate, and performing a counterboring process to mount the semiconductor chip 30 in the cavity. By forming a connection portion that is electrically connected to the semiconductor chip 30 at the same time as forming the semiconductor device, it is possible to manufacture a semiconductor device extremely efficiently.
[0033]
In the above embodiment, as a preferred example of the use of the copper foil with copper bumps, a method of manufacturing a semiconductor device in which circuit components such as a semiconductor chip or a capacitor and a resistor are incorporated in a substrate by applying counterboring processing has been described. Copper foil with copper bumps can be used effectively as conductors (vias) that electrically connect wiring patterns and the like between layers, and flip chip connection by exposing the entire end surface of copper bumps as a conductor when counterboring There is an advantage that it can be suitably used as a terminal. This is not limited to the copper foil with copper bumps, and the method of manufacturing a semiconductor device according to the present invention can be similarly applied to a case where a via used for electrical connection between layers is formed as a filled via. The filled via can be formed by, for example, filling the via hole by plating, or by using a copper or silver paste.
[0034]
In addition to the case using filled vias, as shown in FIG. 7A, a via hole is formed by laser processing from the lower surface side of the laminated plate with respect to the laminated plate provided with pad-shaped wiring patterns 50 on the inner layer. After forming a conductive layer on the inner surface of the via hole by plating to form a via, a counterbore process is performed from the upper surface side of the laminate to form a cavity 52 for housing a semiconductor chip or the like (FIG. 7B). It is also possible. The wiring pattern 50 is exposed on the bottom surface of the cavity 52 by the counterbore processing, and the wiring pattern 50 is electrically connected to the connection portion formed on the outer surface of the substrate via the via 54. After mounting a semiconductor chip or a circuit board in the cavity 52, a prepreg is laminated to fill the cavity 52, and the concave portion of the via 54 is filled. In addition, after forming the via hole and plating the inner surface of the via hole without forming the wiring pattern 50 for the inner layer pad, the concave portion of the via hole is filled with a prepreg, and the inner fixed surface of the cavity 52 is formed by counterboring. The package can also be formed such that the end face of the via is exposed.
[0035]
As described above, when a large number of connection parts for mounting are present at extremely small intervals, such as when mounting a semiconductor chip by flip chip connection, solder adheres to other connection patterns at the connection parts. It is necessary to surely avoid the problem of short circuit. It is possible to expose these connection parts by shaving, but as a method of preventing a short circuit with other patterns, a form in which only the connection end face is exposed, that is, copper bumps or A counterboring method that exposes an end face of a filled via or the like is extremely effective. The present invention can be applied not only to the case where the layers are connected by the copper bumps but also to the case where a package having a filled via or an inner layer pad is formed as described above.
[0036]
【The invention's effect】
According to the semiconductor device and the method of manufacturing the same according to the present invention, an extremely thin and compact product can be provided as a product in which a semiconductor chip is embedded in a wiring board. In particular, by using a copper foil with copper bumps, wiring patterns can be easily electrically connected between layers, so that a semiconductor device having a composite function can be provided. To play.
[Brief description of the drawings]
FIG. 1 is an explanatory view illustrating a method for manufacturing a semiconductor device according to the present invention.
FIG. 2 is an explanatory view illustrating a method for manufacturing a semiconductor device according to the present invention.
FIG. 3 is a cross-sectional view of the semiconductor device in a state where external connection terminals are joined.
FIG. 4 is a sectional view showing another embodiment of the semiconductor device.
FIG. 5 is an explanatory view showing another method of manufacturing the semiconductor device.
FIG. 6 is an explanatory view showing still another method of manufacturing a semiconductor device.
FIG. 7 is an explanatory view showing still another method of manufacturing the semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Resin board 11 Copper foil with copper bumps 12 Conductor parts 14, 17, 19, 36 Wiring patterns 16, 18, 34 Copper foils with copper bumps 16a, 16b, 16c, 18a Copper bumps 20, 30, 32 Prepreg 22 Cavity 24 Resin 26 external connection terminal 30 semiconductor chip 40 substrate 50 wiring pattern 52 cavity

Claims (7)

In a semiconductor device in which a semiconductor chip is mounted in a cavity formed in a wiring board by being sealed with a resin,
The wiring pattern is electrically connected between the layers via the filled via or the inner layer pad,
The cavity is counterbored to expose the filled via or the pad end surface of the inner layer on the mounting surface of the semiconductor chip on the inner surface of the cavity,
A semiconductor device, wherein an end face of the filled via or the pad of the inner layer and the semiconductor chip are electrically connected. In a semiconductor device in which a semiconductor chip is mounted in a cavity formed in a wiring board by being sealed with a resin,
The wiring board is formed by forming a wiring pattern by copper foil with copper bumps, and electrically connecting wiring patterns between layers by copper bumps,
The cavity is counterbored, and the end surface of the copper bump is formed on the mounting surface of the semiconductor chip on the inner surface of the cavity, and is formed,
A semiconductor device, wherein an end face of the copper bump and the semiconductor chip are electrically connected. The whole area of the wiring board including the area where the cavity is formed, on the side of the wiring board where the cavity is formed, is formed as a circuit area where a wiring pattern is formed or a circuit component is mounted. 3. The semiconductor device according to claim 1, wherein: 4. The semiconductor device according to claim 2, wherein the end face of the copper bump and the semiconductor chip are electrically connected by flip-chip connection. 4. The semiconductor device according to claim 2, wherein an end face of the copper bump and the semiconductor chip are electrically connected by wire bonding connection. Pressing and heating the copper foil with copper bumps through the prepreg to form a board that electrically connects the wiring patterns between layers by the copper bumps,
By etching the copper foil exposed on the outer surface of the substrate into a predetermined pattern, a wiring pattern is formed on the outer surface of the substrate,
A counterboring process is performed from one surface side of the substrate to form a cavity for mounting the semiconductor chip, and an end surface of the copper bump is exposed on the mounting surface of the semiconductor chip on the inner surface of the cavity,
Electrically connecting the copper bump and the semiconductor chip, mounting the semiconductor chip in the cavity,
A method of manufacturing a semiconductor device, comprising filling a cavity with a resin and sealing a semiconductor chip. 7. The method of manufacturing a semiconductor device according to claim 6, wherein a wiring pattern is formed in a predetermined pattern over the entire area of the surface of the substrate on which the cavity is formed.

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