JP2004362509A - Clock abnormality detection system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily detect abnormality of a standard clock signal (system clock) in an integrated circuit in a short time. <P>SOLUTION: Each integrated circuit 101 constituting a clock abnormal detection system 100 has a delay signal output part 2 delaying the standard clock signal with a plurality of delay elements connected in a multiple stage and outputting the delay signal for every stages, a synchronizing signal detection part 3 detecting a plurality of delay signals synchronized with the standard clock signal out of the delay signals outputted from the delay signal output part 2, based on a plurality of delay signals detected by the synchronizing signal detection part 3, and a delay stage number operation part 4 calculating the number of stages of the delay elements related to one cycle of the standard clock signal. A storage part 11 stores the value of the number of stages of the delay elements calculated by the delay stage number operation part 4 of each integrated circuit 101. An abnormity detection part 10 detects the abnormality of the standard clock signal in each integrated circuit based on the value of the number of stages of the delay element in each integrated circuit stored by the storage part 11. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock abnormality detection system that detects an abnormality of a clock signal in an integrated circuit.
[0002]
[Prior art]
In general, external noise or the like enters a system clock that operates an LSI (Large Scale Integration) or an ASIC (Application Specific Integrated Circuit) or the like, which causes a malfunction of the LSI. Conventionally, in order to detect such an abnormality of the LSI, an operation of confirming the operation of the system clock with an oscilloscope or the like has been performed by bringing a probe into contact with an electrode of the chip of the LSI. Further, there has been proposed a device that detects that an LSI is affected by external noise and automatically recovers from a malfunction state (for example, see Patent Document 1).
[0003]
[Patent Document 1]
JP 2000-190747 A
[0004]
[Problems to be solved by the invention]
However, in the above-described method of detecting an abnormality of an LSI by using a probe, when a plurality of LSIs are mounted on one board, it is necessary to confirm an abnormality of each LSI by using a probe. Therefore, there is a problem that it takes time to identify the LSI that has caused the abnormality of the system clock. Further, the technique disclosed in Patent Document 1 has a problem in that it is only possible to detect an abnormality of a system clock caused by external noise, but cannot detect an abnormality due to other factors.
[0005]
An object of the present invention is to make it possible to easily detect an abnormality of a system clock in an integrated circuit in a short time.
[0006]
[Means for Solving the Problems]
The invention according to claim 1 is a delay signal output unit that delays a reference clock signal for operating an integrated circuit by a plurality of delay elements connected in multiple stages, and outputs a delay signal for each stage. From among the delay signals output from the signal output unit, a synchronization signal detection unit that detects a plurality of delay signals synchronized with the reference clock signal, based on the plurality of delay signals detected by the synchronization signal detection unit, A plurality of integrated circuits each including a delay stage number calculating unit that calculates the number of stages of the delay element per one cycle of the reference clock signal; and the number of delay elements calculated by the delay stage number calculating unit included in each of the plurality of integrated circuits And an abnormality detector for detecting an abnormality of the reference clock signal in each integrated circuit based on the value of the number of stages of the delay element in each integrated circuit stored in the storage unit. It is characterized in that it comprises a part, a.
[0007]
According to the first aspect of the present invention, the abnormality of the reference clock signal in each integrated circuit can be detected by one abnormality detecting section, so that the integrated circuit in which the abnormality of the reference clock signal has occurred can be detected in a short time. Easy to identify. Further, since the value of the number of delay stages of each integrated circuit is stored in the storage unit, it is possible to analyze the abnormality of the reference clock signal in each integrated circuit in a time series. Further, the relationship between integrated circuits, such as the state of another integrated circuit when a clock abnormality occurs in one integrated circuit, can be grasped.
[0008]
The invention according to claim 2 is a delay signal output unit that delays a reference clock signal for operating an integrated circuit by a plurality of delay elements connected in multiple stages and outputs a delay signal for each stage, From among the delay signals output from the signal output unit, a synchronization signal detection unit that detects a plurality of delay signals synchronized with the reference clock signal, based on the plurality of delay signals detected by the synchronization signal detection unit, A plurality of integrated circuits each including: a delay stage number calculation unit that calculates the number of stages of the delay element per one cycle of the reference clock signal; and a storage unit that stores a value of the number of stages of the delay element calculated by the delay stage number calculation unit. An abnormality detection unit that detects an abnormality of a reference clock signal in each integrated circuit based on a value of the number of stages of the delay element stored in a storage unit of each of the plurality of integrated circuits. It is characterized in.
[0009]
According to the second aspect of the present invention, the value of the number of delay elements per one cycle of the reference clock signal (the number of delay stages) is stored for each integrated circuit, and one abnormality detection unit stores the value of each integrated circuit in each integrated circuit. Since the abnormality of the reference clock signal can be detected, the integrated circuit in which the abnormality of the reference clock signal has occurred can be easily specified in a short time. Further, the abnormality of the reference clock signal in each integrated circuit can be analyzed in time series. Further, the relationship between integrated circuits, such as the state of another integrated circuit when a clock abnormality occurs in one integrated circuit, can be grasped.
[0010]
The invention according to claim 3 is a clock abnormality detection system that detects abnormality of a reference clock signal in a plurality of integrated circuits, wherein each of the plurality of integrated circuits is configured by a plurality of multi-stage connected delay elements. A delay signal output unit that delays a reference clock signal and outputs a delay signal for each stage; and detects a plurality of delay signals synchronized with the reference clock signal from delay signals output from the delay signal output unit. A synchronization signal detector, a delay stage number calculator for calculating the number of delay elements per cycle of the reference clock signal based on the plurality of delay signals detected by the synchronization signal detector, and the delay stage number calculator A storage unit for storing the value of the number of stages of the delay element calculated by the above, and detecting an abnormality of the reference clock signal based on the value of the number of stages of the delay element stored in the storage unit. It is characterized in that it comprises an abnormality detection unit.
[0011]
According to the third aspect of the present invention, the abnormality of the reference clock signal can be detected for each integrated circuit, so that the integrated circuit in which the abnormality of the reference clock signal has occurred can be more easily specified in a short time. be able to. Further, by adopting a configuration in which an abnormality of the reference clock signal is detected for each integrated circuit, the abnormality detection of the reference clock signal can be realized at low cost.
[0012]
According to a fourth aspect of the present invention, in the third aspect of the present invention, the abnormality detecting section detects an abnormality of the reference clock signal using a preset setting value, and performs the preset setting. The value is set from an external device via the CPU.
[0013]
According to the fourth aspect of the present invention, the setting value serving as a reference for the determination by the abnormality determining unit is set from an external device, so that even if the frequency of the reference clock signal changes, the abnormality of the reference clock signal is determined. Can be detected.
[0014]
The invention according to claim 5 is the invention according to any one of claims 1 to 4, wherein the abnormality detection unit calculates an average value of the number of stages of the delay elements stored in the storage unit. When the absolute value of the difference between the calculated average value and the value of the number of stages of the delay element stored in the storage unit is larger than a preset value, an abnormality of the reference clock signal is detected. .
[0015]
According to the fifth aspect of the present invention, when the absolute value of the difference between the value of the number of stages of the delay element (the number of delay stages) and the average value thereof is larger than a preset value, the abnormality detection unit may output the reference clock signal. The abnormality of the reference clock signal can be easily detected by detecting the abnormality of the reference clock signal.
[0016]
The invention according to claim 6 is the invention according to any one of claims 1 to 4, wherein the abnormality detection unit calculates an average value of the number of stages of the delay elements stored in the storage unit. If the ratio of the absolute value of the difference between the calculated average value and the value of the number of stages of the delay element stored in the storage unit to the average value is larger than a preset value, the abnormality of the reference clock signal is determined. It is characterized by detecting.
[0017]
According to the sixth aspect of the present invention, the abnormality detection unit determines that the ratio of the absolute value of the difference between the number of delay element stages (the number of delay stages) and the average value to the average value is larger than a preset value. By detecting the abnormality of the reference clock signal, the abnormality of the reference clock signal can be easily detected.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[First Embodiment]
The first embodiment of the present invention will be described in detail with reference to FIGS. First, a configuration according to the first embodiment will be described.
[0019]
FIG. 1 shows an overall configuration of a clock abnormality detection system 100 according to a first embodiment of the present invention. As illustrated in FIG. 1, the clock abnormality detection system 100 includes a plurality of integrated circuits 101, an abnormality detection unit 10, and a storage unit 11, and the plurality of integrated circuits 101 are connected to the abnormality detection unit 10.
[0020]
FIG. 2 shows an internal configuration of the clock abnormality detection system 100 of FIG. As shown in FIG. 2, the integrated circuit 101 includes a clock cycle detection circuit 1, a CPU I / F5, and user logic, and is connected to the abnormality detection unit 10 via the CPU I / F5. The clock cycle detection circuit 1 includes a delay signal output unit 2, a synchronization signal detection unit 3, and a delay stage number calculation unit 4. Each part configuring the clock cycle detection circuit 1 is configured by a digital circuit.
[0021]
As shown in FIG. 3, the delay signal output unit 2 includes m delay cells (delay elements) DC1 to DCm and a plurality of inverters INV. These delay cells DC1 to DCm are connected in series in multiple stages (m stages). Each input stage and output stage of the delay cells DC1 to DCm has a duty ratio of the reference clock signal input to the delay signal output unit 2. An inverter INV for suppressing collapse is inserted. The number m of the delay cells constituting the delay signal output unit 2 is determined by the characteristics, accuracy, operation guarantee range, and the like of the delay cells. The reference clock signal input to the clock cycle detection circuit 1 is obtained by branching a system clock used in user logic as shown in FIG.
[0022]
Each of the delay cells DC1 to DCm delays the signal input thereto by a predetermined delay amount (for example, X [ps]) and outputs the delayed signal. That is, each of the delay cells DC1 to DCm delays the reference clock signal by an integer multiple (1 to m times) of the predetermined delay amount and outputs the delayed reference clock signal. Therefore, the delay signal output unit 2 outputs an m-bit width signal.
[0023]
Specifically, in FIG. 3, the first-stage delay cell DC1 delays the reference clock signal by a predetermined delay amount (for example, X [ps]) and outputs the delayed reference clock signal. The delay signal DL1 output from the delay cell DC1 is output to the synchronization signal detection unit 3 and to the delay cell DC2. The second-stage delay cell DC2 delays the input delay signal DL1 by a predetermined delay amount (for example, X [ps]) and outputs it. The delay signal DL2 output from the delay cell DC2 is output to the synchronization signal detector 3 and also to the delay cell DC3. The m-th stage delay cell DCm delays the input delay signal DLm-1 by a predetermined delay amount (for example, X [ps]) and outputs it. The delay signal DLm output from the delay cell DCm is output to the synchronization signal detector 3.
[0024]
As shown in FIG. 4, the synchronization signal detector 3 includes D-type flip-flops FF1 to FFm that hold the values of the delay signals (DL1 to DLm) output from the delay signal output unit 2, and NAND circuits N1 to Nm. Consists of As shown in FIG. 4, the output terminal Q of the flip-flop FFk (k = 1, 2,..., M−1) and the inverted output terminal QB of the adjacent flip-flop FFk + 1 are connected to the input stage of the NAND circuit Nk. It is connected.
[0025]
Delay signals DL1 to DLm from the delay signal output unit 2 are input to data input terminals D of the flip-flops FF1 to FFm, respectively. A reference clock signal (DL0) is commonly input to each clock input terminal of the flip-flops FF1 to FFm. The flip-flops FF1 to FFm respectively hold the values (“H” or “L”) of the input delay signals DL1 to DLm in synchronization with the reference clock signal, and output the held values from the output terminal Q. At the same time, a value obtained by inverting the held value is output from an inverted output terminal QB.
[0026]
The NAND circuits N1 to Nm-1 respectively perform a NOT logic of a value output from the output terminal Q of the flip-flop FF1 to FFm-1 and a value output from the inverted output terminal QB of the next-stage flip-flop FF2 to FFm. The product is calculated and output. Of the outputs of the NAND circuits N1 to Nm, only the output of the NAND circuit corresponding to the flip-flop whose delay signal is synchronized with the rising edge of the reference clock signal is at L level. This makes it possible to detect the outputs of the flip-flops of the number of stages synchronized with the reference clock signal.
[0027]
In FIG. 2, a delay stage number calculation unit 4 calculates the number of delay cells (the number of delay stages) corresponding to a delay of one cycle of the reference clock signal, based on the number of NAND circuit stages that output the L level.
[0028]
The CPU I / F 5 is an interface for connecting the integrated circuit 101 and the CPU 10a provided in the abnormality detection unit 10.
[0029]
The abnormality detection unit 10 includes a CPU (Central Processing Unit) 10a, stores the values of the plurality of delay stages calculated by the delay stage number calculation unit 4 in the storage unit 11, and stores the plurality of delay stages stored in the storage unit 11. , An average value of the number of delay stages is calculated, and each time the value of the number of delay stages is input from the delay stage number calculation unit 4 via the CPU I / F 5, the input delay stage number is compared with the average value. . The CPU 10a determines whether or not the absolute value of the difference between the two is greater than the set value α by comparing the number of delay stages input from the delay stage number calculation unit 4 with the average value. If it is determined that the value is larger than the reference clock signal, it is determined that the reference clock signal is abnormal.
[0030]
In the above description, the CPU 10a determines whether or not the absolute value of the difference between the number of delay stages input from the delay stage number calculation unit 4 and the average value is larger than the set value α. It may be determined whether or not the ratio of the absolute value of the difference between the number of delay stages and the average value to the average value is larger than a set value.
[0031]
The storage unit 11 stores a plurality of values of the number of delay stages calculated by the number-of-delay-stages calculation unit 4 for a fixed period for each integrated circuit constituting the clock abnormality detection system 100.
[0032]
Next, the operation in the present embodiment will be described with reference to FIGS.
FIG. 5 is a diagram showing an example of a timing chart of the reference clock signal (DL0) input to the delay signal output unit 2 and the delay signals (DL1 to DLm) output from the delay signal output unit 2.
[0033]
As shown in FIG. 5, the reference clock signal (DL0) input to the delay signal output unit 2 is delayed by a predetermined delay amount X by the delay cell DC1, and the delay signal DL1 is output from the delay cell DC1 via the inverter INV. Is done. The reference clock signal (DL0) is delayed by twice the predetermined delay amount X by the delay cells DC1 and DC2, and a delay signal DL2 is output from the delay cell DC2 via the inverter INV. Similarly, the reference clock signal (DL0) is delayed by k times the predetermined delay amount X by the delay cells DC1 to DCk (k = 1, 2,..., M), and is delayed from the delay cell DCk via the inverter INV. Signal DLk is output.
[0034]
Each delay signal output from the delay signal output unit 2 is input to flip-flops FF1 to FFm in the synchronization signal detection unit 3. The flip-flops FF1 to FFm receive the values (“H” or “L”) of the input delay signals DL1 to DLm at a timing synchronized with the rising edge of the reference clock signal, and hold the captured values. You. The values held in the flip-flops are output from the output terminals Q of the flip-flops FFA to FFm, and the inverted values of the held values are output from the inverted output terminals QB.
[0035]
The output value from the output terminal Q of the flip-flop FFk (k = 1, 2,..., M−1) is input to one terminal of the NAND circuit Nk, and the output value from the inverted output terminal QB of the flip-flop FFk + 1 is , Is input to the other terminal of the NAND circuit Nk. In the NAND circuits N1 to Nm, the NAND of the two values input from the flip-flops FF1 to FFm is calculated, and the calculation result is output to the delay stage number calculation unit 4. An L level is output from the NAND circuit corresponding to the delay signal synchronized with the rising edge of the reference clock signal, and an H level is output from the NAND circuit corresponding to the delay signal not synchronized with the rising edge of the reference clock signal.
[0036]
In the timing chart shown in FIG. 5, the delay signal DL100 is synchronized with the reference clock signal for the first time, and the delay signal DL200 is synchronized with the reference clock signal for the second time. Therefore, the L level is output from the NAND circuits N100 and N200, and the H level is output from the other NAND circuits.
[0037]
The delay stage number calculation unit 4 calculates the number of delay cells (the number of delay stages) corresponding to the delay of one cycle of the reference clock signal from the difference between the two NAND circuits that output the L level. In the example of the timing chart shown in FIG. 5, since the L level is output from the NAND circuits N100 and N200, the number of delay stages is 200-100 = 100 stages. The number of delay stages calculated by the delay stage number calculation unit 4 is output to the abnormality detection unit 10 via the CPU I / F 5.
[0038]
The values of the plurality of delay stages input from the delay stage number calculation unit 4 are stored in the storage unit 11, and the abnormality detection unit 10 calculates the average value of the number of delay stages from the values of the plurality of delay stages stored in the storage unit 11. Is calculated. Every time the value of the number of delay stages is inputted from the number-of-delay-stages calculation unit 4, the abnormality detection unit 10 compares the inputted number of delay stages with the average value, and determines whether the absolute value of the difference between them is greater than the set value α. It is determined whether or not. If it is determined that the absolute value of the difference between the number of delay stages input from the delay stage number calculation unit 4 and the average value is larger than the set value α, it is determined that the reference clock signal is abnormal.
[0039]
For example, when noise or the like enters the delay signal output unit 2, a minute pulse P having a cycle smaller than the cycle of the reference clock signal as shown in FIG. 6 enters the delay signal output from the delay signal output unit 2. In this case, after the delay signal DL100 synchronizes with the reference clock signal for the first time, the delay signal DL105 synchronizes with the reference clock signal for the second time. In this case, the number of delay stages is 105-100 = 5.
[0040]
For example, it is assumed that the average value of the number of delay stages is 100 and the set value α that is a criterion for determination is 3. In this case, the absolute value of the difference between the number of delay stages 5 calculated by the number of delay stages calculation unit 4 and the average value of the number of delay stages 100 is 95, which is significantly larger than the set value α = 3. Is determined to be abnormal. In the above description, as shown in FIG. 6, a case where an abnormality of the reference clock signal is detected when a minute pulse such as noise is input to the delay signal output unit 2 has been described. Even in the case of a sudden change (multi-clock switching), an abnormality in the reference clock signal can be detected.
[0041]
As described above, according to the clock abnormality detection system 100 of the first embodiment, the data of the number of delay cells (the number of delay stages) of one cycle of the reference clock signal (system clock) of each integrated circuit is unified. By managing the integrated circuit, the integrated circuit in which the abnormality of the system clock such as the rapid change of the clock cycle has occurred can be easily specified in a short time. Further, by sampling the data of the number of delay stages of each integrated circuit in the storage unit 11 for a fixed period, it is possible to analyze a system clock abnormality in each integrated circuit in time series. Further, it is possible to grasp the relationship between integrated circuits, such as the status of another integrated circuit when a clock abnormality occurs in one integrated circuit.
[0042]
[Second embodiment]
Next, a second embodiment of the present invention will be described with reference to FIGS. In the first embodiment, the case where the data of the number of delay stages output from the clock cycle detection circuit 1 included in each integrated circuit is stored in one memory (storage unit 11) has been described. Here, a case will be described in which each integrated circuit is provided with a memory for storing data of the number of delay stages.
[0043]
First, a configuration according to the second embodiment will be described. FIG. 7 shows an overall configuration of a clock abnormality detection system 200 according to the second embodiment of the present invention. As illustrated in FIG. 7, the clock abnormality detection system 200 includes a plurality of integrated circuits 201 and an abnormality detection unit 20. The plurality of integrated circuits 201 are connected to the abnormality detection unit 10. Each integrated circuit 201 includes the storage unit 6.
[0044]
FIG. 8 shows an internal configuration of the clock abnormality detection system 200 of FIG. As shown in FIG. 8, the integrated circuit 201 includes a clock cycle detection circuit 1, a CPU I / F 5, a storage unit 6, and user logic, and is connected to the abnormality detection unit 20 via the CPU I / F 5. The clock cycle detection circuit 1 in FIG. 8 is the same as the clock cycle detection circuit 1 shown in FIG. 2 in the first embodiment, and thus the description of the function is omitted.
[0045]
The CPU I / F 5 is an interface for connecting the integrated circuit 201 and the CPU 20a provided in the abnormality detection unit 20.
[0046]
The storage unit 6 stores the values of the plurality of delay stages calculated by the delay stage number calculation unit 4 of the clock cycle detection circuit 1 for a fixed period.
[0047]
The abnormality detection unit 20 includes a CPU 20a, reads out the values of the plurality of delay stages stored in the storage unit 6 of each integrated circuit 201, calculates the average value of the number of delay stages, and reads out the calculated average value and the readout. Is compared with the value of the set number of delay stages. The CPU 20a determines whether or not the absolute value of the difference between the two is greater than the set value α by comparing the average value with the read value of the number of delay stages, and determines that the absolute value of the difference is greater than the set value α. If it is determined, the reference clock signal is considered to be abnormal.
[0048]
In the above description, the CPU 20a determines whether the absolute value of the difference between the average value of the number of delay stages and the value of the number of delay stages read from the storage unit 6 of each integrated circuit 201 is larger than the set value α. Alternatively, it may be determined whether or not the ratio of the absolute value of the difference between the average value and the number of delay stages to the average value is larger than a set value.
[0049]
The operation of the second embodiment is the same as that of the second embodiment except that the abnormality detection unit 20 reads the value of the number of delay stages from the storage unit 6 of each integrated circuit 201 and detects the abnormality of the reference clock signal in each integrated circuit. Since the operation is substantially the same as that of the first embodiment, a description thereof will be omitted.
[0050]
As described above, according to the clock abnormality detection system 200 of the second embodiment, the data of the number of delay cells (the number of delay stages) per cycle of the reference clock signal (system clock) of each integrated circuit is integrated. By managing the integrated circuit, the integrated circuit in which the abnormality of the system clock such as the rapid change of the clock cycle has occurred can be easily specified in a short time. Also, by analyzing the data of the number of delay stages for each integrated circuit for a fixed period and collectively managing the data sampled by each integrated circuit, it is possible to analyze a system clock abnormality in each integrated circuit in a time series. Can be. Further, it is possible to grasp the relationship between integrated circuits, such as the status of another integrated circuit when a clock abnormality occurs in one integrated circuit.
[0051]
[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to FIGS. In the first and second embodiments, the case where the abnormality detection unit connected to the outside of each integrated circuit detects the abnormality of the reference clock signal of each integrated circuit has been described. However, in the third embodiment, And a case where each integrated circuit is provided with a circuit for detecting an abnormality of the reference clock signal.
[0052]
First, a configuration according to the third embodiment will be described. FIG. 9 shows the overall configuration of a clock abnormality detection system 300 according to the third embodiment of the present invention. As shown in FIG. 7, the clock abnormality detection system 300 includes a plurality of integrated circuits 301 and a CPU 30, and the plurality of integrated circuits 301 are connected to the CPU 30. Each integrated circuit 301 includes a clock abnormality detection circuit 8.
[0053]
FIG. 10 shows an internal configuration of the clock abnormality detection system 300 of FIG. As shown in FIG. 10, the integrated circuit 301 includes a clock abnormality detection circuit 8, a CPU I / F5, and user logic, and is connected to the CPU 30 via the CPU I / F5.
[0054]
The clock abnormality detection circuit 8 includes a delay signal output unit 2, a synchronization signal detection unit 3, a delay stage number calculation unit 4, a storage unit 6, and an abnormality detection unit 7. The delay signal output unit 2, the synchronization signal detection unit 3, and the delay stage number operation unit 4 are the same as those of the first embodiment, except that the delay signal output unit 2, the synchronization signal detection unit 3, the delay stage number operation unit 4 shown in FIG. Since they are the same, the description of their functions is omitted.
[0055]
The storage unit 6 stores the values of the plurality of delay stages calculated by the delay stage number calculation unit 4 for a certain period.
[0056]
The abnormality detection unit 7 calculates an average value of the number of delay stages from the values of the plurality of delay stages stored in the storage unit 6, and each time the value of the number of delay stages is input from the delay stage number calculation unit 4, the average value is input. The average number of delay stages is compared with the average value. The abnormality detector 7 determines whether the absolute value of the difference between the average value and the number of delay stages input from the delay stage number calculator 4 is greater than the set value α. When the abnormality detecting unit 7 determines that the absolute value of the difference between the two is greater than the set value α, it determines that the reference clock signal is abnormal, generates an error signal, and outputs the error signal to the CPU 30 via the CPU I / F 5. I do.
[0057]
In the above description, the abnormality detection unit 7 determines whether the absolute value of the difference between the average value of the number of delay stages and the value of the number of delay stages input from the delay stage number calculation unit 4 is larger than the set value α. It may be determined whether or not the ratio of the absolute value of the difference between the average value and the number of delay stages to the average value is larger than a set value.
[0058]
Here, the set value α serving as a criterion for determination in the abnormality detection unit 7 is stored in a register in the abnormality detection unit 7 and can be rewritten from the external device 40 via the CPU 30. Here, the external device 40 is a device such as a personal computer and a switch box. According to the frequency of the reference clock signal, the number of delay stages in one cycle of the reference clock signal changes, and the weight for one delay cell (the ratio of one delay cell to one cycle of the reference clock signal) changes. Therefore, the set value α serving as a reference for determination is rewritten according to the frequency of the reference clock signal.
[0059]
The CPU I / F 5 is an interface for connecting the integrated circuit 301 and the CPU 30. The CPU 30 specifies an integrated circuit in which an error has occurred in the reference clock signal from the input error signal.
[0060]
The operation of the third embodiment is different from that of the second embodiment in that the abnormality detection unit 30 of each integrated circuit 301 detects an abnormality of the reference clock signal instead of the abnormality detection unit 20 (CPU 20a). Is substantially the same as the operation in the second embodiment, and the description thereof is omitted.
[0061]
As described above, according to the clock abnormality detection system 300 of the third embodiment, each integrated circuit 301 can detect the abnormality of the system clock (reference clock signal). An integrated circuit in which an abnormality has occurred can be more easily identified in a short time. Further, by configuring the clock abnormality detection circuit 8 with a digital circuit in the integrated circuit, the abnormality detection of the system clock can be realized at low cost.
[0062]
Furthermore, since the set value α serving as a reference for detecting an abnormality in the system clock can be rewritten by the external device 40 via the CPU 30, even if the frequency of the system clock changes, the abnormality in the system clock can be prevented. Can be detected.
[0063]
The description in each of the above embodiments can be changed as appropriate without departing from the spirit of the present invention.
[0064]
【The invention's effect】
According to the first aspect of the present invention, the abnormality of the reference clock signal in each integrated circuit can be detected by one abnormality detecting section, so that the integrated circuit in which the abnormality of the reference clock signal has occurred can be detected in a short time. Easy to identify. Further, since the value of the number of delay stages of each integrated circuit is stored in the storage unit, it is possible to analyze the abnormality of the reference clock signal in each integrated circuit in a time series. Further, the relationship between integrated circuits, such as the state of another integrated circuit when a clock abnormality occurs in one integrated circuit, can be grasped.
[0065]
According to the second aspect of the present invention, the value of the number of delay elements per one cycle of the reference clock signal (the number of delay stages) is stored for each integrated circuit, and one abnormality detection unit stores the value of each integrated circuit in each integrated circuit. Since the abnormality of the reference clock signal can be detected, the integrated circuit in which the abnormality of the reference clock signal has occurred can be easily specified in a short time. Further, the abnormality of the reference clock signal in each integrated circuit can be analyzed in time series. Further, the relationship between integrated circuits, such as the state of another integrated circuit when a clock abnormality occurs in one integrated circuit, can be grasped.
[0066]
According to the third aspect of the present invention, the abnormality of the reference clock signal can be detected for each integrated circuit, so that the integrated circuit in which the abnormality of the reference clock signal has occurred can be more easily specified in a short time. be able to. Further, by adopting a configuration in which an abnormality of the reference clock signal is detected for each integrated circuit, the abnormality detection of the reference clock signal can be realized at low cost.
[0067]
According to the fourth aspect of the present invention, in addition to the effect of the third aspect of the present invention, the set value serving as the reference for the determination by the abnormality determination unit is set from an external device, so that the frequency of the reference clock signal is reduced. Even if it changes, an abnormality in the reference clock signal can be detected.
[0068]
According to the fifth aspect of the present invention, in addition to the effect of the first aspect of the present invention, the abnormality detecting section includes a difference between the number of delay elements (the number of delay elements) and an average value thereof. When the absolute value of is larger than a preset value, the abnormality of the reference clock signal can be easily detected by detecting the abnormality of the reference clock signal.
[0069]
According to the invention described in claim 6, in addition to the effect of the invention described in any one of claims 1 to 4, the abnormality detection unit may determine the difference between the number of delay elements (the number of delay elements) and the average value thereof. When the ratio of the absolute value to the average value is larger than a preset value, the abnormality of the reference clock signal can be easily detected by detecting the abnormality of the reference clock signal.
[Brief description of the drawings]
FIG. 1 is a diagram showing an overall configuration of a clock abnormality detection system 100 according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing an internal configuration of the clock abnormality detection system 100 of FIG.
FIG. 3 is a diagram showing a circuit configuration of a delay signal output unit 2.
FIG. 4 is a diagram showing a circuit configuration of a synchronization signal detection unit 3;
FIG. 5 is a timing chart showing a delay signal output from a delay signal output unit 2;
FIG. 6 is a timing chart showing a delay signal output from a delay signal output unit 2 when an abnormality occurs in a reference clock signal.
FIG. 7 is a diagram showing an overall configuration of a clock abnormality detection system 200 according to a second embodiment to which the present invention is applied.
FIG. 8 is a block diagram showing an internal configuration of the clock abnormality detection system 200 of FIG. 7;
FIG. 9 is a diagram showing an overall configuration of a clock abnormality detection system 300 according to a third embodiment to which the present invention is applied.
FIG. 10 is a block diagram showing an internal configuration of the clock abnormality detection system 300 in FIG. 9;
[Explanation of symbols]
1 Clock cycle detection circuit
2 Delay signal output section
3 Synchronous signal detector
4 Delay stage number calculation unit
5 CPU I / F
6 storage unit
7 Abnormality detector
8 Clock abnormality detection circuit
10, 20 abnormality detector
10a, 20a, 30 CPU
11 Storage unit
40 External device
100, 200, 300 clock abnormality detection system
101, 201, 301 integrated circuits

Claims (6)

A delay signal output unit that delays a reference clock signal for operating the integrated circuit by a plurality of delay elements connected in multiple stages, and outputs a delay signal for each stage.
From among the delay signals output from the delay signal output unit, a synchronization signal detection unit that detects a plurality of delay signals synchronized with the reference clock signal,
A plurality of integrated circuits having a delay stage number calculation unit that calculates the number of stages of delay elements per one cycle of the reference clock signal based on the plurality of delay signals detected by the synchronization signal detection unit;
A storage unit that stores a value of the number of stages of the delay element calculated by the number-of-delay-stages arithmetic unit of each of the plurality of integrated circuits;
An abnormality detector that detects an abnormality of a reference clock signal in each integrated circuit based on a value of the number of stages of the delay element in each integrated circuit stored in the storage unit;
A clock abnormality detection system comprising: A delay signal output unit that delays a reference clock signal for operating the integrated circuit by a plurality of delay elements connected in multiple stages, and outputs a delay signal for each stage.
From among the delay signals output from the delay signal output unit, a synchronization signal detection unit that detects a plurality of delay signals synchronized with the reference clock signal,
A delay stage number calculation unit that calculates the number of stages of delay elements per cycle of the reference clock signal based on the plurality of delay signals detected by the synchronization signal detection unit;
A plurality of integrated circuits having a storage unit for storing a value of the number of stages of the delay element calculated by the number of delay stages calculation unit,
An abnormality detection unit that detects an abnormality of a reference clock signal in each integrated circuit based on a value of the number of stages of the delay element stored in the storage unit of each of the plurality of integrated circuits;
A clock abnormality detection system comprising: A clock abnormality detection system that detects abnormality of a reference clock signal in a plurality of integrated circuits,
Each of the plurality of integrated circuits includes:
A delay signal output unit that delays the reference clock signal by a plurality of delay elements connected in multiple stages and outputs a delay signal for each stage;
From among the delay signals output from the delay signal output unit, a synchronization signal detection unit that detects a plurality of delay signals synchronized with the reference clock signal,
A delay stage number calculation unit that calculates the number of stages of delay elements per cycle of the reference clock signal based on the plurality of delay signals detected by the synchronization signal detection unit;
A storage unit that stores the value of the number of stages of the delay element calculated by the delay stage number calculation unit,
An abnormality detection unit that detects abnormality of the reference clock signal based on a value of the number of stages of the delay element stored in the storage unit;
A clock abnormality detection system comprising: The abnormality detection unit detects an abnormality in the reference clock signal using a preset setting value, and the preset setting value is set from an external device via a CPU. The clock abnormality detection system according to claim 3. The abnormality detection unit calculates an average value of the number of stages of the delay element stored in the storage unit, and an absolute value of a difference between the calculated average value and the value of the number of stages of the delay element stored in the storage unit. The clock abnormality detection system according to any one of claims 1 to 4, wherein when the value is larger than a preset value, the abnormality of the reference clock signal is detected. The abnormality detection unit calculates an average value of the number of stages of the delay element stored in the storage unit, and an absolute value of a difference between the calculated average value and the value of the number of stages of the delay element stored in the storage unit. 5. The clock abnormality detection system according to claim 1, wherein an abnormality of the reference clock signal is detected when a ratio of the reference clock signal to the average value is larger than a preset value.

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