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JP2004342895A - Semiconductor device, method of manufacturing the same, and electronic circuit apparatus - Google Patents

Semiconductor device, method of manufacturing the same, and electronic circuit apparatus Download PDF

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Publication number
JP2004342895A
JP2004342895A JP2003138875A JP2003138875A JP2004342895A JP 2004342895 A JP2004342895 A JP 2004342895A JP 2003138875 A JP2003138875 A JP 2003138875A JP 2003138875 A JP2003138875 A JP 2003138875A JP 2004342895 A JP2004342895 A JP 2004342895A
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Prior art keywords
insulating layer
semiconductor device
wiring portion
electric component
semiconductor chip
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JP2003138875A
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JP4200812B2 (en
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Osamu Yamagata
修 山形
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Sony Corp
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Sony Corp
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a SiP type semiconductor device having improved heat resistance not to generate deformation and warp even in the high temperature process required for electrostatic capacitance element and resistance element, and also to provide a method of manufacturing the same semiconductor device and an electronic circuit apparatus mounting the same device on a mounting substrate. <P>SOLUTION: Passive elements such as an electrostatic capacitance element C and inductance L are formed on a silicon substrate, insulation layers (17, 23, 28) are formed over these passive elements, and wiring portions (19a, 19b, 25a, 25b, 27) are formed within the insulation layers for connection with the passive elements. Moreover, a semiconductor chip 21 including active elements is built in the insulation layer for connection with these wiring portions, and a salient pole 30 is formed over the surface of the insulation layers for connection with the wiring portions. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置とその製造方法および電子回路装置に関し、特に受動素子を内蔵し、整合回路やフィルタなどを取り込んだＳｉＰ（システムインパッケージ）形態の半導体装置と、その製造方法およびそれを実装基板に実装してなる電子回路装置に関する。
【０００２】
【従来の技術】
デジタルビデオカメラ、デジタル携帯電話、あるいはノートパソコンなど、携帯用電子機器の小型化、薄型化、軽量化に対する要求は強くなる一方であり、これに応えるために近年のＶＬＳＩなどの半導体装置においては３年で７割の縮小化を実現してきた一方で、このような半導体装置をプリント配線基板上に実装した電子回路装置としても、実装基板（プリント配線基板）上の部品実装密度をいかに向上させるかが重要な課題として研究および開発がなされてきた。
【０００３】
例えば、半導体装置のパッケージ形態としては、ＤＩＰ（Ｄｕａｌ Ｉｎｌｉｎｅ Ｐａｃｋａｇｅ ）などのリード挿入型から表面実装型へと移行し、さらには半導体チップのパッド電極にはんだや金などからなるバンプ（突起電極）を設け、フェースダウンでバンプを介して配線基板に接続するフリップチップ実装法が開発された。
【０００４】
さらに、受動素子を内蔵し、整合回路やフィルタなどを取り込んだＳｉＰと呼ばれる複雑な形態のパッケージへと開発が進んでいる。
図１３は、上記の従来におけるＳｉＰ形態の半導体装置の一例の断面図である。
例えば、ＦＲ−４の樹脂基板１００上に配線１０１が形成され、これらを被覆して設けられたプリプレグが固化されて絶縁層１０２が形成されている。
絶縁層１０２には配線１０１に達する開口部１０２ａが形成されており、プラグ１０３が埋め込まれている。
プラグ１０３に接続して、下部電極１０４、誘電体膜１０５および上部電極１０６が積層されてなる受動素子の１つである容量素子や配線１０７が形成されている。
容量素子や配線１０７を被覆して設けられたプリプレグが固化されて絶縁層１０８が形成されている。
絶縁層１０８には容量素子の上部電極１０６や配線１０７に達する開口部１０８ａが形成されており、プラグ１０９が埋め込まれている。
プラグ１０９に接続して配線１１０が形成され、さらにバンプ１１１ａを有する半導体チップ１１１がフェースダウンで、即ち、バンプ１１１ａ形成面側から配線１１０に接続するようにマウントされている。
配線１１０や半導体チップ１１１を被覆して設けられたプリプレグが固化されて絶縁層１１２が形成されている。
絶縁層１１２には配線１１０に達する開口部１１２ａが形成されており、プラグ１１３が埋め込まれており、絶縁層１１２の表面においてプラグ１１３に接続するように導電層１１４を介してバンプ１１５が形成されている。
また、絶縁層１１２には、一部に切欠部１１２ｂが設けられて配線１１０ａが露出しており、容量素子などの外付け電気部品１１６がハンダ１１７などを介して接続されている。
【０００５】
また、例えば特許文献１には、ＢＧＡ（ボールグリッドアレイ）チップの対をなす電源用パッドとグランド用パッドの間隔を、プリント配線基板においてＢＧＡチップの搭載面の反対側の面に実装されるデカップリングコンデンサの電極間隔と見合うようにされた半導体集積回路が開示されている。
【０００６】
上記のような構成の半導体装置において、ＷＬＣＳＰ（ウェハレベルチップサイズパッケージ）に受動素子を内蔵し、整合回路やフィルタなどを取り込んだＳｉＰ（システムインパッケージ）を構成する場合、例えば、ＩＣチップ特性の変動とパッケージプロセスでの配線幅、絶縁層の厚さ、および、コンタクト抵抗などの変動により、フィルタの場合ではインサーションロスや透過帯域のシフトが発生しており、ＩＣチップとの整合回路やフィルタに用いるインダクタンスや静電容量素子などの受動素子の特性のばらつきを考慮してＳｉＰの設計を行なっている。
上記のようなＳｉＰに内蔵される素子の経時変化を含めた変化率について、一般的には５％以内に抑えることが目標とされている。
しかしながら、全てのフィルタ特性をあわせ込むことは困難であり、特性に大きな影響を及ぼすクリティカルな素子については内蔵することができず、図１３の外付け電気部品１１６のように外付けにしなければならない。
【０００７】
【特許文献１】
特開平９−２２３８６１号公報
【０００８】
【発明が解決しようとする課題】
しかしながら、上記のようなＳｉＰにおいて、静電容量素子では限られた面積で単位容量を必要とするため、高誘電膜の形成が必要となる。
しかし、成膜温度６００℃程度では、樹脂基板上の電極材の変形や、マイグレーション絶縁層の熱劣化、樹脂基板全体の熱応力による反りなどの不具合が生じてしまう。
反対に、低温プロセスにすると単位当たりの容量が小さく、結晶化が進まないため、耐圧が小さくなってしまうという問題が生じる。
【０００９】
抵抗素子についても１０００℃程度の高温焼成を必要とし、同様の不具合が発生する。
また、内蔵の場合には、レーザなどによるトリミングを行なう場合があり、その洗浄方法によるコンタミネーション、基板へのダメージから工程に入れることが困難となっている。
【００１０】
本発明は上記の状況に鑑みてなされたものであり、従って本発明の目的は、静電容量素子や抵抗素子に必要な高温プロセスにおいても変形や反りなどを引き起こさない耐熱性が向上したＳｉＰ形態の半導体装置と、その製造方法およびそれを実装基板に実装してなる電子回路装置を提供することである。
【００１１】
【課題を解決するための手段】
上記の目的を達成するため、本発明の半導体装置は、シリコン基板と、前記シリコン基板上に形成された受動素子と、前記受動素子を被覆する絶縁層と、前記受動素子に接続するように前記絶縁層内に形成された配線部と、前記配線部に接続するように前記絶縁層内に内蔵された能動素子を含む半導体チップと、前記配線部に接続するように前記絶縁層の表面に形成された突起電極とを有する。
【００１２】
上記の本発明の半導体装置は、シリコン基板上に受動素子が形成され、これを被覆して絶縁層が形成されている。
受動素子に接続するように絶縁層内に配線部が形成され、また、この配線部に接続するように絶縁層内に能動素子を含む半導体チップが内蔵され、さらに配線部に接続するように絶縁層の表面に突起電極が形成されている。
【００１３】
上記の目的を達成するため、本発明の半導体装置の製造方法装置は、シリコン基板上に受動素子を形成する工程と、前記受動素子に接続するように配線部を形成し、前記配線部に接続するように能動素子を含む半導体チップを内蔵しながら、前記受動素子を被覆して絶縁層を形成する工程と、前記配線部に接続するように前記保護層の表面に突起電極を形成する工程とを有する。
【００１４】
上記の本発明の半導体装置の製造方法は、シリコン基板上に受動素子を形成する。
次に、受動素子に接続するように配線部を形成し、配線部に接続するように能動素子を含む半導体チップを内蔵しながら、受動素子を被覆して絶縁層を形成する。
次に、配線部に接続するように保護層の表面に突起電極を形成する。
【００１５】
上記の目的を達成するため、本発明の電子回路装置は、半導体チップを内蔵し、前記半導体チップに接続する外部電極が設けられたパッケージ形態の半導体装置が、実装基板に実装されてなる電子回路装置であって、前記パッケージ形態の半導体装置は、シリコン基板と、前記シリコン基板上に形成された受動素子と、前記受動素子を被覆する絶縁層と、前記受動素子に接続するように前記絶縁層内に形成された配線部と、前記配線部に接続するように前記絶縁層内に内蔵された能動素子を含む半導体チップと、前記配線部に接続するように前記絶縁層の表面に形成された突起電極とを有する。
【００１６】
上記の本発明の電子回路装置は、半導体チップを内蔵し、半導体チップに接続する外部電極が設けられたパッケージ形態の半導体装置が、実装基板に実装されてなる電子回路装置である。
パッケージ形態の半導体装置は、シリコン基板上に受動素子が形成され、受動素子が絶縁層により被覆され、受動素子に接続するように絶縁層内に配線部が形成され、配線部に接続するように絶縁層内に能動素子を含む半導体チップが内蔵され、配線部に接続するように絶縁層の表面に突起電極が形成された構成である。
【００１７】
【発明の実施の形態】
以下に、本発明の半導体装置とその製造方法および電子回路装置の実施の形態について、図面を参照して説明する。
【００１８】
図１は本実施形態に係るＳｉＰ形態の半導体装置の模式断面図である。
例えば、シリコン基板１０上に酸化シリコンからなる下地絶縁膜１１が形成され、その上層に、例えばアルミニウムあるいは銅からなる下部電極１２、Ｔａ２Ｏ５ 、ＢＳＴ、ＰＺＴ、ＢａＴｉＯ３ 、窒化シリコン、ＰＩ（ポリイミド）あるいは酸化シリコンなどからなる誘電体膜１３、酸化シリコンあるいは窒化シリコンなどの誘電体膜の保護層１４、および、アルミニウムあるいは銅からなる上部電極１５が積層されており、誘電体膜１３を介して下部電極１２と上部電極１５が対向している部分が受動素子の１つである静電容量素子Ｃとなっている。
【００１９】
また、下地絶縁膜１１上にアルミニウムあるいは銅からなる配線１６が形成されており、静電容量素子および配線１６を被覆してＰＩ、ＰＢＯ（ポリパラフェニレンベンゾビスオキサゾール）、エポキシ樹脂、ポリアミドイミド樹脂などからなる第１絶縁層１７が形成されている。
第１絶縁層１７には、下部電極１２、上部電極１５および配線１６に達する開口部１７ａが形成されており、開口部１７ａ内に、バリアメタル膜（アンダーバンプメタル：ＵＢＭ膜とも称する）１８を介して、銅からなるプラグ１９ａと第１絶縁層１７上の配線１９ｂが一体に形成されている。
また、一部の配線はらせん状に形成され、受動素子の１つであるインダクタンス２０（Ｌ）が構成されている。
【００２０】
第１絶縁層１７上に、パッド２１ａを有する半導体チップ２１がフェースアップで、即ち、パッド２１ａ形成面の反対側の面側から、接着剤層２２により接着されてマウントされている。ここで、半導体チップ２１には能動素子が形成されており、半導体チップ２１のパッド２１ａ形成面におけるパッド２１ａを除く領域は酸化シリコンなどの保護層２１ｂで覆われている。
配線１９ｂや半導体チップ２１を被覆してＰＩなどからなる第２絶縁層２３が形成されている。
【００２１】
第２絶縁層２３には、半導体チップ２１のパッド２１ａおよび配線１９ｂに達する開口部２３ａが形成されており、開口部２３ａ内に、バリアメタル膜（ＵＢＭ膜）２４を介して、銅からなるプラグ２５ａと第２絶縁層２３上の配線２５ｂが一体に形成されている。
配線１９ｂに接続して、銅からなるポスト２７が形成されており、その間隙における第２絶縁層２３の上層にＰＩなどからなる絶縁性のバッファ層２８が形成されている。
この銅のポスト２７は、ポスト２７の間隙の第３絶縁層と、ガラスエポキシ系材料からなるＦＲ−４などの実装基板（マザー基板）との接続信頼性向上のためのバッファとしての役割を負う。
バッファ層２８の表面においてポスト２７に接続するように導電層２９を介してバンプ（突起電極）３０が形成されている。
また、一部の導電層２９ａにはバンプが形成されておらず、静電容量素子などの外付け電気部品３１の電極３１ａがハンダ３２などを介して接続されている。
上記の構成において、プラグ（１９ａ、２５ａ）、配線（１９ｂ，２５ｂ）およびポスト２７などを総称して配線部を称することもある。また、第１絶縁層１７、第２絶縁層２３およびバッファ層２８などを総称して絶縁層と称することもある。
【００２２】
上記のように、本実施形態に係る半導体装置は、シリコン基板上に静電容量素子、インダクタンスおよび抵抗素子などの受動素子が形成されており、これを被覆して絶縁層が形成されており、受動素子に接続するように絶縁層内に配線部が形成され、また、この配線部に接続するように絶縁層内に能動素子を含む半導体チップが内蔵され、さらに配線部に接続するように絶縁層の表面にバンプ（突起電極）が形成されている構成となっている。
上記の本実施形態に係る半導体装置は、シリコン基板上に受動素子が形成されているので、シリコン基板の耐熱性が高いことから、静電容量素子や抵抗素子などの受動素子を形成するのに必要な高温プロセスにおいても変形や反りなどを引き起こさず、耐熱性が向上したＳｉＰ形態の半導体装置である。
【００２３】
上記の半導体装置における外付け電気部品３１は、例えば、シリコン基板上に形成された受動素子、配線部および半導体チップを含む電子回路の調整用の電気部品である。例えばフィルタなどを構成する場合、特性に大きな影響を及ぼすクリティカルな素子について上記のように外付けで対応することができる。
また、上記の半導体装置における配線部は、例えば銅を含有する。銅は抵抗が低く電子回路の駆動速度の向上に寄与する。
【００２４】
次に、上記の本実施形態の半導体装置の製造方法について説明する。
まず、図２（ａ）に示すように、オリフラまたはノッチを持つ多結晶／単結晶のシリコン基板（厚さ７２５μｍ、抵抗率１〜２０Ωｃｍ）１０について、ＣＶＤ（化学気相成長）法あるいは熱拡散法により、例えば４００ｎｍの膜厚の酸化シリコンを形成し、下地絶縁膜１１とする。
以降の工程においては、図３（ａ）に示すように、ウェハレベルでプロセスを進める。シリコン基板Ｗ（１０）の各ＳｉＰとなる領域Ａ毎に同様の加工がなされる。
【００２５】
次に、例えばスパッタリング法あるいは蒸着法などによりアルミニウムあるいは銅などを厚さ１μｍで堆積させ、パターン加工して下部電極１２とする。誘電体膜と接するところには酸化反応防止のためにＴｉＮ膜を５０ｎｍの膜厚で形成する。
次に、ＣＶＤ法またはスパッタリング法などにより、Ｔａ２ Ｏ５ 、ＢＳＴ、ＰＺＴ、ＢａＴｉＯ３ 、窒化シリコン、ＰＩ、および酸化シリコンなどから、必要な単位容量および耐圧に応じて選択して堆積させ、誘電体層１３とする。例えば、０． １ｐ〜４０ｐＦ程度のキャパシタではＴａ２ Ｏ５ を採用する。Ｔａ２ Ｏ５膜厚４０ｎｍでの単位容量は、７ｆＦ／μｍ２ 程度である。耐圧は、１μＡ／ｃｍ２において４Ｖ程度である。
次に、ＣＶＤ法などにより、酸化シリコンあるいは窒化シリコンを堆積して誘電体層の保護層１４を形成し、ＲＩＥ（反応性イオンエッチング）などにより電極取り出し用の窓開けを行なう。
次に、例えばスパッタリング法あるいは蒸着法などによりアルミニウムあるいは銅などを厚さ１μｍで堆積させ、パターン加工して上部電極１５とする。以上のようにして、下部電極１２、誘電体層１３および上部電極１５からなる静電容量素子を形成する。
一方、上記の上部電極１５の形成と同時に絶縁膜１１上のその他の配線１６をパターン形成しておく。
【００２６】
次に、図２（ｂ）に示すように、スピンコート法、印刷法あるいはディスペンス法などにより、ＰＩ、ＰＢＯ、エポキシ樹脂あるいはポリアミドイミド樹脂などを供給し、少なくとも５０μｍの膜厚で第１絶縁層１７を形成する。これは受動素子へのシリコン基板からの影響を防止するためである。
【００２７】
感光性ＰＩを用いる場合には、以下の成膜条件により５０μｍ厚として成膜する。
【００２８】
未硬化の感光性ＰＩの粘度：２００Ｐ
スピンコート：８００ｒｐｍ／３０秒＋１５００ｒｐｍ／３０秒
プリベーク：９０℃／３００秒＋１１０℃／３００秒
ポストキュア：１５０℃／０．５時間＋２５０℃／１時間
【００２９】
次に、下部電極１２、上部電極１５および配線１６に達する開口部１７ａを第１絶縁膜１７に形成する。
【００３０】
開口部径：３０μｍφ
露光波長：ブロードバンドの光（ｇ線以降を含む光）
露光エネルギー：４００ｍＪ／ｃｍ２
現像：Ｊ．Ｅ．Ｔ（Ｊｕｓｔ Ｅｔｃｈ Ｔｉｍｅ）×１．５倍にてスプレー現像
【００３１】
次に、スカム処理を行い、シードスパッタリングを以下条件で行なって、Ｔｉ／Ｃｕからなるバリアメタル膜（ＵＢＭ膜）１８を形成する。
【００３２】
Ｔｉ／Ｃｕ：１６０ｎｍ／６００ｎｍの成膜
真空度：３．６×１０−３Ｐａ
スパッタリング圧力：６．１×１０−１Ｐａ
Ａｒ流量：１１０〜１１５ｃｍ３ ／ｍｉｎ
スパッタリング電力：２０００〜３０００Ｗ
【００３３】
次に、図２（ｃ）に示すように、開口部１７ａと配線形成領域以外にメッキされるのを防止するために、レジスト塗布、現像、スカム処理を行い、開口部１７ａと配線形成領域を開口するパターンのレジスト膜（不図示）を成膜する。
次に、レジスト膜をマスクとして電解メッキにより銅をメッキし、銅からなるプラグ１９ａと第１絶縁層１７上の配線１９ｂを一体に形成する。また、受動素子の１つであるインダクタンス２０も同時にパターン形成する。
電解メッキ後、レジスト膜を除去し、アッシャー処理を行い、銅の酸化膜除去のため、ライトエッチを行い、銅エッチングおよびバリアメタル膜（ＵＢＭ膜）１８のエッチングを行う。
【００３４】
次に、第１絶縁層１７上に、パッド２１ａを有する半導体チップ２１を、フェースアップで、即ち、パッド２１ａ形成面の反対側の面側から、接着剤層２２により接着してマウントする。
【００３５】
ここで、上記の半導体チップ２１の形成方法について説明する。
半導体チップ２１は樹脂で埋め込むため、薄型化が必須となる。薄型化するため、ＩＣチップとなるウェハの表面にバックグラインド用保護テープをラミネートし、裏面から研削する。バックグラインド用保護テープ自体に粘着層があるので、加熱することなく、加圧ローラにて貼り付けを行うことができる。例えば、非ＵＶタイプのサポートタイプで、総厚２９５μｍのものを用いることができる。
保護テープ貼り付け後、ＧａＡｓの場合は、＃６００砥石、スピンドル回転数３０００ｒｐｍで粗研削し、＃２０００砥石、スピンドル回転数３０００ｒｐｍで７０μｍの研削を行う。２段階の砥石を使用し、仕上がりを５０μｍ厚とする。
【００３６】
５０μｍ厚のウェハ状態で、ダイアタッチフィルム（ＤＡＦ）をウェーハ裏面にラミネートする。ＤＡＦは、ダイシング用シートと一体型のもので、ダイシングシート（ポリオレフィン）１００μｍ厚、接着層５μｍ厚、ダイアタッチフィルム１０〜５０μｍ厚の３層が積層された構造である。ラミネートは、手動または自動機で行なう。自動機の場合の条件例を以下に示す。
【００３７】
日東電工製（ＰＭ−８５００）を使用する場合
温度：４０℃
圧力：１５Ｎ／ｃｍ２
ラミネート速度：１０ｍｍ／秒
【００３８】
上記条件で、ダイシング用リングに貼りあわせ後、バックグラインド保護テープを剥離しダイシングを行なう。
ダイシング条件は、上記ダイシングフィルムとの一体型ではウェーハ材料により以下のような条件により分けて行なう。
【００３９】
シリコン（５０μｍ厚）の場合
ブレード：２０５０ ２７ＨＥＣＣ（ＤＩＳＣＯ社）
スピンドル回転数：３０００ｒｐｍ
送り速度：３０ｍｍ／秒
ＧａＡｓ（５０μｍ厚）の場合
ブレード：ＺＨ２２６Ｊ−ＳＥ ２７ＨＡＢＢ（ＤＩＳＣＯ社）
スピンドル回転数：３０００ｒｐｍ
送り速度：５ｍｍ／秒
切り込み量：４０〜８５μｍ
【００４０】
上記条件によりフルカットダイシングを行い、図３（ｂ）に示すように個片化された半導体チップＣＰ（２１）を得る。
次に、個片化された半導体チップ２１を上記のように受動素子が形成されたシリコン基板にマウントするが、このときの半導体チップ２１をダイシングテープからピックアップする条件は、例えば以下の通りである。
【００４１】
ニードルを用いたピックアップの場合
プランジアップ速度（ニードルの突き上げ速度）：８０〜１００ｍｍ／秒
ピックアップ保持時間（突き上げ状態で止める時間）：５０×１０ｍ・秒
ピックアップリフト（最も近づいたときのニードル先端からピックアップまでの距離）：４００μｍ
エキスパンド（チップ間距離）：５μｍ
ニードルレスの場合
ストローク：３０００μｍ
速度：１０ｍｍ／秒
【００４２】
ツールは、セラミックス、ラバーあるいは全芳香族ポリイミド樹脂からなる超耐熱性プラスチックなどからなる。
【００４３】
マウントは、ステージ温度１１０℃、荷重１Ｎ／Ｄｉｅ、時間１秒で、ピール強度１ｋｇｆ以上において行う。
シリコン基板との合わせ精度は、５μｍである。精度測定は、画像処理にて、シリコン基板のターゲットとＩＣチップ裏面の重心補正により行う。
マウント後は、ポストキュアを１６０℃で１時間行う。
【００４４】
次に、図４（ａ）に示すように、スピンコート法、印刷法あるいはディスペンス法などにより、ＰＩ、ＰＢＯ、エポキシ樹脂あるいはポリアミドイミド樹脂などを供給し、半導体チップ２１の上面まで埋め込み、第２絶縁層２３を形成する。
【００４５】
次に、図４（ｂ）に示すように、配線１９ｂに達する開口部２３ａ（開口径３０μｍ）を第２絶縁膜２３に形成する。
次に、スカム処理を行い、シードスパッタリングを以下条件で行なって、Ｔｉ／Ｃｕからなるバリアメタル膜（ＵＢＭ膜）２４を形成する。
【００４６】
次に、図５に示すように、レジスト塗布、現像、スカム処理を行い、開口部２３ａと配線形成領域を開口するパターンのレジスト膜（不図示）を成膜し、電解メッキにより銅をメッキし、銅からなるプラグ２５ａと第２絶縁層２３上の配線２５ｂを一体に形成する。
電解メッキ後、レジスト膜を除去し、アッシャー処理を行い、銅の酸化膜除去のため、ライトエッチを行う。
次に、感光性ドライフィルム２６をラミネートし、露光後、カバーフィルムを剥離し、現像、スカム処理を行う。これにより、感光性ドライフィルム２６にポスト用の開口部２６ａを形成する。
【００４７】
次に、電解メッキにより、開口部２６ａ内に例えばφ１５０μｍ高さ１００μｍｔの銅のポスト２７を形成する。
次にドライフィルム２６を剥離し、Ｃｕエッチング、ＵＢＭエッチングを行なう。以上で図６に示す状態となる。
【００４８】
以降の工程としては、Ｃｕポストが立った状態で、エポキシ樹脂、ＰＢＯ、ＰＩ、フェノール樹脂などを用いてスピンコートまたは印刷、トランスファーモールドにて封止し、絶縁性のバッファ層２８を形成する。
印刷の場合は、Ｃｕポストの上面より少なくとも１０μｍの膜厚で塗布とスキージを行い、±３０μｍ程度まで仕上げる。
樹脂硬化後に、研削により銅のポスト２７の頭出しを行う。このときの条件は、例えば＃６００砥石、スピンドル回転数、３０００ｒｐｍとする。
【００４９】
次に、銅のポスト２７の活性化処理後、ポスト２７に接続するように導電層２９を形成し、さらにその上部にバンプ（突起電極）３０を形成する。
バンプ３０は、ハンダボール、無鉛ハンダボール、ランドグリッドアレイ（ＬＧＡ）、印刷バンプなどを用いることができる。
ハンダボールの場合は、ランドにフラックスを塗布しハンダまたは無鉛ハンダボールバンプを搭載し、リフローにて溶融接合を行なう。
ハンダペーストを印刷する場合は、ハンダペーストを印刷した後にリフローにて溶融接合を行なう。
接合後、フラックス洗浄で完了する。
この後、シリコン基板１０をダイシングして個片化処理し、個々のＳｉＰ形態の半導体装置とすることができる。
【００５０】
上記のバンプ３０の形成工程において、同時に外付け電気部品用電極２９ａに外付け電気部品３１を接続することができる。
この場合、上記の導電層２９を形成する工程において、配線部に接続するようにバッファ層２８の表面に外付け電気部品用電極２９ａを予め形成しておくことで対応することができる。バンプを形成していない空き導電層２９を外付け電気部品用電極２９ａとして用いてもよい。
例えば、バンプを形成するためのハンダペーストを印刷するときに、外付け電気部品用電極２９ａにもハンダペーストを供給し、外付け電気部品３１の電極３１ａと外付け電気部品用電極２９ａとが重なるように外付け電気部品３１をマウントし、リフローにて溶融接合を行って外付け電気部品３１を接続する。このリフローにおいて、バンプを同時に形成することができる。
【００５１】
上記の本実施形態の半導体装置の製造方法においては、静電容量素子は抵抗素子などの受動素子の形成工程において、必要に応じて６００℃や１０００℃などの高温プロセスを行う。
本実施形態においては、これらの静電容量素子は抵抗素子などの受動素子を形成する基板をシリコン基板としているため、高温プロセスにおいても変形や反りなどを引き起こさない耐熱性が向上したＳｉＰ形態の半導体装置を製造することができる。
【００５２】
このパッケージのバンプ３０の配置は、図７（ａ）に示すペリフェラル型や図７（ｂ）に示すエリアアレイ型とすることができる。
ペリフェラル型においては、バンプ３０がシリコン基板１０の外周部近傍に配置されており、アリアアレイ型ではバンプ形成面の全面に配置されている。図中、半導体チップ２１の埋め込まれている領域やプラグ（１９ａ，２５ａ）や配線（１９ｂ，２５ｂ）の形成位置を実線で示している。
【００５３】
外付け電気部品３１が１００５外形では、０．８ｍｍピッチ〜１．０ｍｍピッチまで対応可能であり、図８（ａ）に示すように、外付け電気部品３１の電極３１ａを外付け電気部品用電極２９ａに接続して搭載することができる。
一方で、外付け電気部品３１が異形部品（１００５外形や１６０８外形とは異なる外形）の場合は、銅のポストの位置を変更し、図８（ｂ）に示すように外付け電気部品用電極２９ａの位置を調整し、外付け電気部品３１の電極３１ａの位置に合わせる。または、パッケージでの電気的特性評価用のソケットに溝加工することで対応する。
【００５４】
また、図９（ａ）に示すように、外付け電気部品３１の取り付け高さ（ｈ１）とＳｉＰのバンプ３０の高さ（ｈ２）について、ｈ１＜ｈ２の場合、このＳｉＰをこのまま実装基板に実装しても実装基板にはＳｉＰのバンプが接触し、外付け電気部品が実装基板に接触することはない。
【００５５】
一方、図９（ｂ）に示すように、ｈ１＞ｈ２となる場合は、このままではＳｉＰのバンプ３０が実装基板に接するより前に外付け電気部品３１が実装基板に接触してしまう。
ここで、図９（ｃ）に示すように、実装基板４０には、電極４１が形成され、その形成面に保護層４２が形成されているものとする。上記のようにｈ１＞ｈ２となる場合には、実装基板４０側に外付け電気部品３１の高さ分の凹部（掘り込み）４０ａを入れるか、またはピッチに余裕がある場合にはバンプを高くすることで、外付け電気部品と実装基板との接触を回避した電子回路装置とすることができる。
【００５６】
本実施形態の半導体装置によれば、以下の効果を享受することができる。
１．外付け電気部品を搭載しても面積が増加することがないＳｉＰ構造を実現できる。
２．外付け電気部品は回路に合わせてリペア可能であり、フィルタや整合回路によりマッチングした部品を搭載することができる。
３．外付け電気部品は、ＳｉＰの外部電極がハンダボールの場合、ハンダボール搭載時と一括取り付けが可能となり、工程の追加を必要としない。
４．実装基板に掘り込みを行なうことで、バンプの高さより厚い電気部品の搭載に容易に対応でき、電気部品の制約がない。
５．電子部品のほかに、アンテナ、水晶発振子や放熱板も同じ工程でパッケージに外付けが可能である。
【００５７】
（実施例）
図１０は本実施形態に係るＳｉＰ形態の半導体装置を携帯電話用のＧＳＭ（Ｇｌｏｂａｌ Ｓｙｓｔｅｍ ｆｏｒ Ｍｏｂｉｌｅ Ｃｏｍｍｕｎｉｃａｔｉｏｎｓ ）スイッチモジュールに適用したときの回路図である。
ＧＳＭスイッチモジュールは、ダイプレクサＤＩＰ、単極双投回路ＳＰＤＴ、単極四投回路ＳＰ４Ｔ、マッチング回路ＭＣ１、ローパスフィルタＬＰＦ、および、マッチング回路ＭＣ２を有する。
ここで、単極双投回路ＳＰＤＴと単極四投回路ＳＰ４ＴはＧａＡｓ半導体チップＣＰ上に実現される。
一方、ダイプレクサＤＩＰ、マッチング回路ＭＣ１、ローパスフィルタＬＰＦ、および、マッチング回路ＭＣ２は、それぞれ受動素子である静電容量素子とインダクタンスから構成されており、後述のように性能を十分に出すために外付けにする必要があるクリティカルな素子を除いて、本実施形態においてシリコン基板上に形成されている。
【００５８】
アンテナＡＮＴが静電容量素子を介してダイプレクサＤＩＰに接続されており、単極双投回路ＳＰＤＴと単極四投回路ＳＰ４Ｔに分岐して接続されている。
単極双投回路ＳＰＤＴは送信経路ＥＧＳＭ＿ＴＸと受信経路ＥＧＳＭ＿ＲＸを選択する回路であり、一方、単極四投回路ＳＰ４Ｔは１つの送信経路ＤＣＳ／ＰＣＳ＿ＴＸと２つの受信経路ＤＣＳ＿ＲＸとＰＣＳ＿ＲＸおよびＵＭＴＳから選択する回路である。ＵＭＴＳ（Ｕｎｉｖｅｒｓａｌ Ｍｏｂｉｌｅ Ｔｅｌｅｃｏｍｍｕｎｉｃａｔｉｏｎｓ Ｓｙｓｔｅｍ）からは、モジュール外に設けられるデュプレクサ（Ｄｕｐｌｅｘｅｒ）を介して送信経路ＵＭＴＳ＿ＴＸと受信経路ＵＭＴＳ＿ＲＸに接続され、送信と受信を同時に行う。
【００５９】
図１１は上記のローパスフィルタＬＰＦを詳細に示した回路図である。
単極四投回路ＳＰ４Ｔと送信経路ＤＣＳ／ＰＣＳ＿ＴＸの間に、３つの静電容量素子（Ｃ１，Ｃ２，Ｃ３）と、インダクタンス（Ｌ１，Ｌ２，Ｌ３）が設けられている。
ここで、静電容量素子Ｃ１はローパスフィルタＬＰＦの特性を決定するクリティカルな素子となっており、フィルタの性能を十分に出すために外付け電気部品により実現されている。静電容量素子Ｃ１を除く他の素子とは、図１中のプラグ（１９ａ，２５ａ）、配線（１９ｂ，２５ｂ）あるいはポスト２７などにより接続されている。
【００６０】
図１２は上記のＧＳＭスイッチモジュールを含む実現する回路のレイアウト図である。
インダクタンスＬや配線などはそれぞれシリコン基板上に形成されており、単極双投回路ＳＰＤＴと単極四投回路ＳＰ４Ｔを実現するＧａＡｓ半導体チップＣＰが埋め込まれて配置、接続されている。
ここで、ローパスフィルタＬＰＦに含まれる静電容量素子Ｃ１は外付け電気部品３１として外付けされている構成である。
各インダクタンスＬや半導体チップＣＰに接続するように、グラウンドＧＮＤや各送受信経路などがバンプに接続する構成となっている。
【００６１】
本発明は上記の実施形態に限定されない。
例えば、実施例としてＧＳＭスイッチモジュールを挙げているが、これに限らず、種々の受動素子がシリコン基板上に形成され、種々の半導体チップが埋め込まれてなるＳｉＰ形態の半導体装置に適用することができる。
その他、本発明の要旨を逸脱しない範囲で種々の変更が可能である。
【００６２】
【発明の効果】
本発明の半導体装置は、静電容量素子や抵抗素子に必要な高温プロセスにおいても変形や反りなどを引き起こさない耐熱性が向上したＳｉＰ形態の半導体装置である。
【００６３】
本発明の半導体装置の製造方法によれば、静電容量素子や抵抗素子に必要な高温プロセスにおいても変形や反りなどを引き起こさない耐熱性が向上したＳｉＰ形態の半導体装置を製造することができる。
【００６４】
本発明の電子回路装置は、上記の向上したＳｉＰ形態の半導体装置を実装基板に実装してなる電子回路装置である。
【図面の簡単な説明】
【図１】図１は本発明の実施形態に係る半導体装置の模式断面図である。
【図２】図２（ａ）〜（ｃ）は本発明の実施形態に係る半導体装置の製造方法の製造工程を示す模式断面図である。
【図３】図３（ａ）および（ｂ）は本発明の実施形態に係る半導体装置の製造方法の製造工程を示す平面図である。
【図４】図４（ａ）および（ｂ）は本発明の実施形態に係る半導体装置の製造方法の製造工程を示す模式断面図である。
【図５】図５は本発明の実施形態に係る半導体装置の製造方法の製造工程を示す模式断面図である。
【図６】図６は本発明の実施形態に係る半導体装置の製造方法の製造工程を示す模式断面図である。
【図７】図７（ａ）および（ｂ）は本発明の実施形態に係る半導体装置のバンプの配置を示す平面図である。
【図８】図８（ａ）および（ｂ）は本発明の実施形態に係る半導体装置の外付け電気部品用電極の配置を示す平面図である。
【図９】図９（ａ）および（ｂ）は本発明の実施形態に係る半導体装置の模式断面図であり、図９（ｃ）は図９（ｂ）の半導体装置を実装基板に実装した電子回路装置の模式断面図である。
【図１０】図１０は実施例に係るＧＳＭスイッチモジュールの回路図である。
【図１１】図１１はローパスフィルタの回路図である。
【図１２】図１２はＧＳＭスイッチモジュールを含む実現する回路のレイアウト図である。
【図１３】図１３は、従来におけるＳｉＰ形態の半導体装置の一例の断面図である。
【符号の説明】
１０…シリコン基板、１１…下地絶縁膜、１２…下部電極、１３…誘電体層、１４…保護層、１５…上部電極、１６…配線、１７…第１絶縁層、１７ａ…開口部、１８…バリアメタル膜、１９ａ…プラグ、１９ｂ…配線、２０…インダクタンス、２１…半導体チップ、２１ａ…パッド、２１ｂ…保護層、２２…接着剤層２３…第２絶縁層、２３ａ…開口部、２４…バリアメタル膜、２５ａ…プラグ、２５ｂ…配線、２６…ドライフィルム、２７…ポスト、２８…バッファ層、２９…導電層、２９ａ…外付け電気部品用電極、３０…バンプ（突起電極）、３１…外付け電気部品、３１ａ…電極、３２…ハンダ、４０…実装基板、４０ａ…凹部（掘り込み）、４１…電極、４２…保護層、Ｗ…シリコン基板、Ａ…各ＳｉＰとなる領域、ＣＰ…半導体チップ、ＡＮＴ…アンテナ、ＤＩＰ…ダイプレクサ、ＳＰＤＴ…単極双投回路、ＳＰ４Ｔ…単極四投回路、ＭＣ１…マッチング回路、ＬＰＦ…ローパスフィルタ、ＭＣ２…マッチング回路、Ｌ１，Ｌ２，Ｌ３，Ｌ…インダクタンス、Ｃ１，Ｃ２，Ｃ３…静電容量素子。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, a method of manufacturing the same, and an electronic circuit device, and more particularly to a semiconductor device of a SiP (system-in-package) type incorporating a passive element, incorporating a matching circuit, a filter, and the like, a method of manufacturing the same, and a mounting board using the same. The present invention relates to an electronic circuit device mounted on a computer.
[0002]
[Prior art]
The demand for smaller, thinner, and lighter portable electronic devices such as digital video cameras, digital mobile phones, and notebook computers has been increasing, and recent semiconductor devices such as VLSI have responded to these demands. While achieving a reduction of 70% per year, how to improve the component mounting density on a mounting board (printed wiring board) even for an electronic circuit device that mounts such a semiconductor device on a printed wiring board Research and development have been made as important issues.
[0003]
For example, as a package form of a semiconductor device, there is a shift from a lead insertion type such as DIP (Dual Inline Package) to a surface mount type, and further, a bump (projection electrode) made of solder, gold, or the like is provided on a pad electrode of a semiconductor chip. A flip-chip mounting method has been developed, which is provided and connected face-down to a wiring board via bumps.
[0004]
Further, development is progressing into a complex package called SiP in which a passive element is incorporated and a matching circuit, a filter, and the like are incorporated.
FIG. 13 is a cross-sectional view of an example of the above-described conventional SiP type semiconductor device.
For example, a wiring 101 is formed on an FR-4 resin substrate 100, and a prepreg provided to cover the wiring 101 is solidified to form an insulating layer 102.
An opening 102a reaching the wiring 101 is formed in the insulating layer 102, and a plug 103 is embedded therein.
Connected to the plug 103, a capacitive element or a wiring 107, which is one of passive elements in which a lower electrode 104, a dielectric film 105, and an upper electrode 106 are stacked, is formed.
A prepreg provided to cover the capacitor and the wiring 107 is solidified to form an insulating layer 108.
An opening 108 a reaching the upper electrode 106 and the wiring 107 of the capacitor is formed in the insulating layer 108, and a plug 109 is embedded therein.
The wiring 110 is formed by connecting to the plug 109, and the semiconductor chip 111 having the bump 111a is mounted face down, that is, connected to the wiring 110 from the side on which the bump 111a is formed.
A prepreg provided to cover the wiring 110 and the semiconductor chip 111 is solidified to form an insulating layer 112.
An opening 112a reaching the wiring 110 is formed in the insulating layer 112, and a plug 113 is buried. A bump 115 is formed on the surface of the insulating layer 112 via the conductive layer 114 so as to connect to the plug 113. ing.
In addition, a cutout portion 112b is provided in the insulating layer 112 so that the wiring 110a is exposed, and an external electric component 116 such as a capacitive element is connected via a solder 117 or the like.
[0005]
Also, for example, in Patent Document 1, the distance between a power supply pad and a ground pad forming a pair of a BGA (ball grid array) chip is determined by a decoupling mounted on the surface of the printed wiring board opposite to the mounting surface of the BGA chip. A semiconductor integrated circuit adapted to match the electrode spacing of a ring capacitor is disclosed.
[0006]
In the semiconductor device having the above-described configuration, when a passive element is incorporated in a WLCSP (wafer level chip size package) and a SiP (system in package) incorporating a matching circuit, a filter, and the like is configured, for example, an IC chip characteristic Due to fluctuations and fluctuations in the wiring width, insulating layer thickness, contact resistance, etc. in the package process, insertion loss and transmission band shift occur in the case of filters, and matching circuits with IC chips and filters The SiP is designed in consideration of variations in characteristics of passive elements such as an inductance and a capacitance element used in the semiconductor device.
It is generally aimed to suppress the rate of change including the time-dependent change of the element built in the SiP as described above within 5%.
However, it is difficult to match all the filter characteristics, and a critical element having a large effect on the characteristics cannot be built in, and must be externally provided as the external electric component 116 in FIG. .
[0007]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 9-223861
[0008]
[Problems to be solved by the invention]
However, in the above-described SiP, since a capacitance requires a unit capacitance in a limited area, a high dielectric film must be formed.
However, at a film forming temperature of about 600 ° C., problems such as deformation of the electrode material on the resin substrate, thermal degradation of the migration insulating layer, and warpage due to thermal stress of the entire resin substrate occur.
Conversely, when a low-temperature process is used, the capacity per unit is small, and crystallization does not proceed, which causes a problem that the breakdown voltage is reduced.
[0009]
The resistance element also needs to be fired at a high temperature of about 1000 ° C., and the same problem occurs.
In the case of a built-in type, trimming may be performed by a laser or the like, and it is difficult to enter a process due to contamination by the cleaning method and damage to the substrate.
[0010]
The present invention has been made in view of the above circumstances, and an object of the present invention is therefore to provide a SiP form having improved heat resistance which does not cause deformation or warping even in a high-temperature process required for a capacitance element or a resistance element. It is an object of the present invention to provide a semiconductor device, a method of manufacturing the same, and an electronic circuit device obtained by mounting the same on a mounting board.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention includes a silicon substrate, a passive element formed on the silicon substrate, an insulating layer covering the passive element, and a semiconductor device connected to the passive element. A wiring portion formed in the insulating layer, a semiconductor chip including an active element built in the insulating layer so as to connect to the wiring portion, and a semiconductor chip formed on the surface of the insulating layer so as to connect to the wiring portion And a projected electrode.
[0012]
In the above semiconductor device of the present invention, a passive element is formed on a silicon substrate, and an insulating layer is formed to cover the passive element.
A wiring portion is formed in the insulating layer so as to be connected to the passive element, and a semiconductor chip including an active element is built in the insulating layer so as to be connected to the wiring portion, and is further insulated so as to be connected to the wiring portion. A bump electrode is formed on the surface of the layer.
[0013]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a passive element on a silicon substrate, a step of forming a wiring section so as to connect to the passive element, and a step of connecting to the wiring section. Forming an insulating layer by covering the passive element while incorporating a semiconductor chip including an active element so as to form a projecting electrode on the surface of the protective layer so as to be connected to the wiring portion. Having.
[0014]
In the method of manufacturing a semiconductor device according to the present invention, a passive element is formed on a silicon substrate.
Next, a wiring portion is formed so as to be connected to the passive element, and an insulating layer is formed by covering the passive element while incorporating a semiconductor chip including an active element so as to be connected to the wiring portion.
Next, a protruding electrode is formed on the surface of the protective layer so as to be connected to the wiring portion.
[0015]
In order to achieve the above object, an electronic circuit device according to the present invention is an electronic circuit in which a package-type semiconductor device having a built-in semiconductor chip and provided with external electrodes connected to the semiconductor chip is mounted on a mounting board. The package-type semiconductor device may further include a silicon substrate, a passive element formed on the silicon substrate, an insulating layer covering the passive element, and the insulating layer connected to the passive element. A wiring portion formed therein, a semiconductor chip including an active element built in the insulating layer so as to be connected to the wiring portion, and a surface formed on the insulating layer so as to be connected to the wiring portion. And a protruding electrode.
[0016]
The above-described electronic circuit device of the present invention is an electronic circuit device in which a semiconductor device in the form of a package having a built-in semiconductor chip and provided with external electrodes connected to the semiconductor chip is mounted on a mounting board.
In a package-type semiconductor device, a passive element is formed on a silicon substrate, the passive element is covered with an insulating layer, and a wiring portion is formed in the insulating layer so as to be connected to the passive element, and is connected to the wiring portion. In this configuration, a semiconductor chip including an active element is built in the insulating layer, and a protruding electrode is formed on the surface of the insulating layer so as to be connected to the wiring portion.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a semiconductor device, a method of manufacturing the same, and an electronic circuit device according to the present invention will be described with reference to the drawings.
[0018]
FIG. 1 is a schematic sectional view of a semiconductor device of the SiP type according to the present embodiment.
For example, a base insulating film 11 made of silicon oxide is formed on a silicon substrate 10, and a lower electrode 12 made of aluminum or copper,2O5  , BST, PZT, BaTiO3  A dielectric film 13 made of silicon nitride, PI (polyimide) or silicon oxide, a protective layer 14 made of a dielectric film made of silicon oxide or silicon nitride, and an upper electrode 15 made of aluminum or copper. The portion where the lower electrode 12 and the upper electrode 15 face each other via the dielectric film 13 is a capacitance element C which is one of the passive elements.
[0019]
A wiring 16 made of aluminum or copper is formed on the base insulating film 11, and covers the capacitance element and the wiring 16 to cover PI, PBO (polyparaphenylene benzobisoxazole), epoxy resin, polyamideimide resin. A first insulating layer 17 is formed.
An opening 17a reaching the lower electrode 12, the upper electrode 15, and the wiring 16 is formed in the first insulating layer 17, and a barrier metal film (under bump metal: also referred to as a UBM film) 18 is formed in the opening 17a. A plug 19a made of copper and a wiring 19b on the first insulating layer 17 are integrally formed through the intermediary.
Further, a part of the wiring is formed in a spiral shape, and constitutes an inductance 20 (L) which is one of the passive elements.
[0020]
On the first insulating layer 17, the semiconductor chip 21 having the pad 21a is mounted face-up, that is, adhered by the adhesive layer 22 from the surface opposite to the surface on which the pad 21a is formed. Here, an active element is formed on the semiconductor chip 21, and a region other than the pad 21a on the pad 21a forming surface of the semiconductor chip 21 is covered with a protective layer 21b such as silicon oxide.
A second insulating layer 23 made of PI or the like is formed so as to cover the wiring 19b and the semiconductor chip 21.
[0021]
An opening 23a reaching the pad 21a and the wiring 19b of the semiconductor chip 21 is formed in the second insulating layer 23, and a plug made of copper is formed in the opening 23a via a barrier metal film (UBM film) 24. 25a and the wiring 25b on the second insulating layer 23 are formed integrally.
A post 27 made of copper is formed so as to be connected to the wiring 19b, and an insulating buffer layer 28 made of PI or the like is formed above the second insulating layer 23 in the gap.
The copper post 27 serves as a buffer for improving connection reliability between the third insulating layer in the gap between the posts 27 and a mounting board (mother board) such as FR-4 made of a glass epoxy material. .
A bump (protruding electrode) 30 is formed on the surface of the buffer layer 28 via a conductive layer 29 so as to be connected to the post 27.
Further, no bump is formed on some of the conductive layers 29a, and the electrodes 31a of the external electric component 31 such as a capacitance element are connected via the solder 32 or the like.
In the above configuration, the plug (19a, 25a), the wiring (19b, 25b), the post 27 and the like may be collectively referred to as a wiring part. In addition, the first insulating layer 17, the second insulating layer 23, the buffer layer 28, and the like may be collectively referred to as an insulating layer.
[0022]
As described above, in the semiconductor device according to the present embodiment, a passive element such as a capacitance element, an inductance and a resistance element is formed on a silicon substrate, and an insulating layer is formed to cover the passive element. A wiring portion is formed in the insulating layer so as to be connected to the passive element, and a semiconductor chip including an active element is built in the insulating layer so as to be connected to the wiring portion, and is further insulated so as to be connected to the wiring portion. The structure is such that bumps (protruding electrodes) are formed on the surface of the layer.
In the semiconductor device according to the above-described embodiment, since the passive elements are formed on the silicon substrate, the silicon substrate has high heat resistance, so that the passive elements such as the capacitance element and the resistance element are formed. This is a SiP type semiconductor device having improved heat resistance without causing deformation or warping even in a necessary high-temperature process.
[0023]
The external electric component 31 in the above-described semiconductor device is, for example, an electric component for adjusting an electronic circuit including a passive element, a wiring portion, and a semiconductor chip formed on a silicon substrate. For example, in the case of configuring a filter or the like, it is possible to externally deal with a critical element that greatly affects characteristics as described above.
Further, the wiring portion in the above semiconductor device contains, for example, copper. Copper has a low resistance and contributes to an improvement in the driving speed of an electronic circuit.
[0024]
Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
First, as shown in FIG. 2A, a polycrystalline / single-crystal silicon substrate (thickness: 725 μm, resistivity: 1 to 20 Ωcm) 10 having an orientation flat or a notch is subjected to a CVD (chemical vapor deposition) method or a thermal diffusion method. For example, a silicon oxide film having a thickness of, for example, 400 nm is formed by a method to form a base insulating film 11.
In the subsequent steps, the process proceeds at the wafer level as shown in FIG. Similar processing is performed for each region A of the silicon substrate W (10) to be each SiP.
[0025]
Next, aluminum or copper or the like is deposited to a thickness of 1 μm by, for example, a sputtering method or an evaporation method, and is patterned to form the lower electrode 12. A TiN film is formed in a thickness of 50 nm in contact with the dielectric film to prevent an oxidation reaction.
Next, Ta is deposited by a CVD method or a sputtering method.2  O5  , BST, PZT, BaTiO3  , Silicon nitride, PI, silicon oxide, etc., are selected and deposited according to the required unit capacitance and withstand voltage to form a dielectric layer 13. For example, 0. For a capacitor of about 1p to 40pF, Ta2  O5  Is adopted. Ta2  O5The unit capacitance at a film thickness of 40 nm is 7 fF / μm.2  It is about. The withstand voltage is 1 μA / cm2Is about 4V.
Next, silicon oxide or silicon nitride is deposited by a CVD method or the like to form a protective layer 14 of a dielectric layer, and a window for taking out electrodes is opened by RIE (reactive ion etching) or the like.
Next, aluminum or copper is deposited to a thickness of 1 μm by, for example, a sputtering method or a vapor deposition method, and is patterned to form the upper electrode 15. As described above, a capacitance element including the lower electrode 12, the dielectric layer 13, and the upper electrode 15 is formed.
On the other hand, at the same time as the formation of the upper electrode 15, other wirings 16 on the insulating film 11 are patterned.
[0026]
Next, as shown in FIG. 2B, PI, PBO, epoxy resin, polyamideimide resin, or the like is supplied by a spin coating method, a printing method, a dispensing method, or the like, and the first insulating layer is formed to a thickness of at least 50 μm. 17 is formed. This is to prevent the passive element from being affected by the silicon substrate.
[0027]
When the photosensitive PI is used, the film is formed to have a thickness of 50 μm under the following film forming conditions.
[0028]
Viscosity of uncured photosensitive PI: 200P
Spin coating: 800 rpm / 30 seconds + 1500 rpm / 30 seconds
Prebaking: 90 ° C / 300 seconds + 110 ° C / 300 seconds
Post cure: 150 ° C / 0.5 hour + 250 ° C / 1 hour
[0029]
Next, an opening 17 a reaching the lower electrode 12, the upper electrode 15 and the wiring 16 is formed in the first insulating film 17.
[0030]
Opening diameter: 30 μmφ
Exposure wavelength: Broadband light (light including g-line and below)
Exposure energy: 400 mJ / cm2
Development: J. E. FIG. Spray development at T (Just Etch Time) x 1.5 times
[0031]
Next, a scum process is performed, and seed sputtering is performed under the following conditions to form a barrier metal film (UBM film) 18 made of Ti / Cu.
[0032]
Ti / Cu: 160 nm / 600 nm film formation
Vacuum degree: 3.6 × 10-3Pa
Sputtering pressure: 6.1 × 10-1Pa
Ar flow rate: 110-115cm3  / Min
Sputtering power: 2000-3000W
[0033]
Next, as shown in FIG. 2C, resist coating, development, and scum processing are performed to prevent plating on portions other than the opening 17a and the wiring formation region. A resist film (not shown) having an opening pattern is formed.
Next, copper is plated by electrolytic plating using the resist film as a mask, so that a plug 19a made of copper and a wiring 19b on the first insulating layer 17 are integrally formed. In addition, an inductance 20, which is one of the passive elements, is simultaneously patterned.
After the electrolytic plating, the resist film is removed, an asher treatment is performed, a light etch is performed to remove a copper oxide film, and a copper etching and a barrier metal film (UBM film) 18 are etched.
[0034]
Next, on the first insulating layer 17, the semiconductor chip 21 having the pad 21a is mounted face-up, that is, from the side opposite to the surface on which the pad 21a is formed by bonding with the adhesive layer 22.
[0035]
Here, a method for forming the semiconductor chip 21 will be described.
Since the semiconductor chip 21 is embedded with a resin, it is necessary to reduce the thickness. In order to reduce the thickness, a protective tape for back grinding is laminated on the surface of the wafer serving as an IC chip, and ground from the back surface. Since the backgrinding protective tape itself has an adhesive layer, it can be attached by a pressure roller without heating. For example, a non-UV type support type having a total thickness of 295 μm can be used.
After attaching the protective tape, in the case of GaAs, rough grinding is performed with a # 600 grindstone and a spindle rotation speed of 3000 rpm, and a 70 μm grinding is performed with a # 2000 grindstone and a spindle rotation speed of 3000 rpm. Using a two-stage grindstone, the finish is 50 μm thick.
[0036]
In the state of a wafer having a thickness of 50 μm, a die attach film (DAF) is laminated on the back surface of the wafer. DAF is integrated with a dicing sheet and has a structure in which three layers of a dicing sheet (polyolefin) having a thickness of 100 μm, an adhesive layer having a thickness of 5 μm, and a die attach film having a thickness of 10 to 50 μm are laminated. Lamination is performed manually or by an automatic machine. An example of conditions for an automatic machine is shown below.
[0037]
When using Nitto Denko (PM-8500)
Temperature: 40 ° C
Pressure: 15N / cm2
Laminating speed: 10mm / sec
[0038]
After bonding to the dicing ring under the above conditions, the back grinding protective tape is peeled off and dicing is performed.
Dicing conditions are divided according to the following conditions depending on the wafer material in the case of the integrated type with the dicing film.
[0039]
For silicon (50μm thick)
Blade: 2050 27HECC (DISCO)
Spindle rotation speed: 3000rpm
Feed speed: 30 mm / sec
GaAs (50μm thick)
Blade: ZH226J-SE 27HABB (DISCO)
Spindle rotation speed: 3000rpm
Feeding speed: 5mm / sec
Cutting depth: 40-85 μm
[0040]
Full cut dicing is performed under the above conditions to obtain the individualized semiconductor chips CP (21) as shown in FIG.
Next, the singulated semiconductor chip 21 is mounted on the silicon substrate on which the passive elements are formed as described above. Conditions for picking up the semiconductor chip 21 from the dicing tape at this time are as follows, for example. .
[0041]
In the case of a pickup using a needle
Plunge up speed (needle push-up speed): 80 to 100 mm / sec
Pickup holding time (time to stop in the up state): 50 x 10 msec
Pickup lift (distance from the tip of the needle at the time of closest approach to the pickup): 400 μm
Expand (distance between chips): 5 μm
Needleless
Stroke: 3000 μm
Speed: 10mm / sec
[0042]
The tool is made of ceramics, rubber or super heat-resistant plastic made of wholly aromatic polyimide resin.
[0043]
The mounting is performed at a stage temperature of 110 ° C., a load of 1 N / Die, a time of 1 second, and a peel strength of 1 kgf or more.
The alignment accuracy with the silicon substrate is 5 μm. The accuracy measurement is performed by image processing by correcting the center of gravity of the silicon substrate target and the back surface of the IC chip.
After mounting, post cure is performed at 160 ° C. for 1 hour.
[0044]
Next, as shown in FIG. 4A, PI, PBO, an epoxy resin, a polyamideimide resin, or the like is supplied by a spin coating method, a printing method, a dispensing method, or the like, and is buried up to the upper surface of the semiconductor chip 21. An insulating layer 23 is formed.
[0045]
Next, as shown in FIG. 4B, an opening 23a (opening diameter 30 μm) reaching the wiring 19b is formed in the second insulating film 23.
Next, a scum process is performed and seed sputtering is performed under the following conditions to form a barrier metal film (UBM film) 24 made of Ti / Cu.
[0046]
Next, as shown in FIG. 5, resist coating, development, and scum processing are performed to form a resist film (not shown) having a pattern that opens the opening 23a and the wiring formation region, and copper is plated by electrolytic plating. The plug 25a made of copper and the wiring 25b on the second insulating layer 23 are integrally formed.
After the electrolytic plating, the resist film is removed, an asher process is performed, and a light etch is performed to remove a copper oxide film.
Next, the photosensitive dry film 26 is laminated, and after exposure, the cover film is peeled off, and development and scum processing are performed. As a result, an opening 26a for a post is formed in the photosensitive dry film 26.
[0047]
Next, a copper post 27 of, for example, φ150 μm and a height of 100 μm is formed in the opening 26 a by electrolytic plating.
Next, the dry film 26 is peeled off, and Cu etching and UBM etching are performed. Thus, the state shown in FIG. 6 is obtained.
[0048]
In the subsequent steps, the insulating buffer layer 28 is formed by spin coating or printing using epoxy resin, PBO, PI, phenol resin, or the like with the Cu post standing, and sealing by transfer molding.
In the case of printing, application and squeegee are performed with a film thickness of at least 10 μm from the upper surface of the Cu post to finish to about ± 30 μm.
After the resin is cured, the copper post 27 is caught by grinding. The conditions at this time are, for example, a # 600 grindstone, a spindle rotation speed, and 3000 rpm.
[0049]
Next, after the activation process of the copper post 27, a conductive layer 29 is formed so as to be connected to the post 27, and a bump (protruding electrode) 30 is formed thereon.
As the bump 30, a solder ball, a lead-free solder ball, a land grid array (LGA), a printed bump, or the like can be used.
In the case of a solder ball, a flux is applied to a land, and a solder or a lead-free solder ball bump is mounted, and fusion bonding is performed by reflow.
When printing a solder paste, after printing the solder paste, fusion bonding is performed by reflow.
After joining, it is completed by flux cleaning.
Thereafter, the silicon substrate 10 is diced and singulated to obtain individual SiP semiconductor devices.
[0050]
In the step of forming the bump 30, the external electric component 31 can be connected to the external electric component electrode 29a at the same time.
In this case, in the step of forming the conductive layer 29, an external electrical component electrode 29a may be formed in advance on the surface of the buffer layer 28 so as to be connected to the wiring portion. The free conductive layer 29 on which no bump is formed may be used as the external electrical component electrode 29a.
For example, when printing a solder paste for forming a bump, the solder paste is also supplied to the external electrical component electrode 29a, and the electrode 31a of the external electrical component 31 and the external electrical component electrode 29a overlap. The external electrical component 31 is mounted as described above, and the external electrical component 31 is connected by performing fusion bonding by reflow. In this reflow, bumps can be formed simultaneously.
[0051]
In the method of manufacturing a semiconductor device according to the present embodiment, a high-temperature process such as 600 ° C. or 1000 ° C. is performed on the capacitance element in the step of forming a passive element such as a resistance element as needed.
In this embodiment, since these capacitance elements use a silicon substrate as a substrate on which passive elements such as a resistance element are formed, a SiP type semiconductor with improved heat resistance that does not cause deformation or warping even in a high-temperature process. The device can be manufactured.
[0052]
The layout of the bumps 30 of this package can be a peripheral type shown in FIG. 7A or an area array type shown in FIG. 7B.
In the peripheral type, the bumps 30 are arranged near the outer peripheral portion of the silicon substrate 10, and in the area array type, they are arranged on the entire surface of the bump formation surface. In the drawing, the area where the semiconductor chip 21 is embedded and the positions where the plugs (19a, 25a) and the wirings (19b, 25b) are formed are indicated by solid lines.
[0053]
When the external electric component 31 has an outer shape of 1005, the external electric component 31 can correspond to a pitch of 0.8 mm to 1.0 mm. As shown in FIG. 8A, the electrode 31a of the external electric component 31 is replaced with an external electric component electrode. 29a and can be mounted.
On the other hand, when the external electrical component 31 is a deformed component (an external shape different from the 1005 external shape and the 1608 external shape), the position of the copper post is changed, and as shown in FIG. The position of 29 a is adjusted to match the position of the electrode 31 a of the external electric component 31. Alternatively, a groove is formed in a socket for evaluating electrical characteristics in a package.
[0054]
Further, as shown in FIG. 9A, when the height (h1) of the external electric component 31 and the height (h2) of the bump 30 of SiP are h1 <h2, the SiP is directly mounted on the mounting board. Even when mounting is performed, the SiP bumps are in contact with the mounting substrate, and the external electric components are not in contact with the mounting substrate.
[0055]
On the other hand, as shown in FIG. 9B, when h1> h2, the external electrical component 31 comes into contact with the mounting board before the SiP bump 30 comes into contact with the mounting board.
Here, as shown in FIG. 9C, it is assumed that an electrode 41 is formed on the mounting substrate 40, and a protective layer 42 is formed on the surface on which the electrode 41 is formed. When h1> h2 as described above, a recess (digging) 40a corresponding to the height of the external electrical component 31 is provided on the mounting board 40 side, or the bump is raised when there is a margin in the pitch. By doing so, it is possible to provide an electronic circuit device in which contact between the external electric component and the mounting board is avoided.
[0056]
According to the semiconductor device of the present embodiment, the following effects can be obtained.
1. A SiP structure in which the area does not increase even when an external electric component is mounted can be realized.
2. The external electric component can be repaired according to the circuit, and a component matched by a filter or a matching circuit can be mounted.
3. When the external electrode of the SiP is a solder ball, the external electric component can be mounted at the same time as when the solder ball is mounted, and does not require an additional process.
4. By digging into the mounting board, it is possible to easily cope with mounting of an electric component thicker than the height of the bump, and there is no restriction on the electric component.
5. In addition to electronic components, antennas, crystal oscillators and heat sinks can be externally attached to the package in the same process.
[0057]
(Example)
FIG. 10 is a circuit diagram when the SiP type semiconductor device according to the present embodiment is applied to a GSM (Global System for Mobile Communications) switch module for a mobile phone.
The GSM switch module includes a diplexer DIP, a single-pole double-throw circuit SPDT, a single-pole four-throw circuit SP4T, a matching circuit MC1, a low-pass filter LPF, and a matching circuit MC2.
Here, the single pole double throw circuit SPDT and the single pole four throw circuit SP4T are realized on the GaAs semiconductor chip CP.
On the other hand, the diplexer DIP, the matching circuit MC1, the low-pass filter LPF, and the matching circuit MC2 are each composed of a capacitive element and an inductance, which are passive elements, and are externally mounted in order to obtain sufficient performance as described later. Except for the critical elements that need to be formed, they are formed on the silicon substrate in the present embodiment.
[0058]
An antenna ANT is connected to a diplexer DIP via a capacitance element, and is branched and connected to a single pole double throw circuit SPDT and a single pole four throw circuit SP4T.
The single-pole double-throw circuit SPDT is a circuit that selects the transmission path EGSM_TX and the reception path EGSM_RX, while the single-pole four-throw circuit SP4T selects one transmission path DCS / PCS_TX, two reception paths DCS_RX, PCS_RX, and UMTS. Circuit. The UMTS (Universal Mobile Telecommunications System) is connected to a transmission path UMTS_TX and a reception path UMTS_RX via a duplexer provided outside the module, and performs transmission and reception at the same time.
[0059]
FIG. 11 is a circuit diagram showing the low-pass filter LPF in detail.
Three capacitance elements (C1, C2, C3) and inductances (L1, L2, L3) are provided between the single-pole four-throw circuit SP4T and the transmission path DCS / PCS_TX.
Here, the capacitance element C1 is a critical element that determines the characteristics of the low-pass filter LPF, and is realized by an external electric component in order to sufficiently bring out the performance of the filter. Elements other than the capacitance element C1 are connected by plugs (19a, 25a), wirings (19b, 25b), posts 27, and the like in FIG.
[0060]
FIG. 12 is a layout diagram of a realized circuit including the above-described GSM switch module.
The inductance L and the wiring are formed on a silicon substrate, and a GaAs semiconductor chip CP for realizing a single-pole double-throw circuit SPDT and a single-pole four-throw circuit SP4T is embedded and arranged and connected.
Here, the capacitance element C <b> 1 included in the low-pass filter LPF is configured to be externally attached as the external electric component 31.
The ground GND and the respective transmission / reception paths are connected to the bumps so as to be connected to the respective inductances L and the semiconductor chips CP.
[0061]
The present invention is not limited to the above embodiment.
For example, a GSM switch module is given as an example, but the present invention is not limited to this, and the present invention can be applied to a SiP type semiconductor device in which various passive elements are formed on a silicon substrate and various semiconductor chips are embedded. it can.
In addition, various changes can be made without departing from the spirit of the present invention.
[0062]
【The invention's effect】
The semiconductor device of the present invention is an SiP type semiconductor device having improved heat resistance which does not cause deformation or warping even in a high-temperature process required for a capacitance element and a resistance element.
[0063]
According to the method of manufacturing a semiconductor device of the present invention, it is possible to manufacture a semiconductor device of the SiP type with improved heat resistance that does not cause deformation or warping even in a high-temperature process required for a capacitance element and a resistance element.
[0064]
An electronic circuit device of the present invention is an electronic circuit device in which the above-described improved semiconductor device in the form of SiP is mounted on a mounting substrate.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view of a semiconductor device according to an embodiment of the present invention.
FIGS. 2A to 2C are schematic cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 3A and 3B are plan views showing manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 4A and 4B are schematic cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a schematic cross-sectional view showing a manufacturing process of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 6 is a schematic cross-sectional view showing a manufacturing process of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 7A and 7B are plan views showing the arrangement of bumps of the semiconductor device according to the embodiment of the present invention.
FIGS. 8A and 8B are plan views showing the arrangement of electrodes for external electric components of the semiconductor device according to the embodiment of the present invention.
FIGS. 9A and 9B are schematic cross-sectional views of a semiconductor device according to an embodiment of the present invention, and FIG. 9C shows the semiconductor device of FIG. 9B mounted on a mounting board; It is a schematic cross section of an electronic circuit device.
FIG. 10 is a circuit diagram of the GSM switch module according to the embodiment.
FIG. 11 is a circuit diagram of a low-pass filter.
FIG. 12 is a layout diagram of a realized circuit including a GSM switch module.
FIG. 13 is a sectional view of an example of a conventional SiP type semiconductor device.
[Explanation of symbols]
Reference Signs List 10 silicon substrate, 11 base insulating film, 12 lower electrode, 13 dielectric layer, 14 protective layer, 15 upper electrode, 16 wiring, 17 first insulating layer, 17a opening, 18 Barrier metal film, 19a plug, 19b wiring, 20 inductance, 21 semiconductor chip, 21a pad, 21b protective layer, 22 adhesive layer 23 second insulating layer, 23a opening, 24 barrier Metal film, 25a plug, 25b wiring, 26 dry film, 27 post, 28 buffer layer, 29 conductive layer, 29a external electrode for electrical parts, 30 bump (protrusion electrode), 31 external Mounting electric parts, 31a ... electrode, 32 ... solder, 40 ... mounting board, 40a ... recess (digging), 41 ... electrode, 42 ... protective layer, W ... silicon substrate, A ... area to be each SiP, CP ... half Guidance Chip, ANT antenna, DIP diplexer, SPDT single pole double throw circuit, SP4T single pole four throw circuit, MC1 matching circuit, LPF low pass filter, MC2 matching circuit, L1, L2, L3, L inductance , C1, C2, C3 ... Capacitance elements.

Claims (10)

シリコン基板と、
前記シリコン基板上に形成された受動素子と、
前記受動素子を被覆する絶縁層と、
前記受動素子に接続するように前記絶縁層内に形成された配線部と、
前記配線部に接続するように前記絶縁層内に内蔵された能動素子を含む半導体チップと、
前記配線部に接続するように前記絶縁層の表面に形成された突起電極と
を有する半導体装置。A silicon substrate,
A passive element formed on the silicon substrate,
An insulating layer covering the passive element;
A wiring portion formed in the insulating layer to connect to the passive element;
A semiconductor chip including an active element embedded in the insulating layer so as to be connected to the wiring portion;
A semiconductor device having a protruding electrode formed on a surface of the insulating layer so as to be connected to the wiring portion. 前記配線部に接続するように前記絶縁層の表面に形成された外付け電気部品用電極と、
前記外付け電気部品用電極に接続された外付け電気部品と
をさらに有する請求項１に記載の半導体装置。An external electrical component electrode formed on the surface of the insulating layer so as to be connected to the wiring portion,
The semiconductor device according to claim 1, further comprising an external electric component connected to the external electric component electrode. 前記外付け電気部品は、前記受動素子、前記配線部および前記半導体チップを含む電子回路の調整用の電気部品である
請求項２に記載の半導体装置。3. The semiconductor device according to claim 2, wherein the external electric component is an electric component for adjusting an electronic circuit including the passive element, the wiring section, and the semiconductor chip. 前記半導体チップは、前記半導体チップのパッド形成面の反対側の面が前記シリコン基板側となるように配置して内蔵されている
請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the semiconductor chip is arranged and incorporated such that a surface of the semiconductor chip opposite to a pad forming surface is on the silicon substrate side. 3. 前記配線部が銅を含有する
請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein the wiring portion contains copper. シリコン基板上に受動素子を形成する工程と、
前記受動素子に接続するように配線部を形成し、前記配線部に接続するように能動素子を含む半導体チップを内蔵しながら、前記受動素子を被覆して絶縁層を形成する工程と、
前記配線部に接続するように前記保護層の表面に突起電極を形成する工程と
を有する半導体装置の製造方法。Forming a passive element on the silicon substrate;
Forming a wiring portion so as to connect to the passive element, forming a dielectric layer covering the passive element while incorporating a semiconductor chip including an active element so as to connect to the wiring portion,
Forming a protruding electrode on the surface of the protective layer so as to be connected to the wiring portion. 前記配線部に接続するように前記絶縁層の表面に外付け電気部品用電極を形成する工程をさらに有し、
前記突起電極を形成する工程において、同時に前記外付け電気部品用電極に外付け電気部品を接続する
請求項６に記載の半導体装置の製造方法。Forming an external electrical component electrode on the surface of the insulating layer so as to connect to the wiring portion,
7. The method of manufacturing a semiconductor device according to claim 6, wherein in the step of forming the protruding electrode, an external electric component is simultaneously connected to the external electric component electrode. 半導体チップを内蔵し、前記半導体チップに接続する外部電極が設けられたパッケージ形態の半導体装置が、実装基板に実装されてなる電子回路装置であって、
前記パッケージ形態の半導体装置は、
シリコン基板と、
前記シリコン基板上に形成された受動素子と、
前記受動素子を被覆する絶縁層と、
前記受動素子に接続するように前記絶縁層内に形成された配線部と、
前記配線部に接続するように前記絶縁層内に内蔵された能動素子を含む半導体チップと、
前記配線部に接続するように前記絶縁層の表面に形成された突起電極と
を有する電子回路装置。A semiconductor device in the form of a package having a built-in semiconductor chip and provided with external electrodes connected to the semiconductor chip is an electronic circuit device mounted on a mounting board,
The semiconductor device in the package form includes:
A silicon substrate,
A passive element formed on the silicon substrate,
An insulating layer covering the passive element;
A wiring portion formed in the insulating layer to connect to the passive element;
A semiconductor chip including an active element embedded in the insulating layer so as to be connected to the wiring portion;
An electronic circuit device comprising: a protruding electrode formed on a surface of the insulating layer so as to be connected to the wiring portion. 前記配線部に接続するように前記絶縁層の表面に形成された外付け電気部品用電極と、
前記外付け電気部品用電極に接続された外付け電気部品と
をさらに有する請求項８に記載の電子回路装置。An external electrical component electrode formed on the surface of the insulating layer so as to be connected to the wiring portion,
The electronic circuit device according to claim 8, further comprising an external electric component connected to the external electric component electrode. 前記電気部品は前記突起電極の高さよりも厚い形状であり、
前記外付け電気部品と対向する領域において、前記実装基板に前記外付け電気部品を嵌入させる凹部が形成されている
請求項９に記載の電子回路装置。The electric component has a shape thicker than the height of the protruding electrode,
The electronic circuit device according to claim 9, wherein a concave portion for fitting the external electric component into the mounting board is formed in a region facing the external electric component.
JP2003138875A 2003-05-16 2003-05-16 Semiconductor device, method for manufacturing the same, and electronic circuit device Expired - Fee Related JP4200812B2 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006186037A (en) * 2004-12-27 2006-07-13 Oki Electric Ind Co Ltd Inductor chip, its manufacturing method, and packaging method
JP2006344680A (en) * 2005-06-07 2006-12-21 Fujitsu Ltd Ic package, its manufacturing method, and integrated circuit device
JP2008282882A (en) * 2007-05-08 2008-11-20 Nec Corp Component built-in mounting substrate
CN111987088A (en) * 2019-05-23 2020-11-24 中国科学院微电子研究所 Organic substrate embedding packaging structure integrating antenna and radio frequency front end
JP2021185621A (en) * 2017-02-22 2021-12-09 株式会社アムコー・テクノロジー・ジャパン Electronic device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006186037A (en) * 2004-12-27 2006-07-13 Oki Electric Ind Co Ltd Inductor chip, its manufacturing method, and packaging method
JP2006344680A (en) * 2005-06-07 2006-12-21 Fujitsu Ltd Ic package, its manufacturing method, and integrated circuit device
JP2008282882A (en) * 2007-05-08 2008-11-20 Nec Corp Component built-in mounting substrate
JP2021185621A (en) * 2017-02-22 2021-12-09 株式会社アムコー・テクノロジー・ジャパン Electronic device
JP7256240B2 (en) 2017-02-22 2023-04-11 株式会社アムコー・テクノロジー・ジャパン ELECTRONIC DEVICE AND ELECTRONIC DEVICE MANUFACTURING METHOD
CN111987088A (en) * 2019-05-23 2020-11-24 中国科学院微电子研究所 Organic substrate embedding packaging structure integrating antenna and radio frequency front end
CN111987088B (en) * 2019-05-23 2022-07-29 中国科学院微电子研究所 Organic substrate embedding packaging structure integrating antenna and radio frequency front end

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