JP2004234837A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the average time when an interface circuit couples chanels per unit amount of data by making it possible to transfer the data to another internal device when an internal device which ought to be transmitted with the data fails to receive that data. <P>SOLUTION: A negative voltage generating circuit 142 applies a negative voltage lower by the threshold component of NMOS transistors (TRs) than the low level of an equalization signal EQ and signals BS0 to BS3. Then, the TRs 113 and 114 and the TRs 117 to 124 are turned on successively and bit lines 103 to 105 attain the negative voltage. Even if the gate TRs of a memory cell are kept turned off by applying an L to word lines 106, 107, etc., the L can be written as the data to the memory cell. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor having an interface circuit that mediates data exchange with an external device connected to the outside of the semiconductor integrated circuit, and a bus that transmits data from the interface circuit to the inside of the semiconductor integrated circuit. An integrated circuit, a semiconductor integrated circuit having a phase-locked loop (hereinafter, referred to as a PLL circuit) for synchronizing an internal clock with an external clock at a high speed, and a semiconductor integrated circuit having a miniaturized DRAM or a DRAM which is easily tested. It is.

  Generally, a semiconductor integrated circuit has a plurality of functions incorporated in one chip. In other words, a plurality of internal devices having different functions are integrated on the same chip to form a semiconductor integrated circuit. FIG. 15 is a block diagram illustrating the configuration of a semiconductor integrated circuit called a so-called one-chip microcomputer. The one-chip microcomputer is also formed by arranging a plurality of internal devices on one chip 1. On the chip 1, a CPU 2 including a control circuit for interpreting and executing instructions and performing arithmetic processing is arranged. The data such as instructions given to the CPU 2 is given from an internal device inside the semiconductor integrated circuit or an external device outside. The external device is connected to the input / output pin 3. The input / output pin 3 is connected to an interface circuit 4 which is one of the internal devices. The interface circuit 4 exists for achieving electrical and functional matching of exchange between an external device connected to the input / output pin 3 and an internal device of the semiconductor integrated circuit. That is, the interface circuit 4 performs traffic control of data traveling between the inside and outside boundaries of the semiconductor integrated circuit.

  By the way, in order for the CPU 2 to execute a command, the semiconductor integrated circuit must take in data required by the CPU 2. Since the processing speed in the CPU 2 is limited, data generated inside the semiconductor integrated circuit or data provided from the outside must be held in any internal device until the processing is started in the CPU 2. Have to be. Further, in order to efficiently transmit data from an internal device such as the CPU 2 to an external device, it is necessary to temporarily hold the data. In general, a storage device is provided in such a semiconductor integrated circuit in order to hold data to be processed by the CPU 2 and data to be processed and output to the outside by the CPU 2. The storage device provided in the semiconductor integrated circuit includes, for example, an SRAM 5 that transmits and receives data to and from the CPU 2 at a maximum speed, and stores large-scale data required by the CPU 2 and image data when executing image processing. There is a DRAM 6 as a main memory for storing and storing the basic programs and data, and an NVRAM 7 for storing an individual program necessary for an application.

  In addition to the interface circuit 4, there are two types of internal devices that have appeared so far: a storage device such as an SRAM 5 and the CPU 2. When there are a plurality of types of internal devices other than the interface circuit 4 as described above, the semiconductor integrated circuit may, for example, provide a channel for transferring data between the external device and the CPU 2 and a channel between the external device and the storage device. It is also possible to adopt an indirect control method in which two or more channels, such as channels for transferring data, are provided and the switching of the channels is delegated to the interface circuit 4. Further, a direct control method in which an external device directly inputs data to the CPU 2 and transfers the data to the storage device from the CPU 2 may be employed. In the indirect control method, a selector channel for performing data transfer at a time without solving the physical connection relationship between the channel and the interface circuit 4 until the end of the data transfer, and the physical connection relationship between the channel and the interface circuit 4 in a unit. There is a multiplex channel that performs data transfer while switching.

In the case of multi-channel, in order for the interface circuit 4 to perform channel switching, the interface circuit 4 needs information for performing channel switching.
In conventional multi-channel switching, channel switching is performed in units of data bytes, or in units of data blocks in which data is provided with information on channel selection.

  There are several types of data to be transmitted. If the data can be executed immediately by the CPU 2, the data is directly transmitted to the CPU 2. If data needs to be rewritten in the main memory or needs to be stored once, the data is transmitted to the storage device such as the DRAM 6. Of course, there is data to be transmitted to both the CPU 2 and the storage device at the same time. Some of the data transmitted to the DRAM 6 includes data used for a cache, and such data is also stored in the SRAM 5 at the same time.

  The data processed by the CPU 2 and output from the CPU 2 includes not only data transferred to the SRAM 5 and the DRAM 6 but also data that is to be output to an external device as it is. In such a case, conventionally, all data is once stored in the DRAM 6, and the interface circuit 4 and the DRAM 6 are connected by a multiplexer (not shown), and only the data to be output to the external device is transferred from the DRAM 6 to the external device. An output method can also be adopted.

  Next, the PLL circuit 8 used in the semiconductor integrated circuit of FIG. 15 will be described. The PLL circuit 8 is provided for synchronizing an internal clock used inside the semiconductor integrated circuit with an external clock provided from outside the semiconductor integrated circuit. A PLL circuit is also used in the system chip, but in the case of the system chip, the clock constantly changes in a power down mode, a refresh mode, or the like. Even in such a case, realizing high-speed synchronization is important for increasing the speed of a semiconductor integrated circuit that operates according to an internal clock. For communication between an external device and the semiconductor integrated circuit, synchronization between the internal clock and the external clock is indispensable.

  As shown in FIG. 17, the conventional PLL circuit performs a frequency-phase comparator 30 for detecting a difference between a frequency and a phase, and injects or extracts a current for a time corresponding to a detection result of the frequency-phase comparator 30. It comprises a charge pump 31, a loop filter 32 for removing high-frequency components and noise from the output of the charge pump 31 to obtain a DC voltage, and a ring oscillator 33 for generating an internal clock having a frequency corresponding to the output of the loop filter 32. Have been. In a conventional PLL circuit, two processes, that is, a frequency pull-in process for bringing frequencies closer to each other and a phase synchronization process in which phase synchronization is completed in order to synchronize an internal clock and an external clock, are performed by one frequency-phase comparator.

  The following documents are related to the present application.

JP-A-6-152403 JP-A-6-315290 JP-A-9-45509 JP-A-9-74352 JP-A-10-107623 JP-A-6-119777 JP-A-7-85695 JP-A-8-102191 JP-A-8-235862 JP-A-9-213077

Since the conventional semiconductor integrated circuit is configured as described above, the input data always reaches the determined destination, and the data transfer is stopped while the data reception is refused at the destination. Therefore, there is a problem that the data transfer takes a long time until the destination can receive data. For example, referring to FIG. 15, data arrives at the interface circuit 4 from the external device through the input / output pin 3 with destination information. If the destination information of the data indicates the CPU 2, the interface circuit 4 connects the CPU 2 to a channel, and transmits the data using the connected channel. However, when the CPU 2 is in a busy state of command processing or the like and cannot receive data, it is not possible to release the channel coupling until the data transmission is completed, and it is not possible to perform data transfer efficiently. The problem occurs.
FIG. 16 is a block diagram showing a configuration of an expanded version of a semiconductor integrated circuit suitable for processing a larger amount of data than FIG. The expanded version of the semiconductor integrated circuit shown in FIG. 16 naturally has a larger chip size, but the capacity of the SRAM 5 and the DRAM 6 is expanded. In addition, a ROM 9 is provided in addition to the NVRAM 7 as a storage location for basic programs and the like. The problem that the transfer efficiency must be avoided in an expanded version of a semiconductor integrated circuit that handles large-capacity data transmission is a more serious problem than a normal semiconductor integrated circuit.
Also, when transmitting data from an internal device to an external device, if the channel connected to the same external device is fixed, all data necessary for the external device must be transferred to the internal device in advance, This causes a problem that local links connecting internal devices are congested.

  2. Description of the Related Art In a semiconductor integrated circuit having a conventional PLL circuit, two steps of a frequency pull-in process for bringing frequencies closer to each other and a phase synchronization process for completing phase synchronization for synchronizing an internal clock and an external clock are performed by one frequency-phase comparator. Therefore, when the frequency pull-in range is set wide, there is a problem that the setting time becomes long.

  Further, in a semiconductor integrated circuit including a conventional DRAM, the DRAM occupies a large position in the semiconductor integrated circuit in terms of both area and power consumption, and there is a problem that the area and power consumption of the semiconductor integrated circuit increase as the size of the DRAM increases. is there.

  Also, in the DRAM test, there is often a technical demand to write the same data to a plurality of memory cells simultaneously. In such a case, in most cases, a word line is selected and then data is sequentially written to the memory cells, or a register is provided next to the memory cell array, data is first written to the register, and then the memory cells in the memory cell array are written to the memory cells. A configuration in which the same data is written collectively has been proposed. In these cases, in the test mode, the DRAM has a problem in that the speed of the semiconductor integrated circuit is hindered because there is a write cycle overhead in batch writing of data for performing the test.

  SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a function of allowing a destination to be changed by information given from an internal device to an interface circuit to the interface circuit so that an internal circuit to which data is to be transmitted is provided. It is an object of the present invention to enable a device to transfer data to another internal device when it cannot receive the data, and to reduce the average time that the interface circuit couples the channel per unit amount of data.

  It is another object of the present invention to synchronize the external clock and the internal clock even when the frequency fluctuates greatly, and to shorten the time for synchronizing to increase the operation speed of the semiconductor integrated circuit.

  It is another object of the present invention to reduce the size of a semiconductor integrated circuit by simplifying a DRAM.

  It is another object of the present invention to reduce the test time of the DRAM by eliminating the overhead of the write cycle when the test data is collectively written to the DRAM, and to speed up the semiconductor integrated circuit.

  A semiconductor integrated circuit according to a first aspect of the present invention has one current electrode, the other current electrode, and a control electrode connected to a storage node of a memory cell, and is in a conductive state when the control electrode is at a high level, and when the control electrode is at a low level. A first transistor that is turned off, a word line connected to the control electrode of the first transistor, a first bit line connected to the other current electrode of the first transistor, A second bit line provided corresponding to the first bit line; one current electrode connected to the first bit line; another current electrode connected to the second bit line; A second transistor that is turned on when the first signal is at a high level, and is turned off when the first signal is at a low level; It has one current electrode connected to the power supply line, the other current electrode connected to the second bit line, and a control electrode to which a second signal is applied, and is in a conductive state when the second signal is at a high level. And a third transistor which is turned off when the second signal is at a low level, and which can be selectively connected to the power supply line. And a negative voltage generating circuit for supplying a negative voltage capable of turning on the third transistor to the power supply line.

  A semiconductor integrated circuit according to a second invention is a semiconductor integrated circuit, comprising: a word line and a first bit line connected to a memory cell; a second bit line provided corresponding to the first bit line; A first current electrode connected to the second bit line, a second current electrode connected to the second bit line, and a control electrode to which a first signal is applied, wherein the first signal is at a first potential A first transistor that is turned on and is turned off when the first signal is at a second potential, a first current electrode, a second current electrode connected to the second bit line, and a second signal And a power supply line connected to the other current electrode of the second transistor, and the second bit line is selectively connectable to the power supply line. By the first transistor When the second bit line and the second signal are cut off from the first bit line and are at an intermediate potential between the first potential and the second potential, the intermediate potential is applied to the power supply line. A potential generating circuit for applying a potential that is farther than the threshold value of the second transistor.

  According to the semiconductor integrated circuit of the first aspect of the present invention, since batch writing is performed with a negative voltage, there is an effect that the operation of the semiconductor integrated circuit can be sped up without the overhead of the write cycle.

  According to the semiconductor integrated circuit of the present invention, when the bit line is at the precharge potential, the bit line is set to a high potential or a low potential, and the bit line is collectively stored in the memory cells connected to the target word line. There is an effect that data can be written by using

Embodiment 1 FIG.
First Embodiment A semiconductor integrated circuit according to a first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a block diagram showing an example of a relationship between internal devices of a semiconductor integrated circuit and buses connected to them.
In the semiconductor integrated circuit shown in FIG. 1, a multiplexer 10 forming a main parallel data bus is connected to a CPU 2, an interface circuit 4, an SRAM 5, and a DRAM 6 in parallel.

The control of the multiplexer 10 is performed by the interface circuit 4. The multiplexer 10, the CPU 2, the SRAM 5, and the DRAM 6 are selectively connected to the interface circuit 4, and one internal device connected to the interface circuit 4 performs data transmission with an external device. For example, when the multiplexer 10 selects the CPU 2, the CPU 2 transmits data to and from an external device via the interface circuit 4.
Here, a case where data is transmitted from an external device to the CPU 2 will be described. When the CPU 2 is viewed from an external device from the viewpoint of transmitting data, there are two states. One is a state in which the CPU 2 can receive data, and the other is a state in which the CPU 2 cannot receive data. When the CPU 2 is in a data receivable state, the external device transmits data having destination information to the CPU 2 to the interface circuit 4, and the interface circuit 4 controls the multiplexer 10 based on the information to send the data to the CPU 2. Since the channel is opened, data can be transmitted immediately.

  However, if the interface circuit 4 opens a channel to the CPU 2 when the CPU 2 is in a state where data cannot be received, the multiplexer 10 cannot open a channel between another internal device and an external device. A processing signal such as a busy signal 11 indicating that data cannot be received from the CPU 2 is sent to the CPU 4 so that a channel with the CPU 2 is not opened.

FIG. 2 is a block diagram showing the relationship between the interface circuit 4 and the multiplexer 10. The input / output pin 3 includes a control pin 3a to which a control signal is input from an external device, an input pin 3b to which an input signal is input, and an output pin 3c for outputting an output signal from the semiconductor integrated circuit to the external device. .
The signal input from the input / output pin 3 includes a control signal having destination information provided to the control buffer 4a of the interface circuit 4 via the control pin 3a. The control buffer 4a controls the multiplexer 10 according to a control signal. For example, if the data is to be transmitted to the CPU 2, the multiplexer 10 connects the signal line 12 connected to the CPU 2 and the input buffer 4b according to the control signal output from the control buffer 4a. If the data is to be transmitted to the DRAM 6, the signal line 13 connected to the DRAM 6 is connected to the input buffer 4b according to the control signal. Although not shown in FIG. 2, a signal line extending to the SRAM 5 is also provided, which is also connected to the input buffer 4b by the multiplexer 10 for a control signal.

  Considering the relationship between the semiconductor integrated circuit and the external device when the CPU 2 is processing and does not accept data from the external device, the external device is in a state of being unable to transmit data to the semiconductor integrated circuit and waiting. The processing between the device and the external device has not progressed. If the data from the external device is transferred after the processing of the CPU 2 is completed, the transfer efficiency of the data to the semiconductor integrated circuit does not increase. Therefore, when the CPU 2 is processing and does not accept data, the CPU 2 transmits a busy signal 11 to the control buffer 4 a of the interface circuit 4. The control buffer 4a receiving the busy signal 11 changes the destination of data to be transmitted to the CPU 2 according to a predetermined rule. For example, data from an external device to be transmitted to the CPU 2 is transferred to the DRAM 6. By doing so, the data transfer efficiency between the semiconductor integrated circuit and the external device is improved.

  The same holds true for the relationship between the SRAM 5 and the DRAM 6. For example, when the SRAM 5 is in communication with the CPU 2 and cannot communicate with another device, data to be transmitted to the SRAM 5 from an external device can be transferred to the DRAM 6.

  When both the CPU 2 and the SRAM 5 are ready to accept data, it checks whether or not the data to be accepted is stored in the DRAM 6. The CPU 2 or the SRAM 5 accepts any data to be accepted using the local link bus 16.

  Here, the local link bus 16 is provided between three internal devices of the CPU 2, the DRAM 6, and the SRAM 5. If the local link bus 16 is used, unique data transfer can be performed between them. If the DRAM 6 and the SRAM 5 are dual-ported, data can be simultaneously transferred to the other two internal devices to which the local link bus 16 is separately connected by using the two local link buses 16 at the same time. is there. For example, the data to be sent to the CPU 2 and the data to be sent to the SRAM 5 stored in the DRAM 6 can be simultaneously transmitted to further increase the data transfer efficiency. Note that a unique bus 17 for connecting to the NVRAM 7 which is a nonvolatile memory is opened for the CPU 2.

  In the above description, the case where the destination of data is determined to be the only internal device (selector channel) in the interface circuit 4 has been described. However, by executing multi-selection (multiplex channel), the destination of a plurality of internal devices is determined. Can also be specified. In this case, if the DRAM 6 accepts data instead of the CPU 2 in the same manner as described above when the CPU 2 is in a state in which data cannot be accepted, for example, data that should be accepted by the DRAM 6 arrives at the DRAM 6 alternately. become. Therefore, in the DRAM 6, it is necessary to store these data so as not to cause confusion. For example, processing such as transmitting the busy signal 11 from the CPU 2 to the DRAM 6 and distributing the data transmitted to the DRAM 6 while the busy signal 11 arrives to the plurality of blocks in the memory area is required. Become. However, if measures are taken on the DRAM 6 side so as not to cause data confusion even if data distribution is not performed, there is no problem and the same effects as in the above-described embodiment can be obtained.

  Next, a case where data is output from an internal device to an external device will be described. The data processed by the CPU 2 and output from the CPU 2 includes not only data transferred to the SRAM 5 and the DRAM 6 but also data that is to be output to an external device as it is. In such a case, the data output directly from the CPU 2 to the external device and the data output from the DRAM 6 to the external device are switched by the multiplexer 10 by a processing signal such as a busy signal 11 transmitted from the CPU 2 to the interface circuit 4, thereby providing a series of data. Output as data. For example, first, the multiplexer 10 selects a channel according to an instruction from the interface circuit 4 so as to open a channel between the CPU 2 and the external device. Then, when it is the number of the data of the DRAM 6 that is desired to continue the data output of the CPU 2, the busy signal 11 is transmitted from the CPU 2 to the interface circuit 4 to cause the multiplexer 10 to execute the channel switching, and the data of the DRAM 6 is transferred to the CPU 2. Output to external device following data. When it comes to the data output of the CPU 2, the information is passed from the DRAM 6 to the CPU 2, and the multiplexer 2 opens the channel between the CPU 2 and the external device when the CPU 2 stops outputting the busy signal 11. . By repeating such operations, a series of data can be output from two internal devices, the CPU 2 and the DRAM 6, to an external device.

  In the case where a series of data obtained by connecting data held by a plurality of internal devices is desired to be output to one external device at a stretch, the purpose is achieved by alternately selecting necessary internal devices by the multiplexer 10. Thus, the load on the local link bus 16 can be reduced by the amount that the step of collecting these data in one internal device can be omitted. Further, the time required for collecting data in one internal device can be reduced, so that the data processing rate of the semiconductor integrated circuit can be improved.

  In the above embodiment, the busy signal 11 is output to the interface circuit 4 only from the CPU 2, but may be output from other internal devices such as the DRAM 6 as shown in FIG. The same effects as those of the above embodiment can be obtained.

Embodiment 2 FIG.
FIG. 4 is a block diagram showing a configuration of the PLL circuit according to the second embodiment of the present invention. In the PLL circuit 40 of FIG. 4, the frequency comparator 41 compares the frequency of the external clock EXCLK with the frequency of the internal clock INCLK, and the phase comparator 45 compares the frequency of the external clock EXCLK and the internal clock INCLK in parallel with the comparison of the frequency comparator 41. Perform phase comparison.

  Then, the first current output means 50 outputs a current according to the comparison result of the frequency comparator 41. Further, the second current output unit 51 outputs a current according to the comparison result of the phase comparator 45. Ring oscillator 49 generates and outputs an internal clock INCLK having a frequency corresponding to the sum of the output currents of first and second current output means 50 and 51.

  In the PLL circuit 40, the independence between the correction of the internal clock INCLK due to the frequency shift and the correction of the internal clock INCLK due to the phase shift is enhanced. Therefore, when the synchronization with the external clock EXCLK is lost, It is possible to shorten the time until the synchronization is obtained again.

  The first current output means 50 of the PLL circuit 40 includes a comparison result measurement circuit 42 that counts a frequency ratio between the internal clock INCLK and the external clock EXCLK output from the frequency comparator 41, and an output result of the comparison result measurement circuit 42. And a current conversion circuit 44 that converts a code output from the encoder 43 into a current having a current value corresponding to the code.

  The second current output means 51 of the PLL circuit 40 performs a comparison that shifts in a shift direction according to the current phase difference of the external clock EXCLK from the phase difference between the internal clock INCLK output from the phase comparator 45 and the external clock EXCLK. A result measurement circuit 46, an encoder 47 for encoding the output result of the comparison result measurement circuit 46, and a current conversion circuit 48 for converting a code output from the encoder 47 into a current having a current value corresponding to the code. I have.

  FIG. 5 is a block diagram illustrating current control in the PLL circuit. The current conversion circuits 44 and 48 share the reference current generation circuit 60 and the shunt generation circuit 61. Reference current generating circuit 60 generates a current according to internal clock INCLK output from ring oscillator 49. Therefore, if the frequency of the external clock EXCLK matches the frequency of the internal clock INCLK and does not change, the reference current does not change, and the ring oscillator 49 and the frequency of the internal clock INCLK are also constant.

  The shunt generation circuit 61 supplies the current output from the reference current generation circuit 60 to a coarse (Fine) generation circuit 62, a fine (Fine) generation circuit 63, and a sub-counter corresponding circuit 64 at a predetermined ratio. Here, it is shown that the currents applied to the fine generation circuit 63 and the sub-counter correspondence circuit 64 are the same in magnitude, and are not provided by one current path. However, currents may be applied at different ratios, and the effect of the invention can be obtained.

The course generation circuit 62 is provided in the current conversion circuit 44, and makes the current supplied from the shunt generation circuit 61 n times or 1 / n times according to the code output from the encoder 43.
The fine generation circuit 63 is provided in the current conversion circuit 48, and increases or decreases the current supplied from the shunt generation circuit 61 in accordance with the code output from the encoder 47. In some cases, the fine generation circuit 63 has to increase the current according to the phase difference. Therefore, only a certain percentage of the current previously supplied from the shunt generation circuit 61 flows, and the current is increased as needed.
The sub-counter corresponding circuit 64 is also provided in the current conversion circuit 48, and increases or decreases a certain percentage of the current supplied from the shunt generation circuit 61. The addition circuit 65 adds the output currents of the coarse generation circuit 62, the fine generation circuit 63, and the sub counter corresponding circuit 64.
Ring oscillator 49 outputs internal clock INCLK having a frequency corresponding to the current output from adder circuit 65. The adding mechanism 100 includes a first F ring oscillator 66, a second F ring oscillator 67, a first F ring oscillator 68, a second F ring oscillator 69, and a phase detection shifter 70. Each of these outputs a clock having a frequency corresponding to the current output from the addition circuit 65. However, the frequency of the clock oscillated by the ring oscillators 49, 66 to 69 is the same.

  Next, an operation when the frequency comparator 41 compares the frequency difference between the external clock EXCLK and the internal clock INCLK will be described with reference to FIGS. FIG. 7 is a timing chart for describing a case where the frequency of external clock EXCLK is lower than the frequency of internal clock INCLK. Using the rising edge of the external clock EXCLK as a trigger, the first FRL oscillator 66 outputs a clock FRCLK having the same frequency as the internal clock INCLK and its inverted clock bar FRCLK.

  The rising edge of the clock FRCLK and the rising edge of the clock bar FRCLK when the external clock EXCLK is at the high level (excluding those corresponding to the rising edge of the external clock EXCLK) are counted. In FIG. 7, the number is three in total. Similarly, the first FF ring oscillator 68 outputs a clock FFCLK having the same frequency as the internal clock INCLK and its inverted clock FFCLK, triggered by the rising edge of the inverted external clock EXCLK of the external clock EXCLK.

  The rising edge of the clock FFCLK and the rising edge of the clock bar FFCLK when the inverted external clock EXCLK is at the high level (excluding those corresponding to the rising edge of the inverted external clock bar EXCLK) are counted. In FIG. 7, the number is three in total.

  Here, the total of the rising edges of the clocks FRCLK, FRCLK, FFCLK, and FFCLK is divided by 2 to control the course generation circuit 62 according to the value. In the case of FIG. 7, the current output from the shunt generation circuit 61 is tripled by the course generation circuit 62. In this case, the current of the ring oscillator 49 becomes almost three times, and the frequency of the internal clock INCLK becomes almost one third. Therefore, the frequency comparator 41 determines that the frequency ratio between the internal clock INCLK and the external clock EXCLK is 1, and the output of the reference current generating circuit 60 remains stable while rising.

  Next, FIG. 8 is a timing chart for explaining a case where the frequency of the external clock EXCLK is higher than the frequency of the internal clock INCLK. With the rising edge of the external clock EXCLK as a trigger, the second FRL oscillator 67 outputs a clock FRCLK having the same frequency as the internal clock INCLK and its inverted clock bar FRCLK.

  The rising edge of the external clock EXCLK when the clock FRCLK is at the high level and the rising edge of the inverted external clock bar EXCLK when the inverted clock bar FRCLK is at the high level (except for the first one) are counted. In FIG. 8, the number is two in total.

  Similarly, the second FF ring oscillator 69 outputs the clock FFCLK having the same frequency as the internal clock INCLK and the inverted clock FFCLK thereof, triggered by the rising edge of the inverted external clock EXCLK of the external clock EXCLK.

  Then, the rising edge of the inverted external clock EXCLK when the clock FFCLK is at the high level and the rising edge of the inverted external clock EXCLK when the inverted clock FFCLK is at the high level are counted. In FIG. 8, the number is two in total.

  Here, the total of the rising edges of the external clocks EXCLK and EXCLK is divided by 2 to control the course generating circuit 62 according to the value. In the case of FIG. 8, the current output from the shunt generation circuit 61 is halved by the course generation circuit 62. In this case, the current of the ring oscillator 49 is almost halved, and the frequency of the internal clock INCLK is almost doubled. Therefore, the frequency comparator 41 determines that the frequency ratio between the internal clock INCLK and the external clock EXCLK is 1, and the output of the reference current generating circuit 60 is stabilized while being lowered.

  As described above, the frequency comparator 41 obtains, as an integer, a value obtained by dividing the larger one of the frequencies of the external clock EXCLK and the internal clock INCLK by the smaller one. Therefore, the ratio of the two frequencies falls between 1/2 and 2 due to the operation of the first current output means 50.

  As shown in FIG. 6, the comparison result measurement circuit 46 includes a bidirectional shift ring 46a and a sub-counter 46b each configured by connecting a plurality of bidirectional shift registers in a ring. The bidirectional shift ring 46a shifts data to the next shift register according to the clock output from the phase detection shifter 70. Therefore, if the frequency of the internal clock INCLK increases, the shift speed increases, and if the frequency decreases, the shift speed decreases. As described above, the bidirectional comparison result measuring circuit 46 can keep the resolution constant even when the frequency of the internal clock INCLK is increased by changing the shift speed, and can maintain high accuracy. Note that the accuracy of the bidirectional shift ring 46a also depends on the number of stages that compose it.

  The sub-counter 46b increases the count when it is on the up side of the bidirectional shift ring 46a, and decreases the count when it is on the down side. The count number is provided to the sub-counter corresponding circuit 64, and the sub-counter corresponding circuit 64 increases or decreases the current supplied to the adding circuit 65 according to the count number. Here, the current supplied to the fine generation circuit 63 greatly fluctuates depending on the operation of the coarse generation circuit 62, and the current that the fine generation circuit 63 increases and decreases corresponding to one stage of the bidirectional shift ring 46a is a sub-current. The current is set to be larger than the current that the counter corresponding circuit 64 increases or decreases in response to one count of the sub-counter 46b. With this setting, it is possible to further finely adjust the current supplied to the ring oscillator 49.

  Here, the case where the phase comparator 45 has a configuration for detecting only the phase difference has been described, but a conventional phase comparator may be used. In this case, the frequency difference is also detected at the same time, but since the frequency difference is set between 1/2 and 2 times by the loop including the frequency comparator 41, the phase difference is mainly detected by the phase comparator. .

  In the PLL circuit 40 configured as described above, even if the conventional frequency phase comparator 30 is used instead of the phase comparator 45, even if the frequency difference and the phase difference are largely open, in an ideal case, The clock EXCLK and the internal clock INCLK can be synchronized by approximately two clocks on the long cycle side.

  In the above embodiment, the shunt generation circuit 61 is provided to shunt the current, the currents shunted by the course generation circuit 62, the fine generation circuit 63, and the sub-counter corresponding circuit 64 are respectively processed and added by the addition circuit 65. However, for example, the sub-counter corresponding circuit 64, the fine generation circuit 63, and the coarse generation circuit 62 may be connected in series in this order, and the current output from the reference current generation circuit 60 may be used. It may be increased or decreased in series and applied to the ring oscillator, and the same effect as in the above embodiment is obtained.

Embodiment 3 FIG.
Next, a DRAM sense amplifier according to Embodiment 3 of the present invention will be described. FIG. 9 is a circuit diagram showing a configuration of a DRAM sense amplifier according to Embodiment 3 of the present invention. As shown in FIG. 9, a pair of bit lines 102 and 103 are provided on the minus side of the sense amplifier 101, and a pair of bit lines 104 and 105 are provided on the other side. The bit lines 102 and 103 are connected to the left side of the sense amplifier 101. Signals to be read or written to the bit line pairs 102 and 103 are given reference characters BL0 and / BL0, respectively. Word lines 106 and 107 are provided so as to be orthogonal to bit line pairs 102 and 103 and bit line pairs 104 and 105, respectively. Signals transmitted through the word lines 106 and 107 are given symbols WL0 and WL1, respectively.

  When the signals WL0 and WL1 of the word lines 106 and 107 are at a high level (hereinafter, referred to as H), for example, the memory cell 108 and the bit line 102 are connected, and the memory cell 109 and the bit line 105 are connected. , Bit line pairs 102 and 103 and 104 and 105 can transmit data of the memory cells 108 and 109 to the sense amplifier 101.

  In the sense amplifier 101, a bit line 110 is provided on an extension of the bit lines 102 and 104, and a bit line 111 is provided on an extension of the bit lines 103 and 105. The signals on the bit lines 110 and 111 are given symbols BL1 and / BL1, respectively. The NMOS transistor 112 has a gate connected to the signal line 115 and two current electrodes connected to the bit line pair 110 and 111, respectively. The signal lines 115 are also connected to the gates of the transistors 113 and 114. The NMOS transistor 113 has its two current electrodes connected to the power supply line 116 and the bit line 110, respectively. The NMOS transistor 114 has two current electrodes connected to the power supply line 116 and the bit line 111, respectively. When the equalizing signal EQ applied to the signal line 15 is set to H, the transistors 112 to 114 are turned on, and the bit line pair 110, 111 takes an intermediate voltage (Vcc / 2 when the power supply voltage is Vcc) from the power supply line 116. ) Is supplied.

  The NMOS transistors 117 and 121 are isolation transistors connected in series between the bit lines 102 and 110, and connect and disconnect the bit lines 102 and 110. The NMOS transistors 118 and 122 are isolation transistors connected in series between the bit lines 103 and 111, and connect and disconnect the bit lines 103 and 111.

  The NMOS transistors 119 and 123 are isolation transistors connected in series between the bit lines 104 and 110, and connect and disconnect the bit lines 104 and 110. The NMOS transistors 120 and 124 are isolation transistors connected in series between the bit lines 105 and 111, and connect and disconnect the bit lines 105 and 111.

  The gates of the transistors 117 and 118 are both connected to the signal line 126, and are turned on when the signal BS1 supplied through the signal line 126 is H. The gates of the transistors 121 and 122 are both connected to the signal line 125, and are turned on when the signal BS0 supplied through the signal line 125 is H. The gates of the transistors 119 and 120 are both connected to the signal line 127, and are turned on when the signal BS2 supplied through the signal line 127 is H. The gates of the transistors 123 and 124 are both connected to the signal line 128, and are turned on when the signal BS3 supplied through the signal line 128 is H.

  Power supply line 130 is connected to bit lines 110 and 111 via PMOS transistors 131 and 132, respectively. The voltage of the power supply line 130 is indicated by a symbol SP. The threshold voltages of the PMOS transistors 131 and 132 are set lower than Vcc / 2, the gate of the transistor 131 connected between the power supply line 130 and the bit line 110 is connected to the bit line 111, and the power supply line 130 and the bit line The gate of the transistor 132 connected to the bit line 111 is connected to the bit line 110. Although not shown, the power supply line 130 is provided with switch means such as a transistor for connecting or disconnecting the power supply line to or from a power supply for supplying the power supply voltage Vcc.

  The connection point of the transistors 117 and 121 is connected to the power supply line 133 via the transistor 134. Further, the transistor 135 is connected to a connection point of the transistors 118 and 122 via the transistor 135. The voltage of the power supply line 133 is indicated by a symbol SN1. NMOS transistors 134 and 135 have a threshold lower than intermediate voltage Vcc / 2. The gate of transistor 134 connected between power supply line 133 and transistors 117 and 121 is connected to bit line 103, and the gate of transistor 135 connected between power supply line 133 and transistors 118 and 122 is connected to bit line 102. It is connected to the. Although not shown, the power supply line 133 is provided with switch means such as a transistor for connecting or disconnecting a power supply for supplying the power supply voltage GND.

  The power supply line 136 is connected to a connection point between the transistors 119 and 123 via the transistor 137. Further, the transistor 138 is connected to a connection point of the transistors 120 and 124 via the transistor 138. The voltage of the power supply line 136 is indicated by a symbol SN2. The threshold voltage of the NMOS transistors 137 and 138 can be set higher than the intermediate voltage Vcc / 2. The gate of transistor 137 connected between power supply line 136 and transistors 119 and 123 is connected to bit line 105, and the gate of transistor 138 connected between power supply line 136 and bit line 111 is connected to bit line 104. It is connected. Although not shown, the power supply line 136 is provided with switch means such as a transistor for connecting or disconnecting a power supply for supplying the power supply voltage GND.

Next, the operation of the sense amplifier 101 will be described with reference to a timing chart shown in FIG.
At time t1, the signals WL0 and WL1 are at low level (hereinafter referred to as "L"), and the memory cells 108 and 109 are not connected to the bit lines 102 and 105. At this time, the signals BS0 to BS3 are at H, and the bit lines 102, 104, 110 are connected to each other, and the bit lines 103, 105, 111 are connected to each other. At this time, since the equalize signal EQ is at H level, the transistors 112 to 114 are conducting, and the bit lines 102 to 105, 110, 111 are all charged to the intermediate voltage by receiving the charge from the power supply line 116. I have. At this time, since the power supply lines 130, 133, and 136 are all disconnected from the power supply, the voltages SP, SN1, and SN2 of these lines are all intermediate voltages.

  At time t2, the equalize signal EQ becomes L, the transistors 112 to 114 are turned off, and the bit lines 110 and 111 and the power supply line 116 are disconnected from each other. At time t2, the signals BS0 and BS2 also become L, and the transistors 119 to 122 are turned off, so that the bit lines 102, 104 and 110 and the bit lines 103, 105 and 111 are cut off from each other. Therefore, in the operation at the time t2, the bit lines 110 and 111 individually float.

  Immediately after time t2, the power supply line 130 is connected to the power supply, and the voltage SP starts to increase toward Vcc. Since no charge is supplied to the bit lines 110 and 111, the potential difference between the voltage SP and the bit lines 110 and 111 exceeds the threshold voltage of the transistors 131 and 132 at time t3. Then, the transistors 131 and 132 are turned on, and the signals BL1 and / BL1 start rising toward the power supply voltage Vcc following the voltage SP.

  At time t4, when the signal WL0 becomes H, the memory cell 108 is connected to the bit line 102, and a potential difference occurs between the bit lines 102 and 103. This potential difference is considerably smaller than the power supply voltage Vcc and the ground voltage GND, and here, this is called an initial amplitude. Since the bit lines 102 and 103 are cut off from the bit lines 110 and 111, they retain their initial amplitudes.

  At time t5, the voltage of the bit line pair 110, 111 reaches a voltage lower than the power supply voltage Vcc by the threshold voltage of the transistors 131, 132 and is stable. At this time, the power supply line 133 is connected to the power supply GND to gradually lower the voltage.

  At time t6, the potential difference between the bit lines 102 and 103 and the power supply line 133 reaches the threshold voltage of the transistors 134 and 135, the transistors 134 and 135 are turned on, and the voltages of the bit lines 110 and 111 start to drop. However, since the on state of the transistor 135 is stronger than that of the transistor 134 due to the initial amplitude, the current flowing to the transistor 135 is larger than the current flowing to the transistor 134. Therefore, the bit line 111 is earlier than the bit line 110 and will be described below.

  At time t7, when the voltage between the bit line 111 and the power supply line 130 reaches the threshold voltage of the transistor 131, the transistor 131 turns on, and the bit line 110 receives the supply of the electric charge from the power supply line 130 and turns to the power supply voltage Vcc. And start rising. At this point, the voltage on bit line 110 drops only by transistor 134.

  At time t8, when the potential difference between the bit lines 110 and 111 becomes sufficiently large, the signal BS0 is set to H to connect the bit line pairs 102 and 103 and the bit line pairs 110 and 111. When the transistors 121 and 122 are turned on, the transistors 134 and 135 function as latches, and the amplitudes of the bit line pairs 102 and 103 and the bit line pairs 110 and 111 can be fully swung between the power supply voltage Vcc and GND.

  As described above, since the transistors 134 and 135 are used not only as a part of the amplifying means but also as a latch, the configuration of the sense amplifier 1 is simplified.

  In the above embodiment, the relationship between the sense amplifier 101 and the left bit line pairs 102 and 103 has been described. However, since the relationship between the sense amplifier 101 and the bit line pairs 102 to 105 is symmetrical, the sense amplifier 1 The same can be said for the bit line pairs 104 and 105 on the right side.

Embodiment 4 FIG.
Next, a semiconductor integrated circuit according to a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 11 is a circuit diagram showing an example of a configuration of a DRAM according to the fourth embodiment of the present invention. In FIG. 11, components having the same reference numerals as those in FIG. 9 correspond to the portions having the same reference numerals in FIG. 9, and the intermediate voltage generating circuit 140 normally supplies the power supply line 116 with an intermediate voltage corresponding to approximately one half of the power supply voltage Vcc. This is a circuit for supplying the voltage VBL.

  The negative voltage generation circuit 142 is provided for writing L to the memory cells in a lump in order to perform a test. Negative voltage generating circuit 142 is connected to power supply line 116 instead of intermediate voltage generating circuit 140 by switch means 143 according to a command from test mode circuit 141.

  Negative voltage generating circuit 142 applies a negative voltage that is lower than the equalizing signal EQ and the low level of signals BS0 to BS3 by the threshold value of the NMOS transistor. Then, transistors 113 and 114 and transistors 117 to 124 are turned on one after another, and bit lines 103 to 105 become negative voltage. At this time, even when L is applied to the word lines 106 and 107 to turn off the gate transistor of the memory cell, L can be written to the memory cell as data. For example, in the one-transistor / one-capacitor memory cell shown in FIG. 12, the transistor Q is turned on by the potential difference between the bit line B and the word line W, so that data can be written to the capacitor C.

  When the above-described writing is being performed, the power supply lines 130, 133, and 136 are in a floating state.

FIG. 13 is a circuit diagram showing a second mode of the configuration of the DRAM according to the fourth embodiment of the present invention. In FIG. 13, components having the same reference numerals as those in FIG. 9 correspond to portions having the same reference numerals in FIG. The high potential generating circuit 145 is connected to the power supply line 148 by the switch means 147, and is a circuit for setting the power supply line 148 to a high potential higher than the precharge potential. The low potential generation circuit 146 is a circuit that is connected to the power supply line 148 by the switch means 147, and lowers the precharge potential to a lower potential. Here, the precharge potential refers to the potential of the bit lines 110 and 111 when precharged. The high potential refers to a potential higher than the precharge potential by the threshold value of the NMOS transistor, and the low potential refers to a potential lower than the precharge potential by the threshold value of the NMOS transistor.
The test mode circuit 141 controls the switch means 147 to connect the high potential generation circuit 145 or the low potential generation circuit 146 to the power supply line 148 in the test mode. At times other than the test mode, neither the high potential generation circuit 145 nor the low potential generation circuit 146 is connected to the power supply line 148. An NMOS transistor 150 is provided in which one and the other current electrodes are connected to the power supply line 148 and the bit line 110, respectively, and the gate is connected to the signal line 149.

  The signal line 149 has a high-level potential in the test mode. When the power supply line 148 has a high or low potential, the bit line 110 is charged to a high or low potential. Thereafter, by writing this data to the target word line, the data can be written to the memory cells in a lump. In a mode other than the test mode, the signal line 149 is supplied with the ground voltage GND.

  FIG. 14 is a circuit diagram showing a third mode of the configuration of the DRAM according to the fourth embodiment of the present invention. In FIG. 14, components having the same reference numerals as those in FIG. 13 correspond to portions having the same reference numerals in FIG. The DRAM of the third embodiment is different from the DRAM of the second embodiment in that a power supply line 152 is added in addition to the power supply line 148, and a bit line connected to the high potential generation circuit 145 or the low potential generation circuit 146 is provided. The point is that the rows are divided into even columns and odd columns. Power supply line 148 is connected to an odd-numbered bit line via transistor 150, and power supply line 152 is connected to an even-numbered bit line via transistor 153. Further, the switch unit 151 is configured to select the power supply lines 148 and 152.

FIG. 2 is a block diagram showing an example of a configuration of the semiconductor integrated circuit according to the first embodiment. FIG. 2 is a block diagram illustrating a relationship between a multiplexer and an interface circuit illustrated in FIG. 1. FIG. 3 is a block diagram showing another aspect of the configuration of the semiconductor integrated circuit according to the first embodiment. FIG. 13 is a block diagram illustrating an example of a configuration of a semiconductor integrated circuit according to a second embodiment. FIG. 5 is a block diagram illustrating two current conversion circuits of FIG. 4. FIG. 5 is a block diagram illustrating a configuration of a comparison result measurement circuit in FIG. 4. 6 is a timing chart for explaining an operation of the frequency comparator. 6 is a timing chart for explaining an operation of the frequency comparator. FIG. 13 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment. 10 is a timing chart for explaining the operation of the circuit shown in FIG. FIG. 14 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a fourth embodiment. FIG. 15 is a circuit diagram illustrating an example of a configuration of a memory cell according to a fourth embodiment; FIG. 19 is a circuit diagram showing another aspect of the configuration of the semiconductor integrated circuit according to the fourth embodiment. FIG. 19 is a circuit diagram showing another aspect of the configuration of the semiconductor integrated circuit according to the fourth embodiment. FIG. 2 is a block diagram illustrating a general configuration of a semiconductor integrated circuit. FIG. 3 is a block diagram showing a configuration of an expanded version of the semiconductor integrated circuit. FIG. 11 is a block diagram illustrating a configuration of a conventional PLL circuit.

Explanation of reference numerals

1 chip, 2 CPU, 3 phase locked loop circuit, 4 interface circuit, 5 SRAM, 6 DRAM, 7 NVRAM, 10 multiplexer, 16 local link bus, 41 frequency comparator, 42, 45 comparison result measuring circuit, 43, 47 encoder , 44, 48 current conversion circuit, 45 phase comparator, 49 ring oscillator, 46a bidirectional shift ring, 101 sense amplifier, 102 to 105 bit line, 106, 107 word line, 108, 109 memory cell, 140 intermediate voltage generation circuit , 141 test mode circuit, 142 negative voltage generation circuit, 145 high potential generation circuit, 146 low potential generation circuit.

Claims (2)

A first transistor having one current electrode, the other current electrode, and a control electrode connected to a storage node of the memory cell, being in a conductive state when the control electrode is at a high level, and being non-conductive when at a low level;
A word line connected to the control electrode of the first transistor;
A first bit line connected to the other current electrode of the first transistor;
A second bit line provided corresponding to the first bit line;
A first current electrode connected to the first bit line, a second current electrode connected to the second bit line, and a control electrode to which a first signal is supplied, wherein the first signal is at a high level; A second transistor which is turned on when the first signal is at a low level and is turned off when the first signal is at a low level;
Power line,
It has one current electrode connected to the power supply line, the other current electrode connected to the second bit line, and a control electrode to which a second signal is applied, and is in a conductive state when the second signal is at a high level. And a third transistor which is turned off when the second signal is at a low level;
A negative voltage that is selectively connectable to the power supply line and that supplies a negative voltage to the power supply line, the negative voltage being capable of setting the power supply line to a voltage lower than a low level to make the first to third transistors conductive; A semiconductor integrated circuit comprising: a generation circuit. A word line and a first bit line connected to the memory cell;
A second bit line provided corresponding to the first bit line;
A first current electrode connected to the first bit line, a second current electrode connected to the second bit line, and a control electrode to which a first signal is applied, wherein the first signal is a first signal; A first transistor which is turned on when the potential is a potential and is turned off when the first signal is a second potential;
A second transistor having one current electrode, the other current electrode connected to the second bit line, and a control electrode to which a second signal is supplied;
A power line connected to the other current electrode of the second transistor;
Selectively connectable to the power supply line, the second bit line is cut off from the first bit line by the first transistor, and the second bit line and the second signal are connected to the second bit line. A potential generating circuit that, when at an intermediate potential between the first potential and the second potential, applies to the power supply line a potential that is larger than the threshold value of the second transistor with respect to the intermediate potential. Semiconductor integrated circuit.

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