JP2004228869A - Image processor and its processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor in which both the dynamic range and the sensitivity can be ensured to be set with appropriate values by controlling a bias value being applied to each pixel depending on the brightness, and to provide its processing method. <P>SOLUTION: The image processor comprises a solid state imaging element, a signal processing section for processing the output from the solid state imaging element to deliver an image signal and having a means for measuring the brightness of an image picked up by means of the solid state image sensor, and a means for varying a bias value being applied to each pixel of the solid state imaging element depending on the brightness measured at the signal processing section. Since bias setting can be carried out appropriately depending on the brightness at the time of photographing, good image quality can be attained. Dynamic range and sensitivity can thereby be ensured to be set with appropriate values. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

図４（ａ）は、図２のソース電圧供給回路ＶＣ２１ないしＶＣ２ｎの構成を示す回路図である。ソース電圧供給回路ＶＣ２ｈは、コンデンサとトランジスタを含み、各種入力信号に応じて、ソース電圧ＶＰＳｈを出力する。
図４（ｂ）は，図４（ａ）におけるＳ１、Ｓ２、Ｓ３及びＳ４の信号を生成するための回路を示す。
各ソース電圧供給回路ＶＣ２ｈは、クリアパルス信号ＣＬの反転信号Ｓ１〜Ｓ３と、プリセット信号ＰＲの正転信号Ｓ４とが入力され、供給されているＶＣＣＳＤＢ及びＶＣＣＶＰＳを用いて、図５のＳＯＵＲＣＥバイアス電圧を発生して、各センサセルのソースに与える。
【００５８】
図４（ｂ）において、信号Ｓ１〜Ｓ３はクリアパルス信号ＣＬの反転信号であり、プリセット信号ＰＲの正転信号Ｓ４は、クリア前ゲートプリセット信号ＰＲと同一論理レベルの信号である。クリアパルス信号ＣＬ及びクリア前ゲートプリセット信号ＰＲがいずれもＬレベルの場合には、反転信号Ｓ１〜Ｓ３はＨレベルであり、プリセット信号ＰＲの正転信号Ｓ４はＬレベルである。従って、ＮＭＯＳトランジスタＴ１１，Ｔ１３はオンであり、ＰＭＯＳトランジスタＴ１２，Ｔ１４はオフであり、ＮＭＯＳトランジスタＴ１５はオフである。即ち、この場合には、トランジスタＴ１４，Ｔ１５がオフであるので、ソース電圧供給回路ＶＣ２ｈはソース電圧を供給しない。なお、この時点では、ＮＤ１点の電圧値はグランドレベル（ＧＮＤ）であり、ＮＤ２点の電圧値はＶＣＣＳＤＢである。
【００５９】
また、クリアパルス信号ＣＬがＬレベルで、クリア前ゲートプリセット信号ＰＲがＨレベルの場合には、反転信号Ｓ１〜Ｓ３及びプリセット信号ＰＲの正転信号Ｓ４はＨレベルである。従って、トランジスタＴ１１，Ｔ１３，Ｔ１５はオンであり、トランジスタＴ１２，Ｔ１４はオフである。即ち、この場合には、ソース電圧ＶＰＳｈは電圧ＶＣＣＶＰＳとなり、また、ＮＤ１点の電圧値はグランドレベル（ＧＮＤ）であり、ＮＤ２点の電圧値はＶＣＣＳＤＢである。従って、この間、コンデンサＣ１ は電圧ＶＣＣＳＤＢまで充電される。
【００６０】
また、クリアパルス信号ＣＬがＨレベルで、クリア前ゲートプリセット信号ＰＲがＬレベルの場合には、反転信号Ｓ１〜Ｓ３及びプリセット信号ＰＲの正転信号Ｓ４はＬレベルである。従って、トランジスタＴ１１，Ｔ１３，Ｔ１５はオフであり、トランジスタＴ１２，Ｔ１４はオンである。即ち、この場合には、ＮＤ２点の電圧がソース電圧ＶＰＳｈとなる。仮に、この場合の直前に、コンデンサＣ１の電圧がＶＣＣＳＤＢに充電されていれば、トランジスタＴ１２がオンすることによってＮＤ１点は電圧ＶＣＣＳＤＢになるので、ＮＤ２点の電圧値はＶＣＣＳＤＢ×２となる。
【００６１】
即ち、図４の回路は下記表２の状態を得る。

図５は、センサセルへ印加するバイアス電圧を説明するための図である。
図５は、各状態における、各セルのゲート電圧、ソース電圧及びドレイン電圧の電圧値を示す。なお、図５ではバイアス電圧の観点から、“蓄積”、“リセット（Ｓ）”、“変調（Ｓ）”、“プリセット”、“クリア”、“リセット（Ｎ）”及び“変調（Ｎ）”の各状態に分けて示している。
【００６２】
図５において、ＧＡＴＥは、セルのゲート電圧であり、選択状態と非選択状態の２つの状態を有する。ＳＯＵＲＣＥは、セルのソース電圧である。ＤＲＡＩＮは、セルのドレイン電圧であり、選択状態と非選択状態の２つの状態を有する。
【００６３】
まず、蓄積状態の場合について説明する。
“蓄積”の状態（以下、蓄積状態という。）のとき、セルアレー中の全てのセルが選択状態とされ、電圧値がＶＣＣＳＧＨＩである電圧が、ゲートに印加される。蓄積状態のとき、非選択のセルはない。蓄積状態のとき、ソースは、ソース電圧供給回路ＶＣ２ｈからのバイアス電圧の供給を受けないが、ゲートにＶＣＣＳＧＨＩの電圧が印加され、光信号検出用ＭＯＳトランジスタＰＤＴｒがターンオンしているので、ソース・ドレイン間が導通状態になり、蓄積状態ではソースはドレイン電圧（ＶＣＣＳＤＩ）に等しくなる。
【００６４】
次に、“リセット（Ｓ）”の状態（以下、ＲＥＳＳ状態と略す。）の場合について説明する。
選択状態のセルの場合、ＲＥＳＳ状態のとき、電圧値がＬｏ（Ｌレベル）である電圧が、ゲートに印加される。ＲＥＳＳ状態のときは、電圧値がＶＭＰＲである電圧が、ソースに印加される。選択状態のセルの場合、ＲＥＳＳ状態のとき、ゲートにＬｏの電圧が印加され、光信号検出用ＭＯＳトランジスタＰＤＴｒがオフしているので、ソース・ドレイン間が非導通状態になり、ドレインはハイインピーダンス（ＨｉＺ）となる。
【００６５】
また、非選択状態のセルの場合、ＲＥＳＳ状態のときは、電圧値がＬｏ（Ｌレベル）である電圧が、ゲートに印加される。あるセルが非選択状態で、ＲＥＳＳ状態のときは、ドレインはＨｉＺとなる。
“変調（Ｓ）”の状態（以下、ＬＯＡＤＳ状態と略す。）において、選択状態のセルの場合、電圧値がＶＣＣＳＧＨＲである電圧が、ゲートに印加される。選択状態のセルの場合、電圧値がＶＣＣＳＤＲである電圧が、ドレインに印加され、電圧値が（ＶＣＣＳＧＨＲ−ＶｔｈＳ）である電圧が、ソースに出力される。ＬＯＡＤＳ状態では、（ＶＣＣＳＧＨＲ＜ＶＣＣＳＤＲ）の関係が成り立つバイアス電圧を印加する必要がある。
【００６６】
また、非選択状態のセルの場合、ＬＯＡＤＳ状態のとき、電圧値がＬｏである電圧が、ゲートに印加され、電圧値がＶＣＣＳＤＲである電圧が、ドレインに印加される。
続いて、“プリセット”の状態（以下、ＰＲ状態と略す。）の場合について説明する。
選択状態のセルの場合、ＰＲ状態のとき、電圧値がＶＣＣＳＧＨＲである電圧が、ゲートに印加される。ＰＲ状態のとき、電圧値がＶＣＣＶＰＳである電圧が、ソースに印加される。選択状態のセルの場合、ＰＲ状態のとき、光信号検出用ＭＯＳトランジスタＰＤＴｒがターンオンしているので、ドレインはソースと同じ電圧となる。
【００６７】
また、非選択状態のセルの場合、ＰＲ状態のとき、電圧値がＬｏである電圧が、ゲートに印加され、ドレインはＶＣＣＶＰＳとなる。ＶＳＣｉがＬｏレベルのライン（＝非選択ライン）はＴ５がターンオンし、各ラインが共通ノード（ＣＯＭノード）に接続されてＣＯＭノードがＨｉＺとなる。
【００６８】
“クリア”の状態（以下、ＣＬ状態と略す。）において、選択状態のセルの場合、電圧値が（ＶＣＣＳＤＢ×２）である電圧が、ソースに印加され、光信号検出用ＭＯＳトランジスタＰＤＴｒがターンオンしているので、ドレインはソースと同じ電圧となる。その結果、電圧値が（ＶＣＣＳＧＨＲ＋ＶＣＣＳＤＢ×２）の電圧が、ゲートに印加される。
【００６９】
また、非選択状態のセルの場合、ＣＬ状態のとき、電圧値がＬｏである電圧が、ゲートに印加され、電圧値がＶＣＣＳＤＲである電圧が、ドレインに印加される。
次に、“リセット（Ｎ）”の状態（以下、ＲＥＳＮ状態と略す。）の場合について説明する。
選択状態のセルの場合、ＲＥＳＮ状態のとき、電圧値がＬｏである電圧が、ゲートに印加される。ＲＥＳＮ状態のとき、電圧値がＶＭＰＲである電圧が、ソースに印加される。選択状態のセルの場合、ＲＥＳＮ状態のとき、ドレインはＨｉＺとなる。
【００７０】
また、非選択状態のセルの場合、ＲＥＳＮ状態のとき、電圧値がＬｏである電圧が、ゲートに印加される。非選択状態のセルの場合、ＲＥＳＮ状態のとき、ドレインはＨｉＺとなる。
なお、クリアパルス信号ＣＬがＬレベルの期間では、図３のＮＭＯＳトランジスタＴ５がターンオンしている。従って、ＲＥＳＳ状態でもＮＭＯＳトランジスタＴ５はターンオンしてドレインはＣＯＭノードに接続される。読み出しイネーブル信号ＳＤＲ２は、ＲＥＳＳ状態とＲＥＳＮ状態でＨレベルとなるので、ＰＭＯＳトランジスタＴ４がターンオフし、ＣＯＭノードはフローティングとなる。
【００７１】
“変調（Ｎ）”の状態（以下、ＬＯＡＤＮ状態と略す。）において、選択状態のセルの場合、電圧値がＶＣＣＳＧＨＲである電圧が、ゲートに印加される。ＬＯＡＤＮ状態のとき、電圧値がＶＣＣＳＤＲである電圧が、ドレインに印加され、電圧値が（ＶＣＣＳＧＨＲ−ＶｔｈＮ）である電圧が、ソースに出力される。
【００７２】
また、非選択状態のセルの場合、ＬＯＡＤＮ状態のとき、電圧値がＬｏである電圧が、ゲートに印加され、電圧値がＶＣＣＳＤＲである電圧が、ドレインに印加される。
ＬＯＡＤＳ状態と同様に、ＬＯＡＤＮ時も図３のＴ５がターンオンしているのでドレインはＣＯＭノード（＝ＨｉＺ）に接続される。
【００７３】
図６は、センサの読み出しラインとクリアラインを説明するための図である。
【００７４】
図６に示すように、ｍ×ｎの画素マトリックスにおいて、各ラインが第１のラインから第ｍのラインまで順番に走査される。読み出しラインは、光量に応じた信号が読み出されるラインであり、クリアラインは、各セルに蓄積された電荷がクリアされるラインである。第１ラインから順番に走査が行われるので、クリア用選択信号に基づいてクリアされたラインの各セルに、その後に受光した光量に応じてホールが生成される。クリア後、読み出しライン選択信号ＶＳＢｉによって読み出されるまでの時間が露出時間となる。露出時間は、読み出しラインとクリアライン間のライン数ｄｌ に比例し、シャッタースピードの設定、すなわち、１Ｈ（Ｈは水平ライン数を示す。以下同じ。）からｍＨの範囲（あるいは（１フレーム＋１Ｈ以上でもよい）の設定によって変更することができる。
【００７５】
図７は、垂直同期信号ＶＳＹＮＣと水平同期信号ＨＳＹＮＣのタイミングを示すタイミングチャートである。
垂直同期信号ＶＳＹＮＣは、周期ｔ１毎に発生される、ｔ２時間長さのタイミングパルスである。水平同期信号ＨＳＹＮＣは、周期ｔ３毎に発生される、ｔ４時間長さのタイミングパルスである。垂直同期信号ＶＳＹＮＣと水平同期信号ＨＳＹＮＣは、信号処理ＬＳＩ２のタイミングジェネレータ２６からイメージセンサＬＳＩ１へ供給される。
【００７６】
垂直同期信号ＶＳＹＮＣが供給されると、読み出しライン用シフトレジスタ５は、選択信号ＶＳＢｉを順次出力する。垂直同期信号ＶＳＹＮＣの供給後の周期ｔ１内において、水平同期信号ＨＳＹＮＣが、センサセルアレイ３のライン数（＝ｍ）だけ出力される。そして、水平同期信号ＨＳＹＮＣが出力されている期間ｔ４内であってかつＶＧＵＰがＬの期間に、上述した信号成分の読み出し、クリア、そしてオフセット成分の読み出しの動作が行われる期間が存在する。このＶＧＵＰがＬの期間は、Ｈブランキング期間中の所定の期間に設定される。Ｈブランキング期間については、後で図９を用いて詳述する。
【００７７】
周期ｔ３内の期間ｔ４後の期間ｔ５内に、ｎ個の信号成分とオフセット成分のアナログ信号ＶＯＵＴＳとＶＯＵＴＮが出力される。
次に、イメージセンサＬＳＩ１のタイミングジェネレータ（以下、ＴＧという）１３の回路構成について図８を参照して説明する。
図８は、図１のイメージセンサＬＳＩ１のＴＧ１３の構成を示す回路ブロック図である。
【００７８】
ＴＧは、シリアルコントロールブロック７１、マスタタイミング制御ブロック７２、センサレジスタブロック７３、シャッターコントロール部（シャッタスピード上限制御部）７４、フレームコントロール部７５、Ｈ・Ｖカウンタ７６、垂直スキャン制御ブロック７７、水平スキャン制御ブロック７８、アナログ制御ブロック７９を含む。
【００７９】
シリアルコントロールブロック７１には、当該シリアルコントロールブロック７１と、信号処理ＬＳＩ２のレジスタ１４との間のインターフェース信号である３線シリアルＩ／Ｆ信号が入出力される。
マスタタイミング制御ブロック７２には、信号処理ＬＳＩ２のＴＧ２６からセンサ駆動クロックＳＣＬＫ，水平同期信号ＨＳＹＮＣ及び垂直同期信号ＶＳＹＮＣが入力される。またＴＧ１３には、信号処理ＬＳＩ２からのクロック指定信号ＣＬＫ＿ＳＥＬと、スタンバイ信号ＳＴＡＮＤＢＹが入力されている。
【００８０】
シリアルコントロールブロック７１は、信号処理ＬＳＩ２のレジスタ２３に書き込まれているシャッタスピードの設定データ，レギュレータ８の設定データ及びシステムクロック情報などをシリアルＩ／Ｆ信号として入力し、これらのデータについてライトデータ，ライトアドレス及びライトストローブ信号ＷＲを出力し、センサレジスタブロック７３に供給する。
【００８１】
前記センサレジスタブロック７３は、上記の入力信号に応じて、ラインシャッタスピード設定信号，フレームシャッタスピード設定信号，フレームモード設定信号，クリアパルス幅制御設定信号，クリアパルス印加回数設定信号，ゲイン設定信号及びレギュレータ電圧設定信号を出力する。
一方、マスタタイミング制御ブロック７２は、前述の各種入力信号に基づいて、ピクセルクロック，水平リセットパルス，垂直リセットパルス及びリセット信号を出力する。
【００８２】
シャッタコントロール部（シャッタスピード上限制御部）７４には、センサレジスタブロック７３からのラインシャッタスピード設定信号及びフレームシャッタスピード設定信号が入力され、出力としてラインシャッタスピードデータ及びフレームシャッタスピードデータを出力する。
【００８３】
フレームコントロール部７５には、前記マスタタイミング制御ブロック７２からのピクセルクロック，垂直リセットパルス及びリセット信号と、前述のスタンバイ信号ＳＴＡＮＤＢＹが入力され、出力としてフレームカウント値，フレーム制御データ及びバリッド（ＶＡＬＩＤ）制御信号を出力する。
また、Ｈ・Ｖカウンタ７６には、前記マスタタイミング制御ブロック７２からのピクセルクロック，水平リセットパルス，垂直リセットパルス及びリセット信号が入力され、出力としてラインカウント値及びピクセルカウント値を出力する。
【００８４】
垂直スキャン制御ブロック７７には、入力として、前記シャッタコントロール部７４からのラインシャッタスピードデータ及びフレームシャッタスピードデータ、前記フレームコントロール部７５からのフレームカウント値，フレーム制御データ及びバリッド（ＶＡＬＩＤ）制御信号、前記センサレジスタブロック７３からのクリアパルス幅制御設定信号及びクリアパルス印加回数設定信号、前記マスタタイミング制御ブロック７２からのピクセルクロック及びリセット信号、クロック指定信号ＣＬＫ＿ＳＥＬ、前記Ｈ・Ｖカウンタ７６からのラインカウント値及びピクセルカウント値が入力される。
【００８５】
垂直スキャン制御ブロック７７は、出力としてクリアライン用シフトデータＡＶ，クリアライン用シフトクロックＶＣＬＫ＿ＡＳＲ，クリアライン用シフトレジスタリセット信号ＶＳＦＲＡ＿ＲＳＴ，クリアライン選択イネーブル信号ＣＬＳ，読み出しライン用シフトデータＢＶ，読み出しライン用シフトクロックＶＣＬＫ＿ＢＳＲ，読み出しライン用シフトレジスタリセット信号ＶＳＦＲＢ＿ＲＳＴ，読み出しライン選択イネーブル信号ＶＳＭ，蓄積時全ライン選択信号ＶＧＵＰ，蓄積イネーブル信号ＳＤＩ，読み出しイネーブル信号ＳＤＲ，クリア前ゲートプリセット信号ＰＲ，クリアパルスＣＬを出力する。
【００８６】
水平スキャン制御ブロック７８には、入力として、前記フレームコントロール部７５からのバリッド（ＶＡＬＩＤ）制御信号、前記Ｈ・Ｖカウンタ７６からのラインカウント値及びピクセルカウント値、前記センサレジスタブロック７３からのクリアパルス幅制御設定信号、前記マスタタイミング制御ブロック７２からのピクセルクロック及びリセット信号、クロック指定信号ＣＬＫ＿ＳＥＬが入力される。
【００８７】
水平スキャン制御ブロック７８は、出力としてラインメモリ選択用シフトデータＡＨ，ラインメモリ選択用シフトクロックＣＩＮ，ラインメモリ選択イネーブル信号ＨＳＣ＿ＣＫ，蓄積信号用ラインメモリリセット信号ＲＥＳＳ，蓄積信号用ラインメモリデータロード信号ＬＯＡＤＳ，オフセット用ラインメモリリセット信号ＲＥＳＮ，オフセット用ラインメモリデータロード信号ＬＯＡＤＮを出力する。
【００８８】
上記のクロック指定信号ＣＬＫ＿ＳＥＬは、システムクロック信号ＣＬＫＩＮの周波数の高低を示す信号であるが、このＣＬＫ＿ＳＥＬは垂直スキャン制御ブロック７７及び水平スキャン制御ブロック７８に供給されている。各制御ブロック７７及びク７８では、クロック指定信号ＣＬＫ＿ＳＥＬのＨ，Ｌレベルに応じて各ブロック７７及びク７８から出力される各種センサ駆動信号の出力タイミングを制御できるようになっている。
【００８９】
アナログ制御ブロック７９には、前記フレームコントロール部７５からのバリッド（ＶＡＬＩＤ）制御信号、前記Ｈ・Ｖカウンタ７６からのラインカウント値及びピクセルカウント値、前記センサレジスタブロック７３からのゲイン設定信号、スタンバイ信号ＳＴＡＮＤＢＹが入力され、出力としてアナログアンプゲイン制御信号，アンプ用駆動クロックＣＤＬ，スタンバイ制御信号を出力する。
【００９０】
そして、前記フレームコントロール部７５からのバリッド（ＶＡＬＩＤ）制御信号はＶＡＬＩＤ信号としてＴＧ１３から信号処理ＬＳＩ２へ出力されるようになっている。
また、前記センサレジスタブロック７３からのレギュレータ電圧設定信号と、前記アナログ制御ブロック７９からのスタンバイ制御信号とは、図１のイメージセンサＬＳＩ１のセンサ駆動バイアス発生用レギュレータ８に入力される。
【００９１】
前記アナログ制御ブロック７９からのアナログアンプゲイン制御信号とアンプ用駆動クロックＣＤＬとは、図１のイメージセンサＬＳＩ１の出力アンプ１２の制御用信号となる。
【００９２】
図９はセンサセルアレイ３の光電変換を制御する各信号を示すタイミングチャートである。センサセルアレイ３は、“蓄積”、“リセット（Ｓ）”、“変調（Ｓ）”、“プリセット”、“クリア”、“リセット（Ｎ）”及び“変調（Ｎ）”の各状態の繰返しによって、光学像を電気信号に変換して出力する。図９はこれらの各状態における信号の様子を示している。センサセルアレイ３は、図７の垂直同期信号ＶＳＮＹＣ及び水平同期信号ＨＳＹＮＣを単位時間とした所定のフレームレートで動作する。
【００９３】
図９の例では、あるラインカウント信号ＲＯＷＣＴにおいて、ＨＳＹＮＣが、ピクセルクロック信号ＰＸＬＣＴが１から８０までＬレベルであり、さらにＰＸＬＣＴが５から２２までがＬＯＡＤＳ（リセット（Ｓ）＋変調（Ｓ））状態に、ＰＸＬＣＴが２７から４４までがＣＬ（プリセット＋クリア）状態に、ＰＸＬＣＴが４５から６３までがＬＯＡＤＮ（リセット（Ｎ）＋変調（Ｎ））状態に割り当てられている。
【００９４】
なお、各制御信号はＴＧ１３によって生成され出力される。ＴＧ１３は、論理回路で構成されるが、その論理回路は、Ｖｅｒｉｌｏｇ−ＨＤＬ、ＶＨＤＬ等のＨＤＬ（Ｈａｒｄｗａｒｅ Ｄｅｓｃｒｉｐｔｉｏｎ Ｌａｎｇｕａｇｅ：ハードウエア記述言語）を利用した設計システムを用いれば、自動設計することができる。
【００９５】
先ず、蓄積状態について説明する。
図７に示すＨブランキング期間中の所定期間（図９の第５ピクセル〜第６３ピクセル）以外の期間が蓄積期間である。蓄積期間には、全画素が蓄積状態となる。この期間には、蓄積時全ライン選択信号ＶＧＵＰはＨレベルで、蓄積イネーブル信号ＳＤＩ及びクリアパルス信号ＣＬはＬレベルである。図２に示すように、蓄積時全ライン選択信号ＶＧＵＰがＨレベルとなることによって全てのライン選択信号ＶＳＣｉがＨレベルとなり、ドレイン・ゲート電圧供給回路ＶＣ１ｉの動作を示す上記表１に示すように、ゲート電圧ＶＰＧｉはＶＣＣＳＧＨＩとなる。また、ドレイン電圧ＶＰＤｉは電圧ＶＣＣＳＤＩとなる。また、この期間には、クリア前ゲートプリセット信号ＰＲもＬレベルであり、ソース電圧供給回路ＶＣ２ｈの動作を示す上記表２に示すように、ソース電圧供給回路ＶＣ２ｈはソース電圧を供給しない。この場合には、セルアレー中の全てのセルのソースは、光信号検出用ＭＯＳトランジスタＰＤＴｒがターンオンしドレイン電圧に一致する。
【００９６】
Ｈブランキング期間の第５ピクセルにおいて蓄積期間は終了し信号読み出しが開始される。この信号読み出しのための期間（ＬＯＡＤＳ，ＣＬ，ＬＯＡＤＮ期間）においても、受光光量に基づくホールの蓄積は継続されるが、各セルは蓄積期間とは異なる設定値に設定される。また、信号読み出しのための期間には、クリアライン、読み出しライン又は非選択ラインでは、各セルは個別の設定値に設定される。
【００９７】
先ず、リセット（ｓ）状態について説明する。図９に示すように、この期間においても、全てのセルに共通の設定が行われる。
図９に示すように、クリアパルス信号ＣＬ及びクリア前ゲートプリセット信号ＰＲはＬレベルであり、ソース電圧供給回路ＶＣ２ｈはソース電圧を供給しない。この期間においては、蓄積信号用ラインメモリリセット信号ＲＥＳＳがハイアクティブとなり、図２のスイッチＳＷ２２がオンとなって、ラインメモリを構成するコンデンサＣ２ の端子電圧はＶＭＰＲにチャージされる。更に、蓄積信号用ラインメモリデータロード信号ＬＯＡＤＳ及びラインメモリデータロード信号ＬＯＡＤもハイアクティブとなり、スイッチＳＷ２１及びスイッチＳＷ１１がオンとなって、ソースラインを電圧ＶＭＰＲで初期化する。
【００９８】
一方、蓄積時全ライン選択信号ＶＧＵＰはＨからＬに変化し、全てのライン選択信号ＶＳＣｉはＬレベルに変化する。従って、表１に示すように、ゲート電圧ＶＰＳＧｉは全てＬ（ＧＮＤ）レベルとなる。また、蓄積イネーブル信号ＳＤＩはＨレベルであり、ＳＤＲ２もＨレベルであるため、表１に示すように、図３中のＴ５がターンオンしているので、全てのセルのドレインは共通に接続され（ＣＯＭノード）、そのＣＯＭノードはＨｉｚ状態となる。
【００９９】
次に、変調（ｓ）状態について説明する。
図９に示すように、ＣＬ，ＰＲはＬレベルを維持しており、ソース電圧供給回路ＶＣ２ｈはソースラインに電圧を供給していない。各セルに設定した電圧値に応じた出力がソースラインを介して出力される。即ち、クリアライン及び非選択ラインについてはライン選択信号ＶＳＣｉはＬレベルのままであり、ゲート電圧はＬ（ＧＮＤ）レベルである。また、読み出しイネーブル信号ＳＤＲ２もＬレベルであるので、ドレイン電圧ＶＰＤｉはＶＣＣＳＤＲとなる。
【０１００】
読み出しラインについてはライン選択信号ＶＳＣｉはＨレベルである。クリアパルス信号ＣＬ及び信号ＳＤＲがＬレベルであるので、ゲート電圧ＶＰＧｉはＶＣＣＳＧＨＲである。ドレイン電圧ＶＰＤｉはＶＣＣＳＤＲである。これにより、ソース電圧ＶＰＳｉには電圧（ＶＣＣＳＧＨＲ−ＶｔｈＳ）が現れる。なお、ＶｔｈＳは、蓄積されたホールに応じて変化する。ソースラインの電圧（ＶＣＣＳＧＨＲ−ＶｔｈＳ）は、スイッチＳＷ２１を介してラインメモリを構成する各コンデンサＣ２ に蓄積される。
【０１０１】
次に、相関２重サンプリング処理のために、読み出しラインの各セルに蓄積されているホールを除去（クリア）するためのＣＬ状態を設定する。ホールの除去のためには極めて高い電圧をゲートに印加する必要があり、クリア状態の前にプリセット状態を設定して、倍圧回路を利用して高電圧を得るようになっている。なお、読み出しラインのクリアと同時にクリアラインの各セルのクリアも行うようになっている。
【０１０２】
先ず、プリセット状態においては、読み出しラインとクリアラインについては、ライン選択信号ＶＳＣｉはＨレベルである。クリアパルス信号ＣＬ及び信号ＳＤＲはＬレベルであるので、ゲート電圧ＶＰＧｉはＶＣＣＳＧＨＲである。なお、非選択ラインについては、ライン選択信号ＶＳＣｉがＬレベルであるので、ゲート電圧はＬ（ＧＮＤ）レベルである。
【０１０３】
また、クリアパルス信号ＣＬはＬレベルで、クリア前ゲートプリセット信号ＰＲはＨであるので、表２に示すように、全ソースラインの電圧ＶＰＳｈは電圧ＶＣＣＶＰＳ（例えば０Ｖ）にリセットされる。また、図４のコンデンサＣ１ は電圧ＶＣＣＳＤＢがチャージされ、ＮＤ２点は電圧ＶＣＣＳＤＢとなる。なお、蓄積イネーブル信号ＳＤＩ及び読み出しイネーブル信号ＳＤＲ２はＨレベルであるので、ドレインは、光信号検出用ＭＯＳトランジスタＰＤＴｒがターンオンして、ソースと同電位になる。
【０１０４】
次に、クリア状態においては、クリア前ゲートプリセット信号ＰＲがＨレベルからＬレベルに変化し、クリアパルス信号ＣＬがＬレベルからＨレベルに変化する。この場合には、表２に示すように、ソースラインは電圧ＶＣＣＳＤＢ×２に変化する。また、読み出しラインとクリアラインについては、クリアパルス信号ＣＬ及びライン選択信号ＶＳＣｉがＨレベルであるので、表１に示すように、ゲートはフローティング状態となる。従って、ソースとゲートとのカップリング容量によって、ゲート電圧ＶＰＧｉは（ＶＣＣＳＤＢ×２＋ＶＣＣＳＧＨＲ）となる。また、ドレインはプリセット状態時と同様に、光信号検出用ＭＯＳトランジスタＰＤＴｒがターンオンして、ソースと同電位になる。
【０１０５】
一方、非選択ラインについては、ゲート電圧ＶＰＧｉはＬ（ＧＮＤ）レベルのままであり、ドレイン電圧ＶＰＤｉは、トランジスタＴ４ がオンとなるので、ＶＣＣＳＤＲとなる。
【０１０６】
次に、リセット（Ｎ）状態を経て、変調（Ｎ）状態に移行する。これらのリセット（Ｎ）状態及び変調（Ｎ）状態は、夫々リセット（ｓ）状態及び変調（ｓ）状態と略同様の信号が設定される。即ち、リセット（Ｎ）状態においては、蓄積信号用ラインメモリリセット信号ＲＥＳＳ，蓄積信号用ラインメモリデータロード信号ＬＯＡＤＳに夫々代えてオフセット用ラインメモリリセット信号ＲＥＳＮ，オフセット用ラインメモリデータロード信号ＬＯＡＤＮがハイアクティブとなる。これにより、スイッチＳＷ３２がオンとなって、ノイズ読み出し用のラインメモリを構成するコンデンサＣ３ がＶＭＰＲにチャージされる。更に、スイッチＳＷ３１及びスイッチＳＷ１１がオンとなって、ソースラインは電圧ＶＭＰＲで初期化される。
【０１０７】
変調（Ｎ）状態においては、クリアパルス信号ＣＬ，クリア前ゲートプリセット信号ＰＲはＬレベルであり、ソース電圧供給回路ＶＣ２ｈはソースラインに電圧を供給しない。クリアライン及び非選択ラインについてはライン選択信号ＶＳＣｉはＬレベルであり、ゲート電圧ＶＰＧｉはＬ（ＧＮＤ）である。また、読み出しイネーブル信号ＳＤＲ２もＬレベルであるので、ドレイン電圧ＶＰＤｉはＶＣＣＳＤＲとなる。
【０１０８】
読み出しラインについてはライン選択信号ＶＳＣｉはＨレベルである。クリアパルス信号ＣＬ及び信号ＳＤＲがＬレベルであるので、ゲート電圧ＶＰＧｉはＶＣＣＳＧＨＲである。ドレイン電圧ＶＰＤｉはＶＣＣＳＤＲである。これにより、ソース電圧ＶＰＳｈには電圧（ＶＣＣＳＧＨＲ−ＶｔｈＮ）が現れる。このソースに現れる電圧は、直前にクリア状態に設定されていることから、オフセット成分に対応したものとなっている。ソースラインの電圧（ＶＣＣＳＧＨＲ−ＶｔｈＮ）は、スイッチＳＷ３１を介してラインメモリを構成する各コンデンサＣ３ に蓄積される。
【０１０９】
こうして、コンデンサＣ２ には信号成分が蓄積され、コンデンサＣ３ にはオフセット成分が蓄積される。水平シフトレジスタ１１からの選択信号ＨＳＣＡＮｈによって、スイッチＳＷ２３，ＳＷ３３が順番にオンになることで、コンデンサＣ２ ，Ｃ３ に蓄積された電圧が夫々出力アンプ３６，３８を介してＶＯＵＴＳ，ＶＯＵＴＮとして出力される。
【０１１０】
ところで、前述したように、図１において、信号処理ＬＳＩ２では、輝度測光ロジック回路２２において、ＡＤＣ１９から供給される１フレーム期間の全ての緑（Ｇ）の画素のデータを積分することで輝度を測定する。輝度制御ロジック回路２１では、その測定結果に基づいて、ＰＧＡ１８へゲイン制御信号を供給することによって、画像の明るさの調整を行う一方、レジスタ２３へシャッタースピードのデータを書き込む。
【０１１１】
そこで、本発明の実施の形態では、上記のように、画像の平均照度の算出を行い、算出値に応じたシャッタスピード，アンプのゲインの制御を行うと共に、前記算出値に応じてセンサ画素に印可するバイアス電圧の制御を行える構成としている。
【０１１２】
センサ画素のバイアス電圧設定は、（１）図示しないＣＰＵによる設定、（２）信号処理ＬＳＩ２による設定、（３）シャッタスピード，ゲインに応じてイメージセンサＬＳＩ１内で自動的に設定する構成が考えられる。
【０１１３】
例えば、イメージセンサＬＳＩ１内のレジスタ１４には、前記設定を行うために、明るさの複数段階に対応した、複数の組（テーブル）のバイアス電圧値を用意しておく。
【０１１４】
図１０に、複数段階の明るさに対応した複数組のバイアス電圧値を、複数枚のテーブルＡ，Ｂ，Ｃ，…として示してある。バイアス電圧としては、ＶＲＥＦ（信号基準電圧）、ＶＭＰＲ、ＶＣＣＳＤＢ、ＶＣＣＳＧＨＩ、ＶＣＣＳＧＨＲ、ＶＤＤＳＤＲ、ＶＣＣＳＤＩ、ＶＰＳである。これらの英文字で示されるバイアス値は、その内容が図５及び図９において説明されている。図１０には、標準設定時（明るさが標準である時）のバイアス電圧値のテーブルＡの数値を一例として示している。即ち、テーブルＡでは、ＶＲＥＦ＝２．０Ｖ、ＶＭＰＲ＝１．０Ｖ、ＶＣＣＳＤＢ＝２．５Ｖ、ＶＣＣＳＧＨＩ＝２．２Ｖ、ＶＣＣＳＧＨＲ＝３．０Ｖ、ＶＣＣＳＤＲ＝３．３Ｖ、ＶＣＣＳＤＩ＝１．０Ｖ、ＶＣＣＶＰＳ＝０Ｖ である。
【０１１５】
なお、標準設定時におけるテーブルＡの上記ＶＭＰＲ、ＶＣＣＳＤＢ、ＶＣＣＳＧＨＩ、ＶＣＣＳＧＨＲ、ＶＣＣＳＤＲ、ＶＣＣＳＤＩ、ＶＣＣＶＰＳの各電圧値の相互の大小関係は、明るさが標準とは異なった他のテーブルＢ，Ｃ，…におけるそれぞれのバイアス電圧値相互間の関係においても維持される。
【０１１６】
レジスタ１４に設定する手段としては、図１０に示すようなデータテーブルを、信号処理ＬＳＩ２とイメージセンサＬＳＩ１それぞれに配置したレジスタ２３，１４間で送受することによって設定することができる。
【０１１７】
即ち、イメージセンサＬＳＩ１内のレジスタ１４と信号処理ＬＳＩ２内のレジスタ２３は、互いに同じデータをストアするようになっているので、一方のレジスタの内容が変更されると、３線シリアルインターフェース１５を介して、他方のレジスタの内容も変更される。よって、センサセルアレイ３の各画素に印可する、複数ステップの明るさに対応した複数のバイアス値テーブルのデータが、信号処理ＬＳＩ２内のレジスタ２３に書き込まれると、さらに、そのデータは、３線シリアルインターフェース１５を介して、イメージセンサＬＳＩ１内のレジスタ１４に書き込まれる。イメージセンサＬＳＩ１では、ＴＧ１３がレジスタ１４に設定された複数のバイアス値テーブルのデータから、明るさに応じたバイアス値テーブルを読み取ってレギュレータ８を制御することで、レギュレータ８から明るさに応じたバイアス電圧を出力することが可能となる。
【０１１８】
例えばクリア時のバイアス値設定について言えば、従来は明時，暗時にかかわらずクリア時のバイアス電圧は一定（固定）していたが、本発明では、暗い画像の場合は残留電荷がノイズ成分として目立ってくるので高いバイアス電圧をかけて残留電荷を追い出す。つまり、暗い時には、明るさの側結果に基づいて、クリア時のバイアス電圧値を標準時よりも高く設定することが可能となる。これにより、Ｓ／Ｎ比を良くすることができ画質を向上できる。
【０１１９】
図１０で説明した実施の形態によれば、明るさに応じて最適な駆動バイアス制御を行うことで、ダイナミックレンジの確保と感度の確保を行うことが可能となる。
【０１２０】
以上説明した本発明の実施の形態によれば、閾値電圧変調方式のＭＯＳ型固体撮像素子と、前記固体撮像素子の出力を信号処理しかつ撮像した画像の明るさを測定する信号処理部を含む画像処理装置において、前記の測定した明るさに応じて、前記固体撮像素子の各画素に印可するバイアス値を可変とすることにより、撮影時の明るさに応じて適切なバイアス値設定を行え、良好な画質を得ることができる。ダイナミックレンジの確保と感度の確保の両方が適切な値で設定できる。
【０１２１】
尚、上記実施の形態は、固体撮像素子として閾値電圧変調方式のＭＯＳ型イメージセンサを例に説明したが、閾値電圧変調方式のＭＯＳ型イメージセンサに限定されるものではなく、他の方式のイメージセンサについても適応可能であることは言うまでも無い。
【図面の簡単な説明】
【図１】本発明の実施の形態に係わる画像処理装置の構成を示すブロック図。
【図２】本発明の実施の形態に係わるイメージセンサＬＳＩの構成を示す回路図。
【図３】本発明の実施の形態に係わるドレイン・ゲート電圧供給回路の構成を示す回路図。
【図４】本発明の実施の形態に係わるソース電圧供給回路の構成を示す回路図。
【図５】本発明の実施の形態に係わるセンサセルへ印加するバイアス電圧を説明するための図。
【図６】本発明の実施の形態に係わる、センサの読み出しラインとクリアラインを説明するための図。
【図７】本発明の実施の形態に係わる垂直同期信号と水平同期信号のタイミングを示すタイミングチャート。
【図８】本発明の実施の形態に係わるイメージセンサＬＳＩのタイミングジェネレータの構成を示す回路ブロック図。
【図９】本発明の実施の形態に係わるＨブランキング期間における各状態における各信号の状態を説明するためのタイミングチャート。
【図１０】本発明の画像処理装置に係る、明るさに応じて設けた複数のバイアス電圧値のテーブルを説明する説明図。
【符号の説明】
１…イメージセンサＬＳＩ、２…信号処理ＬＳＩ、３…センサセルアレイ、６…垂直ドライブ回路、８…レギュレータ、９…蓄積信号用ラインメモリ、１０…オフセット信号用ラインメモリ、１３，２６…タイミングジェネレータ、１４，２３…レジスタ、１５…３線シリアルインターフェース[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image processing device and a processing method thereof. In particular, the present invention relates to an image processing apparatus including a matrix type solid-state imaging device in which a unit pixel includes a photodiode and a transistor for detecting an optical signal, and in which a plurality of the unit pixels are arranged, and a processing method therefor.
[0002]
[Prior art]
Semiconductor image sensors are used in various image input devices. Recently, a MOS type solid-state image pickup device using a threshold voltage modulation method has a high performance image quality of a CCD (charge coupled device) and a low power consumption of a CMOS. Attention has been paid to lower costs.
[0003]
The technology of the MOS type solid-state imaging device using the threshold voltage modulation method is disclosed in, for example, Japanese Patent Application Laid-Open No. H11-195778. In a threshold voltage modulation type MOS solid-state imaging device, an image signal based on photo-generated charges accumulated in a carrier pocket of each pixel is extracted by repeating three states of initialization, accumulation, and reading. The period of the initialization state is a period in which the residual charges are discharged from the inside of the carrier pocket. The period of the accumulation state is a period in which electric charges are accumulated in the sensor cells. The period of the read state is a period in which the accumulated charge amount is voltage-modulated and read.
[0004]
[Patent Document 1]
JP-A-11-195778 [0005]
[Problems to be solved by the invention]
By the way, in the technology disclosed so far, a light-shielded area is defined as optical black (OB) as a black level reference and an image reference value. Further, regarding brightness, it has been general to calculate an average value of the entire image and control the shutter speed and the gain of the amplifier based on the calculated value.
[0006]
However, the signal level of the pixel after initialization changes depending on the brightness at the time of photographing, and it is difficult to achieve both image quality in a bright place and a dark place. When it is bright, it is necessary to secure a dynamic range rather than sensitivity, and when it is dark, it is necessary to secure sensitivity (S / N ratio). Further, a difference (referred to as an offset) between a signal level of a pixel after initialization in a bright state and a signal level of an OB pixel narrows a dynamic range.
[0007]
In view of the above problem, the present invention controls a bias value applied to each pixel of a threshold voltage modulation type MOS solid-state imaging device in accordance with brightness, and secures both a dynamic range and sensitivity. It is an object of the present invention to provide an image processing apparatus and a processing method thereof that can be set with appropriate values.
[0008]
[Means for Solving the Problems]
An image processing apparatus according to the present invention includes a matrix-type solid-state imaging device in which a plurality of unit pixels each including a photodiode and a transistor for detecting an optical signal are arranged, and outputs an image signal of the solid-state imaging device as an image signal. Means, and a signal processing unit having means for measuring the brightness of the image captured by the solid-state imaging device, and according to the brightness measured by the signal processing unit, to each pixel of the solid-state imaging device Means for varying a bias value to be applied.
[0009]
According to such a configuration, an appropriate bias can be set according to the brightness at the time of shooting, and good image quality can be obtained. Both the securing of the dynamic range and the securing of the sensitivity can be set with appropriate values.
[0010]
In the image processing apparatus according to the aspect of the invention, it is preferable that the solid-state imaging device is a MOS solid-state imaging device using a threshold voltage modulation method.
[0011]
According to such a configuration, good image quality can be realized by using the MOS solid-state imaging device of the threshold voltage modulation method.
[0012]
In the image processing apparatus of the present invention, it is preferable that the variable unit sets a bias value according to brightness in a register, and varies the bias value according to the measured brightness.
[0013]
According to such a configuration, when setting the bias value, the bias value can be finely set according to the brightness.
[0014]
In the image processing apparatus of the present invention, it is preferable that the variable unit writes a bias value corresponding to the brightness in an external nonvolatile memory and changes the bias value according to the measured brightness. .
[0015]
According to such a configuration, the bias value data can be written in the non-volatile memory, and can be used by attaching to the outside of the device.
[0016]
Further, the processing method of the image processing apparatus according to the present invention includes a matrix type solid-state imaging device in which a plurality of unit pixels each including a photodiode and a transistor for detecting an optical signal are arranged, and an output of the solid-state imaging device is subjected to signal processing. And a signal processing unit for measuring the brightness of the captured image, wherein the bias value applied to each pixel of the solid-state imaging device is variable according to the measured brightness. Is what you do.
[0017]
According to such a method, appropriate bias setting can be performed according to the brightness at the time of shooting, and good image quality can be obtained. Both the securing of the dynamic range and the securing of the sensitivity can be set with appropriate values.
[0018]
In the processing method of the image processing apparatus according to the present invention, it is preferable that the solid-state imaging device is a threshold voltage modulation type MOS solid-state imaging device.
[0019]
According to such a method, good image quality can be realized by using the MOS type solid-state imaging device of the threshold voltage modulation method.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the configuration of the image processing apparatus according to the present embodiment will be described with reference to FIG.
[0021]
FIG. 1 is a block diagram showing a configuration of an image processing device including an image sensor LSI (large-scale integrated circuit) 1 as a solid-state imaging device and a signal processing LSI 2 as a signal processing device. The image sensor LSI1 is a two-dimensional solid-state imaging device, photoelectrically converts an optical image, and supplies a pixel signal based on the optical image to the signal processing LSI2. The signal processing LSI 2 performs predetermined signal processing on each received pixel signal and outputs an image signal.
[0022]
The image sensor LSI 1 includes a sensor cell array 3, a clear line shift register 4, a read line shift register 5, a vertical drive circuit 6, a booster circuit 7, a regulator 8, a storage signal line memory 9, an offset It includes a signal line memory 10, a horizontal shift register 11, an output amplifier 12, and a timing generator 13. The timing generator 13 includes a register 14 and a 3-wire serial interface 15.
[0023]
The sensor cell array 3 of the image sensor LSI 1 is, for example, a threshold modulation type solid-state imaging device as described in JP-A-11-195778. Various control signals are supplied from the timing generator 13 to each circuit, and based on the various control signals, the sensor cell array 3 outputs a pixel signal corresponding to the amount of light received by each cell. The sensor cell array 3 includes, for example, 640 × 480 cells and an area (OB area) for optical black (OB). Including the OB area, the sensor array 3 is composed of, for example, 712 × 500 cells. The image sensor LSI1 supplies to the signal processing LSI2 two output signals, a voltage output signal VOUTS of a signal component corresponding to the amount of received light and a voltage output signal VOUTN corresponding to the offset component.
[0024]
The vertical drive circuit 6 is a circuit for selecting a read line and a clear line. The read line shift register 5 and the clear line shift register 4 are circuits for specifying a read line and a clear line, respectively.
[0025]
The regulator 8 is a voltage generation circuit for generating various voltages required in the image sensor LSI1. The booster circuit 7 is a circuit for boosting the voltage supplied from the regulator 8 in order to supply a necessary voltage to the sensor cell array 3 as described later. A more detailed description of the image sensor LSI1 will be described later with reference to FIG.
[0026]
The signal processing LSI 2 includes a difference amplifier circuit 16, an optical black (hereinafter abbreviated as OB) clamp circuit 17, a programmable gain amplifier circuit (PGA) 18, an analog-digital conversion circuit (ADC) 19, and an OB control logic circuit. 20, a luminance control logic circuit 21, a luminance photometry logic circuit 22, a register 23, an image processor 24, a sequencer 25, and a timing generator 26. The register 23 stores data such as shutter speed data.
[0027]
Two analog signals VOUTS and VOUTN from the image sensor LSI1 are input to the difference amplifier circuit 16. The difference amplifier circuit 16 of the signal processing LSI 2 takes the difference between the voltage value of the signal component and the voltage value of the offset component, amplifies the difference, and outputs the difference voltage to the OB clamp circuit 17.
The OB clamp circuit 17 is a circuit for setting the black level of the input pixel signal to an appropriate black level. A cell of a predetermined number of pixels in the sensor cell array 3, that is, an OB area is shielded from light by a light shielding plate or the like. Black level adjustment is performed.
[0028]
The PGA 18 is an amplifier for adjusting a gain in, for example, one decibel unit. The signal amplified by the PGA 18 is supplied to the ADC 19. The ADC 19 converts the output of the PGA 18 into a digital signal.
For the pixels in the OB area, the luminance data of the pixels are supplied from the ADC 19 to the OB control logic circuit 20 as digital signals. The OB control logic circuit 20 inputs a signal from the ADC 19 based on a control signal from the timing generator 26, and outputs a control signal to the OB clamp circuit 17 to adjust a black level.
[0029]
Similarly, the luminance metering logic circuit 22 measures the luminance based on, for example, the data of all the green (G) pixels in one frame supplied from the ADC 19 and supplies the luminance data to the luminance control logic 21. .
The brightness control logic circuit 21 adjusts the brightness of the image by supplying a gain control signal to the PGA 18 based on the brightness data supplied from the brightness photometry logic circuit 22. Further, the brightness control logic circuit 21 writes shutter speed data to the register 23.
[0030]
Since the register 14 and the register 23 store the same data, when the content of one register is changed, the content of the other register is also changed via the 3-wire serial interface 15. You. Therefore, when the shutter speed data is written into the register 23 in the signal processing LSI 2, the data is further transferred to the register 14 in the image sensor LSI 1 via the 3-wire serial interface 15 and written. In the image sensor LSI1, a focal plane shutter is set based on shutter speed data. The function of the focal plane shutter will be described later.
[0031]
For example, on the image sensor LSI1, the width dl of the read line and the clear line of the focal plane is controlled based on the shutter speed data. When the exposure time is shortened, for example, when the image is bright, control is performed so as to reduce the width dl, that is, to reduce the number of lines between the read line and the clear line. In addition, when the exposure time is lengthened as in the case where the image is dark, control is performed so as to increase the width dl, that is, to increase the number of lines between the read line and the clear line. Further, when the exposure is not appropriate only by controlling the shutter speed, the luminance control logic circuit 21 controls the signal amount to be appropriate by adjusting the signal gain.
[0032]
The signal processing LSI 2 is supplied with a system clock signal CLKIN, and the timing generator 26 generates various timing signals based on the system clock signal CLKIN. The signal processing LSI 2 supplies various synchronization signals from various timing signals to the image sensor LSI 1. The synchronization signals include a sensor drive clock signal SCLK, a vertical synchronization signal VSYNC, and a horizontal synchronization signal HSYNC. The image sensor LSI1 synchronizes based on these synchronization signals and supplies an image signal to the signal processing LSI2. Therefore, each signal of SCLK, VSYNC, and HSYNC depends on the system clock signal CLKIN.
[0033]
The signal processing LSI2 registers 23, various parameters, for example, the whole, or partially bright parameters for the like, is input via the I 2 ^C-Bus (Ai Square seabass) I / F, stored You.
In the signal processing LSI 2, the image processor 24 is a circuit for generating an image based on RGB signals, and the sequencer 25 is a circuit for driving the image processor 24.
[0034]
A clock designation signal CLK_SEL is further input to the timing generator 13 of the image sensor LSI1. CLK_SEL is a signal for explicitly instructing the image sensor LSI1 to specify the clock frequency at which the image sensor LSI1 is operated, that is, for inputting a high / low instruction of the clock to the image sensor LSI1 as a control signal. The timing generator 13 changes the output timing of various control signals based on CLK_SEL. Further, the standby signal STANDBY is input to the timing generator 13.
[0035]
Data such as shutter speed, voltage setting of a regulator, designation of a scan direction, and the like are input to a register 14 of the image sensor LSI 1 via a three-wire serial interface 15 and stored.
Further, the image sensor LSI1 supplies a valid signal VALID as one control signal to the timing generator 26 of the signal processing LSI2. VALID is a signal indicating that valid image data is being output from the image sensor LSI1. When this signal is active, valid image data is output from the image sensor LSI1, so that the signal processing LSI2 can know that the data can be used for photometry and the like.
[0036]
Next, the configuration of the image sensor LSI1 will be described. FIG. 2 is a circuit diagram showing a configuration of the image sensor LSI1.
The sensor cell array 3 is a matrix solid-state imaging device including m × n (m rows and n columns) cells S11 to Smn. One cell corresponds to one unit pixel. Each cell corresponding to each unit pixel includes a photodiode PDS and a MOS transistor PDTr which is an insulated gate type field effect transistor for detecting an optical signal. The photodiode PDS includes an impurity diffusion region and a well region, and a hole (hole) is generated in the well region according to incident light. The well region is shared with the optical signal detection MOS transistor PDTr, and forms a gate region of the optical signal detection MOS transistor PDTr. The impurity diffusion region of the photodiode PDS and the drain diffusion region of the MOS transistor PDTr for detecting an optical signal are integrally formed on the surface of the well region. The drain diffusion region is formed so as to surround the outer periphery of the ring-shaped gate electrode. A source diffusion region is formed at the center of the ring-shaped gate electrode. A carrier pocket is formed in the well region below the gate electrode and around the source diffusion region so as to surround the source diffusion region. Details of the sensor structure are described in JP-A-11-195778.
[0037]
In order to obtain a signal corresponding to the light amount from the sensor cell array 3, in each of the three states of accumulation, reading, and clearing, a predetermined bias voltage is applied to the gate, source, and drain of each cell, thereby corresponding to the light amount. A signal can be obtained. Briefly, in the accumulation state, holes generated according to the amount of light incident on the photodiode PDS are accumulated in the carrier pocket. In the read state, a signal voltage is read based on the accumulated holes. The read signal voltage is a voltage signal corresponding to a difference between the gate voltage and a threshold value changed according to the amount of received light. In the clear state, the booster circuit 7 boosts the source voltage of the optical signal detection MOS transistor PDTr to a predetermined value, and also boosts the gate voltage to a predetermined value by the coupling capacitance between the ring gate and the source. The signal detection MOS transistor PDTr is turned on, and a channel is formed below the ring gate. Therefore, the drain voltage has a value substantially equal to the source voltage (when the drain voltage VD = VG-Vth and the gate voltage VG is sufficiently higher than the source voltage), and the accumulated depletion layer under the source, channel, and drain is expanded. The holes are swept toward the substrate to discharge residual charges such as holes. After clearing, an image signal can be obtained by reading an offset voltage including a noise component and calculating a difference between the signal voltage and the offset voltage. By performing the above-described operation for each cell and obtaining an image signal, a two-dimensional image signal can be obtained. The bias conditions, that is, the gate, source, and drain bias voltages of each cell in each state will be described later.
[0038]
The clear line shift register 4 is a circuit for specifying a line to be cleared. The clear line shift register 4 receives the clear line shift data AV, the clear line shift clock signal VCLK_ASR, and the clear line shift register reset signal VSFRA_RST. The clear line shift register 4 outputs clear line selection signals VSA1 to VSAm for selecting a line for clearing the accumulated charge in the matrix-like sensor cell array 3.
[0039]
The read line shift register 5 is a circuit for specifying a read line. The read line shift register 5 receives the read line shift data BV, the read line shift clock signal VCLK_BSR, and the read line shift register reset signal VSFRB_RST. The read line shift register 5 outputs read line selection signals VSB1 to VSBm for selecting a line from which a signal voltage is read in the matrix-like sensor cell array 3.
[0040]
By providing the clear line shift data AV and the read line shift data BV at the output timing determined based on the shutter speed data, the clear line shift register 4 and the read line shift register 5 are sequentially selected. Output a signal. That is, the read line shift data BV is generated at a predetermined timing with respect to the vertical synchronization signal VSYNC, but the phase relationship between the read line shift data BV and the clear line shift data AV is determined by the shutter speed. Then, with the phase relationship maintained, the clear line shift register 4 and the read line shift register 5 sequentially output selection signals. As described later, when a read line and a clear line exist in one frame, two lines in the sensor array are designated and selected.
[0041]
The vertical drive circuit 6 includes two AND circuits 31, 32, an OR circuit 33, a buffer circuit 34, and a drain / gate voltage supply circuit VC1i (i is any one of 1 to m.) And the same.). One AND circuit 31 receives a clear line selection signal VSAi and a clear line selection enable signal CLS as inputs. The other AND circuit 32 receives a read line select signal VSBi and a read line select enable signal VSM for three operations of signal read, clear, and noise read as inputs. The OR circuit 33 receives the output signals of the AND circuits 31 and 32 and the storage-time all-line selection signal VGUP as inputs. The buffer circuit 34 receives an output signal from the OR circuit 33 as an input. The output signal of each buffer circuit 34 is supplied to the drain / gate voltage supply circuit VC1i as a line selection signal VSCi.
[0042]
The drain / gate voltage supply circuit VC1i receives an accumulation enable signal SDI, a read enable signal SDR2, and a clear pulse signal CL in addition to the line selection signal VSCi. The drain-gate voltage supply circuit VC1i selects and outputs a voltage to be applied to the gates and drains of all cells on the corresponding line. That is, the drain / gate voltage supply circuit VC1i supplies the drain voltage VPDi and the gate voltage VPGi to each cell of each line. The details of the drain / gate voltage supply circuit VC1i will be described later.
[0043]
A source voltage supply circuit VC2h (h is any one of 1 to n; the same applies hereinafter) is provided for each column of the matrix. The clear pulse signal CL and the pre-clear gate preset signal PR are input to the source voltage supply circuit VC2h. The source voltage supply circuit VC2h supplies a source voltage VPSh to the sources of all cells in each column. The details of the source voltage supply circuit VC2h will be described later.
[0044]
A source line corresponding to each column is connected to the line memory 9 for accumulation signals and the line memory 10 for offset signals via a switch SW1h to which a line memory data load signal LOAD is input.
The accumulation signal line memory 9 includes a selection circuit HSh corresponding to each column. Each selection circuit HSh includes a charge storage capacitor C2, a read switch SW21, a reset switch SW22, and an output switch SW23.
[0045]
The offset signal line memory 10 includes a selection circuit HNh corresponding to each column. Each selection circuit HNh includes a charge storage capacitor C3, a read switch SW31, a reset switch SW32, and an output switch SW33. When the storage signal line memory data load signal LOADS is input to the storage signal line memory 9, SW21 is turned on, and a voltage corresponding to the amount of light is applied from each source line to the capacitor C2. Electric charges corresponding to the voltage are accumulated. The pixel signals for one line selected by the read line shift register 5 are stored in the accumulation signal line memory 9 in accordance with LOADS.
[0046]
The storage signal line memory reset signal RESS to the storage signal line memory 9 is a signal for setting the capacitor C2 to a predetermined voltage VMPR immediately before reading the signal. The voltage VMPR is supplied to the capacitor C2 from the power supply 35 generated by the regulator 8 by turning on the reset switch SW22.
[0047]
Then, the switches SW23 of the respective selection circuits HSh of the accumulation signal line memory 9 are sequentially turned on by the selection signal HSCANh from the horizontal shift register 11. Since the turned-on SW 23 outputs a voltage corresponding to the electric charge accumulated in the capacitor C2, the pixel signals of one line selected by the read-out line shift register 5 are sequentially output as the VOUTS signal via the output amplifier 36 via the output amplifier 36. Is output.
[0048]
When the line memory data load signal LOADN for the offset component accumulation signal is input to the offset signal line memory 10, the switch SW31 is turned on, and a voltage corresponding to the offset component is applied from each source line to the capacitor C3. An electric charge corresponding to the voltage is accumulated. The pixel signals for one line selected by the read line shift register 5 are stored in the offset signal line memory 10 in accordance with the offset component accumulation signal line memory data load signal LOADN. The offset signal line memory reset signal RESN to the offset signal line memory 10 is a signal for setting the capacitor C3 to the predetermined voltage VMPR immediately before reading the offset component signal. The voltage VMPR is supplied from the power supply 37 generated by the regulator 8 to the capacitor C3 by turning on the reset switch SW32.
[0049]
Then, the horizontal shift register 11 turns on the switches SW33 of the respective selection circuits HNh of the offset signal line memory 10 in order. Since the turned-on SW 33 outputs a voltage corresponding to the electric charge accumulated in the capacitor C3, the offset component signal of the pixel signal of one line selected by the read line shift register 5 is sequentially output as the VOUTN signal. The signal is output via the amplifier 38. Two voltage analog signals VOUTS and VOUTN from the image sensor LSI1 are input to the difference amplifier circuit 16 of the signal processing LSI2.
[0050]
FIG. 3 is a circuit diagram showing a configuration of the drain-gate voltage supply circuits VC11 to VC1m of FIG. The drain / gate voltage supply circuit VC1i includes a NAND circuit, an inverter circuit, and a transistor, and outputs a drain voltage VPD and a gate voltage VPG according to various input signals.
[0051]
A clear pulse signal CL, an accumulation enable signal SDI, and a read enable signal SDR2 are input to each of the drain / gate voltage supply circuits VC1i. , And applied to the drain and gate of each sensor cell.
[0052]
The sensor cell array 3 has the following state. These states are, in detail, “accumulation”, “reset (S)”, “modulation (S)”, “preset”, “clear”, “reset (N)” and “modulation (N)”. An optical image is converted into an electric signal and output by repeating these states. The accumulation enable signal SDI is a low active signal and is a signal indicating an accumulation period. The read enable signal SDR2 is a signal generated based on the signal SDR indicating a period other than the accumulation period, and is a low active signal during modulation, offset modulation, and clearing. Further, the line selection signal VSCi is used for selecting a read line and a clear line, and the clear pulse signal CL is set in a period during which residual charges such as accumulated holes are discharged.
[0053]
In FIG. 3, it is assumed that clear pulse signal CL is at L level and line select signal VSCi is at H level. In this case, the PMOS transistor T1 and the NMOS transistor T2 are turned on, and the PMOS transistor T3 is turned off. Then, the gate voltage VPGi becomes the voltage VCCSGHI or the voltage VCCSGHR. The PMOS transistor T1 is an enhanced type MOS transistor and the NMOS transistor T2 is a depletion type MOS transistor.
[0054]
Conversely, when the clear pulse signal CL is at the H level and the line selection signal VSC is at the L level, the transistors T1 and T2 are turned off and the transistor T3 is turned on. In this case, the gate voltage VPGi is a low level voltage. When the clear pulse signal CL and the line selection signal VSCi are at the H level, the transistors T1, T2, and T3 are turned off, and the gates are in a floating state.
[0055]
When the clear pulse signal CL is at L level or the line selection signal VSC is at L level, the NMOS transistor T5 is turned on. The sources of the transistors T5 in each line are commonly connected to form a COM node. When the transistor T5 is on, the drain of each line is connected to the COM node and enters a floating state. When the transistor T5 is turned on and the accumulation enable signal SDI is at the L level, the PMOS transistor T6 and the NMOS transistor T7 are also turned on, and the drain voltage VPDi becomes the voltage VCCSDI. When the read enable signal SDR2 goes low while the transistor T5 is on, the PMOS transistor T4 also turns on, and the drain voltage VPDi becomes the voltage VCCSDR. When only the transistor T5 among the transistors T4 to T7 is in the ON state, all the drains are connected to the floating COM node and become HiZ.
[0056]
The transistor T1 is supplied with the voltage VCCSGHI when the accumulation enable signal SDI is at the L level, and is supplied with the voltage VCCSGHR when the signal SDR is at the L level.
[0057]
That is, the circuit of FIG. 3 obtains the states shown in Table 1 below. Note that Table 1 shows only the H level and the L level of the signal of interest.

FIG. 4A is a circuit diagram showing a configuration of the source voltage supply circuits VC21 to VC2n in FIG. The source voltage supply circuit VC2h includes a capacitor and a transistor, and outputs a source voltage VPSh according to various input signals.
FIG. 4B shows a circuit for generating the signals S1, S2, S3 and S4 in FIG. 4A.
Each of the source voltage supply circuits VC2h receives the inverted signals S1 to S3 of the clear pulse signal CL and the non-inverted signal S4 of the preset signal PR and uses the supplied VCCSDB and VCCVPS to supply the SOURCE bias voltage shown in FIG. And applies it to the source of each sensor cell.
[0058]
In FIG. 4B, signals S1 to S3 are inverted signals of the clear pulse signal CL, and the non-inverted signal S4 of the preset signal PR is a signal having the same logical level as the gate preset signal PR before clearing. When both the clear pulse signal CL and the pre-clear gate preset signal PR are at L level, the inverted signals S1 to S3 are at H level, and the normal rotation signal S4 of the preset signal PR is at L level. Therefore, the NMOS transistors T11 and T13 are on, the PMOS transistors T12 and T14 are off, and the NMOS transistor T15 is off. That is, in this case, since the transistors T14 and T15 are off, the source voltage supply circuit VC2h does not supply the source voltage. At this point, the voltage value at the point ND1 is at the ground level (GND), and the voltage value at the point ND2 is VCCSDB.
[0059]
When the clear pulse signal CL is at the L level and the gate preset signal PR before clearing is at the H level, the inverted signals S1 to S3 and the normal rotation signal S4 of the preset signal PR are at the H level. Therefore, the transistors T11, T13, T15 are on, and the transistors T12, T14 are off. That is, in this case, the source voltage VPSh becomes the voltage VCCVPS, the voltage value at the point ND1 is the ground level (GND), and the voltage value at the point ND2 is VCCSDB. Therefore, during this time, the capacitor C1 is charged to the voltage VCCSDB.
[0060]
When the clear pulse signal CL is at the H level and the gate preset signal before clearing PR is at the L level, the inverted signals S1 to S3 and the normal rotation signal S4 of the preset signal PR are at the L level. Therefore, the transistors T11, T13, T15 are off, and the transistors T12, T14 are on. That is, in this case, the voltage at the point ND2 becomes the source voltage VPSh. If the voltage of the capacitor C1 is charged to VCCSDB immediately before this case, the ND1 point becomes the voltage VCCSDB by turning on the transistor T12, and the voltage value at the ND2 point becomes VCCSDB × 2.
[0061]
That is, the circuit of FIG.

FIG. 5 is a diagram for explaining a bias voltage applied to the sensor cell.
FIG. 5 shows the voltage values of the gate voltage, source voltage, and drain voltage of each cell in each state. In FIG. 5, “accumulation”, “reset (S)”, “modulation (S)”, “preset”, “clear”, “reset (N)”, and “modulation (N)” from the viewpoint of the bias voltage. Are shown separately for each state.
[0062]
In FIG. 5, GATE is the gate voltage of the cell, and has two states, a selected state and a non-selected state. SOURCE is the source voltage of the cell. DRAIN is a drain voltage of the cell and has two states, a selected state and a non-selected state.
[0063]
First, the case of the accumulation state will be described.
In the state of “accumulation” (hereinafter referred to as accumulation state), all cells in the cell array are set to the selected state, and a voltage having a voltage value of VCCSGHI is applied to the gate. When in the accumulation state, there are no unselected cells. In the accumulation state, the source does not receive the supply of the bias voltage from the source voltage supply circuit VC2h, but since the voltage of VCCSGHI is applied to the gate and the optical signal detection MOS transistor PDTr is turned on, the source / drain In the accumulation state, the source becomes equal to the drain voltage (VCCSDI).
[0064]
Next, the case of the “reset (S)” state (hereinafter, abbreviated as the “RESS state”) will be described.
In the case of the cell in the selected state, in the RESS state, a voltage whose voltage value is Lo (L level) is applied to the gate. In the RESS state, a voltage having a voltage value of VMPR is applied to the source. In the case of the cell in the selected state, in the RESS state, a voltage of Lo is applied to the gate, and the MOS transistor PDTr for detecting an optical signal is turned off. (HiZ).
[0065]
In the case of a cell in a non-selected state, a voltage having a voltage value Lo (L level) is applied to the gate in the RESS state. When a certain cell is in a non-selected state and is in a RESS state, the drain becomes HiZ.
In the state of “modulation (S)” (hereinafter abbreviated as LOADS state), in the case of a cell in a selected state, a voltage having a voltage value of VCCSGHR is applied to the gate. In the case of the selected cell, a voltage having a voltage value of VCCSDR is applied to the drain, and a voltage having a voltage value of (VCCSGHR-VthS) is output to the source. In the LOADS state, it is necessary to apply a bias voltage that satisfies the relationship (VCCSGHR <VCCSDR).
[0066]
In the case of a cell in the non-selected state, in the LOADS state, a voltage having a voltage value of Lo is applied to the gate, and a voltage having a voltage value of VCCSDR is applied to the drain.
Subsequently, the case of the “preset” state (hereinafter, abbreviated as the PR state) will be described.
In the case of the selected cell, in the PR state, a voltage having a voltage value of VCCSGHR is applied to the gate. In the PR state, a voltage having a voltage value of VCCVPS is applied to the source. In the case of the cell in the selected state, in the PR state, the drain has the same voltage as the source because the optical signal detection MOS transistor PDTr is turned on.
[0067]
In addition, in the case of a cell in a non-selected state, in the PR state, a voltage having a voltage value of Lo is applied to the gate, and the drain becomes VCCVPS. T5 turns on the line (= non-selected line) where VSCi is Lo level, each line is connected to the common node (COM node), and the COM node becomes HiZ.
[0068]
In the “clear” state (hereinafter abbreviated as CL state), in the case of a selected cell, a voltage having a voltage value of (VCCSDB × 2) is applied to the source, and the optical signal detection MOS transistor PDTr is turned on. Therefore, the drain has the same voltage as the source. As a result, a voltage having a voltage value of (VCCSGHR + VCCSDB × 2) is applied to the gate.
[0069]
In the case of a cell in a non-selected state, in the CL state, a voltage having a voltage value of Lo is applied to the gate, and a voltage having a voltage value of VCCSDR is applied to the drain.
Next, a case of a “reset (N)” state (hereinafter, abbreviated as a RESN state) will be described.
In the case of the cell in the selected state, in the RESN state, a voltage having a voltage value of Lo is applied to the gate. In the RESN state, a voltage having a voltage value of VMPR is applied to the source. In the case of the cell in the selected state, the drain becomes HiZ in the RESN state.
[0070]
In the case of a cell in a non-selected state, in the RESN state, a voltage having a voltage value of Lo is applied to the gate. In the case of a cell in a non-selected state, the drain becomes HiZ in the RESN state.
Note that while the clear pulse signal CL is at the L level, the NMOS transistor T5 in FIG. 3 is turned on. Therefore, even in the RESS state, the NMOS transistor T5 is turned on and the drain is connected to the COM node. Since the read enable signal SDR2 becomes H level in the RESS state and the RESN state, the PMOS transistor T4 is turned off, and the COM node becomes floating.
[0071]
In the state of “modulation (N)” (hereinafter abbreviated as “LOADN state”), in the case of a selected cell, a voltage having a voltage value of VCCSGHR is applied to the gate. In the LOADN state, a voltage having a voltage value of VCCSDR is applied to the drain, and a voltage having a voltage value of (VCCSGHR-VthN) is output to the source.
[0072]
In the case of a cell in the non-selected state, in the LOADN state, a voltage having a voltage value of Lo is applied to the gate, and a voltage having a voltage value of VCCSDR is applied to the drain.
Similarly to the LOADS state, at the time of LOADN, the drain is connected to the COM node (= HiZ) because T5 in FIG. 3 is turned on.
[0073]
FIG. 6 is a diagram for explaining a read line and a clear line of the sensor.
[0074]
As shown in FIG. 6, in the mxn pixel matrix, each line is sequentially scanned from the first line to the m-th line. The read line is a line from which a signal corresponding to the light amount is read, and the clear line is a line from which charges accumulated in each cell are cleared. Since scanning is performed in order from the first line, holes are generated in each cell of the line cleared based on the clear selection signal in accordance with the amount of light received thereafter. After the clearing, the time until the readout is performed by the readout line selection signal VSBi is the exposure time. The exposure time is proportional to the number dl of lines between the readout line and the clear line, and is set in the shutter speed, that is, in the range of 1H (H indicates the number of horizontal lines; the same applies hereinafter) to mH (or (1 frame + 1H or more). May be changed).
[0075]
FIG. 7 is a timing chart showing the timing of the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC.
The vertical synchronization signal VSYNC is a timing pulse generated for each period t1 and having a time length of t2. The horizontal synchronization signal HSYNC is a timing pulse generated for each cycle t3 and having a time length of t4. The vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC are supplied from the timing generator 26 of the signal processing LSI 2 to the image sensor LSI1.
[0076]
When the vertical synchronization signal VSYNC is supplied, the read line shift register 5 sequentially outputs the selection signal VSBi. Within the period t1 after the supply of the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC is output by the number of lines (= m) of the sensor cell array 3. Then, within the period t4 during which the horizontal synchronization signal HSYNC is being output and during the period when VGUP is L, there is a period during which the above-described operation of reading the signal component, clearing, and reading the offset component is performed. The period in which VGUP is L is set to a predetermined period in the H blanking period. The H blanking period will be described later in detail with reference to FIG.
[0077]
Analog signals VOUTS and VOUTN of n signal components and offset components are output in a period t5 after a period t4 in the period t3.
Next, a circuit configuration of a timing generator (hereinafter, referred to as TG) 13 of the image sensor LSI 1 will be described with reference to FIG.
FIG. 8 is a circuit block diagram showing a configuration of the TG 13 of the image sensor LSI1 of FIG.
[0078]
The TG includes a serial control block 71, a master timing control block 72, a sensor register block 73, a shutter control unit (shutter speed upper limit control unit) 74, a frame control unit 75, an HV counter 76, a vertical scan control block 77, a horizontal scan. A control block 78 and an analog control block 79 are included.
[0079]
The serial control block 71 receives and outputs a 3-wire serial I / F signal which is an interface signal between the serial control block 71 and the register 14 of the signal processing LSI 2.
The master timing control block 72 receives the sensor drive clock SCLK, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC from the TG 26 of the signal processing LSI 2. The clock designation signal CLK_SEL from the signal processing LSI 2 and the standby signal STANDBY are input to the TG 13.
[0080]
The serial control block 71 inputs shutter speed setting data, regulator 8 setting data, system clock information, and the like written in the register 23 of the signal processing LSI 2 as a serial I / F signal. The write address and write strobe signal WR are output and supplied to the sensor register block 73.
[0081]
The sensor register block 73 receives a line shutter speed setting signal, a frame shutter speed setting signal, a frame mode setting signal, a clear pulse width control setting signal, a clear pulse application count setting signal, a gain setting signal, Outputs the regulator voltage setting signal.
On the other hand, the master timing control block 72 outputs a pixel clock, a horizontal reset pulse, a vertical reset pulse, and a reset signal based on the various input signals described above.
[0082]
The shutter control unit (shutter speed upper limit control unit) 74 receives a line shutter speed setting signal and a frame shutter speed setting signal from the sensor register block 73, and outputs line shutter speed data and frame shutter speed data as outputs.
[0083]
The frame control unit 75 receives the pixel clock, the vertical reset pulse, and the reset signal from the master timing control block 72 and the standby signal STANDBY, and outputs a frame count value, frame control data, and valid (VALID) control as outputs. Output a signal.
The HV counter 76 receives the pixel clock, the horizontal reset pulse, the vertical reset pulse, and the reset signal from the master timing control block 72, and outputs a line count value and a pixel count value as outputs.
[0084]
The vertical scan control block 77 receives line shutter speed data and frame shutter speed data from the shutter control unit 74, a frame count value, frame control data, and a valid (VALID) control signal from the frame control unit 75 as inputs. A clear pulse width control setting signal and a clear pulse application count setting signal from the sensor register block 73, a pixel clock and reset signal from the master timing control block 72, a clock designation signal CLK_SEL, and a line count from the HV counter 76 A value and a pixel count value are entered.
[0085]
The vertical scan control block 77 outputs the clear line shift data AV, the clear line shift clock VCLK_ASR, the clear line shift register reset signal VSFRA_RST, the clear line selection enable signal CLS, the read line shift data BV, and the read line shift. A clock VCLK_BSR, a read line shift register reset signal VSFRB_RST, a read line select enable signal VSM, an all-line select signal VGUP during accumulation, an accumulation enable signal SDI, a read enable signal SDR, a gate preset signal PR before clear, and a clear pulse CL are output. .
[0086]
The horizontal scan control block 78 has, as inputs, a valid (VALID) control signal from the frame control unit 75, a line count value and a pixel count value from the HV counter 76, and a clear pulse from the sensor register block 73. A width control setting signal, a pixel clock and a reset signal from the master timing control block 72, and a clock designation signal CLK_SEL are input.
[0087]
The horizontal scan control block 78 outputs line memory selection shift data AH, line memory selection shift clock CIN, line memory selection enable signal HSC_CK, accumulation signal line memory reset signal RESS, accumulation signal line memory data load signal LOADS. , An offset line memory reset signal RESN, and an offset line memory data load signal LOADN.
[0088]
The clock designation signal CLK_SEL is a signal indicating the level of the frequency of the system clock signal CLKIN. The CLK_SEL is supplied to the vertical scan control block 77 and the horizontal scan control block 78. In each of the control blocks 77 and 78, the output timing of various sensor drive signals output from each block 77 and 78 can be controlled in accordance with the H and L levels of the clock designation signal CLK_SEL.
[0089]
The analog control block 79 includes a valid (VALID) control signal from the frame control unit 75, a line count value and a pixel count value from the HV counter 76, a gain setting signal from the sensor register block 73, and a standby signal. STANDBY is input and outputs an analog amplifier gain control signal, an amplifier drive clock CDL, and a standby control signal as outputs.
[0090]
A valid (VALID) control signal from the frame control unit 75 is output from the TG 13 to the signal processing LSI 2 as a VALID signal.
The regulator voltage setting signal from the sensor register block 73 and the standby control signal from the analog control block 79 are input to the sensor drive bias generation regulator 8 of the image sensor LSI 1 in FIG.
[0091]
The analog amplifier gain control signal and the amplifier drive clock CDL from the analog control block 79 are used as control signals for the output amplifier 12 of the image sensor LSI 1 in FIG.
[0092]
FIG. 9 is a timing chart showing signals for controlling the photoelectric conversion of the sensor cell array 3. The sensor cell array 3 repeats each state of “accumulation”, “reset (S)”, “modulation (S)”, “preset”, “clear”, “reset (N)”, and “modulation (N)”. The optical image is converted into an electric signal and output. FIG. 9 shows the state of the signal in each of these states. The sensor cell array 3 operates at a predetermined frame rate using the vertical synchronization signal VSNYC and the horizontal synchronization signal HSYNC in FIG. 7 as a unit time.
[0093]
In the example of FIG. 9, in a certain line count signal ROWCT, HSYNC is at the L level from 1 to 80 for the pixel clock signal PXLCT, and LOADS (reset (S) + modulation (S)) for PXLCT from 5 to 22. In the state, PXLCT from 27 to 44 is assigned to the CL (preset + clear) state, and PXLCT from 45 to 63 is assigned to the LOADN (reset (N) + modulation (N)) state.
[0094]
Each control signal is generated and output by the TG 13. The TG 13 is configured by a logic circuit. The logic circuit can be automatically designed by using a design system using HDL (Hardware Description Language: hardware description language) such as Verilog-HDL or VHDL.
[0095]
First, the accumulation state will be described.
A period other than a predetermined period (the fifth pixel to the 63rd pixel in FIG. 9) in the H blanking period shown in FIG. 7 is an accumulation period. During the accumulation period, all the pixels are in the accumulation state. During this period, the accumulation-time all-line selection signal VGUP is at the H level, and the accumulation enable signal SDI and the clear pulse signal CL are at the L level. As shown in FIG. 2, when all the line selection signals VGUP at the time of accumulation become H level, all the line selection signals VSCi become H level. , And the gate voltage VPGi becomes VCCSGHI. Further, the drain voltage VPDi becomes the voltage VCCSDI. Also, during this period, the gate preset signal PR before clearing is also at the L level, and the source voltage supply circuit VC2h does not supply the source voltage as shown in Table 2 showing the operation of the source voltage supply circuit VC2h. In this case, the sources of all the cells in the cell array are turned on by the optical signal detection MOS transistor PDTr and are equal to the drain voltage.
[0096]
In the fifth pixel of the H blanking period, the accumulation period ends, and signal reading starts. During the signal reading period (LOADS, CL, and LOADN periods), accumulation of holes based on the amount of received light is continued, but each cell is set to a set value different from the accumulation period. In a period for signal reading, each cell is set to an individual set value on a clear line, a read line, or a non-selected line.
[0097]
First, the reset (s) state will be described. As shown in FIG. 9, even during this period, settings common to all cells are performed.
As shown in FIG. 9, the clear pulse signal CL and the pre-clear gate preset signal PR are at L level, and the source voltage supply circuit VC2h does not supply the source voltage. During this period, the storage signal line memory reset signal RESS becomes high active, the switch SW22 in FIG. 2 turns on, and the terminal voltage of the capacitor C2 constituting the line memory is charged to VMPR. Further, the line memory data load signal LOADS for accumulation signals and the line memory data load signal LOAD also become high active, the switches SW21 and SW11 are turned on, and the source line is initialized with the voltage VMPR.
[0098]
On the other hand, during accumulation, all the line selection signals VGUP change from H to L, and all line selection signals VSCi change to L level. Therefore, as shown in Table 1, all the gate voltages VPSGi are at the L (GND) level. Further, since the accumulation enable signal SDI is at the H level and the SDR2 is also at the H level, as shown in Table 1, T5 in FIG. 3 is turned on, and the drains of all the cells are connected in common ( COM node), and the COM node enters the Hiz state.
[0099]
Next, the modulation (s) state will be described.
As shown in FIG. 9, CL and PR maintain the L level, and the source voltage supply circuit VC2h does not supply a voltage to the source line. An output corresponding to the voltage value set for each cell is output via the source line. That is, for the clear line and the non-selected line, the line selection signal VSCi remains at the L level, and the gate voltage is at the L (GND) level. Since the read enable signal SDR2 is also at the L level, the drain voltage VPDi becomes VCCSDR.
[0100]
For the read line, the line selection signal VSCi is at the H level. Since the clear pulse signal CL and the signal SDR are at the L level, the gate voltage VPGi is VCCSGHR. The drain voltage VPDi is VCCSDR. As a result, a voltage (VCCSGHR-VthS) appears in the source voltage VPSi. Note that VthS changes according to the accumulated holes. The source line voltage (VCCSGHR-VthS) is accumulated in each capacitor C2 constituting the line memory via the switch SW21.
[0101]
Next, for the correlation double sampling processing, a CL state for removing (clearing) holes accumulated in each cell of the read line is set. In order to remove holes, it is necessary to apply an extremely high voltage to the gate. A preset state is set before the clear state, and a high voltage is obtained using a voltage doubler circuit. Note that each cell on the clear line is cleared simultaneously with the clearing of the read line.
[0102]
First, in the preset state, the line selection signal VSCi is at the H level for the read line and the clear line. Since the clear pulse signal CL and the signal SDR are at the L level, the gate voltage VPGi is VCCSGHR. Note that the gate voltage of the non-selected line is at the L (GND) level because the line selection signal VSCi is at the L level.
[0103]
Further, since the clear pulse signal CL is at the L level and the gate preset signal PR before clear is at the H level, as shown in Table 2, the voltages VPSh of all the source lines are reset to the voltage VCCVPS (for example, 0 V). Further, the capacitor C1 in FIG. 4 is charged with the voltage VCCSDB, and the point ND2 becomes the voltage VCCSDB. Since the accumulation enable signal SDI and the read enable signal SDR2 are at H level, the drain of the optical signal detection MOS transistor PDTr is turned on, and the drain has the same potential as the source.
[0104]
Next, in the clear state, the pre-clear gate preset signal PR changes from H level to L level, and the clear pulse signal CL changes from L level to H level. In this case, as shown in Table 2, the source line changes to VCCSDB × 2. As for the read line and the clear line, since the clear pulse signal CL and the line selection signal VSCi are at the H level, the gates are in a floating state as shown in Table 1. Therefore, the gate voltage VPGi becomes (VCCSDB × 2 + VCCSGHR) due to the coupling capacitance between the source and the gate. The drain of the optical signal detection MOS transistor PDTr is turned on to have the same potential as the source as in the preset state.
[0105]
On the other hand, for the non-selected line, the gate voltage VPDi remains at the L (GND) level, and the drain voltage VPDi becomes VCCSDR because the transistor T4 is turned on.
[0106]
Next, the state shifts to the modulation (N) state via the reset (N) state. In the reset (N) state and the modulation (N) state, signals substantially similar to the reset (s) state and the modulation (s) state are set, respectively. That is, in the reset (N) state, the offset line memory reset signal RESN and the offset line memory data load signal LOADN are high instead of the accumulation signal line memory reset signal RESS and the accumulation signal line memory data load signal LOADS, respectively. Become active. As a result, the switch SW32 is turned on, and the capacitor C3 constituting the noise reading line memory is charged to the VMPR. Further, the switches SW31 and SW11 are turned on, and the source line is initialized with the voltage VMPR.
[0107]
In the modulation (N) state, the clear pulse signal CL and the pre-clear gate preset signal PR are at the L level, and the source voltage supply circuit VC2h does not supply a voltage to the source line. For the clear line and the non-selected line, the line selection signal VSCi is at the L level, and the gate voltage VPGi is L (GND). Since the read enable signal SDR2 is also at the L level, the drain voltage VPDi becomes VCCSDR.
[0108]
For the read line, the line selection signal VSCi is at the H level. Since the clear pulse signal CL and the signal SDR are at the L level, the gate voltage VPGi is VCCSGHR. The drain voltage VPDi is VCCSDR. As a result, a voltage (VCCSGHR-VthN) appears in the source voltage VPSh. The voltage appearing at the source corresponds to the offset component since it was set to the clear state immediately before. The source line voltage (VCCSGHR-VthN) is accumulated in each capacitor C3 constituting the line memory via the switch SW31.
[0109]
Thus, the signal component is stored in the capacitor C2, and the offset component is stored in the capacitor C3. When the switches SW23 and SW33 are sequentially turned on by the selection signal HSCANh from the horizontal shift register 11, the voltages accumulated in the capacitors C2 and C3 are output as VOUTS and VOUTN via the output amplifiers 36 and 38, respectively. .
[0110]
By the way, as described above, in FIG. 1, in the signal processing LSI 2, the luminance is measured by the luminance photometric logic circuit 22 by integrating the data of all the green (G) pixels for one frame period supplied from the ADC 19. I do. The brightness control logic circuit 21 adjusts the brightness of the image by supplying a gain control signal to the PGA 18 based on the measurement result, and writes the shutter speed data into the register 23.
[0111]
Therefore, in the embodiment of the present invention, as described above, the average illuminance of the image is calculated, the shutter speed and the gain of the amplifier are controlled in accordance with the calculated value, and the sensor pixel is controlled in accordance with the calculated value. The configuration is such that the applied bias voltage can be controlled.
[0112]
The bias voltage setting of the sensor pixel may be (1) set by a CPU (not shown), (2) set by the signal processing LSI 2, (3) automatically set in the image sensor LSI 1 according to the shutter speed and gain. .
[0113]
For example, in the register 14 in the image sensor LSI 1, a plurality of sets (tables) of bias voltage values corresponding to a plurality of brightness levels are prepared in order to perform the setting.
[0114]
FIG. 10 shows a plurality of sets of bias voltage values corresponding to a plurality of levels of brightness as a plurality of tables A, B, C,. The bias voltages are VREF (signal reference voltage), VMPR, VCCSDB, VCCSGHI, VCCSGHR, VDDSDR, VCCSDI, and VPS. The contents of the bias values indicated by these English characters are described in FIGS. 5 and 9. FIG. 10 shows, as an example, the values in Table A of the bias voltage values at the time of standard setting (when the brightness is standard). That is, in Table A, VREF = 2.0V, VMPR = 1.0V, VCCSDB = 2.5V, VCCSGHI = 2.2V, VCCSGHR = 3.0V, VCCSDR = 3.3V, VCCSDI = 1.0V, VCCVPS = 0V.
[0115]
Note that the relative magnitude relationship between the above-described voltage values of the VMPR, VCCSDB, VCCSGHI, VCCSGHR, VCCSDR, VCCSDI, and VCCVPS in the table A at the time of the standard setting is shown in the other tables B, C,. Are maintained in the relationship between the respective bias voltage values.
[0116]
As a means for setting in the register 14, the data table as shown in FIG. 10 can be set by transmitting and receiving between the registers 23 and 14 arranged in the signal processing LSI 2 and the image sensor LSI 1, respectively.
[0117]
That is, since the register 14 in the image sensor LSI 1 and the register 23 in the signal processing LSI 2 store the same data, when the content of one of the registers is changed, the register 14 is connected via the 3-wire serial interface 15. Thus, the contents of the other register are also changed. Therefore, when data of a plurality of bias value tables corresponding to a plurality of steps of brightness applied to each pixel of the sensor cell array 3 are written in the register 23 in the signal processing LSI 2, the data is further converted to a three-wire serial data. The data is written to the register 14 in the image sensor LSI 1 via the interface 15. In the image sensor LSI 1, the TG 13 reads the bias value table corresponding to the brightness from the data of the plurality of bias value tables set in the register 14 and controls the regulator 8. It is possible to output a voltage.
[0118]
For example, regarding the setting of the bias value at the time of clearing, conventionally, the bias voltage at the time of clearing is constant (fixed) regardless of whether it is bright or dark. As it becomes conspicuous, a high bias voltage is applied to drive out residual charges. That is, when dark, the bias voltage value at the time of clearing can be set higher than the standard time based on the brightness result. Thereby, the S / N ratio can be improved and the image quality can be improved.
[0119]
According to the embodiment described with reference to FIG. 10, it is possible to secure the dynamic range and the sensitivity by performing the optimal drive bias control according to the brightness.
[0120]
According to the embodiment of the present invention described above, a MOS-type solid-state imaging device using a threshold voltage modulation method and a signal processing unit that performs signal processing on the output of the solid-state imaging device and measures the brightness of a captured image are included. In the image processing apparatus, by varying the bias value applied to each pixel of the solid-state imaging device according to the measured brightness, it is possible to perform appropriate bias value setting according to the brightness at the time of shooting, Good image quality can be obtained. Both the securing of the dynamic range and the securing of the sensitivity can be set with appropriate values.
[0121]
In the above embodiment, the solid-state imaging device has been described by taking a threshold voltage modulation type MOS image sensor as an example. However, the present invention is not limited to the threshold voltage modulation type MOS image sensor. It goes without saying that the sensor can be applied.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of an image sensor LSI according to the embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a drain / gate voltage supply circuit according to the embodiment of the present invention.
FIG. 4 is a circuit diagram showing a configuration of a source voltage supply circuit according to the embodiment of the present invention.
FIG. 5 is a diagram for explaining a bias voltage applied to a sensor cell according to the embodiment of the present invention.
FIG. 6 is a diagram illustrating a read line and a clear line of a sensor according to the embodiment of the present invention.
FIG. 7 is a timing chart showing timings of a vertical synchronization signal and a horizontal synchronization signal according to the embodiment of the present invention.
FIG. 8 is a circuit block diagram showing a configuration of a timing generator of the image sensor LSI according to the embodiment of the present invention.
FIG. 9 is a timing chart for explaining the state of each signal in each state during the H blanking period according to the embodiment of the present invention.
FIG. 10 is an explanatory diagram illustrating a table of a plurality of bias voltage values provided according to brightness according to the image processing apparatus of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Image sensor LSI, 2 ... Signal processing LSI, 3 ... Sensor cell array, 6 ... Vertical drive circuit, 8 ... Regulator, 9 ... Line memory for accumulation signals, 10 ... Line memory for offset signals, 13, 26 ... Timing generator, 14, 23 ... register, 15 ... 3-wire serial interface

Claims (6)

A matrix-type solid-state imaging device in which a plurality of unit pixels each including a photodiode and a transistor for detecting an optical signal are arranged,
A signal processing unit that performs signal processing on the output of the solid-state imaging device and outputs the image signal, and a signal processing unit that includes a unit that measures the brightness of an image captured by the solid-state imaging device.
Means for varying a bias value applied to each pixel of the solid-state imaging device according to the brightness measured by the signal processing unit;
An image processing apparatus comprising: The image processing apparatus according to claim 1, wherein the solid-state imaging device is a threshold voltage modulation type MOS solid-state imaging device. 3. The image according to claim 1, wherein the variable unit sets a bias value according to the brightness in a register, and changes the bias value by reading the bias value according to the measured brightness. Processing equipment. 3. The variable unit according to claim 1, wherein the variable unit writes the bias value according to the brightness in an external nonvolatile memory and reads the bias value according to the measured brightness. An image processing apparatus according to claim 1. Matrix-type solid-state imaging device in which a plurality of unit pixels each including a photodiode and a transistor for detecting an optical signal are arranged; and signal processing for processing the output of the solid-state imaging device and measuring the brightness of a captured image. A processing method of an image processing apparatus including a unit,
A processing method for an image processing apparatus, wherein a bias value applied to each pixel of the solid-state imaging device is varied according to the measured brightness. 6. The processing method according to claim 5, wherein the solid-state imaging device is a threshold voltage modulation type MOS solid-state imaging device.

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