JP2004221952A - Transmission method and apparatus - Google Patents

Abstract

A transmission method and apparatus for preventing a normal asynchronous packet from being discarded due to a clock deviation are provided.
A transmission method for encapsulating a signal received from an asynchronous network, transmitting the encapsulated signal between transmission devices of a synchronous network, and then transmitting the signal to the asynchronous network. The clock information measured in the above is mapped to the overhead of the signal transmitted in the synchronous network and transmitted, and the clock information is extracted from the overhead of the signal transmitted in the synchronous network, and is transmitted to the asynchronous network based on the extracted clock information. Adjust the clock frequency of the signal.
[Selection] Fig. 9

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a transmission method and apparatus, and more particularly, to a transmission method and apparatus for transmitting a signal received from an asynchronous network between transmission apparatuses of a synchronous network and then transmitting the signal to the asynchronous network.
[0002]
[Prior art]
2. Description of the Related Art In recent years, methods for transmitting asynchronous packets such as Ethernet (registered trademark) frames and IP packets over a long distance with high quality using a highly reliable SONET (Synchronous Optical Network) network have become widespread (for example, Patent Documents). 1).
[0003]
As a well-known technique, a transmission device having an EOS (Ethernet (registered trademark) Over SONET) / POS (Packet Over SONET) function converts an asynchronous packet received from an asynchronous network such as a LAN into an RFC 1662 (PPP in HDLC like framing). Encapsulation using such standards as standard, mapping to SONET frame and carrying it on SONET for long-distance transmission of the packet, and converting the encapsulated asynchronous packet to an asynchronous packet by a transmission device with EOS / POS function The data is transmitted to an asynchronous network such as a LAN.
[0004]
Originally, since Ethernet (registered trademark) is an asynchronous network, a clock of an asynchronous packet receiving unit that receives an asynchronous packet and transmits it to SONET, and a clock of an asynchronous packet transmitting unit that receives SONET and transmits it to the asynchronous network A clock error of ± 50 ppm to ± 100 ppm is allowed for the frequency of ８０ in the standard defined by IEEE802.3. Therefore, when the clock frequency of the received data in the asynchronous packet receiving unit is faster than the clock frequency of the asynchronous packet transmitting unit, data may be lost due to a delay in transmission.
[0005]
FIG. 1 shows a transmission method using a conventional transmission device having an EOS / POS function, and shows a signal flow in only one direction. In FIG. 1, an asynchronous communication device 11 transmits an asynchronous packet to a SONET network. The transmission device 12 receives the asynchronous packet, encapsulates it, and sends it out to the SONET network. The transmission device 13 converts the encapsulated asynchronous packet transmitted from the SONET network again into an asynchronous packet and sends out the packet to the asynchronous network. The asynchronous communication device 14 receives an asynchronous packet from the SONET network through the transmission device 13.
[0006]
The asynchronous communication device 11 uses an oscillator that outputs a fixed frequency f1, and all data transmitted at that frequency is transmitted by the transmission device 12 to the SONET network. Assuming that a sufficient band is secured in the SONET network, the data rate of the Ethernet (registered trademark) data reaching the transmission device 13 reflects the frequency created by the asynchronous communication device 11.
[0007]
In the transmission device 13, an oscillator that outputs a fixed frequency f2 is used. When f1> f2, the transmission data rate in the transmission device 13 cannot catch up with the data rate received from the asynchronous communication device 11, and the transmission The normal asynchronous packet was discarded in the device 13.
[0008]
Closely speaking only for data transmission / reception of the asynchronous network, it is possible to cope with the flow control described in IEEE802.3. However, when transmitting over a long distance SONET network, the control is not always effective. , The asynchronous packet discard state described above may be sufficient.
[0009]
FIG. 2 is a diagram for explaining a rescue method when data is lost. In the figure, an asynchronous communication device 21 transmits an asynchronous packet directed to a SONET network. The transmission device 22 receives the asynchronous packet, encapsulates it, and sends it out to the SONET network. The transmission device 23 converts the encapsulated asynchronous packet transmitted from the SONET network again into an asynchronous packet and sends it out to the asynchronous network, and is a device that actually discards the asynchronous packet. The asynchronous communication device 24 receives an asynchronous packet from the SONET network.
[0010]
In FIG. 2, the numbers 1 to 4 indicate a sequence when data is discarded. The asynchronous packet transmitted with the circled number 1 is discarded in the transmission device 23. At this time, a response timeout indicated by a circled number 2 usually occurs because a response signal that should return in the upper layer of the transmission source does not arrive within a specified time, and the transmission source recognizes that the data has been discarded. .
[0011]
Next, the transmission source compensates for the discarded data by retransmitting the data with the number 3 in a circle. If this data arrives at the destination without being discarded on the route, a response with a circled number 4 is returned to the transmission source, and this sequence is used to rescue the data loss.
[0012]
[Patent Document 1]
JP 2001-274824 A
[0013]
[Problems to be solved by the invention]
However, with the conventional method, when data is discarded, the same data must be transmitted twice, and the source must wait for a response timeout to confirm that the data has not reached the destination. Rather, it has a significant effect on transmission efficiency, especially when transmitting over long distances. Furthermore, depending on the type of the host application, data loss cannot be actually tolerated, and there is a problem that if all the transfer data has not completely arrived, all procedures must be executed again. .
[0014]
Further, when controlling the clock frequency of the asynchronous packet transmission unit, the transmission clock is controlled to an unintended state due to a sudden error in the SONET transmission network. Further, in controlling the clock frequency in the asynchronous packet transmitting unit, if the transmission clock is rapidly changed, there arises a problem that the asynchronous communication device cannot follow the clock.
[0015]
Furthermore, by gently controlling the fluctuation of the transmission clock, a fixed amount of data can be stored in the buffer of the asynchronous packet transmitting unit even in a steady state in which the clock frequency of the asynchronous packet transmitting unit is synchronized with the clock frequency of the asynchronous packet receiving unit. This causes a problem that the data is accumulated and the residence time of data is increased.
[0016]
The present invention has been made in view of the above points, and has as its object to provide a transmission method and apparatus capable of preventing normal asynchronous packets from being discarded due to clock deviation.
[0017]
[Means for Solving the Problems]
According to the present invention, clock information obtained by measuring a clock frequency of a signal received from an asynchronous network at a timing of a reference clock of a synchronous network is mapped to an overhead of a signal transmitted on the synchronous network, and transmitted. By extracting the clock information from the overhead of the signal transmitted in the network, by adjusting the clock frequency of the signal transmitted to the asynchronous network based on the extracted clock information,
The clock frequency of the signal transmitted to the asynchronous network is equal to or higher than the clock frequency of the signal received from the asynchronous network, and normal asynchronous packets can be prevented from being discarded.
[0018]
According to a second aspect of the present invention, there is provided a receiving clock measuring unit for measuring a clock frequency of a signal received from an asynchronous network at a timing of a reference clock of the synchronous network to obtain clock information, and transmitting the clock information over a synchronous network. Mapping means for mapping to the overhead of the signal
The invention according to claim 3 is a clock information extracting means for extracting clock information of the asynchronous network from overhead of a received signal, and a clock frequency of a signal transmitted to the asynchronous network based on the extracted clock information. The invention according to claim 1 can be realized by having the clock frequency adjusting means for adjusting the clock frequency.
[0019]
The invention according to claim 4 maps clock information to overhead of a plurality of paths transmitted in a synchronous network,
Further, according to a fifth aspect of the present invention, the clock information of the asynchronous network is extracted from the received overheads of the plurality of paths, and the majority of the plurality of clock information extracted from the overheads of the plurality of paths is determined. Providing the clock information selecting means for selecting the clock information and supplying the clock information to the clock frequency adjusting means enables more reliable transmission of the clock information.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0021]
FIG. 3 is a block diagram for explaining the principle of mapping the clock information of the receiving unit to the SONET frame, and shows only a part of the asynchronous packet receiving unit that obtains the clock deviation.
[0022]
In the figure, a clock extracting unit 30 performs clock data recovery (CDR) from an asynchronous packet input from the LAN by a normal method, and extracts a LAN clock. When the LAN is, for example, Gigabit Ethernet (registered trademark), a clock provided by a standard interface such as GMII (Gigabit Media Independent Interface) is used, and its frequency is centered on 125 MHz.
[0023]
The clock measuring unit 32 measures a clock deviation of the LAN clock extracted from the LAN based on, for example, 8 kHz which is a SONET reference clock. The counter 33 in the clock measuring unit 32 counts the LAN clock supplied in the SONET reference clock cycle.
[0024]
The subtractor 34 subtracts a reference value as a standard count value from the count value of the counter 33. For example, if the SONET and the LAN have no deviation from the standard frequency, 8 kHz is counted at 125 MHz, the reference value is 15625, and if there is a deviation of +100 ppm, the expected value 152626.5625 is counted, The expected value is 1.5625. The result of subtraction from the reference value by the subtractor 34 is obtained as an integer value of ± 2 or less each time.
[0025]
The shift register 35 has, for example, a 64-stage shift register and holds the past 64 subtraction results. The adder / subtractor 36 adds the output of the adder / subtractor 36 and the subtractor 34, and subtracts the output of the subtractor 34 delayed by the shift register 35 to obtain a total of 64 deviations in the past. For example, in the case of Gigabit Ethernet (registered trademark), the result is obtained as a deviation value in ppm as it is.
[0026]
When calculating the deviation of 100Base-TX of Fast Ethernet (registered trademark), for example, a reference value is set to 3125 using a 25 MHz clock of MII (Media Independent Interface), and a 320-stage shift register is prepared. To obtain a deviation value in ppm.
[0027]
The POH mapping unit 38 maps the LAN clock deviation information calculated as described above as clock information to a POH (Path Overhead) area of the SONET frame. In this way, it is possible to map the clock deviation information at the receiving unit to the SONET frame.
[0028]
FIG. 4 is a block diagram for explaining the principle of adjusting the transmission clock based on the clock information of the receiving unit mapped to the SONET frame, and shows only a part of adjusting the clock of the asynchronous packet transmitting unit.
[0029]
In the figure, a clock information extracting unit 40 extracts LAN clock deviation information as clock information mapped to the POH area of the SONET frame. VCXO (voltage controlled crystal oscillator) 42 changes the frequency according to the control voltage. The clock measuring unit 44 has the same configuration as the clock measuring unit 32 used in the asynchronous packet receiving unit, and measures the frequency of the clock output from the VCXO 42 of the asynchronous packet transmitting unit based on the SONET reference clock. That is, the VCXO42 output clock supplied in the SONET reference clock cycle is counted and subtracted from the reference value, the adder / subtractor output and the subtraction output are added, and the delayed subtraction output is subtracted to obtain the past 64 deviations. Get the sum. The frequency to be measured may be centered at 125 MHz, if necessary, using a clock provided by a standard interface such as GMII inside the transmission unit 86, for example.
[0030]
The comparison control unit 46 determines the deviation information (transmission end deviation) that is the measurement result of the clock (output of the VCXO 42) generated by the asynchronous packet transmission unit and the asynchronous packet reception unit side transmitted from the clock information extraction unit 40. Is compared, and if the clock generated by the asynchronous packet transmission unit is slow, a control voltage for adjusting the transmission clock to increase the clock is generated and supplied to the VCXO 42. I do. The clock output from the VCXO 42 is supplied from the terminal 48 to the transmission circuit unit of the asynchronous packet transmission unit.
[0031]
In this way, the clock frequency of the asynchronous packet receiving unit and the clock frequency of the asynchronous packet transmitting unit can be matched based on the SONET reference frequency for which frequency synchronization is guaranteed as a SONET synchronous network.
[0032]
If the clock deviation information extracted by the clock information extraction unit 40 indicates information outside the IEEE 802.3 standard, the comparison control unit 46 sets the data as invalid data, and the control voltage for adjusting the transmission clock is the previous voltage. Is provided to the comparison control unit 46.
[0033]
Further, in the comparison control unit 46, an upper limit value and a lower limit value are set in advance, and when the result obtained by subtracting the reception end deviation from the transmission end deviation exceeds the upper limit value, the output is set to the upper limit value, and the output is lower than the lower limit value. In such a case, a limiter function for setting the output to the lower limit may be provided. This function is realized by a simple comparison circuit.
[0034]
In this way, it is possible to prevent the transmission clock from becoming out of the IEEE802.3 standard and keep the clock of the asynchronous packet transmission unit so as not to hinder the normal operation of the asynchronous communication device that receives the asynchronous packet from the SONET network. It becomes.
[0035]
Further, the comparison control unit 46 holds the clock deviation information extracted by the clock information extraction unit 40 a plurality of times in the comparison control unit 46, compares it with the previous and next deviation information, and discards the information if there is a sudden change. 46. The comparison control unit 46 generates a control voltage to be applied to the VCXO 42 by using the temporally intermediate data of the held deviation information.
[0036]
This avoids a sudden change in the transmission clock. The above function may be realized by digital signal processing, but in general, the control voltage may be analogly smoothed by a high-frequency rejection filter. In FIG. 5, a broken line indicates a comparison operation result which is a difference between the extracted clock deviation information (reception end deviation) in the comparison control unit 46 and deviation information (transmission end deviation) which is a measurement result of the output clock of the VCXO 42, The smoothed control voltage is shown by a solid line.
[0037]
By doing so, it is possible to keep the clock fluctuation of the asynchronous packet transmitting unit gradual so as not to hinder the normal operation of the asynchronous communication device that receives the asynchronous packet from the SONET network.
[0038]
FIG. 6 is a block diagram for explaining the principle of adjusting the transmission clock based on the amount of stored data. In the figure, a buffer 50 is a transmission buffer provided in an asynchronous packet transmitting unit, which holds data to be transmitted, and passes transmittable data to the asynchronous packet transmitting unit.
[0039]
The buffer management unit 52 controls the writing and reading of data to and from the buffer 50, monitors the usage rate of the buffer 50, and controls the clock of the asynchronous packet transmission unit according to the amount of data stored in the buffer 50. The control voltage VF to the VCXO 54 that generates
[0040]
When the VCXO 54 has a characteristic of 100 ppm / V at VF = 1.65 V, for example, the control voltage VF is generated using, for example, equation (1).
[0041]
VF = 1.65 + (buffer usage rate) / 100 (1)
When the buffer usage rate is 10%, the control voltage becomes 1.75 V, a clock that is 10 ppm earlier is generated, and acts to reduce the usage rate of the buffer 50. In this way, the transmission frequency of the asynchronous packet can be controlled according to the usage rate of the buffer 50.
[0042]
FIG. 7 is a block diagram for explaining the principle of transmitting the clock information of the receiving unit using the virtual concatenation (VC). In the figure, a VC mapping section 60 is provided in an asynchronous packet receiving section, and a plurality of POH mapping sections 62 are provided. ₁ To 62n. Multiple POH mapping units 62 ₁ 3 to 62n each has the same configuration as the POH mapping unit 38 shown in FIG. 3, and maps the LAN clock deviation information supplied from the clock measuring unit 32 to the POH area of each path of the VC.
[0043]
The VC path terminating unit 64 is provided in the asynchronous packet receiving unit, and includes a plurality of clock information extracting units 66. ₁ ６６66n. Clock information extraction unit 66 ₁ 4 to 66n have the same configuration as the clock information extraction unit 40 shown in FIG. 4, extract the receiver clock deviation information mapped to the POH area of each path of the VC, and supply it to the clock information selection unit 68.
[0044]
The clock information selecting unit 68 includes a clock information extracting unit 66 ₁ Ｎ66n, a sudden value and an abnormal value are removed from a plurality of pieces of clock deviation information supplied from each of them, and the most correct clock deviation information is selected by majority decision of remaining clock deviation information.
[0045]
The detection method of the sudden value and the abnormal value is, for example, in the case of monitoring at five stages, in order to select the n-th deviation information of each path, the n + 2, n + 1, and n-1 times of the n-th deviation information are selected. , N−2 times are calculated. The maximum value of this difference is detected, and if the difference from the (n-1) -th time is the largest, the n-th data is discarded and the (n-1) -th data is used. This function can be constituted by a subtractor, a maximum value judgment circuit and a coincidence comparison circuit.
[0046]
After this result is collected for each path of the VC, a majority decision is made. Since the clock deviation information of the same value should be mapped to all paths, the majority decision is simplified, the coincidence detection of n / 2 or more paths is performed only for all paths, and even if there is at least one coincident information, For example, the information is adopted as a majority decision result.
[0047]
FIG. 8 shows one embodiment of the majority decision. FIG. 8A shows the deviation values (clock deviation information) obtained from the eight paths, and an error has occurred in path # 3, which results in different deviation values. In this example, if at least five paths have the same value, majority logic is established. Therefore, for example, three stages of majority circuits are prepared, and a group of paths # 1 to # 5 (representation is path # 1) shown in FIG. 8B and paths # 1, # 2, and # 6 shown in FIG. Match detection is performed for groups # 8 to # 8 (representative is path # 1) and groups # 4 to # 8 (representative is path # 4) shown in FIG. Each majority circuit outputs positive logic only when a match is detected.
[0048]
As a result, the coincidence detection result becomes a positive logic in FIG. 8C and FIG. 8D. In this example, the same deviation value is obtained from FIG. 8C and FIG. And a logical OR of the representative deviation values is obtained. In FIG. 8B, since the coincidence detection result has negative logic, the representative deviation value becomes invalid by the logical sum operation with the coincidence detection result. If a match is detected in a plurality of groups, the same value can be obtained regardless of which group the deviation value is obtained from, so that there is no problem.
[0049]
It should be noted that the path numbers # 1 to # 8 shown in FIG. 8 indicate the order of frame assembly in the VC, and thus the clock deviation information mapped to some paths due to a sudden error in the SONET. Even if erroneous, correct clock deviation information can be selected based on clock deviation information obtained from another path, and more reliable transmission of clock deviation information becomes possible.
[0050]
FIG. 9 shows a block diagram of an embodiment of a transmission system to which the transmission method of the present invention is applied. 3, the same parts as those in FIGS. 3, 4, and 6 are denoted by the same reference numerals. In FIG. 9, each of the transmission devices 70 and 80 has an EOS or POS function. The transmission device 70 receives the asynchronous packet from the LAN, encapsulates it, and sends it out to the SONET network. The transmission device 80 converts the encapsulated asynchronous packet transmitted from the SONET network again into an asynchronous packet and sends it out to the LAN. A path is connected between the transmission devices 70 and 80 by an STS-n (Synchronous Transfer Module Level-n).
[0051]
The clock of the signal received by the transmission device 70 from the LAN is converted to a GMII clock, for example, 125 MHz + 50 ppm, and the transmission clock of the transmission device 80 is set to 125 MHz-50 ppm at the start of service. In addition, since the SONET reference clock deviation is relatively canceled between transmission and reception, it is assumed here that there is no deviation. For example, under these conditions, if an asynchronous packet having a length of 64 bytes is input at a line usage rate of 100%, 150 frames per second are conventionally discarded.
[0052]
Data transmitted from the LAN with the GMII clock of 125 MHz + 50 ppm is received by the transmission device 70. The clock extraction unit 30 of the transmission device 70 extracts the LAN clock from the received asynchronous packet, and the clock measurement unit 32 measures the clock deviation of the LAN clock extracted from the LAN based on the SONET reference clock, for example, 8 kHz. .
[0053]
At this time, the clock measuring unit 32 counts each time one measurement with the expected value of 125M × (1 + 50 ppm) /8k-15625=0.78125, and is actually obtained from the subtractor 34 in the clock measuring unit 32. The value is, for example, the deviation is 0 for the first time, the deviation is 1 for the second time, the deviation is 1 for the third time, the deviation is 1 for the fourth time, and the deviation is 0 for the fifth time. Later, from the adder / subtractor 36 in the clock measuring unit 32, a deviation value is obtained as a total value of +50.
[0054]
Then, the calculated deviation value +50 is mapped by the POH mapping unit 60 to n STS POHs used in the VC. As a mapping method, for example, the ZOH byte of the POH shown in FIG. 10 is used, the upper 1 bit of the Z3 byte is used as a code, and the remaining 7 bits are used as numerical values, and values of -127 ppm to +127 ppm can be transmitted. This is enough to transmit a value of ± 100 ppm within the standard.
[0055]
In the transmission device 80, the clock information extraction unit 66 in the VC path termination unit 64 ₁ At 66n, clock deviation information is extracted from the POH of each STS, a sudden value and an abnormal value are removed from a plurality of clock deviation information by the clock information selection unit 68, and the most accurate clock deviation information is determined by majority decision of the remaining clock deviation information. The selected value is supplied to the comparison control unit 46 as the receiving end deviation.
[0056]
In the transmission device 80, clock deviation information of the transmission clock output from the VCXO 42 is measured by the clock measuring unit 44 and supplied to the comparison control unit 46 as a transmission end deviation.
[0057]
In the above example, the clock deviation information extracted from the POH is +50 ppm, and the clock deviation information of the transmission clock of the transmission device 80 is −50 ppm in the initial state. Therefore, the comparison control unit 46 sets the transmission clock to +100 ppm. A first correction value to be increased is generated and supplied to the adder 12.
[0058]
Further, data (asynchronous packet) to be transmitted from the VC path terminating unit 64 is supplied and stored in the buffer 50, and the buffer management unit 52 is expressed by the equation (1) according to the buffer usage rate of the buffer 50. Then, a second correction value is generated and supplied to the adder 82.
[0059]
In the above example, the LAN reception speed is faster than the LAN transmission speed in the initial state, and data is stored in the buffer 50 of the transmission unit of the transmission device 80 before the clock is adjusted. A clock adjustment function for discharging the signal operates. If the total correction value output from the adder 82 deviates from the preset upper and lower limit standards, the frequency of the transmission clock is limited to the upper and lower limit standards by the standard limiter 84 and given to the VCXO 42. The transmission clock output from the VCXO 42 is supplied to the transmission unit 86, and the transmission unit 86 transmits the data (asynchronous packet) read from the buffer to the LAN in synchronization with the transmission clock.
[0060]
As a result, the speed of the LAN transmission data is equal to the speed of the LAN reception data, or the speed of the LAN transmission data is increased by the buffer usage rate. When the receiving unit clock deviation information becomes equal to the transmitting unit lock deviation information, an instruction of no change is output from the comparison control unit 46. In the steady state, the speed of the LAN transmission data matches the speed of the LAN transmission data. Become.
[0061]
Therefore, the transmission method of the present embodiment can prevent normal asynchronous packets from being discarded due to clock deviation. For this reason, the data retransmission procedure is not performed in the transmission apparatus having the EOS / POS function, which greatly contributes to the improvement of the transmission efficiency.
[0062]
The clock extracting unit 30 and the clock measuring unit 32 correspond to the receiving clock measuring unit described in the claims, the POH mapping unit 38 and the VC mapping unit 60 correspond to the mapping unit, and the clock information extracting units 40 and 66. ₁ 66n correspond to the clock information extracting means, the VCXO 42, the clock measuring section 44, and the comparison control section 46 correspond to the clock frequency adjusting means, the clock information selecting section 68 corresponds to the clock information selecting means, and the buffer managing section 82 Corresponds to buffer management means.
[0063]
(Supplementary Note 1) In a transmission method of encapsulating a signal received from an asynchronous network, transmitting the signal between transmission apparatuses of a synchronous network, and then transmitting the signal to the asynchronous network,
Mapping the clock information of the clock frequency of the signal received from the asynchronous network at the timing of the reference clock of the synchronous network to the overhead of the signal transmitted on the synchronous network and transmitting the mapped information;
Extracting the clock information from the overhead of the signal transmitted on the synchronization network,
Adjusting a clock frequency of a signal to be transmitted to the asynchronous network based on the extracted clock information;
A transmission method characterized in that:
[0064]
(Supplementary Note 2) In a transmission device for encapsulating a signal received from an asynchronous network and sending the signal to a synchronous network,
Receiving clock measuring means for measuring a clock frequency of a signal received from the asynchronous network at a timing of a reference clock of the synchronous network to obtain clock information,
Mapping means for mapping the clock information to overhead of a signal transmitted in a synchronous network.
A transmission device comprising:
[0065]
(Supplementary note 3) In a transmission device for receiving a signal in which the clock information of the asynchronous network is mapped to the overhead while being received and encapsulated from the asynchronous network and transmitting the signal asynchronously from the synchronous network,
Clock information extracting means for extracting clock information of the asynchronous network from overhead of a received signal,
A clock frequency adjusting unit that adjusts a clock frequency of a signal to be transmitted to the asynchronous network based on the extracted clock information.
A transmission device comprising:
[0066]
(Supplementary note 4) In the transmission device according to supplementary note 2,
The transmission device, wherein the mapping unit maps the clock information to overheads of a plurality of paths transmitted through a synchronous network.
[0067]
(Supplementary note 5) In the transmission device according to supplementary note 3,
The clock information extracting unit extracts the asynchronous network clock information from the received overhead of the plurality of paths,
A clock information selecting unit that performs majority decision on a plurality of clock information extracted from the overheads of the plurality of paths to select one clock information and supplies the selected clock information to the clock frequency adjusting unit;
A transmission device comprising:
[0068]
(Supplementary note 6) In the transmission device according to supplementary note 3 or 5,
A buffer management unit that generates a second correction value that adjusts a clock frequency of a signal to be transmitted to the asynchronous network according to an amount of data stored in a buffer that stores a signal to be transmitted to the asynchronous network;
The transmission device, wherein the clock frequency adjustment unit adjusts a clock frequency of a signal transmitted to the asynchronous network based on a sum of a first correction value and a second correction value based on the extracted clock information. .
[0069]
(Supplementary note 7) In the transmission device according to supplementary note 5,
The transmission apparatus, wherein the clock information selecting means performs a majority decision by using the value of the previous clock information when the extracted clock information is a sudden value or an abnormal value.
[0070]
(Supplementary note 8) In the transmission device according to Supplementary note 3 or 5 or 6 or 7,
The clock frequency adjusting means, when the clock frequency of the signal to be transmitted to the asynchronous network deviates from the upper and lower limits, the limiting means for limiting the upper and lower limits.
A transmission device comprising:
[0071]
(Supplementary note 9) In the transmission device according to any one of supplementary notes 2 to 8,
The transmission device, wherein the asynchronous network is Gigabit Ethernet (registered trademark).
[0072]
(Supplementary note 10) In the transmission device according to any one of Supplementary notes 2 to 8,
The transmission device, wherein the synchronization network is SONET.
[0073]
【The invention's effect】
As described above, according to the first aspect of the present invention, the clock frequency of the signal transmitted to the asynchronous network is equal to or higher than the clock frequency of the signal received from the asynchronous network, and a normal asynchronous packet is discarded. Can be prevented.
[0074]
According to the second and third aspects of the invention, the first aspect of the invention can be realized.
[0075]
According to the fourth and fifth aspects of the present invention, it is possible to transmit clock information with higher reliability.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a transmission method by a conventional transmission device having an EOS / POS function.
FIG. 2 is a diagram for explaining a rescue method when data is lost.
FIG. 3 is a block diagram for explaining a principle of mapping clock information of a receiving unit to a SONET frame.
FIG. 4 is a block diagram illustrating a principle of adjusting a transmission clock based on clock information of a receiving unit mapped to a SONET frame.
FIG. 5 is a diagram illustrating a comparison operation result and a smoothed control voltage.
FIG. 6 is a block diagram for explaining a principle of adjusting a transmission clock based on an accumulated data amount.
FIG. 7 is a block diagram for explaining a transmission principle of receiving section clock information using VC.
FIG. 8 is a diagram showing one embodiment of majority decision.
FIG. 9 is a block diagram of one embodiment of a transmission system to which the transmission method of the present invention is applied.
FIG. 10 is a diagram for explaining mapping of received clock deviation information.
[Explanation of symbols]
30 Clock extractor
32 Clock measurement unit
33 counter
34 Subtractor
35 shift register
36 Adder / Subtractor
38 POH mapping unit
40 Clock information extraction unit
42,54 VCXO (voltage controlled crystal oscillator)
44 Clock measurement unit
46 Comparison control unit
48 terminals
50 buffers
52 Buffer management unit
60 VC mapping unit
62 ₁ ~ 62n POH mapping unit
64 VC path termination
66 ₁ ~ 66n Clock information extraction unit
68 Clock information selector
70,80 transmission equipment
82 adder
84 Standard restriction section
86 transmission unit

Claims (5)

A transmission method for encapsulating a signal received from an asynchronous network, transmitting the signal between transmission devices of a synchronous network, and then transmitting the signal to the asynchronous network,
Mapping the clock information of the clock frequency of the signal received from the asynchronous network at the timing of the reference clock of the synchronous network to the overhead of the signal transmitted on the synchronous network and transmitting the mapped information;
Extracting the clock information from the overhead of the signal transmitted on the synchronization network,
A transmission method, comprising: adjusting a clock frequency of a signal to be transmitted to the asynchronous network based on the extracted clock information. In a transmission device for encapsulating a signal received from an asynchronous network and sending it out to a synchronous network,
Receiving clock measuring means for measuring a clock frequency of a signal received from the asynchronous network at a timing of a reference clock of the synchronous network to obtain clock information,
A transmission apparatus comprising a mapping unit for mapping the clock information to an overhead of a signal transmitted through a synchronous network. A transmission device for receiving from a synchronous network and asynchronously transmitting a signal in which clock information of the asynchronous network is mapped to an overhead while being received and encapsulated from the asynchronous network,
Clock information extracting means for extracting clock information of the asynchronous network from overhead of a received signal,
A transmission apparatus comprising: a clock frequency adjusting unit that adjusts a clock frequency of a signal transmitted to the asynchronous network based on the extracted clock information. The transmission device according to claim 2,
The transmission device, wherein the mapping unit maps the clock information to overheads of a plurality of paths transmitted through a synchronous network. The transmission device according to claim 3,
The clock information extracting unit extracts the asynchronous network clock information from the received overhead of the plurality of paths,
A transmission apparatus comprising: a clock information selecting unit that performs majority decision on a plurality of pieces of clock information extracted from overheads of the plurality of paths, selects one piece of clock information, and supplies the selected piece of clock information to the clock frequency adjustment unit.

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