[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JP2004207494A - Electronic device, mounting method and manufacturing method thereof - Google Patents

Electronic device, mounting method and manufacturing method thereof Download PDF

Info

Publication number
JP2004207494A
JP2004207494A JP2002374966A JP2002374966A JP2004207494A JP 2004207494 A JP2004207494 A JP 2004207494A JP 2002374966 A JP2002374966 A JP 2002374966A JP 2002374966 A JP2002374966 A JP 2002374966A JP 2004207494 A JP2004207494 A JP 2004207494A
Authority
JP
Japan
Prior art keywords
electronic device
solder
connection member
substrate
volume
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002374966A
Other languages
Japanese (ja)
Other versions
JP2004207494A5 (en
JP4022139B2 (en
Inventor
Toshiya Akamatsu
俊也 赤松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2002374966A priority Critical patent/JP4022139B2/en
Publication of JP2004207494A publication Critical patent/JP2004207494A/en
Publication of JP2004207494A5 publication Critical patent/JP2004207494A5/ja
Application granted granted Critical
Publication of JP4022139B2 publication Critical patent/JP4022139B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/264—Bi as the principal constituent
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/36—Selection of non-metallic compositions, e.g. coatings, fluxes; Selection of soldering or welding materials, conjoint with selection of non-metallic compositions, both selections being of interest
    • B23K35/3612—Selection of non-metallic compositions, e.g. coatings, fluxes; Selection of soldering or welding materials, conjoint with selection of non-metallic compositions, both selections being of interest with organic compounds as principal constituents
    • B23K35/3613—Polymers, e.g. resins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve mounting reliability by preventing the generation of a short-circuit between first connecting members upon secondary mounting with respect to an electronic device, the mounting method of the electronic device, and the manufacturing method of the electronic device, which employ lead-free solder. <P>SOLUTION: The electronic device is equipped with: a semiconductor element 11; a substrate 12, on which the semiconductor element 11 is arranged; a solder bump 31, connecting the semiconductor element 11 to the substrate 12 electrically; a solder ball 36 for effecting external connection of the substrate 12 electrically; and an underfill 15 provided between the semiconductor element 11 and the substrate 12. In the device, a solder alloy, in which the rate of a volume difference between the volume in the state of solid and the volume upon melting to the volume in the state of a solid is not more than 5 percent, is employed as the material of the solder bump 31. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は電子装置及び電子装置の実装方法及び電子装置の製造方法に係り、特に鉛を用いないはんだを用いた電子装置及び電子装置の実装方法及び電子装置の製造方法に関する。
【０００２】
近年、半導体装置に代表される電子装置では、高密度化に伴い接続端子の数が増加する傾向にある。半導体装置を例に挙げて説明すると、この接続端子の増加に対応するため、半導体素子は素子下面に形成したはんだバンプによって、基板にフリップチップ実装する方法が提案され実用化されている。
【０００３】
従来、 このフリップチップ実装は、高性能な大型コンピュータの高密度実装のために適用されていたが、近年ではＬＳＩの高集積化（接続端子の増加）に対応するため、民生機器にも、ＦＣ−ＢＧＡ(Flip Chip Ball Grid Array)パッケージとして用いられるようになってきている。
【０００４】
その際、半導体素子を実装する基板（パッケージ基板）は、樹脂ビルドアップ基板が使用されており、はんだバンプ接合部の信頼性の確保にアンダーフィル（樹脂）が必須となっている。
【０００５】
【従来の技術】
従来、ＦＣ−ＢＧＡにおいて、半導体素子を基板に接合する接合技術として用いられる、はんだバンプを用いたフリップチップ実装としては、例えば、「６ｔｈ Symposium on “Microjoining and Assembly Technology in Electronics 2000”」の予稿集、P157-162に記載の「2000pin級Flip-Chip BGAにおけるフリップチップ接合技術」に著されている。
【０００６】
図１（Ａ）は、従来のＦＣ−ＢＧＡパッケージ構造を有した半導体装置１０を示している。また、同図では半導体装置１０を実装基板２０に実装した状態を示している。
【０００７】
半導体装置１０は、大略すると半導体素子１１，基板１２，リッド１３，及びはんだボール１６等により構成されている。半導体素子１１は、図中下面を回路形成面としており、この回路形成面には複数のはんだバンプ１４が配設されている。このはんだバンプ１４を用いて半導体素子１１は、基板１２にフリップチップ接合された構成となっている。
【０００８】
また、半田バンプ１４の代わりに、金属ボールやワイヤバンピング端子を用い、いったん金属ボールやワイヤバンピング端子を半導体素子１１に接合した後、基板１２に接合する方法もある（例えば、特許文献１参照）。
【０００９】
半導体素子１１と基板１２の間には、はんだバンプ１４による半導体素子１１と基板１２の接合強度（機械的強度）を高めるため、アンダーフィル１５が配設されている。更に、半導体素子１１を覆うよう、基板１２の上部にはリッド１３が形成されている。
【００１０】
はんだボール１６は外部接続端子となるものであり、実装基板２０に形成された電極２１と対応して配設されている。このはんだボール１６は、基板１２の図中下面（半導体素子１１が配設される面と反対側の面）に配設されている。
【００１１】
基板１２は、樹脂ビルドアップ基板であり、その上面にははんだバンプ１４が接続される上部電極が形成されると共に、下面にははんだボール１６が接続される下部電極が形成されている（上部及び下部電極は図示せず）。そして、この上部電極と下部電極は、基板１２の内層配線により接続されている。上記構成とされた半導体装置１０は、はんだボール１６が実装基板２０の電極２１に接合されることにより実装基板２０に実装される。
【００１２】
電子部品の電気的機械的接合には、鉛（Ｐｂ）系のはんだ材料がもっとも使用されており、特にＳｎ−Ｐｂ共晶はんだ（Ｓｎ−３７Ｐｂ：融点183℃）が一般的に用いられてきた。特に、ＦＣ−ＢＧＡパッケージ構造の半導体装置１０では、上記したように半導体素子１１をはんだバンプ１４（突起電極）によって基板１２にフリップチップ接合する。この工程を、１次実装と呼ばれている。
【００１３】
その後、半導体素子１１と基板１２との間にアンダーフィル１５を形成し、基板１２の下面にはんだボール１６を形成する。そして、半導体装置１０を実装基板２０に実装するのには、このはんだボール１６を用いて行なわれる。このはんだボール１６を用いて半導体装置１０を実装基板２０に実装する工程を２次実装と呼んでいる。
【００１４】
半導体素子１１を基板１２に接合する１次実装用のはんだバンプ１４のはんだ材料は、２次実装の際に溶融することを防止するために、２次実装用のはんだボール１６の融点よりも融点の高いＰｂ-5%Ｓｎ（融点314℃）が用いられている。
【００１５】
しかし、近年環境問題の点から、電子部品の実装に使用されているはんだ材料のＰｂフリー化が強く望まれるようになってきている（例えば、特許文献２参照）。現在、実用化レベルのＰｂフリーはんだは、接合信頼性の点から、Ｓｎ−Ａｇ−Ｃｕ系はんだ（融点：218℃）しかない。そのため、１次実装、２次実装ともにＳｎ−Ａｇ−Ｃｕ系の鉛フリーはんだ（以下、Ｐｂフリーはんだという）を用いることが不可避となっている。
【００１６】
【特許文献１】
特開２００２−２５４１９４（第１２頁〜第１３頁、図１６）
【００１７】
【特許文献２】
特開平０９−１８１１２５号公報（第３頁〜第４頁）
【００１８】
【発明が解決しようとする課題】
しかしながら、１次実装に用いるはんだバンプ１４と２次実装に用いるはんだボール１６に同じ材質（Ｓｎ−Ａｇ−Ｃｕはんだ）を用いると、２次実装時の加熱（リフロー）時に、１次実装側のはんだバンプ１４も融解してしまう。
【００１９】
図２は、Ｓｎ−Ａｇ−Ｃｕはんだの、固体時と溶融時の体積変化を説明するための図である。同図では、Ｓｎ−Ａｇ−Ｃｕはんだにより形成されたはんだバンプ１４を例に挙げ、固体時と溶融時の体積変化をはんだバンプ１４の直径変化として示している。
【００２０】
図２（Ａ）は、固体時におけるはんだバンプ１４を示している。この時のはんだバンプ１４の直径をＲとする。このはんだバンプ１４を加熱すると、やがて溶融が開始される。そして、更に加熱処理を進めはんだバンプ１４を完全に溶融した場合、図２（Ｂ）に模式的に示すように、はんだバンプ１４の体積は固体時に比べて大きく増加する（８％以上）。
【００２１】
このようにはんだバンプ１４に体積膨張が発生すると、アンダーフィル１５と半導体素子１１の界面、或いはアンダーフィル１５と基板１２との界面に応力が発生し、最悪の場合には図１（Ｂ）に矢印Ａで示すように、アンダーフィル１５と半導体素子１１或いは基板１２との界面に溶融したはんだバンプ１４が流れ込み、バンプ間でショートが発生するおそれがあるという問題点があった。
【００２２】
本発明は上記の点に鑑みてなされたものであり、２次実装における第１の接続部材間でショートが発生することを防止することにより実装信頼性を高めた電子装置及び電子装置の実装方法及び電子装置の製造方法を提供することを目的とする。
【００２３】
【課題を解決するための手段】
上記の課題を解決するために本発明では、次に述べる各手段を講じたことを特徴とするものである。
【００２４】
請求項１記載の発明は、
電子素子と、
該電子素子が配設される被配設部材と、
前記電子素子と前記被配設部材とを電気的に接続する第１の接続部材と、
前記被配設部材を電気的に外部接続する第２の接続部材と、
前記電子素子と前記被配設部材との間に設けられる樹脂材とを具備する電子装置において、
前記第１の接続部材の材料として、固体時体積と溶融時体積との体積差の、前記固体時体積に対する割合が、５パーセント以下であるはんだ合金を用いたことを特徴とするものである。
【００２５】
上記発明によれば、第１の接続部材は、固体時体積と溶融時体積との体積差の、固体時体積に対する割合が５パーセント以下と小さいため、２次実装時の加熱により第１の接続部材が溶融したとしても、はんだバンプ間でショートが発生するようなことはない。
【００２６】
また、請求項２記載の発明は、
請求項１記載の電子装置において、
前記第１の接続部材の材料は、ビスマスを15重量パーセント以上80重量パーセント以下、残りが錫であるはんだ合金であることを特徴とするものである。
【００２７】
また、請求項３記載の発明は、
請求項１記載の電子装置において、
前記第１の接続部材の材料は、ビスマスを15重量パーセント以上80重量パーセント以下、銀を0.5重量パーセント以上３重量パーセント以下、残りが錫であるはんだ合金であることを特徴とするものである。
【００２８】
請求項１記載の発明のように、固体時体積と溶融時体積との体積差の固体時体積に対する割合が５パーセント以下とするには、第１の接続部材の組成を請求項２または請求項３のようにするのが望ましい。
【００２９】
また、請求項４記載の発明は、
請求項１乃至３のいずれか１項に記載の電子装置において、
前記第１の接続部材の融点が130℃以上200℃以下であることを特徴とするものである。
【００３０】
上記発明によれば、従来から用いられている鉛−錫共晶はんだとほぼ等しい融点であるため、第１の接続部材を接続処理するのに、従来から用いられているはんだ処理装置を用いることが可能となる。
【００３１】
また、請求項５記載の発明は、
請求項１乃至４のいずれか１項に記載の電子装置において、
前記第１の接続部材は、前記電子素子の電極に設けられたバンプ、または前記被配設部材、または前記電子素子と前記被配設部材の両方の電極上に設けられたバンプであることを特徴とするものである。
【００３２】
上記発明のように、第１の接続部材をバンプとして用いることができる。
【００３３】
また、請求項６記載の発明は、
請求項１乃至５のいずれか１項に記載の電子装置に設けられた第２の接続部材を基板に接合することにより、前記電子装置を前記基板に実装する電子装置の実装方法であって、
前記第２の接続部材を前記基板に接続する際、前記第１の接続部材の融点により高い温度に加熱して接続することを特徴とするものである。
【００３４】
上記発明によれば、第２の接続部材を選定する際、第１の接続部材の融点より高い融点を有する材料を選定することが可能となる。よって、第２の接続部材を選定する際、その選定の自由度を高めることができる。
【００３５】
また、請求項７記載の発明は、
請求項１乃至５のいずれか１項に記載の電子装置の製造方法であって、
前記被配設部材の電極に、前記第１の接続部材とは異なる材質よりなり、かつ前記第１の接続部材の体積より小さい体積の第３の接続部材を配設する工程と、
前記第１の接続部材と前記第３の接続部材とを接合させることにより前記電子素子を前記被配設部材に配設する工程を含むことを特徴とするものである。
【００３６】
上記発明によれば、被配設部材の電極上に第１の接続部材と異なる材質の第３の接続部材を配設しても、第１の接続部材の体積は第３の接続部材の体積よりも大きいため、第１の接続部材と第３の接続部材とを接合した際、第１の接続部材の特性を維持する。このため、２次実装時の加熱により第１の接続部材と第３の接続部材との接合部分が溶融しても、固体時体積と溶融時体積との体積差の、固体時体積に対する割合を５パーセント以下とすることができる。
【００３７】
【発明の実施の形態】
次に、本発明の実施の形態について図面と共に説明する。
【００３８】
図３は、本発明の一実施例である電子装置を示している。本実施例では、電子装置としてＦＣ−ＢＧＡパッケージ構造を有した半導体装置３０を例に挙げて説明するものとする。また本実施例では、半導体装置３０は、実装基板２０に実装されるものとする。尚、図３において、図１に示した半導体装置１０と同一構成については同一符号を付して説明するものとする。
【００３９】
半導体装置３０は、大略すると半導体素子１１（請求項に記載の電子素子に相当する），基板１２（請求項に記載の被配設部材に相当する），リッド１３，及びはんだボール３６（請求項に記載の第２の接続部材に相当する）等により構成されている。半導体素子１１は、図中下面を回路形成面としており、この回路形成面には複数のはんだバンプ３１（請求項に記載の第１の接続部材に相当する）が配設されている。このはんだバンプ３１を用いて半導体素子１１は、基板１２にフリップチップ接合されている。
【００４０】
また、半導体素子１１と基板１２の間には、はんだバンプ３１による半導体素子１１と基板１２の機械的な接合強度を高めるため、アンダーフィル１５（請求項に記載の樹脂材に相当する）が配設されている。このアンダーフィル１５は熱硬化型樹脂であり、上面が半導体素子１１と接着され、下面が基板１２に接着された構成となっている。更に、基板１２の上部には、半導体素子１１を覆うようにリッド１３が配設されている。
【００４１】
はんだボール３６は外部接続端子となるものであり、実装基板２０に形成された電極２１に対応した位置に配設されている。このはんだボール３６は、基板１２の図中下面（半導体素子１１が配設される面と反対側の面）に配設されている。
【００４２】
図４に示すように、基板１２は樹脂ビルドアップ基板であり、その上面にははんだバンプ３１が接合される上部電極３２が形成されると共に、下面にははんだボール１６が接合される下部電極が形成されている（下部電極は図示せず）。そして、この上部電極３２と下部電極は、基板１２の内層配線により接続されている。上記構成とされた半導体装置３０は、図５に示すようにはんだボール３６が実装基板２０の電極２１に接合されることにより実装基板２０に実装される。
【００４３】
上記した半導体装置３０において、本実施例でははんだバンプ３１とはんだボール３６の材質としてはＰｂフリーのはんだ材料を使用している。はんだバンプ３１のはんだ材料は、固体時体積（Ｖ１）と溶融時体積（Ｖ２）との体積差（Ｖ２−Ｖ１）の、固体時体積に対する割合［｛（Ｖ２−Ｖ１）／Ｖ１｝×１００］が、５パーセント（％）以下である金属材料を用いている（以下、この割合を体積膨張率という）。
【００４４】
ここで、体積膨張率が５％以下の材料と規定したのは、それ以上の体積膨張率であると、はんだバンプ３１間でショートが発生する確率が格段に上昇するためである。特に従来用いられていたＳｎ−Ａｇ−Ｃｕ系のはんだ材料では、体積膨張率約１０％であることから、これ以下に制御する必要がある。
【００４５】
このように体積膨張率を５％以下としうる金属材料としては、ビスマス（Ｂｉ）を15重量％以上80重量％以下、Ａｇを0.5重量％以上３重量％以下、残りがＳｎである組成を有した金属材料が考えられる。Ｂｉは融解した場合に体積が減少する特性を有しており、よってＳｎに対してＢｉの添加量を変化させた場合、Ｂｉ濃度の上昇に伴って融解時の体積膨張率を低下させることができる。特に、共晶付近の組成（Ｂｉが５７％）ではほとんど膨張しない。
【００４６】
また、Ｂｉの添加量が15重量％未満となると、ＢｉはＳｎに対して固溶し、膨張率を低下させる効果がなくなってしまう。一方、Ｂｉの添加量が80重量％を超えると、このはんだ材料はもろくなり、はんだバンプ３１として要求される強度を得ることができない。
【００４７】
以上の各理由から本実施例では、はんだバンプ３１の金属材料として、ビスマス（Ｂｉ）を15重量％以上80重量％以下、銀（Ａｇ）を0.5重量％以上３重量％以下、残りが錫（Ｓｎ）である組成を有した金属材料を用いている。この金属材料の組成をこのように設定することにより、体積膨張率は−５％以上+５以下となる。
【００４８】
本実施例の組成範囲では、融点直上の温度では、固体から液体に変化する際に体積が減少し、膨張率としてはマイナス（減少）となる。しかし、温度を上げていくことによって、液体の熱膨張により体積が膨張する。本実施例の組成範囲では、完全に固体が溶融し液体となった状態で、５％以下となる。また、下限値として、融点直上の温度を想定して−５％としたが、更に低くなっても問題はない。
【００４９】
また、上記組成とされた金属材料の融点は、130℃以上200℃以下である。この融点は、従来から用いられているＰｂ−Ｓｎ共晶はんだとほぼ等しい融点であるため、はんだバンプ３１及びはんだボール３６の接合処理に、従来から用いられているはんだ処理装置を用いることが可能となり、設備コストの低減を図ることができる。
【００５０】
図４は、半導体装置３０の製造工程において、半導体素子１１を基板１２に実装する方法（１次実装の方法）を示している。前記のように、本実施例でははんだバンプ３１を用いて半導体素子１１を基板１２にフリップチップ接合する方法を採っている。
【００５１】
このフリップチップ接合する際、基板１２に形成された上部電極３２には、予めはんだの濡れ性を高めるフラックスが塗布されていたり、はんだペースト３３が印刷されている場合がある。このはんだペースト３３は、いわゆるはんだの濡れ性を高める各種材料と、金属材料の粒体（以下、金属粒体という）とにより構成されている。
【００５２】
本実施例では、このはんだペースト３３に含まれる金属粒体としてSn-3Ag-0.5Cuを用いており、はんだバンプ３１の材料と異なる材料を用いている。しかしながら、はんだペースト３３に含まれる金属粒体の全体積（個々の上部電極３２に塗布される全体積）は、１個のはんだバンプ３１の体積に比べて非常に小さい。
【００５３】
したがって、はんだペースト３３に含まれる金属粒体としてはんだバンプ３１と異なる材質の金属材料を用いても、はんだバンプ３１を上部電極３２に接合し、これによりはんだペースト３３に含まれる金属粒体がはんだバンプ３１を構成する金属材料に混入しても（以下、これを接合後金属材料という）、この接合後金属材料は接合前のはんだバンプ３１の特性を維持する。よって、この接合後金属材料の体積膨張率をはんだバンプ３１の材料の体積膨張率と同じ５％以下とすることができる。
【００５４】
続いて、半導体装置３０を実装基板２０に実装する実装方法（２次実装の方法）について説明する。半導体装置３０を実装基板２０に実装するには、図３に示すように、予め実装基板２０に設けられた各電極２１にはんだペースト２２を塗布しておく。このはんだペースト２２もはんだの濡れ性を高める各種材料と金属粒体とよりなる構成とされている。このはんだペースト２２に添加される金属粒体は、はんだボール３６と同一の金属材料を用いることが一般的である。
【００５５】
半導体装置３０は、はんだボール３６と電極２１とが一致するよう実装基板２０に載置される。はんだペースト２２は、ある程度の粘着性を有しているため、半導体装置３０は実装基板２０に仮止めされる。そして、仮止めされた状態で、半導体装置３０及び実装基板２０は、リフロー炉に入れられ加熱処理が実施される。この時の加熱温度は、はんだバンプ３１の融点（130℃以上200℃以下）以上の温度に設定されている。
【００５６】
この加熱処理により、はんだボール３６は溶融して電極２１に接合する。この際、はんだボール３６が溶融する温度で加熱処理を行なうと、はんだバンプ３１も溶融する。しかしながら、はんだバンプ３１は体積膨張割合が５パーセント以下と小さいため、この加熱によりはんだバンプ３１がアンダーフィル１５と半導体素子１１との界面、及びアンダーフィル１５と基板１２との界面に侵入するようなことはない。これにより、隣接するはんだバンプ３１間がショートすることを防止でき、実装信頼性を高めることができる。
【００５７】
また、上記のように本実施例では、はんだボール３６を電極２１に接合する際、はんだバンプ３１の融点により高い温度に加熱して接続する構成としている。
【００５８】
前記したように、はんだバンプ３１を構成する金属材料は、ＳｎにＢｉを添加した材料である。しかしながら、ＳｎにＢｉを添加した材料は、アンダーフィル１５（熱硬化性樹脂）の形成時に実施される加熱処理によって、ＳｎとＢｉが分離してはんだ組織が粗大化してしまう。このように粗大化した組織は、疲労寿命を低下させる傾向がある。
【００５９】
このため、本実施例では２次実装時にバンプ３１の融点により高い温度に加熱して溶融させることにより、アンダーフィル１５の形成時における熱履歴によって粗大化した組織を、対疲労性の高い微細な組織に改善している。これにより、はんだバンプ３１と基板１２との接合信頼性を更に向上させることができる。
【００６０】
はんだバンプ３１とはんだボール３６が同一材料としても、問題はない。また、前記のように、はんだバンプ３１とはんだボール３６を異なる材質とする場合には、はんだボール３６の材質を選定する際にはんだバンプ３１の融点より高い融点を有する材料を選定することが可能となり、はんだボール３６の材質選定の自由度を高めることもできる。
【００６１】
続いて、本発明者が上記した発明に係る半導体装置３０を用いて実際に実装処理を行なった実施例について説明する。
【００６２】
【実施例１】
Sn-2.6Ag、Sn-3Ag-0.5Cu、Sn-37Pb、Sn-30Bi、Sn-40Bi、Sn-57Bi、Sn-57Bi-0.5Ag、Sn-57Bi-0.9Ag、Sn-57Bi-2.5Agのはんだ9種について、室温と２５０℃において、ピクノメータ法によって、密度を測定し、その密度から体積膨張率を求めた。尚、ピクノメータ法とは、セルの中にサンプルと分散媒を入れ、サンプルの細孔や粒子間に液体を浸入させるための脱気を行い、その後ある液面まで液を足して重量を量り、そのときの液温を計るという方法である。この方法によれば、サンプルによって置換される液体の重量から比重を得ることができる。
【００６３】
結果を以下の表１に示す。
【００６４】
【表１】

Figure 2004207494
上記の表１より、ＳｎにＢｉを添加することによって、体積膨張率を低下させることができることが判る。更に、Ａｇを添加することにより、体積膨張をほぼ抑制できることが判る。
［実施例２］
Ｓｎ-57Ｂｉはんだ粉末をフラックスと重量比で９０：１０で混合したはんだペーストを、エッチングでくぼみを形成したシリコン基板に印刷し、ピーク温度２００℃の窒素リフローによりはんだボールを作製した。
【００６５】
このはんだボールを、□１４ｍｍ、φ１００μｍ、ピッチ２５０μｍの半導体素子の電極上に、位置合わせを行い、半導体素子に、ピーク温度２００℃の窒素リフローにより、はんだバンプを形成した。更に、このバンプと、フラックスを供給した□４０ｍｍのガラスセラミック製ＢＧＡ回路基板上に位置合わせを行い、ピーク温度２００℃の窒素リフローによりフリップチップ接合体を作製した。その後、チップ基板間にアンダーフィル剤を、７０℃のホットプレート上で供給し、１００℃１ｈで硬化させた。
【００６６】
このサンプルについて、ボール付け、２次実装を考慮して、最高温度250℃のリフローを５回行い、熱負荷をかけた。そのサンプルについて、１次実装の接合部の抵抗を測定した。その結果、ショートもなく良好なはんだ接合部が得られた。
比較のために、Ｓｎ−3Ａｇ−0.5Ｃｕはんだボールではんだバンプを形成した半導体素子を用いて作製したサンプルの試験を行なった結果、リフロー５回後で、１５個中７個ショートが発生した。
【００６７】
【発明の効果】
上述の如く本発明によれば、次に述べる種々の効果を実現することができる。
【００６８】
請求項１，２，３，５記載の発明によれば、第１の接続部材の加熱時における体積変化が５パーセント以下と小さいため、２次実装時の加熱により第１の接続部材が溶融したとしても、はんだバンプ間でショートが発生するようなことはなく、よって電子装置の信頼性を高めることができる。
【００６９】
また、請求項４記載の発明によれば、第１の接続部材を接続処理するのに従来から用いられているはんだ処理装置を用いることが可能となり、設備コストの低減を図ることができる。
【００７０】
また、請求項６記載の発明によれば、第２の接続部材を選定する際、第１の接続部材の融点より高い融点を有する材料を選定することが可能となるため、第２の接続部材を選定する自由度を高めることができる。
【００７１】
また、請求項７記載の発明によれば、被配設部材の電極上に第１の接続部材と異なる材質の第３の接続部材を配設しても、第１の接続部材と第３の接続部材との接合金属材料は第１の接続部材の特性を示すため、加熱により接合金属材料が溶融したとしてもはんだバンプ間でショートが発生するようなことはなく、よって電子装置の信頼性を高めることができる。
【図面の簡単な説明】
【図１】従来の一例である半導体装置を説明するための図である。
【図２】従来のはんだで発生する体積膨張を説明するための図である。
【図３】本発明の一実施例である半導体装置の構成及び実装方法を説明するための図である。
【図４】本発明の一実施例である半導体装置の製造方法を説明するための図である。
【図５】本発明の一実施例である半導体装置の実装方法を説明するための図である。
【符号の説明】
１１ 半導体素子
１２ 基板
１３ リッド
１４，３１ はんだバンプ
１５ アンダーフィル
１６，３６ はんだボール
２０ 実装基板
２１ 電極
２２，３３ はんだペースト
３０ 半導体装置
３２ 上部電極[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electronic device, an electronic device mounting method, and an electronic device manufacturing method, and more particularly, to an electronic device using lead-free solder, an electronic device mounting method, and an electronic device manufacturing method.
[0002]
2. Description of the Related Art In recent years, in electronic devices represented by semiconductor devices, the number of connection terminals tends to increase as the density increases. Taking the semiconductor device as an example, in order to cope with the increase in the number of connection terminals, a method of flip-chip mounting a semiconductor element on a substrate using solder bumps formed on the lower surface of the element has been proposed and put into practical use.
[0003]
Conventionally, this flip-chip mounting has been applied for high-density mounting of high-performance large-sized computers. However, in recent years, in order to cope with high integration of LSIs (increase in connection terminals), FCs have been used in consumer devices as well. -It has been used as a BGA (Flip Chip Ball Grid Array) package.
[0004]
At this time, a resin build-up substrate is used as a substrate (package substrate) on which the semiconductor element is mounted, and an underfill (resin) is essential to ensure the reliability of the solder bump joint.
[0005]
[Prior art]
Conventionally, in the FC-BGA, as a flip-chip mounting using a solder bump, which is used as a joining technology for joining a semiconductor element to a substrate, for example, a preliminary report of “6th Symposium on“ Microjoining and Assembly Technology in Electronics 2000 ”” Pp. 157-162, "Flip-chip bonding technology in 2000-pin class flip-chip BGA".
[0006]
FIG. 1A shows a semiconductor device 10 having a conventional FC-BGA package structure. FIG. 1 shows a state where the semiconductor device 10 is mounted on the mounting board 20.
[0007]
The semiconductor device 10 generally includes a semiconductor element 11, a substrate 12, a lid 13, solder balls 16, and the like. The semiconductor element 11 has a circuit forming surface on the lower surface in the figure, and a plurality of solder bumps 14 are provided on the circuit forming surface. The semiconductor element 11 is flip-chip bonded to the substrate 12 using the solder bumps 14.
[0008]
There is also a method in which a metal ball or a wire bumping terminal is used instead of the solder bump 14, and the metal ball or the wire bumping terminal is once bonded to the semiconductor element 11 and then bonded to the substrate 12 (for example, see Patent Document 1). .
[0009]
An underfill 15 is provided between the semiconductor element 11 and the substrate 12 in order to increase the bonding strength (mechanical strength) between the semiconductor element 11 and the substrate 12 by the solder bumps 14. Further, a lid 13 is formed above the substrate 12 so as to cover the semiconductor element 11.
[0010]
The solder balls 16 serve as external connection terminals, and are arranged corresponding to the electrodes 21 formed on the mounting board 20. The solder balls 16 are provided on the lower surface of the substrate 12 in the figure (the surface opposite to the surface on which the semiconductor element 11 is provided).
[0011]
The substrate 12 is a resin build-up substrate, on the upper surface of which an upper electrode to which a solder bump 14 is connected is formed, and on the lower surface, a lower electrode to which a solder ball 16 is connected (upper and lower). The lower electrode is not shown). The upper electrode and the lower electrode are connected by an inner layer wiring of the substrate 12. The semiconductor device 10 having the above configuration is mounted on the mounting substrate 20 by joining the solder balls 16 to the electrodes 21 of the mounting substrate 20.
[0012]
Lead (Pb) -based solder materials are most used for electrical and mechanical joining of electronic components, and in particular, Sn-Pb eutectic solder (Sn-37Pb: melting point 183 ° C.) has been generally used. . In particular, in the semiconductor device 10 having the FC-BGA package structure, the semiconductor element 11 is flip-chip bonded to the substrate 12 by the solder bumps 14 (protruding electrodes) as described above. This step is called primary mounting.
[0013]
Thereafter, an underfill 15 is formed between the semiconductor element 11 and the substrate 12, and a solder ball 16 is formed on the lower surface of the substrate 12. Then, the semiconductor device 10 is mounted on the mounting substrate 20 using the solder balls 16. The step of mounting the semiconductor device 10 on the mounting board 20 using the solder balls 16 is called secondary mounting.
[0014]
The solder material of the primary mounting solder bumps 14 for joining the semiconductor element 11 to the substrate 12 has a melting point higher than that of the secondary mounting solder balls 16 in order to prevent melting during secondary mounting. Pb-5% Sn (melting point: 314 ° C.) is used.
[0015]
However, in recent years, Pb-free solder materials used for mounting electronic components have been strongly desired in view of environmental problems (for example, see Patent Document 2). At present, there is only Sn-Ag-Cu-based solder (melting point: 218 ° C.) as a Pb-free solder at a practical level from the viewpoint of joining reliability. Therefore, it is inevitable to use Sn-Ag-Cu-based lead-free solder (hereinafter, referred to as Pb-free solder) for both the primary mounting and the secondary mounting.
[0016]
[Patent Document 1]
JP-A-2002-254194 (pages 12 to 13, FIG. 16)
[0017]
[Patent Document 2]
JP-A-09-181125 (pages 3 to 4)
[0018]
[Problems to be solved by the invention]
However, if the same material (Sn-Ag-Cu solder) is used for the solder bumps 14 used for the primary mounting and the solder balls 16 used for the secondary mounting, the heating (reflow) at the time of the secondary mounting causes The solder bumps 14 also melt.
[0019]
FIG. 2 is a diagram for explaining a change in volume of the Sn-Ag-Cu solder between a solid state and a molten state. In the figure, a solder bump 14 formed of Sn-Ag-Cu solder is taken as an example, and a volume change between a solid state and a molten state is shown as a diameter change of the solder bump 14.
[0020]
FIG. 2A shows the solder bump 14 in a solid state. The diameter of the solder bump 14 at this time is R. When the solder bumps 14 are heated, melting is started. Then, when the heat treatment is further advanced to completely melt the solder bumps 14, as schematically shown in FIG. 2B, the volume of the solder bumps 14 is greatly increased as compared with the solid state (8% or more).
[0021]
When the volume expansion of the solder bumps 14 occurs, stress is generated at the interface between the underfill 15 and the semiconductor element 11 or at the interface between the underfill 15 and the substrate 12, and in the worst case, as shown in FIG. As shown by the arrow A, there is a problem that the molten solder bump 14 flows into the interface between the underfill 15 and the semiconductor element 11 or the substrate 12, and a short circuit may occur between the bumps.
[0022]
The present invention has been made in view of the above points, and an electronic device and a mounting method of an electronic device with improved mounting reliability by preventing a short circuit from occurring between first connection members in secondary mounting. And a method for manufacturing an electronic device.
[0023]
[Means for Solving the Problems]
In order to solve the above problems, the present invention is characterized by taking the following means.
[0024]
The invention according to claim 1 is
Electronic elements,
A member on which the electronic element is provided;
A first connection member that electrically connects the electronic element and the member to be disposed;
A second connection member for electrically connecting the member to be externally connected;
An electronic device comprising: a resin material provided between the electronic element and the member to be provided;
As a material of the first connection member, a solder alloy having a ratio of a volume difference between a solid volume and a molten volume to the solid volume of 5% or less is used.
[0025]
According to the above invention, since the ratio of the volume difference between the solid-state volume and the molten-state volume to the solid-state volume is as small as 5% or less, the first connection member is heated by the second mounting to perform the first connection. Even if the members are melted, no short circuit occurs between the solder bumps.
[0026]
The invention according to claim 2 is
The electronic device according to claim 1,
The material of the first connection member is a solder alloy in which bismuth is contained in an amount of 15% by weight or more and 80% by weight or less, with the balance being tin.
[0027]
The invention according to claim 3 is:
The electronic device according to claim 1,
The material of the first connection member is a solder alloy in which bismuth is 15% by weight to 80% by weight, silver is 0.5% by weight to 3% by weight, and the balance is tin.
[0028]
In order for the ratio of the volume difference between the solid volume and the molten volume to the solid volume to be 5% or less as in the first aspect of the invention, the composition of the first connection member is set to the second or third aspect. It is desirable to make it like 3.
[0029]
The invention according to claim 4 is
The electronic device according to any one of claims 1 to 3,
The melting point of the first connection member is 130 ° C. or more and 200 ° C. or less.
[0030]
According to the above invention, since the melting point is substantially equal to that of the conventionally used lead-tin eutectic solder, a conventionally used solder processing apparatus is used for connecting the first connection member. Becomes possible.
[0031]
The invention according to claim 5 is
The electronic device according to any one of claims 1 to 4,
The first connection member may be a bump provided on an electrode of the electronic element, or the provided member, or a bump provided on both electrodes of the electronic element and the provided member. It is a feature.
[0032]
As in the above invention, the first connection member can be used as a bump.
[0033]
The invention according to claim 6 is:
A mounting method for an electronic device, comprising: bonding a second connection member provided on the electronic device according to claim 1 to a substrate, thereby mounting the electronic device on the substrate.
When the second connection member is connected to the substrate, the first connection member is heated to a higher temperature due to a melting point of the first connection member and connected.
[0034]
According to the above invention, when selecting the second connection member, it is possible to select a material having a melting point higher than the melting point of the first connection member. Therefore, when selecting the second connection member, the degree of freedom in the selection can be increased.
[0035]
The invention according to claim 7 is
A method for manufacturing an electronic device according to claim 1, wherein:
Disposing a third connection member made of a material different from that of the first connection member and having a smaller volume than the volume of the first connection member on the electrode of the disposed member;
A step of disposing the electronic element on the member to be disposed by joining the first connection member and the third connection member.
[0036]
According to the above invention, even if the third connection member made of a different material from the first connection member is provided on the electrode of the member to be provided, the volume of the first connection member is equal to the volume of the third connection member. Therefore, when the first connection member and the third connection member are joined, the characteristics of the first connection member are maintained. Therefore, even if the joint between the first connection member and the third connection member is melted by heating during the secondary mounting, the ratio of the volume difference between the solid state volume and the molten state volume to the solid state volume is determined. It can be up to 5 percent.
[0037]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0038]
FIG. 3 shows an electronic device according to one embodiment of the present invention. In this embodiment, a semiconductor device 30 having an FC-BGA package structure will be described as an example of an electronic device. In this embodiment, the semiconductor device 30 is mounted on the mounting board 20. In FIG. 3, the same components as those of the semiconductor device 10 shown in FIG.
[0039]
The semiconductor device 30 generally includes a semiconductor element 11 (corresponding to an electronic element described in the claims), a substrate 12 (corresponding to a member to be disposed described in the claims), a lid 13, and a solder ball 36 (claims). , Etc.). The semiconductor element 11 has a lower surface in the drawing as a circuit forming surface, and a plurality of solder bumps 31 (corresponding to first connecting members described in claims) are disposed on the circuit forming surface. The semiconductor element 11 is flip-chip bonded to the substrate 12 using the solder bump 31.
[0040]
An underfill 15 (corresponding to a resin material described in the claims) is provided between the semiconductor element 11 and the substrate 12 in order to increase the mechanical bonding strength between the semiconductor element 11 and the substrate 12 by the solder bumps 31. Is established. The underfill 15 is a thermosetting resin, and has an upper surface bonded to the semiconductor element 11 and a lower surface bonded to the substrate 12. Further, a lid 13 is provided above the substrate 12 so as to cover the semiconductor element 11.
[0041]
The solder balls 36 serve as external connection terminals, and are arranged at positions corresponding to the electrodes 21 formed on the mounting board 20. The solder balls 36 are provided on the lower surface of the substrate 12 in the drawing (the surface opposite to the surface on which the semiconductor element 11 is provided).
[0042]
As shown in FIG. 4, the substrate 12 is a resin build-up substrate, on the upper surface of which an upper electrode 32 to which a solder bump 31 is bonded is formed, and on the lower surface, a lower electrode to which a solder ball 16 is bonded. (The lower electrode is not shown). The upper electrode 32 and the lower electrode are connected by an inner layer wiring of the substrate 12. The semiconductor device 30 having the above configuration is mounted on the mounting substrate 20 by bonding the solder balls 36 to the electrodes 21 of the mounting substrate 20 as shown in FIG.
[0043]
In the above-described semiconductor device 30, in this embodiment, a Pb-free solder material is used as the material of the solder bumps 31 and the solder balls 36. The solder material of the solder bump 31 is a ratio [{(V2−V1) / V1} × 100] of the volume difference (V2−V1) between the solid volume (V1) and the molten volume (V2) to the solid volume. However, a metal material of 5% (%) or less is used (hereinafter, this ratio is referred to as a volume expansion coefficient).
[0044]
Here, the reason that the volume expansion coefficient is specified to be 5% or less is that if the volume expansion coefficient is more than 5%, the probability that a short circuit occurs between the solder bumps 31 is significantly increased. In particular, the Sn-Ag-Cu-based solder material conventionally used has a volume expansion rate of about 10%, so it is necessary to control the volume expansion rate to less than this.
[0045]
As the metal material capable of reducing the volume expansion coefficient to 5% or less, there is a composition in which bismuth (Bi) is 15 to 80% by weight, Ag is 0.5 to 3% by weight, and the balance is Sn. Metal materials are considered. Bi has the property of decreasing the volume when melted, and therefore, when the amount of Bi added to Sn is changed, the volume expansion rate at the time of melting may decrease with an increase in the Bi concentration. it can. In particular, the composition hardly expands in the composition near the eutectic (Bi is 57%).
[0046]
If the amount of added Bi is less than 15% by weight, Bi forms a solid solution with Sn and loses the effect of lowering the expansion coefficient. On the other hand, if the added amount of Bi exceeds 80% by weight, the solder material becomes brittle, and the strength required for the solder bump 31 cannot be obtained.
[0047]
For each of the above reasons, in the present embodiment, as the metal material of the solder bump 31, bismuth (Bi) is 15 to 80% by weight, silver (Ag) is 0.5 to 3% by weight, and the rest is tin ( A metal material having a composition of Sn) is used. By setting the composition of the metal material in this way, the volume expansion coefficient becomes −5% or more and +5 or less.
[0048]
In the composition range of this example, at a temperature just above the melting point, the volume decreases when changing from a solid to a liquid, and the expansion coefficient becomes minus (decrease). However, as the temperature is increased, the volume expands due to thermal expansion of the liquid. In the composition range of this embodiment, the content is 5% or less in a state where the solid is completely melted and turned into a liquid. In addition, the lower limit is set to -5% assuming the temperature immediately above the melting point, but there is no problem even if the temperature is further lowered.
[0049]
The melting point of the metal material having the above composition is 130 ° C. or more and 200 ° C. or less. Since this melting point is almost the same as that of the conventionally used Pb-Sn eutectic solder, it is possible to use a conventionally used solder processing apparatus for bonding the solder bumps 31 and the solder balls 36. Thus, equipment costs can be reduced.
[0050]
FIG. 4 shows a method of mounting the semiconductor element 11 on the substrate 12 (primary mounting method) in the manufacturing process of the semiconductor device 30. As described above, in this embodiment, the method of flip-chip bonding the semiconductor element 11 to the substrate 12 using the solder bumps 31 is employed.
[0051]
At the time of the flip chip bonding, the upper electrode 32 formed on the substrate 12 may be coated with a flux for increasing the wettability of the solder or printed with the solder paste 33 in advance. The solder paste 33 is composed of various materials that enhance the so-called solder wettability, and particles of a metal material (hereinafter, referred to as metal particles).
[0052]
In this embodiment, Sn-3Ag-0.5Cu is used as the metal particles contained in the solder paste 33, and a material different from the material of the solder bump 31 is used. However, the total volume of the metal particles contained in the solder paste 33 (the total volume applied to the individual upper electrodes 32) is much smaller than the volume of one solder bump 31.
[0053]
Therefore, even if a metal material different from that of the solder bumps 31 is used as the metal particles contained in the solder paste 33, the solder bumps 31 are joined to the upper electrode 32, whereby the metal particles contained in the solder paste 33 Even if the metal material is mixed with the metal material forming the bump 31 (hereinafter, referred to as a metal material after bonding), the metal material after bonding maintains the characteristics of the solder bump 31 before bonding. Therefore, the volume expansion coefficient of the metal material after the joining can be set to 5% or less, which is the same as the volume expansion coefficient of the material of the solder bump 31.
[0054]
Subsequently, a mounting method (second mounting method) for mounting the semiconductor device 30 on the mounting substrate 20 will be described. To mount the semiconductor device 30 on the mounting board 20, as shown in FIG. 3, a solder paste 22 is applied to each electrode 21 provided on the mounting board 20 in advance. The solder paste 22 is also composed of various materials for improving the wettability of the solder and metal particles. Generally, the same metal material as that of the solder balls 36 is used for the metal particles added to the solder paste 22.
[0055]
The semiconductor device 30 is mounted on the mounting board 20 so that the solder balls 36 and the electrodes 21 match. Since the solder paste 22 has a certain degree of adhesiveness, the semiconductor device 30 is temporarily fixed to the mounting board 20. Then, in a state where the semiconductor device 30 and the mounting substrate 20 are temporarily fixed, the semiconductor device 30 and the mounting substrate 20 are placed in a reflow furnace and subjected to a heat treatment. The heating temperature at this time is set to a temperature not lower than the melting point of the solder bump 31 (130 ° C. or more and 200 ° C. or less).
[0056]
By this heat treatment, the solder balls 36 are melted and joined to the electrodes 21. At this time, if a heat treatment is performed at a temperature at which the solder balls 36 melt, the solder bumps 31 also melt. However, since the solder bump 31 has a small volume expansion ratio of 5% or less, the heating may cause the solder bump 31 to enter the interface between the underfill 15 and the semiconductor element 11 and the interface between the underfill 15 and the substrate 12. Never. As a result, a short circuit between the adjacent solder bumps 31 can be prevented, and the mounting reliability can be improved.
[0057]
Further, as described above, in the present embodiment, when the solder ball 36 is joined to the electrode 21, the solder ball 36 is heated to a higher temperature due to the melting point of the solder bump 31 for connection.
[0058]
As described above, the metal material forming the solder bump 31 is a material obtained by adding Bi to Sn. However, in a material in which Bi is added to Sn, Sn and Bi are separated due to the heat treatment performed when the underfill 15 (thermosetting resin) is formed, and the solder structure is coarsened. Such a coarsened structure tends to reduce the fatigue life.
[0059]
For this reason, in the present embodiment, by heating and melting at a higher temperature than the melting point of the bump 31 at the time of the secondary mounting, the structure coarsened by the heat history at the time of forming the underfill 15 can be reduced to a fine structure with high fatigue resistance. The organization has improved. Thereby, the bonding reliability between the solder bump 31 and the substrate 12 can be further improved.
[0060]
There is no problem even if the solder bumps 31 and the solder balls 36 are made of the same material. Further, as described above, when the solder bumps 31 and the solder balls 36 are made of different materials, it is possible to select a material having a melting point higher than the melting point of the solder bumps 31 when selecting the material of the solder balls 36. Thus, the degree of freedom in selecting the material of the solder ball 36 can be increased.
[0061]
Next, a description will be given of an embodiment in which the inventor has actually performed a mounting process using the semiconductor device 30 according to the above-described invention.
[0062]
Embodiment 1
Sn-2.6Ag, Sn-3Ag-0.5Cu, Sn-37Pb, Sn-30Bi, Sn-40Bi, Sn-57Bi, Sn-57Bi-0.5Ag, Sn-57Bi-0.9Ag, Sn-57Bi-2.5Ag solder The densities of the nine types were measured at room temperature and 250 ° C. by a pycnometer method, and the volume expansion coefficient was determined from the densities. In addition, the pycnometer method is to put a sample and a dispersion medium in a cell, perform degassing for infiltrating the liquid between the pores and particles of the sample, then add the liquid to a certain liquid level, weigh, The method is to measure the liquid temperature at that time. According to this method, the specific gravity can be obtained from the weight of the liquid replaced by the sample.
[0063]
The results are shown in Table 1 below.
[0064]
[Table 1]
Figure 2004207494
From Table 1 above, it can be seen that the volume expansion coefficient can be reduced by adding Bi to Sn. Furthermore, it turns out that volume expansion can be suppressed substantially by adding Ag.
[Example 2]
A solder paste in which Sn-57Bi solder powder was mixed with a flux at a weight ratio of 90:10 was printed on a silicon substrate having pits formed by etching, and solder balls were produced by nitrogen reflow at a peak temperature of 200 ° C.
[0065]
This solder ball was aligned on an electrode of a semiconductor element having a square of 14 mm, φ100 μm, and pitch of 250 μm, and a solder bump was formed on the semiconductor element by nitrogen reflow at a peak temperature of 200 ° C. Further, the bumps were aligned with a 40 mm glass ceramic BGA circuit board supplied with a flux, and a flip chip joined body was produced by nitrogen reflow at a peak temperature of 200 ° C. Thereafter, an underfill agent was supplied between the chip substrates on a hot plate at 70 ° C., and was cured at 100 ° C. for 1 hour.
[0066]
With respect to this sample, a reload at a maximum temperature of 250 ° C. was performed five times in consideration of ball attachment and secondary mounting, and a heat load was applied. With respect to the sample, the resistance at the junction of the primary mounting was measured. As a result, a good solder joint without a short circuit was obtained.
For comparison, as a result of a test of a sample manufactured using a semiconductor element having a solder bump formed with a Sn-3Ag-0.5Cu solder ball, 7 out of 15 short circuits occurred after 5 reflows.
[0067]
【The invention's effect】
As described above, according to the present invention, the following various effects can be realized.
[0068]
According to the first, second, third, and fifth aspects of the present invention, since the volume change during heating of the first connection member is as small as 5% or less, the first connection member is melted by heating during the secondary mounting. However, no short circuit occurs between the solder bumps, and the reliability of the electronic device can be improved.
[0069]
According to the fourth aspect of the present invention, it is possible to use a conventional solder processing apparatus for connecting the first connecting member, and it is possible to reduce equipment costs.
[0070]
According to the invention of claim 6, when selecting the second connection member, it is possible to select a material having a melting point higher than the melting point of the first connection member. Can be increased.
[0071]
According to the seventh aspect of the present invention, even if the third connection member made of a different material from the first connection member is provided on the electrode of the member to be provided, the first connection member and the third connection member can be provided. Since the joining metal material with the connecting member exhibits the characteristics of the first connecting member, even if the joining metal material is melted by heating, no short-circuit occurs between the solder bumps, and thus the reliability of the electronic device is improved. Can be enhanced.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a semiconductor device which is an example of a related art.
FIG. 2 is a view for explaining volume expansion occurring in a conventional solder.
FIG. 3 is a diagram illustrating a configuration and a mounting method of a semiconductor device according to one embodiment of the present invention;
FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating a method for mounting a semiconductor device according to an embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 Semiconductor element 12 Substrate 13 Lid 14, 31 Solder bump 15 Underfill 16, 36 Solder ball 20 Mounting substrate 21 Electrode 22, 33 Solder paste 30 Semiconductor device 32 Upper electrode

Claims (7)

電子素子と、
該電子素子が配設される被配設部材と、
前記電子素子と前記被配設部材とを電気的に接続する第１の接続部材と、
前記被配設部材を電気的に外部接続する第２の接続部材と、
前記電子素子と前記被配設部材との間に設けられる樹脂材とを具備する電子装置において、
前記第１の接続部材の材料として、固体時体積と溶融時体積との体積差の、前記固体時体積に対する割合が、５パーセント以下であるはんだ合金を用いたことを特徴とする電子装置。Electronic elements,
A member on which the electronic element is provided;
A first connection member that electrically connects the electronic element and the member to be disposed;
A second connection member for electrically connecting the member to be externally connected;
An electronic device comprising: a resin material provided between the electronic element and the member to be provided;
An electronic device, wherein a solder alloy is used as a material of the first connection member, wherein a ratio of a volume difference between a solid volume and a molten volume to the solid volume is 5% or less. 請求項１記載の電子装置において、
前記第１の接続部材の材料は、ビスマスを15重量パーセント以上80重量パーセント以下、残りが錫であるはんだ合金であることを特徴とする電子装置。The electronic device according to claim 1,
The electronic device according to claim 1, wherein a material of the first connection member is a solder alloy in which bismuth is contained in an amount of 15% by weight or more and 80% by weight or less, and the balance is tin. 請求項１記載の電子装置において、
前記第１の接続部材の材料は、ビスマスを15重量パーセント以上80重量パーセント以下、銀を0.5重量パーセント以上３重量パーセント以下、残りが錫であるはんだ合金であることを特徴とする電子装置。The electronic device according to claim 1,
The electronic device according to claim 1, wherein a material of the first connection member is a solder alloy containing bismuth in a range of 15% by weight to 80% by weight, silver in a range of 0.5% by weight to 3% by weight, and a balance of tin. 請求項１乃至３のいずれか１項に記載の電子装置において、
前記第１の接続部材の融点が130℃以上200℃以下であることを特徴とする電子装置。The electronic device according to any one of claims 1 to 3,
An electronic device, wherein the melting point of the first connection member is 130 ° C. or more and 200 ° C. or less. 請求項１乃至４のいずれか１項に記載の電子装置において、
前記第１の接続部材は、前記電子素子の電極に設けられたバンプ、または前記被配設部材、または前記電子素子と前記被配設部材の両方の電極上に設けられたバンプであることを特徴とする電子装置。The electronic device according to any one of claims 1 to 4,
The first connection member may be a bump provided on an electrode of the electronic element, or the provided member, or a bump provided on both electrodes of the electronic element and the provided member. Electronic device characterized by. 請求項１乃至５のいずれか１項に記載の電子装置に設けられた第２の接続部材を基板に接合することにより、前記電子装置を前記基板に実装する電子装置の実装方法であって、
前記第２の接続部材を前記基板に接続する際、前記第１の接続部材の融点より高い温度に加熱して接続することを特徴とする電子装置の実装方法。A mounting method for an electronic device, comprising: bonding a second connection member provided on the electronic device according to claim 1 to a substrate, thereby mounting the electronic device on the substrate.
A method of mounting an electronic device, comprising: connecting the second connection member to the substrate by heating to a temperature higher than a melting point of the first connection member. 請求項１乃至５のいずれか１項に記載の電子装置の製造方法であって、
前記被配設部材の電極に、前記第１の接続部材とは異なる材質よりなり、かつ前記第１の接続部材の体積より小さい体積の第３の接続部材を配設する工程と、
前記第１の接続部材と前記第３の接続部材とを接合させることにより前記電子素子を前記被配設部材に配設する工程を含むことを特徴とする電子装置の製造方法。A method for manufacturing an electronic device according to claim 1, wherein:
Disposing a third connection member made of a material different from that of the first connection member and having a smaller volume than the volume of the first connection member on the electrode of the disposed member;
A method of manufacturing an electronic device, comprising a step of disposing the electronic element on the member to be disposed by joining the first connection member and the third connection member.
JP2002374966A 2002-12-25 2002-12-25 Electronic device, electronic device mounting method, and electronic device manufacturing method Expired - Fee Related JP4022139B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002374966A JP4022139B2 (en) 2002-12-25 2002-12-25 Electronic device, electronic device mounting method, and electronic device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002374966A JP4022139B2 (en) 2002-12-25 2002-12-25 Electronic device, electronic device mounting method, and electronic device manufacturing method

Publications (3)

Publication Number Publication Date
JP2004207494A true JP2004207494A (en) 2004-07-22
JP2004207494A5 JP2004207494A5 (en) 2006-01-19
JP4022139B2 JP4022139B2 (en) 2007-12-12

Family

ID=32812835

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002374966A Expired - Fee Related JP4022139B2 (en) 2002-12-25 2002-12-25 Electronic device, electronic device mounting method, and electronic device manufacturing method

Country Status (1)

Country Link
JP (1) JP4022139B2 (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007018288A1 (en) 2005-08-11 2007-02-15 Senju Metal Industry Co., Ltd. Lead free solder paste and application thereof
JP2007123478A (en) * 2005-10-27 2007-05-17 Shindengen Electric Mfg Co Ltd Chip-carrier package
JP2009054790A (en) * 2007-08-27 2009-03-12 Oki Electric Ind Co Ltd Semiconductor device
JP2009224700A (en) * 2008-03-18 2009-10-01 Fujitsu Ltd Jointing material and jointing method using it
JP2009302539A (en) * 2008-06-16 2009-12-24 Intel Corp Processing method for low profile solder grid array, device, and computer system
US7759793B2 (en) 2004-12-13 2010-07-20 Renesas Technology Corp. Semiconductor device having elastic solder bump to prevent disconnection
JP2010161419A (en) * 2010-04-19 2010-07-22 Sony Corp Method of manufacturing semiconductor device
US7785024B2 (en) 2005-07-25 2010-08-31 Olympus Corporation Imaging apparatus and method of manufacturing the same
JP2011134750A (en) * 2009-12-22 2011-07-07 Panasonic Electric Works Co Ltd Semiconductor device
JP2012142192A (en) * 2010-12-28 2012-07-26 Fujitsu Component Ltd Connector and solder sheet
JP2014045222A (en) * 2013-12-09 2014-03-13 Fujitsu Ltd Electronic apparatus
WO2021085180A1 (en) * 2019-10-30 2021-05-06 株式会社村田製作所 Electronic component module and method for manufacturing electronic component module

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7951701B2 (en) 2004-12-13 2011-05-31 Renesas Electronics Corporation Semiconductor device having elastic solder bump to prevent disconnection
US8101514B2 (en) 2004-12-13 2012-01-24 Renesas Electronics Corporation Semiconductor device having elastic solder bump to prevent disconnection
US7759793B2 (en) 2004-12-13 2010-07-20 Renesas Technology Corp. Semiconductor device having elastic solder bump to prevent disconnection
US7785024B2 (en) 2005-07-25 2010-08-31 Olympus Corporation Imaging apparatus and method of manufacturing the same
EP1914035A1 (en) * 2005-08-11 2008-04-23 Senju Metal Industry Co., Ltd. Lead free solder paste and application thereof
JP4894758B2 (en) * 2005-08-11 2012-03-14 千住金属工業株式会社 Lead-free solder paste and its application
EP1914035A4 (en) * 2005-08-11 2009-09-09 Senju Metal Industry Co Lead free solder paste and application thereof
WO2007018288A1 (en) 2005-08-11 2007-02-15 Senju Metal Industry Co., Ltd. Lead free solder paste and application thereof
US8227536B2 (en) 2005-08-11 2012-07-24 Senju Metal Industry Co., Ltd. Lead-free solder paste and its use
CN101232967B (en) * 2005-08-11 2010-12-08 千住金属工业株式会社 Lead free solder paste used for electronic component, soldering method and the electronic component
JP2007123478A (en) * 2005-10-27 2007-05-17 Shindengen Electric Mfg Co Ltd Chip-carrier package
JP2009054790A (en) * 2007-08-27 2009-03-12 Oki Electric Ind Co Ltd Semiconductor device
JP2009224700A (en) * 2008-03-18 2009-10-01 Fujitsu Ltd Jointing material and jointing method using it
JP2009302539A (en) * 2008-06-16 2009-12-24 Intel Corp Processing method for low profile solder grid array, device, and computer system
JP2011134750A (en) * 2009-12-22 2011-07-07 Panasonic Electric Works Co Ltd Semiconductor device
JP2010161419A (en) * 2010-04-19 2010-07-22 Sony Corp Method of manufacturing semiconductor device
JP2012142192A (en) * 2010-12-28 2012-07-26 Fujitsu Component Ltd Connector and solder sheet
JP2014045222A (en) * 2013-12-09 2014-03-13 Fujitsu Ltd Electronic apparatus
WO2021085180A1 (en) * 2019-10-30 2021-05-06 株式会社村田製作所 Electronic component module and method for manufacturing electronic component module

Also Published As

Publication number Publication date
JP4022139B2 (en) 2007-12-12

Similar Documents

Publication Publication Date Title
US7145236B2 (en) Semiconductor device having solder bumps reliably reflow solderable
JP4051893B2 (en) Electronics
JP4428448B2 (en) Lead-free solder alloy
US7838954B2 (en) Semiconductor structure with solder bumps
JP4152596B2 (en) Electronic member having solder alloy, solder ball and solder bump
US6802446B2 (en) Conductive adhesive material with metallurgically-bonded conductive particles
JP3689407B2 (en) Method for forming electronic structure
TWI238502B (en) Structure and method for lead free solder electronic package interconnections
KR102517794B1 (en) Solder materials, solder paste, foam solder and solder joint
JP4022139B2 (en) Electronic device, electronic device mounting method, and electronic device manufacturing method
JP2007251053A (en) Mounting structure of semiconductor device and method of manufacturing mounting structure
EP0751847A1 (en) A method for joining metals by soldering
JP4831502B2 (en) Connection terminal balls and connection terminals with excellent drop impact resistance and electronic components
JP2002261104A (en) Semiconductor device and electronic equipment
US7973412B2 (en) Semiconductor device using lead-free solder as die bonding material and die bonding material not containing lead
JP5630060B2 (en) Solder bonding method, semiconductor device and manufacturing method thereof
JP6969070B2 (en) Solder materials, solder pastes, foam solders and solder fittings
JP2017107955A (en) Electronic device and method of manufacturing electronic device
JP2000101014A (en) Semiconductor device
JP2002076605A (en) Semiconductor module and circuit board for connecting semiconductor device
JP3002965B2 (en) Connection member for surface mounting of electronic components
US9741676B1 (en) Tin-indium based low temperature solder alloy
JP2018140436A (en) Solder material, solder paste, foam solder and solder joint
JP2012061508A (en) Joining material
JP5083000B2 (en) Electronic component device and method of manufacturing electronic component device

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051130

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051130

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070625

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070703

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070830

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070925

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070928

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101005

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101005

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111005

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111005

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121005

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121005

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131005

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees