JP2004288779A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent imperfect gate insulation of an LDMOS (Laterally Diffused Metal Oxide Semiconductor) FET. <P>SOLUTION: After a gate insulation film 7a is formed on a semiconductor substrate 1, the gate electrode 8 of a power n channel LDMOS FETQn is formed on the gate insulation film 7a. Continuously, a thin insulating film 15 is laid to cover the gate electrode 8 and the surface of the semiconductor substrate 1 on the semiconductor substrate 1. After that, impurities for forming n<SP>+</SP>type semiconductor regions for the source and the drain of the power n channel LDMOS FETQn are introduced in the semiconductor substrate 1 in the state that the thin insulating film 15 is still left. As a result, the gate insulation film 7b in the vicinity of the end of the gate electrode 8 of a source side can be protected with the insulating film 15 when the impurities for forming the source and the drain are introduced, and the gate insulation film 7b can be protected from damaging or the like, so that imperfect gate insulation of the power n channel LDMOS FETQn can be prevented. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device technology, and more particularly to a method of manufacturing a semiconductor device having an LDMOS • FET (Laterally Diffused Metal Oxide Semiconductor / Field Effect Transistor) and a technology effective when applied to a semiconductor device. It is.
[0002]
[Prior art]
The method of forming an n-channel LDMOS-FET studied by the present inventors is, for example, as follows. First, a p-well serving as a channel region of an LDMOS-FET is formed on a semiconductor substrate made of p-type silicon. Subsequently, after a gate insulating film is formed on the main surface of the semiconductor substrate, a conductor film made of a polycrystalline silicon film or the like is deposited thereon, and the gate electrode is formed by patterning the conductor film. Then, after performing a light oxidation treatment on the semiconductor substrate, n is self-aligned with the end of the gate electrode. ⁻ A semiconductor region of a mold is formed on a semiconductor substrate. Then, n for source and drain ⁺ A semiconductor region of a mold is formed on a semiconductor substrate. At this time, n ⁺ The type semiconductor region is formed in a self-aligned manner with respect to the gate electrode so that the end thereof substantially coincides with the end of the gate electrode. N for drain ⁺ The end of the type semiconductor region is the above-mentioned n from the end of the gate electrode. ⁻ It is formed so as to be separated by the semiconductor region of the mold.
[0003]
The configuration of a high-frequency power module using this type of LDMOS • FET is disclosed in, for example, Japanese Patent Application Laid-Open No. 2002-111415 (for example, Patent Document 1).
[0004]
[Patent Document 1]
JP-A-2002-111415
[0005]
[Problems to be solved by the invention]
By the way, the present inventor, when forming a high-gain amplifier circuit, lowers the on-resistance of the LDMOS-FET constituting the amplifier circuit, and introduces a gate to the source region when introducing impurities for forming a source region and a drain region. When formed in a self-aligned manner with respect to the electrode end position and introducing a high-concentration impurity into the semiconductor substrate, damage and impurity levels occur in the gate insulating film near the gate electrode end on the source region side. As a result, it has been found for the first time that a defect (hereinafter referred to as a gate insulating defect) in which a leak current flows between the gate electrode and the semiconductor substrate due to the damage or the impurity level occurs.
[0006]
An object of the present invention is to provide a technique capable of suppressing or preventing gate insulation failure of a lateral field-effect transistor.
[0007]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0008]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0009]
That is, according to the present invention, after a gate electrode of an LDMOS-FET is patterned on a semiconductor substrate, a thin insulating film covering the gate electrode and the surface of the semiconductor substrate is deposited on the semiconductor substrate, and further, a source and a drain are formed. And a step of introducing impurities for forming a semiconductor region into the semiconductor substrate while leaving the thin insulating film.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Before describing the embodiments of the present invention in detail, the meanings of terms in the present embodiment will be described as follows.
[0011]
1. GSM (Global System for Mobile Communication) refers to one or a standard of wireless communication systems used in digital mobile phones. GSM has three radio frequency bands to be used. The 900 MHz band is GSM900 or simply GSM, the 1800 MHz band is GSM1800 or DCS (Digital Cellular System) 1800 or PCN, the 1900 MHz band is GSM1900 or DCS1900 or PCS (Personal Communication Services). ). GSM1900 is mainly used in North America. In North America, GSM850 in the 850 MHz band may be used.
[0012]
2. The GMSK modulation method is a method used for communication of a voice signal, and is a method of shifting the phase of a carrier wave according to transmission data.
[0013]
3. The EDGE modulation method is a method used for data communication, in which a phase shift of GMSK modulation is further added with an amplitude shift.
[0014]
In the following embodiments, when necessary for the sake of convenience, the description will be made by dividing into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other and one is the other. In some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), a case where it is particularly specified, and a case where it is clearly limited to a specific number in principle, etc. However, the number is not limited to the specific number, and may be more than or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified, and when it is deemed essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of the constituent elements, the shapes are substantially the same unless otherwise specified and in cases where it is considered that it is not clearly apparent in principle. And the like. This is the same for the above numerical values and ranges. In all the drawings for describing the present embodiment, components having the same function are denoted by the same reference numerals, and repeated description thereof will be omitted. Further, in some drawings used in the present embodiment, hatching is used even in a plan view so as to make the drawings easy to see. Further, in this embodiment, a MOS / FET (Metal Oxide Semiconductor / Field Effect Transistor), which is a typical example of a field effect transistor, is abbreviated as MOS, a p-channel MOS is abbreviated as a pMOS, and an n-channel MOS is an nMOS. Abbreviated. Further, an n-channel type LDMOS • FET (Laterally Diffused MOSFET), which is a lateral field-effect transistor, is abbreviated as nLDMOS, and a p-channel type LDMOS • FET is abbreviated as pLDMOS.
[0015]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
(Embodiment 1)
First, a problem found by the present inventors will be described. For example, a reduction in on-resistance is required for an LDMOS constituting an amplifier of an RF (Radio Frequency) power module used for a mobile communication device such as a mobile phone. This is to improve the load efficiency of the RF signal (the ratio between the input signal and the output signal to the RF power module) and to realize a high gain amplifier. Another purpose is to reduce power consumption by reducing a voltage drop due to on-resistance in a device having a low power supply voltage. In developing the above-mentioned RF power module, the present inventor, in order to lower the on-resistance of the LDMOS constituting the RF power module, introduces the source region with respect to the gate electrode when introducing impurities for forming the source and drain regions of the LDMOS. When formed in a consistent manner and high-concentration impurities are introduced into a semiconductor substrate (hereinafter simply referred to as a substrate), a problem arises in that the occurrence rate of the gate insulation failure increases in a reliability test. The cause is caused by damage, impurity levels, etc. (hereinafter simply referred to as damage, etc.) generated in the gate insulating film near the end of the gate electrode on the source region side during the introduction of impurities for forming the source region and the drain region. This has been found by the present inventors.
[0017]
FIG. 1 is a partial cross-sectional view of the substrate 80 for explaining the mechanism of occurrence of the damage and the like. On the main surface of the substrate 80, for example, silicon oxide (SiO 2) ₂ The gate electrode 82 of the nLDMOS is patterned via a gate insulating film 81 made of the same. The vicinity of the end of the gate electrode 82 on the drain region side of the nLDMOS is partially covered with a photoresist pattern (hereinafter, simply referred to as a resist pattern) 83. On the other hand, the end of the gate electrode 82 on the source region side of the nLDMOS is exposed. This is because if the end of the source region is too far from the end of the gate electrode 82, the on-resistance of the nLDMOS increases, so that the end of the source region overlaps with the end of the gate electrode 82 to prevent this. This is because the source region is formed in a self-alignment manner with the gate electrode 82 so as to (substantially match).
[0018]
In this state, when impurities for forming the source region and the drain region are introduced into the substrate 80, a portion of the gate insulating film 81 near the end of the gate electrode 82 on the source region side (region A indicated by a broken line) is exposed. Therefore, it is affected by the collision of impurity ions. As a result, the above-described damage or the like occurs in the gate insulating film 81 near the end of the gate electrode 82 on the source region side, and a leak current flows between the gate electrode 82 and the substrate 80 through the damage or the like. In particular, since the electric field tends to concentrate at the corner at the lower end of the gate electrode 82, if there is damage or the like in the vicinity of the gate insulating film 81, the problem of leakage current is likely to occur. Therefore, at present, a burn-in test (for example, 125 ° C., 2 to 4 hours, application of a power supply voltage of 5.2 V) is performed after the assembly process of the RF power module, thereby removing initial defects and corresponding to mass production. However, this test has a problem that the rate of occurrence of gate insulation failure is high (for example, 1000 ppm (parameter: about 40,000)), and that the burn-in test requires much time and cost.
[0019]
The cause of the above-mentioned damage and the like is that, in order to lower the on-resistance of the LDMOS, the dose of impurities at the time of forming a high-concentration region for the source and drain of the LDMOS is higher by one digit than that of a general LDMOS. 10 ^Fifteen / Cm ² It is mentioned that it is a stand. In order to reduce the ON resistance while maintaining the fine dimensions of the LDMOS, arsenic (As) having a large atomic weight (mass) is used as an impurity, and a source region with a high impurity concentration is formed at a shallow position on the main surface of the substrate 80. However, the greater the atomic weight of the impurity, the greater the degree of the damage and the like. Therefore, the use of an impurity with a large atomic weight is also a major cause of the above problem.
[0020]
Therefore, in the first embodiment, at the time of introducing the impurity for forming the source region of the LDMOS, the gate electrode is located near the end of the gate electrode on the source region side (at least near the corner at the lower end of the gate electrode). A protection member for protecting the gate insulating film near the portion is formed. This can reduce or prevent damage to the gate insulating film near the end of the gate electrode on the source region side (especially near the corner of the lower end of the gate electrode), thereby reducing the occurrence of the above-described gate insulation failure. Can be suppressed or prevented. Therefore, a highly reliable RF power module can be provided while maintaining the electrical characteristics (RF characteristics, DC characteristics, high gain, on-resistance). Further, the yield of the RF power module can be improved. Furthermore, since the burn-in test can be eliminated, the manufacturing time of the RF power module can be reduced, and the cost can be significantly reduced.
[0021]
Meanwhile, as a specific method, a method in which an impurity is introduced in a state where a so-called sidewall is formed on a side surface of the gate electrode is considered. Hereinafter, an example of the method and the problems will be described with reference to cross-sectional views of main parts of the semiconductor device of FIGS.
[0022]
First, as shown in FIG. 2, after a gate insulating film Gox and a gate electrode GP are formed on a main surface of a substrate Sub made of p-type silicon (Si) single crystal, these are used as a part of a mask, for example, phosphorus. Is implanted into the substrate Sub by n. ⁻ Type semiconductor region NMA is formed in self-alignment with gate electrode GP. Subsequently, as shown in FIG. 3, after an insulating film IFS is deposited on the main surface of the substrate Sub by a CVD (Chemical Vapor Deposition) method, this is etched back by an anisotropic dry etching method. As shown in FIG. 4, a sidewall IFSW is formed on the side surface of the gate electrode GP. At this time, the main surface of the substrate Sub not covered with the gate electrode GP and the gate insulating film Gox are damaged by dry etching (indicated by x). Thereafter, while leaving the damage and the like, as shown in FIG. 5, the resist pattern RPA exposes the source region on the main surface of the substrate Sub and covers a part of the drain region near the end of the gate electrode GP. Is formed, for example, arsenic (As) is introduced to introduce n for the source. ⁺ Semiconductor region NSA and n for drain ⁺ A semiconductor region of a mold is formed. At this time, n for source ⁺ Since the sidewall IFSW is formed on the side surface of the gate electrode GP on the side of the semiconductor region NSA of the mold type, n for the source is formed. ⁺ Direct collision of impurity ions with the gate insulating film Gox near the end of the gate electrode GP on the side of the semiconductor region NSA of the mold type can be avoided, and the gate insulating film Gox near the end of the gate electrode GP is protected. Therefore, occurrence of the above-described gate insulation failure can be suppressed or prevented. However, in the case of this method, the etch back process for forming the sidewall IFSW has a large effect due to damage or the like generated on the main surface of the substrate Sub and the gate insulating film Gox, such as a decrease in drain withstand voltage and an increase in on-resistance. , The electrical characteristics of the LDMOS deteriorate. It is difficult to quantitatively grasp the damage and the like of the substrate Sub main surface and the gate insulating film Gox due to such an etch back, and it is difficult to control the etch back so as not to cause the damage or the like. It is difficult. Also, since the sidewall IFSW is generally wide (about 400 nm), n ⁺ As a result of the end of the semiconductor region NSA of the type being far from the end of the gate electrode GP, there is a problem that the on-resistance of the nLDMOS increases. This problem goes against the original idea of obtaining a high gain amplifier by reducing the on-resistance. Further, there is a problem that the number of manufacturing steps increases because an etch-back step is added.
[0023]
Therefore, in the first embodiment, a method that can further avoid the problem that occurs when the above-described sidewall process is used will be described with reference to the flowchart of FIG. 6 and the cross-sectional views of the main parts during the manufacturing process of the semiconductor device of FIGS. explain. Here, for example, a manufacturing process of a semiconductor chip for an amplifier of an RF (Radio Frequency) power module used for a digital mobile phone that transmits information using a network of a GSM (Global System for Mobile Communication) system is described as an example. A method for manufacturing the semiconductor device according to the first embodiment will be described. 7 to 17 (excluding FIG. 14), the left side illustrates a power nLDMOS formation region for an amplifier, for example, and the right side illustrates a standard pLDMOS formation region for a switching element, for example.
[0024]
First, as shown in FIG. 7, the substrate 1 is prepared. The substrate 1 at this stage is made of a substantially circular member in a plane called a semiconductor wafer, and includes a substrate body 1a, a semiconductor layer 1b formed on a main surface thereof, and an insulating layer 2 formed on a back surface of the substrate body 1a. have. The substrate main body 1a is formed by a p-type crystal formed by a crystal pulling method such as the Czochralski method. ⁺ It is made of a silicon (Si) single crystal of a mold, and its resistivity is, for example, about 3 to 6 mΩcm. The semiconductor layer 1b is made of, for example, a p-type silicon single crystal formed by an epitaxial method, has a thickness of, for example, about 3 μm, and has a resistivity of, for example, about 18 Ωcm to 23 Ωcm. The insulating layer 2 on the back surface of the substrate 1 is made of, for example, silicon oxide (SiO 2) formed by a CVD method. ₂ Etc.) and has a function of protecting the back surface of the substrate 1 from contamination, breakage, and the like. Subsequently, after a resist pattern is formed on the main surface of the semiconductor layer 1b by photolithography, impurity ions such as boron (B) are selectively introduced into the semiconductor layer 1b using the resist pattern as a mask. Thus, p ⁺⁺ A semiconductor region 3 of a mold is formed. The semiconductor region 3 is formed so as to reach from the main surface of the semiconductor layer 1b to the substrate main body 1a, and is electrically connected to the substrate main body 1a. Thereafter, after removing the resist pattern, a field insulating film 4 made of, for example, silicon oxide is formed on the main surface of the semiconductor layer 1b by LOCOS (Local Oxidation of Silicon). The region where the field insulating film 4 is formed can be defined as an isolation region, and the other region can be defined as an element formation region (active region).
[0025]
Next, a resist pattern is formed by photolithography on the main surface of the semiconductor layer 1b so that the standard pLDMOS formation region is exposed and the rest is covered, and then the resist pattern is used as a mask to form, for example, phosphorus (P) or the like. By selectively introducing such impurity ions into the semiconductor layer 1b, an n-well 5 is formed in the standard pLDMOS formation region. Subsequently, after removing the resist pattern for forming the n-well 5, a resist pattern RP1 is formed on the main surface of the semiconductor layer 1b such that a part of the power nLDMOS formation region is exposed and the other part is covered by a photolithography technique. Then, using the resist pattern RP1 as a mask, impurity ions such as boron are selectively introduced into the semiconductor layer 1b to form a p-well (first semiconductor region) 6 in the power nLDMOS formation region. I do. The p-well 6 is also a portion that becomes a channel region of the power nLDMOS (step PWLP in FIG. 6).
[0026]
Next, after removing the resist pattern RP1, the substrate 1 is subjected to a cleaning treatment to expose a clean main surface of the semiconductor layer 1b, for example, by performing a wet oxidation treatment, as shown in FIG. Next, a gate insulating film 7a made of, for example, silicon oxide having a thickness of about 11 nm is formed on the main surface of the active region of the semiconductor layer 1b (step GOXP in FIG. 6). Subsequently, on the main surface of the substrate 1, for example, a conductive film such as low-resistance polycrystalline silicon or the like, tungsten silicide (WSi ₂ ) And a cap insulating film such as silicon oxide are deposited in order from the bottom by a CVD method or the like, and then patterned by a photolithography technique and a dry etching technique to form a power nLDMOS formation region and a standard. A gate electrode 8 and a cap insulating film 9 are formed in the pLDMOS formation region. The gate electrode 8 has a laminated structure of a low-resistance polycrystalline silicon film and a tungsten silicide film. Instead of the tungsten silicide film, a barrier metal film such as titanium nitride (TiN) and tungsten (W) are used. ) May be sequentially laminated from the lower layer (step GP in FIG. 6). Thereafter, by subjecting the substrate 1 to a light oxidation treatment, as shown in FIG. 9, the edge of the gate insulating film 7a slightly etched in the step of forming the gate electrode 8 is repaired. At this time, a gate insulating film 7b is formed on the active surface main surface of substrate 1 around gate electrode 8. The gate insulating film 7b is made of, for example, silicon oxide and is formed thicker than the gate insulating film 7a (step LOXP in FIG. 6).
[0027]
Next, as shown in FIG. 10, a resist pattern RP2 is formed on the main surface of the substrate 1 by photolithography so that the drain region of the standard pLDMOS formation region is exposed and the other region is covered by a photolithography technique. As, for example, di-fucca boron (BF ₂ ) Is implanted into the semiconductor layer 1b, so that the drain region of the standard pLDMOS formation region has a drain p. ⁻ The semiconductor region 12a is formed (LDD (Lightly Doped Drain) structure). At this time, the implantation energy of the impurity ions is, for example, about 30 KeV, and the dose is, for example, 10 keV. ¹² / Cm ² (Step PMP in FIG. 6). Subsequently, after removing the resist pattern PR2, as shown in FIG. 11, a resist pattern RP3 is formed on the main surface of the substrate 1 so that the drain region of the power nLDMOS formation region is exposed and the rest is covered by photolithography. After the formation by the technique, using this as a mask, for example, phosphorus is ion-implanted into the semiconductor layer 1b to form a drain n in the drain region of the power nLDMOS formation region. ⁻ A semiconductor region (second semiconductor region) 13a is formed (LDD structure). n ⁻ The semiconductor region 13a of the mold is formed such that its end overlaps (substantially coincides with) the end of the gate electrode 8 on the drain side. At this time, the implantation energy of the impurity ions is, for example, about 50 KeV, and the dose is, for example, 10 keV. ^Thirteen / Cm ² (Step NMP in FIG. 6). Thereafter, after removing the resist pattern RP3, an annealing process is performed on the substrate 1 (step SG / ANP in FIG. 6).
[0028]
Next, as shown in FIG. 12, a thin insulating film 15 made of, for example, silicon oxide or the like is deposited on the main surface of the substrate 1 by a CVD method or the like. This insulating film 15 is deposited so as to cover the field insulating film 4 on the main surface of the substrate 1, the gate insulating film 7b, the side surfaces of the gate electrode 8, the side surfaces and the upper surface of the cap insulating film 9. That is, the insulating film 15 is formed to protect the gate insulating film 7b near the end of the gate electrode 8. The thickness of the insulating film 15 (that is, the width of the portion of the insulating film 15 provided on the side surface of the gate electrode 8) is smaller than the width of the sidewall, for example, about 15 nm (step NTHDP in FIG. 6). Subsequently, as shown in FIGS. 13 and 14, on the main surface of the substrate 1 (on the insulating film 15), the source region and the drain region of the power nLDMOS formation region (the drain region is slightly apart from the end of the gate electrode 8). Is formed, and arsenic (As) is ion-implanted into the semiconductor layer 1b using the resist pattern RP4 as a mask. That is, impurity ions are implanted while the insulating film 15 is formed as described above. Thereby, the n for drain of the power nLDMOS formation region is provided in the semiconductor layer 1b. ⁺ Type semiconductor region (third semiconductor region) 13b and n for source ⁺ A semiconductor region (fourth semiconductor region) 13c is formed. N for drain ⁺ Type semiconductor region 13b has an end portion corresponding to the n ⁻ It is formed at a position separated from the gate electrode 8 by the semiconductor region 13a of the mold. Also, n for the source ⁺ As shown in FIG. 14, the end of the semiconductor region 13c is formed at a position away from the gate electrode 8 by a length L1 corresponding to the thickness of the insulating film 15. N for this drain and source ⁺ Energy of impurity ions at the time of forming the semiconductor regions 13b and 13c is, for example, about 100 KeV, and the dose is, for example, 1 × 10 ^Fifteen / Cm ² The ion implantation angle is, for example, about 0 degree (perpendicular to the main surface of the substrate 1). n ⁺ The impurity concentration of the semiconductor regions 13b and 13c is, for example, 1 × 10 ²⁰ / Cm ³ Degree (or more). The reason for using arsenic as an impurity is that arsenic having a large atomic weight (mass) is used, so that a high impurity concentration drain n is formed at a shallow position in the semiconductor layer 1b. ⁺ Semiconductor region 13b and n for the source ⁺ This is because the on-resistance can be reduced while maintaining the fine dimensions of the power nLDMOS by forming the semiconductor region 13c of the mold type. The power nLDMOS Qn is formed as described above. The power nLDMOSQn is, for example, an element configuring an amplifier of an RF power module.
[0029]
As described above, according to the first embodiment, while the gate insulating film 7b near the end of the gate electrode 8 is covered with the insulating film 15, the source and drain n ⁺ By introducing impurity ions for forming the semiconductor regions 13b and 13c of the power type, it is possible to prevent the impurity ions from directly colliding with the gate insulating film 7b near the end of the gate electrode 8 on the source region side of the power nLDMOS Qn. Can be avoided. That is, the gate insulating film 7b near the end of the gate electrode 8 on the source region side of the power nLDMOS Qn can be protected by the insulating film 15. Accordingly, it is possible to suppress or prevent the occurrence of damage or the like in the gate insulating film 7b near the end of the gate electrode 8 on the source region side of the power nLDMOS Qn. Therefore, it is possible to suppress or prevent the gate insulation failure of the power nLDMOS Qn. Also, n for the source ⁺ As shown in FIG. 14, the end of the semiconductor region 13c is separated from the end of the gate electrode 8 by a length L1 corresponding to the thickness of the insulating film 15, and the thickness of the insulating film 15 is as described above. Since the width is extremely small and the length L1 is also small as compared with the width of the sidewall, the on-resistance of the power nLDMOS Qn can be prevented from increasing. FIG. 14 is an enlarged sectional view of a main part of FIG. 13 (step NP in FIG. 6).
[0030]
Next, after removing the resist pattern RP4, while leaving the insulating film 15, the source region and the drain region of the power nLDMOS formation region (the drain region is the gate electrode 8) as shown in FIG. Of the power nLDMOS forming region by forming a resist pattern RP5 such that a portion slightly away from the end of the semiconductor layer 1b is exposed and the other portion is covered, and then using this as a mask, for example, boron is ion-implanted into the semiconductor layer 1b. N for the above drain and source ⁺ On the lower side (mainly on the channel side of the power nLDMOS) of the semiconductor regions 13b and 13c of ⁻ A semiconductor region 17 of a mold is formed. This p ⁻ The semiconductor region 17 is a so-called halo region (or punch-through stopper region) for suppressing or preventing a short channel effect. In this impurity introducing step, impurity ions are implanted from a direction oblique to the main surface of the substrate 1. (Step PHP in FIG. 6).
[0031]
Next, after the resist pattern RP5 is removed, while the insulating film 15 is left, a part of the power nLDMOS formation region, the source and drain regions of the standard pLDMOS formation region are formed on the main surface of the substrate 1 as shown in FIG. After forming a resist pattern RP6 that exposes (a part of the drain region a little away from the end of the gate electrode 8) and covers the rest, using this as a mask, for example, boron is ion-implanted into the semiconductor layer 1b. As a result, the p for the drain of the standard pLDMOS ⁺ Semiconductor region 12b and p for source ⁺ Type semiconductor region 12c and a p-type nLDMOS formation region ⁺ A mold semiconductor region 12d is formed. Thus, a standard pLDMOS Qp is formed. The standard pLDMOS Qp is, for example, an element forming a switching element, and therefore does not require a higher gain than the power nLDMOS Qn. For this reason, the channel length of the standard pLDMOSQp is longer than the channel length of the power nLDMOSQn. Note that p in the power nLDMOS formation region ⁺ Type semiconductor region 12d is ⁺⁺ The semiconductor region 3 is electrically connected to the substrate body 1a through the semiconductor region 3 (step PP in FIG. 6).
[0032]
Next, after removing the resist pattern RP6, the substrate 1 is subjected to an annealing treatment such as, for example, RTA (Rapid Thermal Anneal) (step DI · ANP in FIG. 6). Subsequently, as shown in FIG. 17, an insulating film 20 made of, for example, silicon oxide is deposited on the main surface of the substrate 1 by a CVD method or the like while the insulating film 15 is left. A contact hole CNT reaching the layer 1b is formed by a photolithography technique and a dry etching technique (step IDP and step CNTP in FIG. 6). After that, for example, a titanium nitride (TiN) film is deposited on the main surface of the substrate 1 by a sputtering method, and then a tungsten film is deposited thereon by a CVD method or the like. Subsequently, after the tungsten film is etched back, for example, a titanium (Ti) film, an aluminum (Al) -silicon-copper (Cu) alloy film, a titanium film and a titanium nitride film are formed on the main surface of the substrate 1 from below. The layers are sequentially deposited by a sputtering method. Subsequently, the first layer wiring M1 is formed by patterning the laminated film by a photolithography technique and a dry etching technique (step M1P in FIG. 6). Thereafter, the semiconductor chip for the amplifier is manufactured through a normal semiconductor device manufacturing process. Thereafter, this semiconductor chip is mounted on a module substrate together with other semiconductor chips and electronic components to assemble an RF power module.
[0033]
As described above, according to the first embodiment, n for the source and the drain of the power nLDMOS Qn ⁺ In the step of introducing impurity ions for forming the semiconductor regions 13 b and 13 c of the mold type, the gate insulating film 7 b near the end of the gate electrode 8 on the source region side can be protected by the insulating film 15. It is possible to suppress or prevent the occurrence of damage or the like in the nearby gate insulating film 7b, and it is possible to suppress or prevent the gate insulation failure of the power nLDMOS Qn. Therefore, the yield and reliability of the RF power module can be improved.
[0034]
Further, since the thickness of the insulating film 15 for protection is extremely smaller than the width of the sidewall, the on-resistance of the power nLDMOS Qn can be prevented from increasing. FIG. 18 is a graph simply showing the relationship between the thickness (horizontal axis) of the insulating film 15 and the on-resistance Ron of the nLDMOS Qn and the incidence N of gate insulation failure (vertical axis). As the thickness of the insulating film 15 increases, the gate insulation failure occurrence rate N decreases, but conversely, the on-resistance Ron increases. Therefore, the lower limit of the thickness of the insulating film 15 is determined by the target value of the incidence rate of the gate insulation failure, and the upper limit of the thickness of the insulating film 15 is determined by the target value of the on-resistance Ron. According to the study of the present inventors, the thickness of the insulating film 15 is preferably, for example, about 7 to 40 nm. In particular, from the target value of the on-resistance of the first embodiment (that is, the on-resistance is 1 to 5 Ωmm), the thickness of the insulating film 15 is preferably, for example, about 7 to 23 nm, and more preferably, for example, about 10 to 20 nm. . In the first embodiment, as described above, the thickness of the insulating film 15 is selected to be, for example, 15 nm in the middle of 10 to 20 nm, so that the rate of occurrence of gate insulation failure is reduced to, for example, 150 ppm (parameter of about 40,000). It was reduced to the extent.
[0035]
Further, according to the first embodiment, since there is no etch-back step as in the above-described sidewall process, the main surface of the substrate 80 and the gate insulating film 81 are not damaged, and the power nLDMOS Qn Also, there is no deterioration in electrical characteristics such as a decrease in drain withstand voltage and an increase in on-resistance. Therefore, the performance and reliability of the RF power module can be secured. Further, since an etch-back step such as the above-described sidewall process is not added, the number of steps for manufacturing a semiconductor chip for an amplifier of an RF power module does not increase. Therefore, the manufacturing time and cost of the RF power module do not increase.
[0036]
Also, n for the drain of the standard pLDMOS Qp ⁻ When the step of introducing impurities for forming the semiconductor region 12a of the mold type is performed after the step of forming the insulating film 15 for protection, n ⁻ The end of the semiconductor region 12a of the mold is separated from the end of the gate electrode 8 by the thickness of the insulating film 15, and the on-resistance of the standard pLDMOS Qp increases. Therefore, in the first embodiment, n for the drain of the standard pLDMOS Qp is used. ⁻ By performing the impurity introduction step for forming the semiconductor region 12a of the mold type before the formation step of the insulating film 15 for protection, n ⁻ Since the end of the semiconductor region 12a of the mold can be prevented from separating from the gate electrode 8, an increase in the on-resistance of the standard pLDMOS Qp can be prevented, and good electrical characteristics of the standard pLDMOS Qp can be secured.
[0037]
Next, FIG. 19 shows an example of a digital mobile phone system using the RF power module PM of the first embodiment.
[0038]
The digital mobile phone system 22 can use, for example, two frequency bands of GSM900 and DCS1800 (dual band system), and can use two communication systems of a GMSK modulation system and an EDGE modulation system in each frequency band. MIC for inputting audio, etc., the signal processing circuit unit SPC, the RF power module PM, the switch circuit SWC for switching between transmission and reception, the antenna ANT for transmitting and receiving signal radio waves, and the low noise amplifier LAMP. , And a speaker SP for outputting audio and the like.
[0039]
The signal processing circuit SPC is a circuit that performs various kinds of signal processing, and has a baseband circuit and a modulation / demodulation circuit. The baseband circuit has a function of converting an audio signal into a baseband signal, converting a received signal into an audio signal, generating a modulation scheme switching signal or a band switching signal, and includes a DSP (Digital Signal). (Processor), a microprocessor, a semiconductor memory and the like. The modulation / demodulation circuit has a function of down-converting and demodulating a received signal to generate a baseband signal and modulating a transmission signal.
[0040]
The RF power module PM has a high-frequency power amplifier circuit AMP1 for handling transmission signals in the DCS band of radio waves and a high-frequency power amplifier circuit AMP2 for handling transmission signals in the GSM band of radio waves. Further, a changeover switch is provided so that both the GMSK modulation method and the EDGE modulation method can be used in each of the two frequency bands of GSM900 and DCS1800. FIG. 20 is an explanatory diagram showing basic functions of the RF power module PM. When a signal in the GSM band or an input signal Pin in the DCS band is input, the signal is amplified and an output signal Pout is output. FIG. 21 shows an example of a circuit diagram of the high-frequency power amplifier circuit AMP (AMP1, AMP2) of the RF power module PM. The high-frequency power amplifier circuit AMP of the first embodiment includes, for example, three-stage power nLDMOSs Qn1 to Qn3 (the above power nLDMOSQn), a bias circuit BIAS for applying a bias voltage to these power nLDMOSs Qn1 to Qn3, and matching circuits M1 to M9. , A capacitor, a coil, and a resistor. The output level of the high frequency power amplifier AMP is controlled by the supply voltage from the bias circuit BIAS and the power supply voltage Vdd from the power supply circuit. The power supply voltage Vdd is, for example, about 4.7 V, and is supplied to the drains of the power nLDMOSs Qn1 to Qn3. The bias circuit BIAS has a plurality of resistors. In this circuit, when the control voltage Vabc (when the GMSK method is selected) or the control voltage Vapc (when the EDGE method is selected) is input to the input of the bias circuit BIAS, the voltage is divided by the resistance of the bias circuit BIAS. As a result, a desired gate bias voltage is generated, and the gate bias voltage is input to the gate electrodes of the respective nMOSs Qn1, Qn2, and Qn3.
[0041]
(Embodiment 2)
In the second embodiment, an example in which a step of removing the protective insulating film 15 is added will be described with reference to a flowchart of FIG. 22 and a cross-sectional view of a main part during manufacturing steps of the semiconductor device of FIGS. I do. In FIGS. 23 and 24, the left side illustrates the power nLDMOS formation region, for example, and the right side illustrates the standard pLDMOS formation region, for example.
[0042]
First, the difference from the first embodiment (see FIG. 6) in the process PWLP to the process SG / ANP in FIG. 22 of the second embodiment in FIG. ⁻ That is, there is no step of forming the semiconductor region 12a (step PMP in FIG. 6).
[0043]
Subsequently, also in the second embodiment, similarly to the first embodiment, an insulating film 15 is deposited on the main surface of the substrate 1 as shown in FIG. Although the thickness and the forming method of the insulating film 15 are the same as those in the first embodiment, in the second embodiment, the insulating film 15 is made of, for example, silicon nitride (Si). ₃ N ₄ Etc.) (step NTHDP in FIG. 22).
[0044]
After that, similarly to the first embodiment, after forming the resist pattern RP4 on the main surface (insulating film 15) of the substrate 1, the semiconductor layer 1b is ion-implanted with impurities such as arsenic. N for drain and source of power n LDMOS ⁺ Form semiconductor regions 13b and 13c (Step NP in FIG. 22). Also in the second embodiment, similarly to the first embodiment, the gate insulating film 7b near the end of the gate electrode 8 can be protected by the insulating film 15, so that the gate insulating film 7b near the end of the gate electrode 8 can be protected. Can be suppressed or prevented, and defective gate insulation of the power nLDMOS can be suppressed or prevented.
[0045]
Next, after removing the resist pattern RP4, the insulating film 15 is also made of, for example, hot phosphoric acid (phosphoric acid (H ₃ PO ₄ )) And the like to selectively remove as shown in FIG. 24 (step NTHEP in FIG. 22). In the second embodiment, since the insulating film 15 is a silicon nitride film, only the insulating film 15 can be selectively removed without removing the silicon oxide film of the substrate 1. Further, by using a wet etching method as a method for removing the insulating film 15, the insulating film 15 can be removed without damaging the gate insulating films 7a and 7b and the field insulating film 4 on the main surface of the substrate 1. it can.
[0046]
Subsequently, as described with reference to FIG. 15 of the first embodiment, the p-type ⁻ A semiconductor region 17 of a mold is formed (step PHP in FIG. 22). Thereafter, as described with reference to FIG. 10 (Step PMP in FIG. 6) of the first embodiment, the p ⁻ The semiconductor region 12a of the mold is formed. In the second embodiment, since the insulating film 15 is removed, p ⁻ The step of forming the semiconductor region 12a of the type is performed by the step of depositing the insulating film ⁺ It can be performed after the impurity introduction step for forming the semiconductor regions 13b and 13c of the mold. That is, p ⁻ The step of forming the mold semiconductor region 12a can be performed in a step subsequent to the first embodiment (step PMP in FIG. 22). Thereafter, as described with reference to FIG. ⁺ The semiconductor region 12b of the mold is formed (step PP in FIG. 22). Subsequent steps are the same as in the first embodiment, and a description thereof will be omitted.
[0047]
According to the second embodiment, since the insulating film 15 is removed, the number of steps is increased by that much, but other effects are the same as those of the first embodiment. In addition, the following effects can be obtained.
[0048]
In other words, when the insulating film 15 is left, in the impurity introducing step after the insulating film 15 is deposited, the impurity ion introducing condition is set in consideration of the thickness of the insulating film 15 or the order of the steps is changed. However, in the second embodiment, since the insulating film 15 is removed, the effect that such a need does not occur can be obtained.
[0049]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.
[0050]
For example, in the first and second embodiments, the power nLDMOS of the RF power module is provided in three stages, but may be formed in a two-stage configuration or a four-stage configuration.
[0051]
In the first and second embodiments, the case where the present invention is applied to a power nLDMOS is described. However, the present invention can be applied to a power pLDMOS.
[0052]
In the first and second embodiments, the case where the present invention is applied to a dual band system capable of handling radio waves in two frequency bands, GSM900 and DCS1800, has been described. In addition to the above two frequency bands, for example, The present invention may be applied to a so-called triple band system that can handle radio waves in the PCS band.
[0053]
In the above description, the case where the invention made by the present inventor is applied to a digital mobile phone, which is the field of use as the background, has been described. However, the present invention is not limited to this case, and for example, PDA (Personal Digital Assistants) The present invention can also be applied to an information processing apparatus having a mobile communication function such as described above and an information processing apparatus such as a personal computer.
[0054]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0055]
That is, after patterning a gate electrode of an LDMOS • FET on a semiconductor substrate, a thin insulating film covering the gate electrode and the surface of the semiconductor substrate is deposited on the semiconductor substrate, and further, a semiconductor region for source and drain is formed. Is introduced into the semiconductor substrate while leaving the thin insulating film, the gate insulating film near the gate electrode end can be protected by the thin insulating film when the impurity is introduced, and the gate electrode end Since it is possible to suppress or prevent damage and impurity levels from being generated in the nearby gate insulating film, it is possible to suppress or prevent the gate insulation failure of the LDMOS • FET.
[Brief description of the drawings]
FIG. 1 is a partial cross-sectional view of a semiconductor substrate for explaining a mechanism of occurrence of damage to a gate insulating film and the like.
FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step studied by the present inventors;
3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2;
FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3;
5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4;
FIG. 6 is a flowchart of a manufacturing process of the semiconductor device according to the embodiment of the present invention;
FIG. 7 is a fragmentary cross-sectional view of the semiconductor device according to the embodiment of the invention during a manufacturing step;
8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7;
9 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8;
10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9;
11 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 10;
12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11;
13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12;
FIG. 14 is an enlarged cross-sectional view of a main part during a manufacturing step of the semiconductor device of FIG. 13;
FIG. 15 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIGS. 13 and 14;
16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15;
17 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 16;
FIG. 18 briefly shows the relationship between the thickness of a protective insulating film (horizontal axis) of a semiconductor device according to an embodiment of the present invention, the on-resistance of a lateral transistor, and the rate of occurrence of gate insulation failure (vertical axis). FIG.
FIG. 19 is a diagram illustrating an example of a digital mobile phone system using the semiconductor device according to the first embodiment of the present invention;
FIG. 20 is an explanatory diagram showing basic functions of the semiconductor device according to one embodiment of the present invention;
FIG. 21 is a circuit diagram illustrating an example of a power amplifier circuit of the semiconductor device in FIG. 20;
FIG. 22 is a flowchart of a manufacturing process of a semiconductor device according to another embodiment of the present invention.
FIG. 23 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention during a manufacturing step thereof;
24 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 23;
[Explanation of symbols]
1 semiconductor substrate
1a Semiconductor substrate body
1b Semiconductor layer
2 Insulating layer
3 Semiconductor area
4 Field insulation film
5 n-well
6p well (first semiconductor region)
7a, 7b Gate insulating film
8 Gate electrode
9 Cap insulating film
12a Semiconductor region
13a Semiconductor region (second semiconductor region)
13b Semiconductor region (third semiconductor region)
13c semiconductor region (fourth semiconductor region)
15 Insulating film
17 Semiconductor area
20 Insulating film
22 Digital Mobile Phone System
80 Semiconductor substrate
81 Gate insulating film
82 Gate electrode
83 Photoresist pattern
Sub semiconductor substrate
Gox Gate insulation film
NMA semiconductor area
IFS insulation film
IFSW sidewall
NSA semiconductor area
RPA photoresist pattern
RP1 to RP6 Photoresist pattern
Qn, Qn1 to Qn3 Power n-channel type LDMOS • FET
Qp Standard p-channel type LDMOS ・ FET
PM RF power module
MIC microphone
SPC signal processing circuit
SWC switch circuit
SP speaker
ANT antenna
LAMP low noise amplifier
Pin input signal
Pout output signal
BIAS bias circuit
M1-M9 matching circuit
Vdd power supply voltage
Vabc control voltage
Vapc control voltage

Claims (18)

A method for manufacturing a semiconductor device having an LDMOS-FET having a source, a gate electrode, and a drain includes the following steps:
(A) forming a first semiconductor region of a first conductivity type in a region including the source of a semiconductor substrate;
(B) forming a gate insulating film on the semiconductor substrate;
(C) forming a gate electrode on the gate insulating film;
(D) forming a second semiconductor region of a second conductivity type opposite to the first conductivity type on the semiconductor substrate on the drain side of the LDMOS-FET by introducing a first impurity into the semiconductor substrate; ,
(E) forming an insulating film on a side surface of the gate electrode;
(F) In a state in which the insulating film is formed, a second impurity having a higher concentration than the first impurity is introduced into the semiconductor substrate, so that a drain-side semiconductor substrate of the LDMOS-FET is formed. A third semiconductor region of two conductivity type is formed such that an end of the third semiconductor region is disposed at a position away from an end of the gate electrode on the drain side, and a source side of the LDMOS-FET is formed. Forming a fourth semiconductor region of the second conductivity type for the source in the first semiconductor region. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said insulating film is also formed on said semiconductor substrate and on a gate electrode. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the second impurity is left on the semiconductor substrate without processing the insulating film after the step of forming the insulating film. A method for manufacturing a semiconductor device, comprising: introducing semiconductor into a semiconductor substrate. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness of the insulating film is 7 to 40 nm. 5. The method of manufacturing a semiconductor device according to claim 4, wherein said insulating film has a thickness of 10 to 20 nm. 5. The method for manufacturing a semiconductor device according to claim 4, wherein said insulating film is made of silicon oxide. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a dose of said second impurity is 1 × 10 ¹⁵ / cm ² or more. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said second impurity is arsenic. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the on-resistance of the LDMOS-FET is 5 Ωmm or less. A method for manufacturing a semiconductor device having an LDMOS-FET having a source, a gate electrode, and a drain includes the following steps:
(A) forming a first semiconductor region of a first conductivity type in a region including the source of a semiconductor substrate;
(B) forming a gate insulating film on the semiconductor substrate;
(C) forming a gate electrode on the gate insulating film;
(D) forming a second semiconductor region of a second conductivity type opposite to the first conductivity type on the semiconductor substrate on the drain side of the LDMOS-FET by introducing a first impurity into the semiconductor substrate; ,
(E) forming an insulating film made of silicon oxide having a thickness of 7 to 40 nm on a side surface of the gate electrode;
(F) In the state where the insulating film is formed, arsenic of a second impurity having a higher concentration than the first impurity is introduced into the semiconductor substrate so that a dose amount is 1 × 10 ¹⁵ / cm ² or more. Thereby, the third semiconductor region of the second conductivity type for the drain is separated from the semiconductor substrate on the drain side of the LDMOS-FET, and the end of the third semiconductor region is separated from the end of the gate electrode on the drain side. Forming a fourth semiconductor region of the second conductivity type for the source in the first semiconductor region on the source side of the LDMOS-FET, while forming the fourth semiconductor region on the source side of the LDMOS-FET. A semiconductor device having an LDMOS • FET having a source, a gate electrode and a drain, including the following configuration:
(A) a first semiconductor region of a first conductivity type formed in a region including the source of a semiconductor substrate;
(B) a gate insulating film formed on the semiconductor substrate;
(C) a gate electrode formed on the gate insulating film;
(D) an insulating film formed on the semiconductor substrate, on the side and top surfaces of the gate electrode,
(E) a semiconductor region having a first impurity concentration formed on the drain side of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type;
(F) a drain formed on the semiconductor substrate, the second impurity concentration being higher than the first impurity concentration, and a second impurity concentration provided at a position away from an end of the gate electrode on the drain side; A conductive third semiconductor region,
(G) a source formed in the first semiconductor region of the semiconductor substrate, wherein a source is formed such that an end thereof is separated from a side surface of the gate electrode on the source side according to a thickness of the insulating film. A second conductivity type fourth semiconductor region having a two impurity concentration. 12. The semiconductor device according to claim 11, wherein said insulating film has a thickness of 7 to 40 nm. 13. The semiconductor device according to claim 12, wherein said insulating film has a thickness of 10 to 20 nm. 12. The semiconductor device according to claim 11, wherein the third and fourth semiconductor regions have an impurity concentration of 1 × 10 ²⁰ / cm ³ or more. 12. The semiconductor device according to claim 11, wherein said second impurity is arsenic. 12. The semiconductor device according to claim 11, wherein the on-resistance of the LDMOS-FET is 5 Ωmm or less. 12. The semiconductor device according to claim 11, wherein the insulating films formed on the semiconductor substrate, the side surfaces and the upper surface of the gate electrode are the same insulating film. 12. The semiconductor device according to claim 11, wherein the insulating film is made of silicon oxide having a thickness of 7 to 40 nm, and the third and fourth semiconductor regions have an impurity concentration of 1 × 10 ²⁰ / cm ³ or more. 3. A semiconductor device, wherein the fourth semiconductor region contains arsenic.

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