JP2004266272A - Field effect transistor and liquid crystal display apparatus employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To develop a field effect transistor having high performance both in the carrier mobility and in the on/off ratio and the semiconductor layer of which employs an organic polymer semiconductor with highly general versatility and a crystal liquid display apparatus employing the field effect transistors. <P>SOLUTION: The field effect transistor controls the conductivity of the semiconductor layer provided between a source electrode and a drain electrode by a gate electrode provided via an insulating layer and the semiconductor layer is formed by the organic polymer semiconductor in which carbon nano-tubes are dispersed and the current is controlled in the depletion mode. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a field effect transistor using an organic polymer semiconductor as a semiconductor layer, and particularly to a field effect transistor in which carbon nanotubes are dispersed in a semiconductor layer.

  Conventionally, a field-effect transistor (hereinafter referred to as an FET element) uses an inorganic semiconductor such as silicon or germanium. It was necessary throughout the stages. In the semiconductor industry which has adopted such a manufacturing method, there is an increasing demand for a reduction in manufacturing cost and an increase in the area of a liquid crystal display device which is one of the main applications. However, it is considered that it is difficult to further reduce the cost and increase the area of the inorganic semiconductor due to the limitation of the manufacturing apparatus.

  For this reason, an FET device using an organic polymer semiconductor having excellent moldability as a semiconductor layer has been proposed. By using an organic polymer semiconductor or a conductive polymer as an ink, a circuit pattern can be directly formed on a substrate by an ink-jet technique, a screening technique, or the like.

  As a technology of an FET device using an organic polymer semiconductor as a semiconductor layer, an FET device selected from polyacetylene, polythienylenevinylene, polyfuranylenevinylene, and their substituted derivatives (for example, see Patent Document 1) and a semiconductor layer are described. An FET composed of one π-conjugated polymer, a source electrode made of a second π-conjugated polymer, a drain electrode made of a third π-conjugated polymer, and a gate electrode made of a fourth π-conjugated polymer An element (for example, see Patent Document 2) is disclosed.

Indices indicating the performance of the FET element include a carrier mobility and an on / off ratio. The improvement of the carrier mobility means that the on-current is increased. On the other hand, the improvement of the on / off ratio means that the on-current is increased and the off-current is decreased. Both of these are to improve the switching characteristics of the FET element, and specifically to realize high contrast and high resolution in, for example, a liquid crystal display device. In the case of a liquid crystal display device, these values are required to have a carrier mobility of at least 10 ⁻³ cm ² / V · sec and an on / off ratio of at least 10 ^{4 under} the conditions of a source-drain voltage of several V and a gate voltage range of about 20 V. .

In the prior art, an FET device using an organic polymer semiconductor for a semiconductor layer has not been able to achieve performance that meets industrial requirements in terms of the carrier mobility and the on / off ratio. For example, an FET device selected from polythiophene and a substituted derivative thereof is disclosed as having higher performance than an FET device using the organic polymer semiconductor in terms of carrier mobility (see Patent Document 3). The carrier mobility has a very low value of 2.2 × 10 ⁻⁵ cm ² / V · sec.

In addition, the relationship between the solvent and the on / off ratio of an FET device manufactured by forming a semiconductor layer with a poly-3-hexylthiophene solution using a different solvent has been studied (see Non-Patent Document 1), but the value is enhanced mode. Was less than 10 ⁴ , which was insufficient. Furthermore, in a FET device in which a semiconductor layer of poly-3-hexylthiophene is covered with a silicon oxide film and a polyphenylene vinylene derivative film, a carrier mobility of about 0.05 cm ² / V · sec and an on / off ratio of 10 ⁶ or more have been reported. (See Non-Patent Document 2), but the range of the gate voltage at this time is 60 V or more, which greatly exceeds the gate voltage range of 20 to 30 V when controlling a general FET element. The on / off ratio when changing from 0V to -20V is as low as 10 ³ or less. In addition, it is possible only with the special configuration as described above, and furthermore, there are various problems in the production due to restrictions such as that the element production process must be performed in a nitrogen atmosphere.

Although the above is an example in which an FET element using poly-3-hexylthiophene as a semiconductor layer is used in an enhancement mode, an example in which the FET element is used in a depletion mode is also disclosed (see Non-Patent Document 1). The mobility is 0.01 cm ² / V · sec, but the on / off ratio is very low at 10 ¹ .

On the other hand, isolation of a semiconductor layer between elements is usually performed using a patterning technique by photolithography. However, an organic semiconductor is generally easily dissolved in an organic solvent, and has a problem that it is difficult to selectively remove the semiconductor by patterning. At present, a technique is disclosed in which a gate electrode is provided in a semiconductor layer portion between elements to form a depletion layer to achieve insulation (isolation) (see Patent Document 4).
JP-A-64-36076 (Claims) JP-A-1-259563 (Claims) JP-A-6-177380 (Claims) JP-T-2003-508797 (Claims) Applied Physics Letters, vol. 69, 1998 (October 2, 1998), p4108 "Science", vol. 280, 1998 (issued on June 12, 1998), p1741

  As described above, all of the conventional field effect transistors using an organic polymer semiconductor as a semiconductor layer have problems in performance, manufacturing method, configuration, and the like. An object of the present invention is to develop an FET device using a high-versatility organic polymer semiconductor as a semiconductor layer with high carrier mobility and on / off ratio, and a liquid crystal display device using the FET device. And

The present invention has the following configuration in order to achieve the object of the present invention.
(1) A field-effect transistor in which the conductivity of a semiconductor layer provided between a source electrode and a drain electrode is controlled by a gate electrode provided via an insulating layer, wherein the semiconductor layer is an organic polymer in which carbon nanotubes are dispersed. A field-effect transistor formed of a semiconductor and controlling current in a depletion mode.
(2) A field effect transistor in which the conductivity of an organic polymer semiconductor layer in which carbon nanotubes are provided between a source electrode and a drain electrode is dispersed is controlled by a gate electrode provided through an insulating layer. The field effect transistor according to (1), wherein the weight fraction of the organic polymer semiconductor is 0.1% by weight or more and 1% by weight or less, and the thickness of the organic polymer semiconductor layer is 10 nm or more and 100 nm or less.
(3) The field effect transistor according to (1) or (2), wherein the length of the carbon nanotube is smaller than the distance between the source electrode and the drain electrode.
(4) The field effect transistor according to any one of (1) to (3), wherein the organic polymer semiconductor is an organic polymer semiconductor having a polythiophene-based polymer.
(5) A plurality of address lines and a plurality of data lines are provided on a pair of opposed substrates in a matrix so as to face each other, and a field-effect transistor arranged at an intersection of the matrix wiring; An active matrix liquid crystal display device in which a liquid crystal layer is sandwiched between a pixel electrode connected to the data line via a type transistor and a counter electrode facing the pixel electrode, wherein the field effect transistor is (1) A liquid crystal display device which is the field-effect transistor according to any one of (1) to (4).

  According to the present invention, it is possible to provide a field-effect transistor using an organic polymer semiconductor having a high performance in carrier mobility and on-off ratio as a semiconductor layer, and a liquid crystal display device using the field-effect transistor as a driving element.

  The present invention is a high-performance FET device obtained by forming an organic polymer semiconductor layer of a FET device from a polythiophene-based polymer and dispersing a single-walled or multi-walled carbon nanotube in the semiconductor layer. This is a method for easily manufacturing a high-performance FET device used in a depletion mode by using a composite of a polymer and a carbon nanotube (hereinafter, referred to as CNT). The specific configuration and manufacturing method of the FET device will be described below.

  FIG. 1 is a schematic sectional view showing an example of the FET device of the present invention. On the substrate 1 having the gate electrode 2 covered with the insulating layer 3, a source electrode 5 and a drain electrode 6 made of gold or the like were formed by using a normal photolithography technique, a vacuum evaporation method, or a sputtering method in FIG. After that, the semiconductor layer 4 of the organic polymer semiconductor in which the CNTs are dispersed is formed by spin coating. In (B), after a semiconductor layer 4 of an organic polymer semiconductor in which CNTs are dispersed is formed on the substrate by spin coating, a source electrode 5 and a drain electrode 6 of gold or the like are formed by mask evaporation or the like. Have been.

  As the substrate 1, for example, an inorganic material such as a silicon wafer, glass, or a sintered body of alumina, or an organic material such as polyimide, polyester, polyethylene, polyphenylene sulfide, or polyparaxylene can be used. Here, the FET device of the present invention has higher performance than the conventional FET device without performing any process for improving the substrate surface other than the substrate cleaning.For example, in the case of a silicon oxide-based substrate such as a silicon wafer or a glass substrate, It is known that treatment with a surface modifier, such as a silane coupling agent, has the effect of improving the performance of FET devices, and such a surface treatment is of course possible in the present invention. It is.

  As the gate electrode 2, the source electrode 5 and the drain electrode 6, metals such as gold, platinum, silver, copper, chromium, palladium, aluminum, indium, molybdenum, low-resistance polysilicon, low-resistance amorphous silicon, tin oxide, and oxide Metallic inorganic compounds such as indium, indium tin oxide (ITO), platinum silicide and indium silicide, and metallic organic compounds such as poly-3,4-ethylenedioxythiophene / polystyrene sulfonate (PEDOT / PSS) can be used. Two or more of these materials may be used in combination, but a metal having high conductivity and being chemically stable is preferred, and gold and platinum are particularly preferred.

  The gate electrode 2, the source electrode 5, and the drain electrode 6 can be formed by vapor deposition, sputtering, plating, various types of CVD growth, a spin coating method, a so-called semiconductor process technology such as photolithography technology or etching, cluster ion beam deposition, or the like. .

  Specific examples of the material used for the insulating layer 3 (gate insulating film) include inorganic materials such as silicon oxide and alumina; organic polymer materials such as polyimide, polyvinyl alcohol, polyvinyl chloride, polyethylene terephthalate, and polyvinylidene fluoride; A mixture of an inorganic material powder and an organic polymer material can be used. The insulating layer can be formed by sputtering, vapor deposition, spin coating, or the like.

  The kind of the organic polymer semiconductor that plays a semiconducting role in the FET device of the present invention is not particularly limited, but those that are soluble in a solvent are preferable because of ease of film formation, and among them, a polythiophene-based polymer is preferable. The polythiophene-based polymer has a structure in which a side chain is attached to a polymer having a skeleton of a polythiophene structure. Specific examples include poly-3-alkylthiophene (alkyl group) such as poly-3-methylthiophene, poly-3-butylthiophene, poly-3-hexylthiophene, poly-3-octylthiophene, and poly-3-dodecylthiophene. Is not particularly limited, but is preferably 1 to 12), and poly-3-alkoxythiophenes such as poly-3-methoxythiophene, poly-3-ethoxythiophene, poly-3-dodecyloxythiophene (carbon of alkoxy group) Although the number is not particularly limited, preferably 1 to 12), poly-3-alkoxy-4-alkylthiophene (alkoxy) such as poly-3-methoxy-4-methylthiophene and poly-3-dodecyloxy-4-methylthiophene The carbon number of the group and the alkyl group is not particularly limited, but is preferably 1 to 12), and poly-3 Poly-3-thioalkylthiophenes (the number of carbon atoms of the alkyl group is not particularly limited, but preferably 1 to 12) such as thiohexylthiophene and poly-3-thiododecylthiophene, and one or more kinds are used. be able to. Among them, poly-3-alkylthiophene and poly-3-alkoxythiophene are preferable, and as the former, poly-3-hexylthiophene is particularly preferable. The preferred molecular weight is 800 to 100,000 in terms of weight average molecular weight. The polymer does not necessarily have to have a high molecular weight, but may be an oligomer.

  The bonding mode of the side chain of the polythiophene polymer used in the present invention is preferably one having a regioregular structure as described above, and is preferably applied to a polythiophene polymer having a regioregularity of at least 80% or more. You.

  The method of dispersing CNTs in the semiconductor layer 4, which is a point of the present invention, is not particularly limited. For example, (i) a method in which a dispersion of CNTs dispersed in a solvent is applied on a predetermined substrate by spin coating or the like, and A method of forming a thin film of an organic polymer semiconductor by a method and heat-treating the organic polymer semiconductor at about the glass transition temperature to disperse the CNTs in the thin film; A method in which a dispersion liquid in which CNTs are dispersed in a solvent is applied and formed by heat treatment, or (iii) a method in which a composite containing an organic polymer semiconductor and CNTs (hereinafter referred to as a semiconductive composite) is prepared, In which a thin film is formed. Among them, the method of using the semiconductor composite (iii) as the semiconductor layer is preferable.

  Examples of the method for producing the above-mentioned semiconductive composite include (I) a method in which CNT is added to a molten organic polymer semiconductor and mixed, and (II) a method in which the organic polymer semiconductor is dissolved in a solvent and CNT is added thereto. (III) a method in which CNTs are preliminarily dispersed in a solvent by ultrasonic waves or the like, and an organic polymer semiconductor is added and mixed, and (IV) an organic polymer semiconductor in a solvent. And CNTs, and irradiating the mixed system with ultrasonic waves to mix them. In the present invention, any method may be used alone or any method may be combined, and there is no particular limitation.

  The weight fraction of the CNTs contained in the semiconductive composite is not particularly limited, but is preferably 0.1 to 1 wt% in order to not impair the semiconductivity when using a method of dispersing the CNTs by ultrasonic irradiation. . To give a specific example, in the case of a semiconductor composite prepared using poly-3-hexylthiophene and single-walled CNT, the weight fraction of carbon nanotubes is preferably 0.1 to 0.6% by weight. If the weight fraction is higher than this, the conductivity of the composite excessively increases, so that the composite is not suitable for use as a semiconductor layer. In order to determine such a detailed range of the weight fraction, the critical content in percolation theory that explains the conductivity phenomenon of the composite material is obtained by plotting the conductivity of the composite against the weight fraction, and this critical content is determined. It is preferable to determine the weight fraction so as to be smaller than the ratio. As an example, FIG. 2 shows a plot of the conductivity of a semiconducting composite of poly-3-hexylthiophene and single-walled CNT prepared by irradiating ultrasonic waves by the above method with respect to the weight fraction of CNT. . In this case, the critical content was about 0.6% by weight, so that the weight fraction of CNT is preferably 0.6% by weight or less based on the organic polymer semiconductor. By determining the optimal CNT weight fraction in this manner, the FET element characteristics can be improved.

  The CNT used in the present invention needs to have a length shorter than at least the distance (channel length) between the source electrode and the drain electrode. If the length is longer than this, the electrodes may be short-circuited, which is unsuitable for fabricating FET devices. On the other hand, generally commercially available CNTs have a distribution in length, and may include CNTs longer than the channel length. Therefore, it is better to add a step of making the CNT shorter than the channel length, and a short circuit between the electrodes can be reliably prevented.

  In the present invention, it is preferable to provide a step of uniformly dispersing the CNTs in a solvent and filtering the CNT dispersion using a filter. By obtaining CNTs smaller than the filter pore diameter from the filtrate, carbon nanotubes smaller than the distance between the source electrode and the drain electrode can be efficiently obtained.

  In order to uniformly disperse CNTs in a solution, a surfactant such as sodium dodecylsulfonate, or a polymer having a coil-like structure, or a conjugated polymer is added together with CNTs in a solvent, and ultrasonic irradiation or heat reflux is performed. The method is preferably used. In consideration of improving the characteristics of the FET element, it is preferable to use a substance having more excellent semiconductor characteristics, and it is particularly preferable to use a conjugated polymer. Among them, a linear conjugated polymer is preferably used, and poly-3-alkylthiophene and the like can be used.

  Any type of filter, such as a membrane filter, a cellulose filter paper, or a glass fiber filter paper, may be used as long as the filter used for filtration has a pore size smaller than the channel length. Above all, a membrane filter can be preferably used because it can reduce the amount of CNT adsorbed inside the filter paper and can recover CNT from the filtrate in good yield.

  The pore size of the filter used for filtration only needs to be smaller than the channel length. For example, when the channel length is 20 μm, a short circuit between the electrodes can be reliably prevented by using a filter having a pore size of 10 μm. Actually, a filter having a pore size of 0.5 to 10 μm can be preferably used, and can be used properly according to the channel length.

  As another method for shortening CNT, a method of shortening CNT itself by acid treatment is known, and can be used in the present invention. In this case, shortened CNTs can be obtained by adding CNTs to a mixed acid of sulfuric acid and nitric acid and irradiating with ultrasonic waves or performing heat treatment at 100 ° C. or more. Further, a method of heating in a hydrogen peroxide solution can also be used. When these methods are performed, the CNTs treated as a post-treatment using a filter having a pore size of 0.1 to 1 μm are separated by filtration and washed with water, so that the carbon having a distance smaller than the distance between the source electrode and the drain electrode is obtained. Nanotubes can be obtained.

  The CNT includes a single-layer CNT in which one carbon film (graphene sheet) is wound in a cylindrical shape, a two-layer CNT in which two graphene sheets are wound concentrically, and a plurality of graphene sheets in a concentric circle. There is a multilayer CNT wound in a shape, and in the present invention, each of them can be used alone, or two or three of a single layer, a double layer, and a multilayer can be used simultaneously. In addition, the CNT used in the present invention is obtained by any method, such as an arc discharge method, a chemical vapor deposition method (hereinafter, referred to as a CVD method), or a laser ablation method. There may be.

  The organic polymer semiconductor and the thin film of the semiconductor composite are dissolved in a solvent to form a solution, formed on a predetermined substrate by a dipping method, a printing transfer method, a spin coating method, a casting method using a blade, or the like, and removing the solvent. It can be obtained by:

  The concentration of the solution at that time is 0.1 to 10% by weight, preferably 0.1 to 1% by weight. For example, a 40 nm-thick thin film is formed by spin-coating a chloroform solution (concentration: 0.34% by weight) of a semiconductor composite prepared by the above method using poly-3-hexylthiophene on a silicon wafer at 1000 rpm. be able to.

The thickness of the semiconductor layer is not particularly limited, but is preferably 10 nm or more and 100 nm or less. Within this range, it is possible to realize an on / off ratio of 10 ³ or more (Examples 1, 3, and 4), but if the film thickness is larger than this range, the source-drain current that cannot be controlled by the gate voltage Increases, and the on / off ratio of the FET element decreases. Further, below this range, there is a problem that the carrier mobility decreases.

  The FET device of the present invention can be used for various devices, and can be used particularly as a driving device for a display device such as a liquid crystal display device and an electroluminescence display device.

  FIG. 3 is a schematic sectional view showing an example of a liquid crystal display device using the FET device of the present invention. In a matrix display type liquid crystal display device including a plurality of address lines 7 and a plurality of data lines 8, the FET element of the present invention is formed at the intersection of the matrix lines. The matrix display is performed by driving the liquid crystal layer composed of the liquid crystal molecules 11 sandwiched between the pixel electrode 9 connected to the data wiring 8 and the counter electrode 13 facing the electrode via the FET element. At this time, the conductivity of the semiconductor layer 4 provided between the source electrode and the drain electrode of the FET element is controlled by the gate electrode 2 provided via the insulating layer 3 to drive the liquid crystal.

  According to the present invention, an FET element can be easily formed on a large-sized substrate such as a liquid crystal display device. The current between the source and the drain can be largely modulated by the voltage applied to the gate, and high gradation characteristics can be obtained and the operation thereof is stable, so that an excellent matrix-type liquid crystal display device can be provided.

  The excellent characteristics of the FET element used in the depletion mode according to the present invention are estimated as follows.

  When carriers move between polymers or domains such as crystallites, the carriers are trapped or scattered by the disorder of the structure between the polymers or domains. The mobility is much lower than that of the polymer crystal. On the other hand, when CNTs are contained appropriately, it is considered that CNTs having high carrier mobility bridge between polymers and domains, and thus high mobility can be obtained.

  In addition, since CNTs are considered to be one-third in single-walled CNTs and entirely metallic in multi-walled CNTs, the electric field is uniform in each CNT in CNTs highly dispersed in the semiconductor layer, Therefore, it is assumed that an electric field is effectively applied to the semiconductor layer. For this reason, it is presumed that the gate voltage is effectively applied to the semiconductor layer, and the depletion layer region expands more at the time of off than in the case where there is no CNT, so that the off current is extremely suppressed.

  Further, according to the present invention, since the off-state current can be suppressed in the depletion mode, the present invention may be applied to provide isolation between FET elements. That is, isolation of a semiconductor layer between FET elements is usually performed using a patterning technique by photolithography. However, an organic semiconductor is generally easily dissolved in an organic solvent, and it is difficult to selectively remove the semiconductor by patterning. Therefore, if an off-voltage is applied by providing a gate electrode in a portion of a semiconductor layer to be removed by using the present invention, a depletion layer is formed and an off-current can be suppressed to a very low level. In addition, the same effect as that in which the elements are substantially electrically insulated (isolated) can be obtained. As a specific manufacturing means, for example, a method described in JP-T-2003-508797 may be used.

  Since the carrier mobility is improved as described above, the current between the source and drain when the gate voltage is 0 V to -10 V is increased, and the on / off ratio is improved. The current flowing at the time of the value (depletion mode) is further suppressed, and as a result, by using the present invention, excellent characteristics can be obtained in the FET operation by the gate voltage operation in the depletion mode.

  Hereinafter, the present invention will be specifically described based on examples. However, the present invention is not limited to the following examples.

Example 1
An FET device of the present invention as shown in the schematic sectional view (A) of FIG. 1 was produced. An antimony-doped silicon wafer (resistivity of 0.02 Ωcm or less) with a thermal oxide film (thickness: 300 nm) was used for the substrate 1. Here, the silicon wafer is the gate electrode 2 at the same time as the substrate 1, and the thermal oxide film is the insulating layer 3.

  Next, a gold source electrode 5 and a drain electrode 6 were formed using a photolithography technique and a vacuum evaporation method. The width (channel width) of these two electrodes was 50 cm, the interval (channel length) between both electrodes was 20 μm, and the electrode height was 40 nm.

  Next, a method for manufacturing a semiconductor composite including an organic polymer semiconductor used as the semiconductor layer 4 and single-layer CNT (hereinafter, referred to as SWCNT) will be described.

  A volume ratio of 50 mg of SWCNT (manufactured by CNI, purity 95%) to sulfuric acid (manufactured by Wako Pure Chemical Industries, Ltd., purity: 95% or more) and nitric acid (manufactured by Wako Pure Chemical Industries, Ltd., density: 1.38) is 3 : 1 and mixed in 200 mL of an acid mixture, and subjected to ultrasonic stirring for 19 hours using an ultrasonic cleaner (US-2, produced by Inuchi Seieido Co., Ltd., output: 120 W, 2.6 L) to reduce the length of SWCNT to 500 nm or less. did. The mixture of the mixed acid and SWCNT was filtered through a polytetrafluoroethylene (PTFE) membrane filter (manufactured by Millipore Corporation, filter type: JH) to filter out short SWCNT (hereinafter referred to as s-SWCNT).

  0.2 mg of the above s-SWCNT was added to 10 mL of chloroform, 0.2 mg of poly-3-hexylthiophene (manufactured by Aldrich, Regioregular) was added as an organic polymer semiconductor, and an ultrasonic homogenizer (VCX-manufactured by Sonics) was added while cooling with ice. 500), and the mixture was ultrasonically stirred at an output of 250 W for 30 minutes to obtain an s-SWCNT dispersion. 50 mg of poly-3-hexylthiophene was further added to the obtained SWCNT dispersion liquid, and the mixture was ultrasonically stirred for 30 minutes using an ultrasonic cleaner to thereby form a semiconductor composite containing poly-3-hexylthiophene and s-SWCNT as components. To give a chloroform solution. The chloroform solution was dropped on the substrate to form a thin film having a thickness of 40 nm by a spin coating method (rotation speed: 1000 rpm). This was left in a vacuum oven at 70 ° C. for 2 hours to remove the solvent, thereby forming a semiconductor layer.

  Next, the characteristics of the source-drain current (Id) -source-drain voltage (Vsd) when the gate voltage (Vg) of the FET element was changed were measured. The measurement was carried out under reduced pressure (1 torr or less) using a picoammeter / voltage source 4140B manufactured by Hewlett-Packard Company. Table 1 shows the results.

From Table 1, when Vg = 0 V, the Id of Vsd = -4 V is -2.49 × 10 ⁻⁵ A, whereas the Id at Vg = 20 V is greatly reduced to −2.41 × 10 ⁻⁹ A. You can see that it is doing. Here, such an operation of controlling Vg from 0 V to 20 V is called an operation in a depletion mode, and its range is only 20 V and the on / off ratio has reached 10 ⁴ or more.

When the carrier mobility was determined from the current-voltage characteristics obtained from the above measurement, it was 2.54 × 10 ⁻³ cm ² / V · sec.

Example 2
FIG. 3 is a cross-sectional view showing a liquid crystal display device using an FET device having a configuration similar to that of the first embodiment. The gate electrode 2 formed on the glass substrate 1 is connected to the address wiring 7. Of the source electrode 5 and the drain electrode 6 formed on the gate electrode 2 via the insulating layer 3, the source electrode 5 is connected to the data line 8, and the drain electrode is connected to the pixel electrode 9 made of ITO. A semiconductor layer 4 made of a semiconductor composite thin film is formed on the source electrode 5 and the drain electrode 6, and an alignment film 10 made of polyimide is formed on the entire FET element and the pixel electrode on the semiconductor layer 4. A counter electrode 13 and an alignment film 12 made of ITO are formed on a glass substrate 14 facing the glass substrate 14. A liquid crystal cell is formed by facing the glass substrate 14 including the counter electrode 12 and the glass substrate 1 including the pixel electrode 9 and the FET element by a usual method, and a liquid crystal is sealed between the two substrates. Note that the alignment films 10 and 12 made of polyimide are subjected to a rubbing treatment after the film formation.

  When the polarizing films were arranged in a crossed Nicol state on the upper and lower sides of the liquid crystal display device and the response was examined, a voltage of -5 V was applied to the data wiring (source electrode), a voltage of 0 V was applied to the counter electrode, and a voltage of 20 V was applied to the gate electrode through the address wiring. , And then a voltage of 0 V was applied. The liquid crystal was in a white display state when a voltage of 20 V was applied to the gate electrode, but quickly changed to a black display state without delay with respect to the potential of 0 V.

Example 3
An FET element was fabricated by performing the same operation as in the method of Example 1 except that a semiconductor layer having a thickness of 10 nm was formed using the semiconductor composite of Example 1.

Among the results of measuring the source-drain current (Id) -source-drain voltage (Vsd) characteristics when the gate voltage (Vg) is changed, Id when Vsd is -4V and Vg is 0V and 20V. Are shown in Table 1. When the on / off ratio was determined from this result, it was 3.97 × 10 ⁴ under the conditions of Vsd = −4 V and Vg in the range of 0 to 20 V, and the carrier mobility was 1.08 × 10 ⁻⁵ cm ² / V ·. sec.

Example 4
The method of Example 1 was repeated except that a semiconductor layer having a thickness of 100 nm was formed using poly-3-butylthiophene (Aldrich, Regioregular) as the organic polymer semiconductor constituting the semiconductor composite of Example 1. The same operation was performed to produce an FET device.

Among the results of measuring the source-drain current (Id) -source-drain voltage (Vsd) characteristics when the gate voltage (Vg) is changed, Id when Vsd is -4V and Vg is 0V and 20V. Are shown in Table 1. When the on / off ratio was determined from this result, it was 9.83 × 10 ³ under the conditions of Vsd = −4 V and Vg in the range of 0 to 20 V, and the carrier mobility was 3.56 × 10 ⁻³ cm ² / V ·. sec.

Example 5
An FET device was manufactured by performing the same operation as in the method of Example 1 except that a semiconductor layer of 1 μm was formed using the semiconductor composite of Example 1.

Among the results of measuring the source-drain current (Id) -source-drain voltage (Vsd) characteristics when the gate voltage (Vg) is changed, Id when Vsd is -4V and Vg is 0V and 20V. Are shown in Table 1. When the carrier mobility was calculated from the obtained current-voltage characteristics, it was 1.04 × 10 ⁻² cm ² / V · sec.

Comparative Example 1
An FET device was manufactured by performing the same operation as in the method of Example 1 except that the same poly-3-hexylthiophene used in manufacturing the composite was used instead of the semiconductor composite of Example 1. The thickness of the semiconductor layer of poly-3-hexylthiophene was 40 nm as in Example 1.

Of the results of measuring the source-drain current (Id) -source-drain voltage (Vsd) characteristics when the gate voltage (Vg) is changed, Id when Vsd is -4 V and Vg is 0 V and 20 V Are shown in Table 1. When the carrier mobility was calculated from the result, it was 7.23 × 10 ⁻⁵ cm ² / V · sec. Further, the on / off ratio in the range of Vg of 0 to 20 V at Vsd = -4 V was 3.47 × 10 ² .

Example 6
Fabrication of FET element by performing the same operation as in Example 1 except that the method of treating CNT contained in the semiconductor composite of Example 1 was changed from ultrasonic treatment in acid to filtration treatment of CNT dispersion liquid. did. The filtration treatment of the CNT dispersion was performed as follows. In a 50 mL glass sample tube, 2 mg of SWCNT (purity: 95%, manufactured by CNI), 2 mg of poly-3-hexylthiophene (manufactured by Aldrich, regioregular), which is a linear conjugated polymer, and 20 mL of chloroform were placed. And sonicated for 30 minutes using an ultrasonic crusher (VCX-500, manufactured by Tokyo Rika Instruments Co., Ltd., output 250 W, direct irradiation) to uniformly disperse the CNTs. 5 mL of this dispersion was collected and suction-filtered using a PTFE omnipore membrane filter (Advantech, 25 mm in diameter) having a nominal pore size of 10 μm. Although a trace amount of the separated substance was present on the filter, most of the CNTs were contained in the filtrate, and the filtrate was diluted 20 times to obtain a CNT dispersion having a CNT concentration of about 0.5 mg / 100 mL. Further, 500 mg of poly-3-hexylthiophene was added thereto, and the mixture was irradiated with ultrasonic waves for 30 minutes using an ultrasonic cleaning machine (US-2, produced by Inuchi Seieido Co., Ltd., output: 120 W, 2.6 L) to disperse CNTs. A semiconductive composite coating solution was obtained.

Next, an FET element having a semiconductor layer thickness of 40 nm was formed using this coating solution, and the FET element was moved to a vacuumed measurement box, and a voltage-current characteristic between a drain and a source was applied while a gate voltage was applied. Was measured. Among the results of measuring the source-drain current (Id) -source-drain voltage (Vsd) characteristics when the gate voltage was changed (Vg), the results were obtained when Vsd was -4 V, and Vg was 0 V and 20 V. Id is shown in Table 1. When the on / off ratio was determined from this result, it was 4.62 × 10 ³ under the conditions of Vsd = −4 V and Vg in the range of 0 to 20 V, and the carrier mobility was 7.30 × 10 ⁻³ cm ² / V /. sec.

Example 7
An FET device was produced in exactly the same manner as in Example 6, except that the CNT dispersion was not filtered through a filter having a pore size of 10 μm. The current-voltage characteristics between the source and the drain were measured, and Id when Vsd was −4 V and Vg was 0 V and 20 V was shown in Table 1. When the on / off ratio was determined from this result, it was 1.61 × 10 ⁰ under the conditions of Vsd = −4 V and Vg in the range of ⁰ to ²⁰ V, and the carrier mobility was 2.97 × 10 ⁻³ cm ² / V /. sec.

FIG. 2 is a schematic cross-sectional view showing an FET device according to the present invention. Plot of Conductivity of Semiconducting Composite of Poly-3-hexylthiophene and Single-Walled Carbon Nanotube Prepared by Irradiating Ultrasonic Waves against Carbon Nanotube Weight Fraction Example 2 is a schematic cross-sectional view of a liquid crystal display device according to a second exemplary embodiment of the present invention.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1, 14 Substrate 2 Gate electrode 3 Insulating layer 4 Semiconductor layer 5 Source electrode 6 Drain electrode 7 Address wiring 8 Data wiring 9 Pixel electrode 10, 12 Alignment film 11 Liquid crystal molecule 13 Counter electrode

Claims (8)

A field-effect transistor in which the conductivity of a semiconductor layer provided between a source electrode and a drain electrode is controlled by a gate electrode provided through an insulating layer, wherein the semiconductor layer is formed of an organic polymer semiconductor in which carbon nanotubes are dispersed. And controlling the current in a depletion mode. A field-effect transistor in which the conductivity of an organic polymer semiconductor layer in which carbon nanotubes are provided between a source electrode and a drain electrode is dispersed is controlled by a gate electrode provided through an insulating layer. 2. The field effect transistor according to claim 1, wherein the ratio is 0.1% by weight or more and 1% by weight or less with respect to the organic polymer semiconductor, and the film thickness of the organic polymer semiconductor layer is 10 nm or more and 100 nm or less. 3. The field effect transistor according to claim 1, wherein a length of the carbon nanotube is smaller than a distance between the source electrode and the drain electrode. The field effect transistor according to any one of claims 1 to 3, wherein the organic polymer semiconductor is an organic polymer semiconductor having a polythiophene-based polymer. A plurality of address lines and a plurality of data lines are provided in a matrix on a pair of opposed substrates, and a field-effect transistor disposed at an intersection of the matrix wiring and a field-effect transistor. An active matrix type liquid crystal display device in which a liquid crystal layer is sandwiched between a pixel electrode connected to the data line via a pixel electrode and a counter electrode facing the pixel electrode, wherein the field effect transistor is a liquid crystal display device according to claim 1. A liquid crystal display device, which is the field-effect transistor according to any one of the above. 4. The carbon nanotube according to claim 3, wherein the carbon nanotube is dispersed in a solvent together with the linear conjugated polymer, and the obtained carbon nanotube dispersion is filtered to obtain a carbon nanotube smaller than the distance between the source electrode and the drain electrode. Field-effect transistor. The field effect transistor according to claim 6, wherein the preparation of the carbon nanotube dispersion liquid is performed by ultrasonic irradiation. 7. The field effect transistor according to claim 6, wherein the filter used for filtering the carbon nanotube dispersion liquid is a membrane filter having a pore size of 0.5 to 10 [mu] m.

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